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clk: qcom: gcc-msm8998: Use parent_data/hws for internal clock relations

Use parent_data and parent_hws to specify internal relations using
pointers instead of names, and use .fw_name to retrieve external clocks
from clock-names in the DT rather than the global clock tree.

Note that this change relies on the "xo" and "sleep_clk" clocks to be
provided in DT, as per the relevant qcom,gcc-mnsm8998.yaml dt-bindings.
These clocks have been added in a prior patch [1].

[1]: https://lore.kernel.org/linux-arm-msm/20210911120101.248476-1-marijn.suijten@somainline.org/

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-3-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marijn Suijten and committed by
Stephen Boyd e815e34b d6f1c681

+281 -241
+281 -241
drivers/clk/qcom/gcc-msm8998.c
··· 63 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 64 64 .clkr.hw.init = &(struct clk_init_data){ 65 65 .name = "gpll0_out_even", 66 - .parent_names = (const char *[]){ "gpll0" }, 66 + .parent_hws = (const struct clk_hw*[]) { 67 + &gpll0.clkr.hw, 68 + }, 67 69 .num_parents = 1, 68 70 .ops = &clk_alpha_pll_postdiv_fabia_ops, 69 71 }, ··· 76 74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 77 75 .clkr.hw.init = &(struct clk_init_data){ 78 76 .name = "gpll0_out_main", 79 - .parent_names = (const char *[]){ "gpll0" }, 77 + .parent_hws = (const struct clk_hw*[]) { 78 + &gpll0.clkr.hw, 79 + }, 80 80 .num_parents = 1, 81 81 .ops = &clk_alpha_pll_postdiv_fabia_ops, 82 82 }, ··· 89 85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 90 86 .clkr.hw.init = &(struct clk_init_data){ 91 87 .name = "gpll0_out_odd", 92 - .parent_names = (const char *[]){ "gpll0" }, 88 + .parent_hws = (const struct clk_hw*[]) { 89 + &gpll0.clkr.hw, 90 + }, 93 91 .num_parents = 1, 94 92 .ops = &clk_alpha_pll_postdiv_fabia_ops, 95 93 }, ··· 102 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 103 97 .clkr.hw.init = &(struct clk_init_data){ 104 98 .name = "gpll0_out_test", 105 - .parent_names = (const char *[]){ "gpll0" }, 99 + .parent_hws = (const struct clk_hw*[]) { 100 + &gpll0.clkr.hw, 101 + }, 106 102 .num_parents = 1, 107 103 .ops = &clk_alpha_pll_postdiv_fabia_ops, 108 104 }, ··· 132 124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 133 125 .clkr.hw.init = &(struct clk_init_data){ 134 126 .name = "gpll1_out_even", 135 - .parent_names = (const char *[]){ "gpll1" }, 127 + .parent_hws = (const struct clk_hw*[]) { 128 + &gpll1.clkr.hw, 129 + }, 136 130 .num_parents = 1, 137 131 .ops = &clk_alpha_pll_postdiv_fabia_ops, 138 132 }, ··· 145 135 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 146 136 .clkr.hw.init = &(struct clk_init_data){ 147 137 .name = "gpll1_out_main", 148 - .parent_names = (const char *[]){ "gpll1" }, 138 + .parent_hws = (const struct clk_hw*[]) { 139 + &gpll1.clkr.hw, 140 + }, 149 141 .num_parents = 1, 150 142 .ops = &clk_alpha_pll_postdiv_fabia_ops, 151 143 }, ··· 158 146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 159 147 .clkr.hw.init = &(struct clk_init_data){ 160 148 .name = "gpll1_out_odd", 161 - .parent_names = (const char *[]){ "gpll1" }, 149 + .parent_hws = (const struct clk_hw*[]) { 150 + &gpll1.clkr.hw, 151 + }, 162 152 .num_parents = 1, 163 153 .ops = &clk_alpha_pll_postdiv_fabia_ops, 164 154 }, ··· 171 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 172 158 .clkr.hw.init = &(struct clk_init_data){ 173 159 .name = "gpll1_out_test", 174 - .parent_names = (const char *[]){ "gpll1" }, 160 + .parent_hws = (const struct clk_hw*[]) { 161 + &gpll1.clkr.hw, 162 + }, 175 163 .num_parents = 1, 176 164 .ops = &clk_alpha_pll_postdiv_fabia_ops, 177 165 }, ··· 201 185 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 202 186 .clkr.hw.init = &(struct clk_init_data){ 203 187 .name = "gpll2_out_even", 204 - .parent_names = (const char *[]){ "gpll2" }, 188 + .parent_hws = (const struct clk_hw*[]) { 189 + &gpll2.clkr.hw, 190 + }, 205 191 .num_parents = 1, 206 192 .ops = &clk_alpha_pll_postdiv_fabia_ops, 207 193 }, ··· 214 196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 215 197 .clkr.hw.init = &(struct clk_init_data){ 216 198 .name = "gpll2_out_main", 217 - .parent_names = (const char *[]){ "gpll2" }, 199 + .parent_hws = (const struct clk_hw*[]) { 200 + &gpll2.clkr.hw, 201 + }, 218 202 .num_parents = 1, 219 203 .ops = &clk_alpha_pll_postdiv_fabia_ops, 220 204 }, ··· 227 207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 228 208 .clkr.hw.init = &(struct clk_init_data){ 229 209 .name = "gpll2_out_odd", 230 - .parent_names = (const char *[]){ "gpll2" }, 210 + .parent_hws = (const struct clk_hw*[]) { 211 + &gpll2.clkr.hw, 212 + }, 231 213 .num_parents = 1, 232 214 .ops = &clk_alpha_pll_postdiv_fabia_ops, 233 215 }, ··· 240 218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 241 219 .clkr.hw.init = &(struct clk_init_data){ 242 220 .name = "gpll2_out_test", 243 - .parent_names = (const char *[]){ "gpll2" }, 221 + .parent_hws = (const struct clk_hw*[]) { 222 + &gpll2.clkr.hw, 223 + }, 244 224 .num_parents = 1, 245 225 .ops = &clk_alpha_pll_postdiv_fabia_ops, 246 226 }, ··· 270 246 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 271 247 .clkr.hw.init = &(struct clk_init_data){ 272 248 .name = "gpll3_out_even", 273 - .parent_names = (const char *[]){ "gpll3" }, 249 + .parent_hws = (const struct clk_hw*[]) { 250 + &gpll3.clkr.hw, 251 + }, 274 252 .num_parents = 1, 275 253 .ops = &clk_alpha_pll_postdiv_fabia_ops, 276 254 }, ··· 283 257 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 284 258 .clkr.hw.init = &(struct clk_init_data){ 285 259 .name = "gpll3_out_main", 286 - .parent_names = (const char *[]){ "gpll3" }, 260 + .parent_hws = (const struct clk_hw*[]) { 261 + &gpll3.clkr.hw, 262 + }, 287 263 .num_parents = 1, 288 264 .ops = &clk_alpha_pll_postdiv_fabia_ops, 289 265 }, ··· 296 268 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 297 269 .clkr.hw.init = &(struct clk_init_data){ 298 270 .name = "gpll3_out_odd", 299 - .parent_names = (const char *[]){ "gpll3" }, 271 + .parent_hws = (const struct clk_hw*[]) { 272 + &gpll3.clkr.hw, 273 + }, 300 274 .num_parents = 1, 301 275 .ops = &clk_alpha_pll_postdiv_fabia_ops, 302 276 }, ··· 309 279 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 310 280 .clkr.hw.init = &(struct clk_init_data){ 311 281 .name = "gpll3_out_test", 312 - .parent_names = (const char *[]){ "gpll3" }, 282 + .parent_hws = (const struct clk_hw*[]) { 283 + &gpll3.clkr.hw, 284 + }, 313 285 .num_parents = 1, 314 286 .ops = &clk_alpha_pll_postdiv_fabia_ops, 315 287 }, ··· 339 307 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 340 308 .clkr.hw.init = &(struct clk_init_data){ 341 309 .name = "gpll4_out_even", 342 - .parent_names = (const char *[]){ "gpll4" }, 310 + .parent_hws = (const struct clk_hw*[]) { 311 + &gpll4.clkr.hw, 312 + }, 343 313 .num_parents = 1, 344 314 .ops = &clk_alpha_pll_postdiv_fabia_ops, 345 315 }, ··· 352 318 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 353 319 .clkr.hw.init = &(struct clk_init_data){ 354 320 .name = "gpll4_out_main", 355 - .parent_names = (const char *[]){ "gpll4" }, 321 + .parent_hws = (const struct clk_hw*[]) { 322 + &gpll4.clkr.hw, 323 + }, 356 324 .num_parents = 1, 357 325 .ops = &clk_alpha_pll_postdiv_fabia_ops, 358 326 }, ··· 365 329 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 366 330 .clkr.hw.init = &(struct clk_init_data){ 367 331 .name = "gpll4_out_odd", 368 - .parent_names = (const char *[]){ "gpll4" }, 332 + .parent_hws = (const struct clk_hw*[]) { 333 + &gpll4.clkr.hw, 334 + }, 369 335 .num_parents = 1, 370 336 .ops = &clk_alpha_pll_postdiv_fabia_ops, 371 337 }, ··· 378 340 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 379 341 .clkr.hw.init = &(struct clk_init_data){ 380 342 .name = "gpll4_out_test", 381 - .parent_names = (const char *[]){ "gpll4" }, 343 + .parent_hws = (const struct clk_hw*[]) { 344 + &gpll4.clkr.hw, 345 + }, 382 346 .num_parents = 1, 383 347 .ops = &clk_alpha_pll_postdiv_fabia_ops, 384 348 }, ··· 403 363 { P_CORE_BI_PLL_TEST_SE, 7 }, 404 364 }; 405 365 406 - static const char * const gcc_parent_names_0[] = { 407 - "xo", 408 - "gpll0_out_main", 409 - "gpll0_out_main", 410 - "core_bi_pll_test_se", 366 + static const struct clk_parent_data gcc_parent_data_0[] = { 367 + { .fw_name = "xo" }, 368 + { .hw = &gpll0_out_main.clkr.hw }, 369 + { .hw = &gpll0_out_main.clkr.hw }, 370 + { .fw_name = "core_bi_pll_test_se" }, 411 371 }; 412 372 413 373 static const struct parent_map gcc_parent_map_1[] = { ··· 416 376 { P_CORE_BI_PLL_TEST_SE, 7 }, 417 377 }; 418 378 419 - static const char * const gcc_parent_names_1[] = { 420 - "xo", 421 - "gpll0_out_main", 422 - "core_bi_pll_test_se", 379 + static const struct clk_parent_data gcc_parent_data_1[] = { 380 + { .fw_name = "xo" }, 381 + { .hw = &gpll0_out_main.clkr.hw }, 382 + { .fw_name = "core_bi_pll_test_se" }, 423 383 }; 424 384 425 385 static const struct parent_map gcc_parent_map_2[] = { ··· 430 390 { P_CORE_BI_PLL_TEST_SE, 7 }, 431 391 }; 432 392 433 - static const char * const gcc_parent_names_2[] = { 434 - "xo", 435 - "gpll0_out_main", 436 - "core_pi_sleep_clk", 437 - "gpll0_out_main", 438 - "core_bi_pll_test_se", 393 + static const struct clk_parent_data gcc_parent_data_2[] = { 394 + { .fw_name = "xo" }, 395 + { .hw = &gpll0_out_main.clkr.hw }, 396 + { .fw_name = "sleep_clk" }, 397 + { .hw = &gpll0_out_main.clkr.hw }, 398 + { .fw_name = "core_bi_pll_test_se" }, 439 399 }; 440 400 441 401 static const struct parent_map gcc_parent_map_3[] = { ··· 444 404 { P_CORE_BI_PLL_TEST_SE, 7 }, 445 405 }; 446 406 447 - static const char * const gcc_parent_names_3[] = { 448 - "xo", 449 - "core_pi_sleep_clk", 450 - "core_bi_pll_test_se", 407 + static const struct clk_parent_data gcc_parent_data_3[] = { 408 + { .fw_name = "xo" }, 409 + { .fw_name = "sleep_clk" }, 410 + { .fw_name = "core_bi_pll_test_se" }, 451 411 }; 452 412 453 413 static const struct parent_map gcc_parent_map_4[] = { ··· 457 417 { P_CORE_BI_PLL_TEST_SE, 7 }, 458 418 }; 459 419 460 - static const char * const gcc_parent_names_4[] = { 461 - "xo", 462 - "gpll0_out_main", 463 - "gpll4_out_main", 464 - "core_bi_pll_test_se", 420 + static const struct clk_parent_data gcc_parent_data_4[] = { 421 + { .fw_name = "xo" }, 422 + { .hw = &gpll0_out_main.clkr.hw }, 423 + { .hw = &gpll4_out_main.clkr.hw }, 424 + { .fw_name = "core_bi_pll_test_se" }, 465 425 }; 466 426 467 427 static const struct parent_map gcc_parent_map_5[] = { ··· 471 431 { P_CORE_BI_PLL_TEST_SE, 7 }, 472 432 }; 473 433 474 - static const char * const gcc_parent_names_5[] = { 475 - "xo", 476 - "gpll0_out_main", 477 - "aud_ref_clk", 478 - "core_bi_pll_test_se", 434 + static const struct clk_parent_data gcc_parent_data_5[] = { 435 + { .fw_name = "xo" }, 436 + { .hw = &gpll0_out_main.clkr.hw }, 437 + { .fw_name = "aud_ref_clk" }, 438 + { .fw_name = "core_bi_pll_test_se" }, 479 439 }; 480 440 481 441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { ··· 492 452 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 493 453 .clkr.hw.init = &(struct clk_init_data){ 494 454 .name = "blsp1_qup1_i2c_apps_clk_src", 495 - .parent_names = gcc_parent_names_1, 496 - .num_parents = 3, 455 + .parent_data = gcc_parent_data_1, 456 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 497 457 .ops = &clk_rcg2_ops, 498 458 }, 499 459 }; ··· 517 477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 518 478 .clkr.hw.init = &(struct clk_init_data){ 519 479 .name = "blsp1_qup1_spi_apps_clk_src", 520 - .parent_names = gcc_parent_names_0, 521 - .num_parents = 4, 480 + .parent_data = gcc_parent_data_0, 481 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 522 482 .ops = &clk_rcg2_ops, 523 483 }, 524 484 }; ··· 531 491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 532 492 .clkr.hw.init = &(struct clk_init_data){ 533 493 .name = "blsp1_qup2_i2c_apps_clk_src", 534 - .parent_names = gcc_parent_names_1, 535 - .num_parents = 3, 494 + .parent_data = gcc_parent_data_1, 495 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 536 496 .ops = &clk_rcg2_ops, 537 497 }, 538 498 }; ··· 545 505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 546 506 .clkr.hw.init = &(struct clk_init_data){ 547 507 .name = "blsp1_qup2_spi_apps_clk_src", 548 - .parent_names = gcc_parent_names_0, 549 - .num_parents = 4, 508 + .parent_data = gcc_parent_data_0, 509 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 550 510 .ops = &clk_rcg2_ops, 551 511 }, 552 512 }; ··· 559 519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 560 520 .clkr.hw.init = &(struct clk_init_data){ 561 521 .name = "blsp1_qup3_i2c_apps_clk_src", 562 - .parent_names = gcc_parent_names_1, 563 - .num_parents = 3, 522 + .parent_data = gcc_parent_data_1, 523 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 564 524 .ops = &clk_rcg2_ops, 565 525 }, 566 526 }; ··· 573 533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 574 534 .clkr.hw.init = &(struct clk_init_data){ 575 535 .name = "blsp1_qup3_spi_apps_clk_src", 576 - .parent_names = gcc_parent_names_0, 577 - .num_parents = 4, 536 + .parent_data = gcc_parent_data_0, 537 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 578 538 .ops = &clk_rcg2_ops, 579 539 }, 580 540 }; ··· 587 547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 588 548 .clkr.hw.init = &(struct clk_init_data){ 589 549 .name = "blsp1_qup4_i2c_apps_clk_src", 590 - .parent_names = gcc_parent_names_1, 591 - .num_parents = 3, 550 + .parent_data = gcc_parent_data_1, 551 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 592 552 .ops = &clk_rcg2_ops, 593 553 }, 594 554 }; ··· 601 561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 602 562 .clkr.hw.init = &(struct clk_init_data){ 603 563 .name = "blsp1_qup4_spi_apps_clk_src", 604 - .parent_names = gcc_parent_names_0, 605 - .num_parents = 4, 564 + .parent_data = gcc_parent_data_0, 565 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 606 566 .ops = &clk_rcg2_ops, 607 567 }, 608 568 }; ··· 615 575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 616 576 .clkr.hw.init = &(struct clk_init_data){ 617 577 .name = "blsp1_qup5_i2c_apps_clk_src", 618 - .parent_names = gcc_parent_names_1, 619 - .num_parents = 3, 578 + .parent_data = gcc_parent_data_1, 579 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 620 580 .ops = &clk_rcg2_ops, 621 581 }, 622 582 }; ··· 629 589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 630 590 .clkr.hw.init = &(struct clk_init_data){ 631 591 .name = "blsp1_qup5_spi_apps_clk_src", 632 - .parent_names = gcc_parent_names_0, 633 - .num_parents = 4, 592 + .parent_data = gcc_parent_data_0, 593 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 634 594 .ops = &clk_rcg2_ops, 635 595 }, 636 596 }; ··· 643 603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 644 604 .clkr.hw.init = &(struct clk_init_data){ 645 605 .name = "blsp1_qup6_i2c_apps_clk_src", 646 - .parent_names = gcc_parent_names_1, 647 - .num_parents = 3, 606 + .parent_data = gcc_parent_data_1, 607 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 648 608 .ops = &clk_rcg2_ops, 649 609 }, 650 610 }; ··· 657 617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 658 618 .clkr.hw.init = &(struct clk_init_data){ 659 619 .name = "blsp1_qup6_spi_apps_clk_src", 660 - .parent_names = gcc_parent_names_0, 661 - .num_parents = 4, 620 + .parent_data = gcc_parent_data_0, 621 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 662 622 .ops = &clk_rcg2_ops, 663 623 }, 664 624 }; ··· 690 650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 691 651 .clkr.hw.init = &(struct clk_init_data){ 692 652 .name = "blsp1_uart1_apps_clk_src", 693 - .parent_names = gcc_parent_names_0, 694 - .num_parents = 4, 653 + .parent_data = gcc_parent_data_0, 654 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 695 655 .ops = &clk_rcg2_ops, 696 656 }, 697 657 }; ··· 704 664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 705 665 .clkr.hw.init = &(struct clk_init_data){ 706 666 .name = "blsp1_uart2_apps_clk_src", 707 - .parent_names = gcc_parent_names_0, 708 - .num_parents = 4, 667 + .parent_data = gcc_parent_data_0, 668 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 709 669 .ops = &clk_rcg2_ops, 710 670 }, 711 671 }; ··· 718 678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 719 679 .clkr.hw.init = &(struct clk_init_data){ 720 680 .name = "blsp1_uart3_apps_clk_src", 721 - .parent_names = gcc_parent_names_0, 722 - .num_parents = 4, 681 + .parent_data = gcc_parent_data_0, 682 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 723 683 .ops = &clk_rcg2_ops, 724 684 }, 725 685 }; ··· 732 692 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 733 693 .clkr.hw.init = &(struct clk_init_data){ 734 694 .name = "blsp2_qup1_i2c_apps_clk_src", 735 - .parent_names = gcc_parent_names_1, 736 - .num_parents = 3, 695 + .parent_data = gcc_parent_data_1, 696 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 737 697 .ops = &clk_rcg2_ops, 738 698 }, 739 699 }; ··· 746 706 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 747 707 .clkr.hw.init = &(struct clk_init_data){ 748 708 .name = "blsp2_qup1_spi_apps_clk_src", 749 - .parent_names = gcc_parent_names_0, 750 - .num_parents = 4, 709 + .parent_data = gcc_parent_data_0, 710 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 751 711 .ops = &clk_rcg2_ops, 752 712 }, 753 713 }; ··· 760 720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 761 721 .clkr.hw.init = &(struct clk_init_data){ 762 722 .name = "blsp2_qup2_i2c_apps_clk_src", 763 - .parent_names = gcc_parent_names_1, 764 - .num_parents = 3, 723 + .parent_data = gcc_parent_data_1, 724 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 765 725 .ops = &clk_rcg2_ops, 766 726 }, 767 727 }; ··· 774 734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 775 735 .clkr.hw.init = &(struct clk_init_data){ 776 736 .name = "blsp2_qup2_spi_apps_clk_src", 777 - .parent_names = gcc_parent_names_0, 778 - .num_parents = 4, 737 + .parent_data = gcc_parent_data_0, 738 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 779 739 .ops = &clk_rcg2_ops, 780 740 }, 781 741 }; ··· 788 748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 789 749 .clkr.hw.init = &(struct clk_init_data){ 790 750 .name = "blsp2_qup3_i2c_apps_clk_src", 791 - .parent_names = gcc_parent_names_1, 792 - .num_parents = 3, 751 + .parent_data = gcc_parent_data_1, 752 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 793 753 .ops = &clk_rcg2_ops, 794 754 }, 795 755 }; ··· 802 762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 803 763 .clkr.hw.init = &(struct clk_init_data){ 804 764 .name = "blsp2_qup3_spi_apps_clk_src", 805 - .parent_names = gcc_parent_names_0, 806 - .num_parents = 4, 765 + .parent_data = gcc_parent_data_0, 766 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 807 767 .ops = &clk_rcg2_ops, 808 768 }, 809 769 }; ··· 816 776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 817 777 .clkr.hw.init = &(struct clk_init_data){ 818 778 .name = "blsp2_qup4_i2c_apps_clk_src", 819 - .parent_names = gcc_parent_names_1, 820 - .num_parents = 3, 779 + .parent_data = gcc_parent_data_1, 780 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 821 781 .ops = &clk_rcg2_ops, 822 782 }, 823 783 }; ··· 830 790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 831 791 .clkr.hw.init = &(struct clk_init_data){ 832 792 .name = "blsp2_qup4_spi_apps_clk_src", 833 - .parent_names = gcc_parent_names_0, 834 - .num_parents = 4, 793 + .parent_data = gcc_parent_data_0, 794 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 835 795 .ops = &clk_rcg2_ops, 836 796 }, 837 797 }; ··· 844 804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 845 805 .clkr.hw.init = &(struct clk_init_data){ 846 806 .name = "blsp2_qup5_i2c_apps_clk_src", 847 - .parent_names = gcc_parent_names_1, 848 - .num_parents = 3, 807 + .parent_data = gcc_parent_data_1, 808 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 849 809 .ops = &clk_rcg2_ops, 850 810 }, 851 811 }; ··· 858 818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 859 819 .clkr.hw.init = &(struct clk_init_data){ 860 820 .name = "blsp2_qup5_spi_apps_clk_src", 861 - .parent_names = gcc_parent_names_0, 862 - .num_parents = 4, 821 + .parent_data = gcc_parent_data_0, 822 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 863 823 .ops = &clk_rcg2_ops, 864 824 }, 865 825 }; ··· 872 832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 873 833 .clkr.hw.init = &(struct clk_init_data){ 874 834 .name = "blsp2_qup6_i2c_apps_clk_src", 875 - .parent_names = gcc_parent_names_1, 876 - .num_parents = 3, 835 + .parent_data = gcc_parent_data_1, 836 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 877 837 .ops = &clk_rcg2_ops, 878 838 }, 879 839 }; ··· 886 846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 887 847 .clkr.hw.init = &(struct clk_init_data){ 888 848 .name = "blsp2_qup6_spi_apps_clk_src", 889 - .parent_names = gcc_parent_names_0, 890 - .num_parents = 4, 849 + .parent_data = gcc_parent_data_0, 850 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 891 851 .ops = &clk_rcg2_ops, 892 852 }, 893 853 }; ··· 900 860 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 901 861 .clkr.hw.init = &(struct clk_init_data){ 902 862 .name = "blsp2_uart1_apps_clk_src", 903 - .parent_names = gcc_parent_names_0, 904 - .num_parents = 4, 863 + .parent_data = gcc_parent_data_0, 864 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 905 865 .ops = &clk_rcg2_ops, 906 866 }, 907 867 }; ··· 914 874 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 915 875 .clkr.hw.init = &(struct clk_init_data){ 916 876 .name = "blsp2_uart2_apps_clk_src", 917 - .parent_names = gcc_parent_names_0, 918 - .num_parents = 4, 877 + .parent_data = gcc_parent_data_0, 878 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 919 879 .ops = &clk_rcg2_ops, 920 880 }, 921 881 }; ··· 928 888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 929 889 .clkr.hw.init = &(struct clk_init_data){ 930 890 .name = "blsp2_uart3_apps_clk_src", 931 - .parent_names = gcc_parent_names_0, 932 - .num_parents = 4, 891 + .parent_data = gcc_parent_data_0, 892 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 933 893 .ops = &clk_rcg2_ops, 934 894 }, 935 895 }; ··· 949 909 .freq_tbl = ftbl_gp1_clk_src, 950 910 .clkr.hw.init = &(struct clk_init_data){ 951 911 .name = "gp1_clk_src", 952 - .parent_names = gcc_parent_names_2, 953 - .num_parents = 5, 912 + .parent_data = gcc_parent_data_2, 913 + .num_parents = ARRAY_SIZE(gcc_parent_data_2), 954 914 .ops = &clk_rcg2_ops, 955 915 }, 956 916 }; ··· 963 923 .freq_tbl = ftbl_gp1_clk_src, 964 924 .clkr.hw.init = &(struct clk_init_data){ 965 925 .name = "gp2_clk_src", 966 - .parent_names = gcc_parent_names_2, 967 - .num_parents = 5, 926 + .parent_data = gcc_parent_data_2, 927 + .num_parents = ARRAY_SIZE(gcc_parent_data_2), 968 928 .ops = &clk_rcg2_ops, 969 929 }, 970 930 }; ··· 977 937 .freq_tbl = ftbl_gp1_clk_src, 978 938 .clkr.hw.init = &(struct clk_init_data){ 979 939 .name = "gp3_clk_src", 980 - .parent_names = gcc_parent_names_2, 981 - .num_parents = 5, 940 + .parent_data = gcc_parent_data_2, 941 + .num_parents = ARRAY_SIZE(gcc_parent_data_2), 982 942 .ops = &clk_rcg2_ops, 983 943 }, 984 944 }; ··· 998 958 .freq_tbl = ftbl_hmss_ahb_clk_src, 999 959 .clkr.hw.init = &(struct clk_init_data){ 1000 960 .name = "hmss_ahb_clk_src", 1001 - .parent_names = gcc_parent_names_1, 1002 - .num_parents = 3, 961 + .parent_data = gcc_parent_data_1, 962 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1003 963 .ops = &clk_rcg2_ops, 1004 964 }, 1005 965 }; ··· 1017 977 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1018 978 .clkr.hw.init = &(struct clk_init_data){ 1019 979 .name = "hmss_rbcpr_clk_src", 1020 - .parent_names = gcc_parent_names_1, 1021 - .num_parents = 3, 980 + .parent_data = gcc_parent_data_1, 981 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1022 982 .ops = &clk_rcg2_ops, 1023 983 }, 1024 984 }; ··· 1036 996 .freq_tbl = ftbl_pcie_aux_clk_src, 1037 997 .clkr.hw.init = &(struct clk_init_data){ 1038 998 .name = "pcie_aux_clk_src", 1039 - .parent_names = gcc_parent_names_3, 1040 - .num_parents = 3, 999 + .parent_data = gcc_parent_data_3, 1000 + .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1041 1001 .ops = &clk_rcg2_ops, 1042 1002 }, 1043 1003 }; ··· 1055 1015 .freq_tbl = ftbl_pdm2_clk_src, 1056 1016 .clkr.hw.init = &(struct clk_init_data){ 1057 1017 .name = "pdm2_clk_src", 1058 - .parent_names = gcc_parent_names_1, 1059 - .num_parents = 3, 1018 + .parent_data = gcc_parent_data_1, 1019 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1060 1020 .ops = &clk_rcg2_ops, 1061 1021 }, 1062 1022 }; ··· 1080 1040 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1081 1041 .clkr.hw.init = &(struct clk_init_data){ 1082 1042 .name = "sdcc2_apps_clk_src", 1083 - .parent_names = gcc_parent_names_4, 1084 - .num_parents = 4, 1043 + .parent_data = gcc_parent_data_4, 1044 + .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1085 1045 .ops = &clk_rcg2_floor_ops, 1086 1046 }, 1087 1047 }; ··· 1104 1064 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1105 1065 .clkr.hw.init = &(struct clk_init_data){ 1106 1066 .name = "sdcc4_apps_clk_src", 1107 - .parent_names = gcc_parent_names_1, 1108 - .num_parents = 3, 1067 + .parent_data = gcc_parent_data_1, 1068 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1109 1069 .ops = &clk_rcg2_floor_ops, 1110 1070 }, 1111 1071 }; ··· 1123 1083 .freq_tbl = ftbl_tsif_ref_clk_src, 1124 1084 .clkr.hw.init = &(struct clk_init_data){ 1125 1085 .name = "tsif_ref_clk_src", 1126 - .parent_names = gcc_parent_names_5, 1127 - .num_parents = 4, 1086 + .parent_data = gcc_parent_data_5, 1087 + .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1128 1088 .ops = &clk_rcg2_ops, 1129 1089 }, 1130 1090 }; ··· 1144 1104 .freq_tbl = ftbl_ufs_axi_clk_src, 1145 1105 .clkr.hw.init = &(struct clk_init_data){ 1146 1106 .name = "ufs_axi_clk_src", 1147 - .parent_names = gcc_parent_names_0, 1148 - .num_parents = 4, 1107 + .parent_data = gcc_parent_data_0, 1108 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1149 1109 .ops = &clk_rcg2_ops, 1150 1110 }, 1151 1111 }; ··· 1165 1125 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 1166 1126 .clkr.hw.init = &(struct clk_init_data){ 1167 1127 .name = "ufs_unipro_core_clk_src", 1168 - .parent_names = gcc_parent_names_0, 1169 - .num_parents = 4, 1128 + .parent_data = gcc_parent_data_0, 1129 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1170 1130 .ops = &clk_rcg2_ops, 1171 1131 }, 1172 1132 }; ··· 1187 1147 .freq_tbl = ftbl_usb30_master_clk_src, 1188 1148 .clkr.hw.init = &(struct clk_init_data){ 1189 1149 .name = "usb30_master_clk_src", 1190 - .parent_names = gcc_parent_names_0, 1191 - .num_parents = 4, 1150 + .parent_data = gcc_parent_data_0, 1151 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1192 1152 .ops = &clk_rcg2_ops, 1193 1153 }, 1194 1154 }; ··· 1201 1161 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1202 1162 .clkr.hw.init = &(struct clk_init_data){ 1203 1163 .name = "usb30_mock_utmi_clk_src", 1204 - .parent_names = gcc_parent_names_0, 1205 - .num_parents = 4, 1164 + .parent_data = gcc_parent_data_0, 1165 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1206 1166 .ops = &clk_rcg2_ops, 1207 1167 }, 1208 1168 }; ··· 1220 1180 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1221 1181 .clkr.hw.init = &(struct clk_init_data){ 1222 1182 .name = "usb3_phy_aux_clk_src", 1223 - .parent_names = gcc_parent_names_3, 1224 - .num_parents = 3, 1183 + .parent_data = gcc_parent_data_3, 1184 + .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1225 1185 .ops = &clk_rcg2_ops, 1226 1186 }, 1227 1187 }; ··· 1247 1207 .enable_mask = BIT(0), 1248 1208 .hw.init = &(struct clk_init_data){ 1249 1209 .name = "gcc_aggre1_ufs_axi_clk", 1250 - .parent_names = (const char *[]){ 1251 - "ufs_axi_clk_src", 1210 + .parent_hws = (const struct clk_hw *[]) { 1211 + &ufs_axi_clk_src.clkr.hw, 1252 1212 }, 1253 1213 .num_parents = 1, 1254 1214 .flags = CLK_SET_RATE_PARENT, ··· 1265 1225 .enable_mask = BIT(0), 1266 1226 .hw.init = &(struct clk_init_data){ 1267 1227 .name = "gcc_aggre1_usb3_axi_clk", 1268 - .parent_names = (const char *[]){ 1269 - "usb30_master_clk_src", 1228 + .parent_hws = (const struct clk_hw *[]) { 1229 + &usb30_master_clk_src.clkr.hw, 1270 1230 }, 1271 1231 .num_parents = 1, 1272 1232 .flags = CLK_SET_RATE_PARENT, ··· 1388 1348 .enable_mask = BIT(1), 1389 1349 .hw.init = &(struct clk_init_data){ 1390 1350 .name = "gcc_mmss_gpll0_clk", 1391 - .parent_names = (const char *[]){ 1392 - "gpll0_out_main", 1351 + .parent_hws = (const struct clk_hw *[]) { 1352 + &gpll0_out_main.clkr.hw, 1393 1353 }, 1394 1354 .num_parents = 1, 1395 1355 .ops = &clk_branch2_ops, ··· 1430 1390 .enable_mask = BIT(0), 1431 1391 .hw.init = &(struct clk_init_data){ 1432 1392 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1433 - .parent_names = (const char *[]){ 1434 - "blsp1_qup1_i2c_apps_clk_src", 1393 + .parent_hws = (const struct clk_hw *[]) { 1394 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1435 1395 }, 1436 1396 .num_parents = 1, 1437 1397 .flags = CLK_SET_RATE_PARENT, ··· 1448 1408 .enable_mask = BIT(0), 1449 1409 .hw.init = &(struct clk_init_data){ 1450 1410 .name = "gcc_blsp1_qup1_spi_apps_clk", 1451 - .parent_names = (const char *[]){ 1452 - "blsp1_qup1_spi_apps_clk_src", 1411 + .parent_hws = (const struct clk_hw *[]) { 1412 + &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1453 1413 }, 1454 1414 .num_parents = 1, 1455 1415 .flags = CLK_SET_RATE_PARENT, ··· 1466 1426 .enable_mask = BIT(0), 1467 1427 .hw.init = &(struct clk_init_data){ 1468 1428 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1469 - .parent_names = (const char *[]){ 1470 - "blsp1_qup2_i2c_apps_clk_src", 1429 + .parent_hws = (const struct clk_hw *[]) { 1430 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1471 1431 }, 1472 1432 .num_parents = 1, 1473 1433 .flags = CLK_SET_RATE_PARENT, ··· 1484 1444 .enable_mask = BIT(0), 1485 1445 .hw.init = &(struct clk_init_data){ 1486 1446 .name = "gcc_blsp1_qup2_spi_apps_clk", 1487 - .parent_names = (const char *[]){ 1488 - "blsp1_qup2_spi_apps_clk_src", 1447 + .parent_hws = (const struct clk_hw *[]) { 1448 + &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1489 1449 }, 1490 1450 .num_parents = 1, 1491 1451 .flags = CLK_SET_RATE_PARENT, ··· 1502 1462 .enable_mask = BIT(0), 1503 1463 .hw.init = &(struct clk_init_data){ 1504 1464 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1505 - .parent_names = (const char *[]){ 1506 - "blsp1_qup3_i2c_apps_clk_src", 1465 + .parent_hws = (const struct clk_hw *[]) { 1466 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1507 1467 }, 1508 1468 .num_parents = 1, 1509 1469 .flags = CLK_SET_RATE_PARENT, ··· 1520 1480 .enable_mask = BIT(0), 1521 1481 .hw.init = &(struct clk_init_data){ 1522 1482 .name = "gcc_blsp1_qup3_spi_apps_clk", 1523 - .parent_names = (const char *[]){ 1524 - "blsp1_qup3_spi_apps_clk_src", 1483 + .parent_hws = (const struct clk_hw *[]) { 1484 + &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1525 1485 }, 1526 1486 .num_parents = 1, 1527 1487 .flags = CLK_SET_RATE_PARENT, ··· 1538 1498 .enable_mask = BIT(0), 1539 1499 .hw.init = &(struct clk_init_data){ 1540 1500 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1541 - .parent_names = (const char *[]){ 1542 - "blsp1_qup4_i2c_apps_clk_src", 1501 + .parent_hws = (const struct clk_hw *[]) { 1502 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1543 1503 }, 1544 1504 .num_parents = 1, 1545 1505 .flags = CLK_SET_RATE_PARENT, ··· 1556 1516 .enable_mask = BIT(0), 1557 1517 .hw.init = &(struct clk_init_data){ 1558 1518 .name = "gcc_blsp1_qup4_spi_apps_clk", 1559 - .parent_names = (const char *[]){ 1560 - "blsp1_qup4_spi_apps_clk_src", 1519 + .parent_hws = (const struct clk_hw *[]) { 1520 + &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1561 1521 }, 1562 1522 .num_parents = 1, 1563 1523 .flags = CLK_SET_RATE_PARENT, ··· 1574 1534 .enable_mask = BIT(0), 1575 1535 .hw.init = &(struct clk_init_data){ 1576 1536 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1577 - .parent_names = (const char *[]){ 1578 - "blsp1_qup5_i2c_apps_clk_src", 1537 + .parent_hws = (const struct clk_hw *[]) { 1538 + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1579 1539 }, 1580 1540 .num_parents = 1, 1581 1541 .flags = CLK_SET_RATE_PARENT, ··· 1592 1552 .enable_mask = BIT(0), 1593 1553 .hw.init = &(struct clk_init_data){ 1594 1554 .name = "gcc_blsp1_qup5_spi_apps_clk", 1595 - .parent_names = (const char *[]){ 1596 - "blsp1_qup5_spi_apps_clk_src", 1555 + .parent_hws = (const struct clk_hw *[]) { 1556 + &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1597 1557 }, 1598 1558 .num_parents = 1, 1599 1559 .flags = CLK_SET_RATE_PARENT, ··· 1610 1570 .enable_mask = BIT(0), 1611 1571 .hw.init = &(struct clk_init_data){ 1612 1572 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1613 - .parent_names = (const char *[]){ 1614 - "blsp1_qup6_i2c_apps_clk_src", 1573 + .parent_hws = (const struct clk_hw *[]) { 1574 + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1615 1575 }, 1616 1576 .num_parents = 1, 1617 1577 .flags = CLK_SET_RATE_PARENT, ··· 1628 1588 .enable_mask = BIT(0), 1629 1589 .hw.init = &(struct clk_init_data){ 1630 1590 .name = "gcc_blsp1_qup6_spi_apps_clk", 1631 - .parent_names = (const char *[]){ 1632 - "blsp1_qup6_spi_apps_clk_src", 1591 + .parent_hws = (const struct clk_hw *[]) { 1592 + &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1633 1593 }, 1634 1594 .num_parents = 1, 1635 1595 .flags = CLK_SET_RATE_PARENT, ··· 1659 1619 .enable_mask = BIT(0), 1660 1620 .hw.init = &(struct clk_init_data){ 1661 1621 .name = "gcc_blsp1_uart1_apps_clk", 1662 - .parent_names = (const char *[]){ 1663 - "blsp1_uart1_apps_clk_src", 1622 + .parent_hws = (const struct clk_hw *[]) { 1623 + &blsp1_uart1_apps_clk_src.clkr.hw, 1664 1624 }, 1665 1625 .num_parents = 1, 1666 1626 .flags = CLK_SET_RATE_PARENT, ··· 1677 1637 .enable_mask = BIT(0), 1678 1638 .hw.init = &(struct clk_init_data){ 1679 1639 .name = "gcc_blsp1_uart2_apps_clk", 1680 - .parent_names = (const char *[]){ 1681 - "blsp1_uart2_apps_clk_src", 1640 + .parent_hws = (const struct clk_hw *[]) { 1641 + &blsp1_uart2_apps_clk_src.clkr.hw, 1682 1642 }, 1683 1643 .num_parents = 1, 1684 1644 .flags = CLK_SET_RATE_PARENT, ··· 1695 1655 .enable_mask = BIT(0), 1696 1656 .hw.init = &(struct clk_init_data){ 1697 1657 .name = "gcc_blsp1_uart3_apps_clk", 1698 - .parent_names = (const char *[]){ 1699 - "blsp1_uart3_apps_clk_src", 1658 + .parent_hws = (const struct clk_hw *[]) { 1659 + &blsp1_uart3_apps_clk_src.clkr.hw, 1700 1660 }, 1701 1661 .num_parents = 1, 1702 1662 .flags = CLK_SET_RATE_PARENT, ··· 1726 1686 .enable_mask = BIT(0), 1727 1687 .hw.init = &(struct clk_init_data){ 1728 1688 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1729 - .parent_names = (const char *[]){ 1730 - "blsp2_qup1_i2c_apps_clk_src", 1689 + .parent_hws = (const struct clk_hw *[]) { 1690 + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1731 1691 }, 1732 1692 .num_parents = 1, 1733 1693 .flags = CLK_SET_RATE_PARENT, ··· 1744 1704 .enable_mask = BIT(0), 1745 1705 .hw.init = &(struct clk_init_data){ 1746 1706 .name = "gcc_blsp2_qup1_spi_apps_clk", 1747 - .parent_names = (const char *[]){ 1748 - "blsp2_qup1_spi_apps_clk_src", 1707 + .parent_hws = (const struct clk_hw *[]) { 1708 + &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1749 1709 }, 1750 1710 .num_parents = 1, 1751 1711 .flags = CLK_SET_RATE_PARENT, ··· 1762 1722 .enable_mask = BIT(0), 1763 1723 .hw.init = &(struct clk_init_data){ 1764 1724 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1765 - .parent_names = (const char *[]){ 1766 - "blsp2_qup2_i2c_apps_clk_src", 1725 + .parent_hws = (const struct clk_hw *[]) { 1726 + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1767 1727 }, 1768 1728 .num_parents = 1, 1769 1729 .flags = CLK_SET_RATE_PARENT, ··· 1780 1740 .enable_mask = BIT(0), 1781 1741 .hw.init = &(struct clk_init_data){ 1782 1742 .name = "gcc_blsp2_qup2_spi_apps_clk", 1783 - .parent_names = (const char *[]){ 1784 - "blsp2_qup2_spi_apps_clk_src", 1743 + .parent_hws = (const struct clk_hw *[]) { 1744 + &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1785 1745 }, 1786 1746 .num_parents = 1, 1787 1747 .flags = CLK_SET_RATE_PARENT, ··· 1798 1758 .enable_mask = BIT(0), 1799 1759 .hw.init = &(struct clk_init_data){ 1800 1760 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1801 - .parent_names = (const char *[]){ 1802 - "blsp2_qup3_i2c_apps_clk_src", 1761 + .parent_hws = (const struct clk_hw *[]) { 1762 + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1803 1763 }, 1804 1764 .num_parents = 1, 1805 1765 .flags = CLK_SET_RATE_PARENT, ··· 1816 1776 .enable_mask = BIT(0), 1817 1777 .hw.init = &(struct clk_init_data){ 1818 1778 .name = "gcc_blsp2_qup3_spi_apps_clk", 1819 - .parent_names = (const char *[]){ 1820 - "blsp2_qup3_spi_apps_clk_src", 1779 + .parent_hws = (const struct clk_hw *[]) { 1780 + &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1821 1781 }, 1822 1782 .num_parents = 1, 1823 1783 .flags = CLK_SET_RATE_PARENT, ··· 1834 1794 .enable_mask = BIT(0), 1835 1795 .hw.init = &(struct clk_init_data){ 1836 1796 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1837 - .parent_names = (const char *[]){ 1838 - "blsp2_qup4_i2c_apps_clk_src", 1797 + .parent_hws = (const struct clk_hw *[]) { 1798 + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1839 1799 }, 1840 1800 .num_parents = 1, 1841 1801 .flags = CLK_SET_RATE_PARENT, ··· 1852 1812 .enable_mask = BIT(0), 1853 1813 .hw.init = &(struct clk_init_data){ 1854 1814 .name = "gcc_blsp2_qup4_spi_apps_clk", 1855 - .parent_names = (const char *[]){ 1856 - "blsp2_qup4_spi_apps_clk_src", 1815 + .parent_hws = (const struct clk_hw *[]) { 1816 + &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1857 1817 }, 1858 1818 .num_parents = 1, 1859 1819 .flags = CLK_SET_RATE_PARENT, ··· 1870 1830 .enable_mask = BIT(0), 1871 1831 .hw.init = &(struct clk_init_data){ 1872 1832 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1873 - .parent_names = (const char *[]){ 1874 - "blsp2_qup5_i2c_apps_clk_src", 1833 + .parent_hws = (const struct clk_hw *[]) { 1834 + &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1875 1835 }, 1876 1836 .num_parents = 1, 1877 1837 .flags = CLK_SET_RATE_PARENT, ··· 1888 1848 .enable_mask = BIT(0), 1889 1849 .hw.init = &(struct clk_init_data){ 1890 1850 .name = "gcc_blsp2_qup5_spi_apps_clk", 1891 - .parent_names = (const char *[]){ 1892 - "blsp2_qup5_spi_apps_clk_src", 1851 + .parent_hws = (const struct clk_hw *[]) { 1852 + &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1893 1853 }, 1894 1854 .num_parents = 1, 1895 1855 .flags = CLK_SET_RATE_PARENT, ··· 1906 1866 .enable_mask = BIT(0), 1907 1867 .hw.init = &(struct clk_init_data){ 1908 1868 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1909 - .parent_names = (const char *[]){ 1910 - "blsp2_qup6_i2c_apps_clk_src", 1869 + .parent_hws = (const struct clk_hw *[]) { 1870 + &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1911 1871 }, 1912 1872 .num_parents = 1, 1913 1873 .flags = CLK_SET_RATE_PARENT, ··· 1924 1884 .enable_mask = BIT(0), 1925 1885 .hw.init = &(struct clk_init_data){ 1926 1886 .name = "gcc_blsp2_qup6_spi_apps_clk", 1927 - .parent_names = (const char *[]){ 1928 - "blsp2_qup6_spi_apps_clk_src", 1887 + .parent_hws = (const struct clk_hw *[]) { 1888 + &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1929 1889 }, 1930 1890 .num_parents = 1, 1931 1891 .flags = CLK_SET_RATE_PARENT, ··· 1955 1915 .enable_mask = BIT(0), 1956 1916 .hw.init = &(struct clk_init_data){ 1957 1917 .name = "gcc_blsp2_uart1_apps_clk", 1958 - .parent_names = (const char *[]){ 1959 - "blsp2_uart1_apps_clk_src", 1918 + .parent_hws = (const struct clk_hw *[]) { 1919 + &blsp2_uart1_apps_clk_src.clkr.hw, 1960 1920 }, 1961 1921 .num_parents = 1, 1962 1922 .flags = CLK_SET_RATE_PARENT, ··· 1973 1933 .enable_mask = BIT(0), 1974 1934 .hw.init = &(struct clk_init_data){ 1975 1935 .name = "gcc_blsp2_uart2_apps_clk", 1976 - .parent_names = (const char *[]){ 1977 - "blsp2_uart2_apps_clk_src", 1936 + .parent_hws = (const struct clk_hw *[]) { 1937 + &blsp2_uart2_apps_clk_src.clkr.hw, 1978 1938 }, 1979 1939 .num_parents = 1, 1980 1940 .flags = CLK_SET_RATE_PARENT, ··· 1991 1951 .enable_mask = BIT(0), 1992 1952 .hw.init = &(struct clk_init_data){ 1993 1953 .name = "gcc_blsp2_uart3_apps_clk", 1994 - .parent_names = (const char *[]){ 1995 - "blsp2_uart3_apps_clk_src", 1954 + .parent_hws = (const struct clk_hw *[]) { 1955 + &blsp2_uart3_apps_clk_src.clkr.hw, 1996 1956 }, 1997 1957 .num_parents = 1, 1998 1958 .flags = CLK_SET_RATE_PARENT, ··· 2009 1969 .enable_mask = BIT(0), 2010 1970 .hw.init = &(struct clk_init_data){ 2011 1971 .name = "gcc_cfg_noc_usb3_axi_clk", 2012 - .parent_names = (const char *[]){ 2013 - "usb30_master_clk_src", 1972 + .parent_hws = (const struct clk_hw *[]) { 1973 + &usb30_master_clk_src.clkr.hw, 2014 1974 }, 2015 1975 .num_parents = 1, 2016 1976 .flags = CLK_SET_RATE_PARENT, ··· 2027 1987 .enable_mask = BIT(0), 2028 1988 .hw.init = &(struct clk_init_data){ 2029 1989 .name = "gcc_gp1_clk", 2030 - .parent_names = (const char *[]){ 2031 - "gp1_clk_src", 1990 + .parent_hws = (const struct clk_hw *[]) { 1991 + &gp1_clk_src.clkr.hw, 2032 1992 }, 2033 1993 .num_parents = 1, 2034 1994 .flags = CLK_SET_RATE_PARENT, ··· 2045 2005 .enable_mask = BIT(0), 2046 2006 .hw.init = &(struct clk_init_data){ 2047 2007 .name = "gcc_gp2_clk", 2048 - .parent_names = (const char *[]){ 2049 - "gp2_clk_src", 2008 + .parent_hws = (const struct clk_hw *[]) { 2009 + &gp2_clk_src.clkr.hw, 2050 2010 }, 2051 2011 .num_parents = 1, 2052 2012 .flags = CLK_SET_RATE_PARENT, ··· 2063 2023 .enable_mask = BIT(0), 2064 2024 .hw.init = &(struct clk_init_data){ 2065 2025 .name = "gcc_gp3_clk", 2066 - .parent_names = (const char *[]){ 2067 - "gp3_clk_src", 2026 + .parent_hws = (const struct clk_hw *[]) { 2027 + &gp3_clk_src.clkr.hw, 2068 2028 }, 2069 2029 .num_parents = 1, 2070 2030 .flags = CLK_SET_RATE_PARENT, ··· 2152 2112 .enable_mask = BIT(21), 2153 2113 .hw.init = &(struct clk_init_data){ 2154 2114 .name = "gcc_hmss_ahb_clk", 2155 - .parent_names = (const char *[]){ 2156 - "hmss_ahb_clk_src", 2115 + .parent_hws = (const struct clk_hw *[]) { 2116 + &hmss_ahb_clk_src.clkr.hw, 2157 2117 }, 2158 2118 .num_parents = 1, 2159 2119 .flags = CLK_SET_RATE_PARENT, ··· 2183 2143 .enable_mask = BIT(0), 2184 2144 .hw.init = &(struct clk_init_data){ 2185 2145 .name = "gcc_hmss_rbcpr_clk", 2186 - .parent_names = (const char *[]){ 2187 - "hmss_rbcpr_clk_src", 2146 + .parent_hws = (const struct clk_hw *[]) { 2147 + &hmss_rbcpr_clk_src.clkr.hw, 2188 2148 }, 2189 2149 .num_parents = 1, 2190 2150 .flags = CLK_SET_RATE_PARENT, ··· 2219 2179 .freq_tbl = ftbl_hmss_gpll0_clk_src, 2220 2180 .clkr.hw.init = &(struct clk_init_data) { 2221 2181 .name = "hmss_gpll0_clk_src", 2222 - .parent_names = gcc_parent_names_1, 2223 - .num_parents = ARRAY_SIZE(gcc_parent_names_1), 2182 + .parent_data = gcc_parent_data_1, 2183 + .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2224 2184 .ops = &clk_rcg2_ops, 2225 2185 }, 2226 2186 }; ··· 2304 2264 .enable_mask = BIT(0), 2305 2265 .hw.init = &(struct clk_init_data){ 2306 2266 .name = "gcc_pcie_0_aux_clk", 2307 - .parent_names = (const char *[]){ 2308 - "pcie_aux_clk_src", 2267 + .parent_hws = (const struct clk_hw *[]) { 2268 + &pcie_aux_clk_src.clkr.hw, 2309 2269 }, 2310 2270 .num_parents = 1, 2311 2271 .flags = CLK_SET_RATE_PARENT, ··· 2374 2334 .enable_mask = BIT(0), 2375 2335 .hw.init = &(struct clk_init_data){ 2376 2336 .name = "gcc_pcie_phy_aux_clk", 2377 - .parent_names = (const char *[]){ 2378 - "pcie_aux_clk_src", 2337 + .parent_hws = (const struct clk_hw *[]) { 2338 + &pcie_aux_clk_src.clkr.hw, 2379 2339 }, 2380 2340 .num_parents = 1, 2381 2341 .flags = CLK_SET_RATE_PARENT, ··· 2392 2352 .enable_mask = BIT(0), 2393 2353 .hw.init = &(struct clk_init_data){ 2394 2354 .name = "gcc_pdm2_clk", 2395 - .parent_names = (const char *[]){ 2396 - "pdm2_clk_src", 2355 + .parent_hws = (const struct clk_hw *[]) { 2356 + &pdm2_clk_src.clkr.hw, 2397 2357 }, 2398 2358 .num_parents = 1, 2399 2359 .flags = CLK_SET_RATE_PARENT, ··· 2462 2422 .enable_mask = BIT(0), 2463 2423 .hw.init = &(struct clk_init_data){ 2464 2424 .name = "gcc_sdcc2_apps_clk", 2465 - .parent_names = (const char *[]){ 2466 - "sdcc2_apps_clk_src", 2425 + .parent_hws = (const struct clk_hw *[]) { 2426 + &sdcc2_apps_clk_src.clkr.hw, 2467 2427 }, 2468 2428 .num_parents = 1, 2469 2429 .flags = CLK_SET_RATE_PARENT, ··· 2493 2453 .enable_mask = BIT(0), 2494 2454 .hw.init = &(struct clk_init_data){ 2495 2455 .name = "gcc_sdcc4_apps_clk", 2496 - .parent_names = (const char *[]){ 2497 - "sdcc4_apps_clk_src", 2456 + .parent_hws = (const struct clk_hw *[]) { 2457 + &sdcc4_apps_clk_src.clkr.hw, 2498 2458 }, 2499 2459 .num_parents = 1, 2500 2460 .flags = CLK_SET_RATE_PARENT, ··· 2537 2497 .enable_mask = BIT(0), 2538 2498 .hw.init = &(struct clk_init_data){ 2539 2499 .name = "gcc_tsif_ref_clk", 2540 - .parent_names = (const char *[]){ 2541 - "tsif_ref_clk_src", 2500 + .parent_hws = (const struct clk_hw *[]) { 2501 + &tsif_ref_clk_src.clkr.hw, 2542 2502 }, 2543 2503 .num_parents = 1, 2544 2504 .flags = CLK_SET_RATE_PARENT, ··· 2568 2528 .enable_mask = BIT(0), 2569 2529 .hw.init = &(struct clk_init_data){ 2570 2530 .name = "gcc_ufs_axi_clk", 2571 - .parent_names = (const char *[]){ 2572 - "ufs_axi_clk_src", 2531 + .parent_hws = (const struct clk_hw *[]) { 2532 + &ufs_axi_clk_src.clkr.hw, 2573 2533 }, 2574 2534 .num_parents = 1, 2575 2535 .flags = CLK_SET_RATE_PARENT, ··· 2651 2611 .enable_mask = BIT(0), 2652 2612 .hw.init = &(struct clk_init_data){ 2653 2613 .name = "gcc_ufs_unipro_core_clk", 2654 - .parent_names = (const char *[]){ 2655 - "ufs_unipro_core_clk_src", 2614 + .parent_hws = (const struct clk_hw *[]) { 2615 + &ufs_unipro_core_clk_src.clkr.hw, 2656 2616 }, 2657 2617 .num_parents = 1, 2658 2618 .flags = CLK_SET_RATE_PARENT, ··· 2669 2629 .enable_mask = BIT(0), 2670 2630 .hw.init = &(struct clk_init_data){ 2671 2631 .name = "gcc_usb30_master_clk", 2672 - .parent_names = (const char *[]){ 2673 - "usb30_master_clk_src", 2632 + .parent_hws = (const struct clk_hw *[]) { 2633 + &usb30_master_clk_src.clkr.hw, 2674 2634 }, 2675 2635 .num_parents = 1, 2676 2636 .flags = CLK_SET_RATE_PARENT, ··· 2687 2647 .enable_mask = BIT(0), 2688 2648 .hw.init = &(struct clk_init_data){ 2689 2649 .name = "gcc_usb30_mock_utmi_clk", 2690 - .parent_names = (const char *[]){ 2691 - "usb30_mock_utmi_clk_src", 2650 + .parent_hws = (const struct clk_hw *[]) { 2651 + &usb30_mock_utmi_clk_src.clkr.hw, 2692 2652 }, 2693 2653 .num_parents = 1, 2694 2654 .flags = CLK_SET_RATE_PARENT, ··· 2718 2678 .enable_mask = BIT(0), 2719 2679 .hw.init = &(struct clk_init_data){ 2720 2680 .name = "gcc_usb3_phy_aux_clk", 2721 - .parent_names = (const char *[]){ 2722 - "usb3_phy_aux_clk_src", 2681 + .parent_hws = (const struct clk_hw *[]) { 2682 + &usb3_phy_aux_clk_src.clkr.hw, 2723 2683 }, 2724 2684 .num_parents = 1, 2725 2685 .flags = CLK_SET_RATE_PARENT,