Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"I've been sitting on some of these fixes for a while.
- Corner case of returning to delay slot from interrupt
- Changing default interrupt prioiry level
- Kconfig'ize support for super pages
- Other minor fixes"
* tag 'arc-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: mm: Introduce explicit super page size support
ARCv2: intc: Allow interruption by lowest priority interrupt
ARCv2: Check for LL-SC livelock only if LLSC is enabled
ARC: shrink cpuinfo by not saving full timer BCR
ARCv2: clocksource: Rename GRTC -> GFRC ...
ARCv2: STAR 9000950267: Handle return from intr to Delay Slot #2
+119
-61
+20
-1
arch/arc/Kconfig
+20
-1
arch/arc/Kconfig
···
338
338
339
339
endchoice
340
340
341
+
choice
342
+
prompt "MMU Super Page Size"
343
+
depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
344
+
default ARC_HUGEPAGE_2M
345
+
346
+
config ARC_HUGEPAGE_2M
347
+
bool "2MB"
348
+
349
+
config ARC_HUGEPAGE_16M
350
+
bool "16MB"
351
+
352
+
endchoice
353
+
341
354
if ISA_ARCOMPACT
342
355
343
356
config ARC_COMPACT_IRQ_LEVELS
···
423
410
default n
424
411
depends on !SMP
425
412
426
-
config ARC_HAS_GRTC
413
+
config ARC_HAS_GFRC
427
414
bool "SMP synchronized 64-bit cycle counter"
428
415
default y
429
416
depends on SMP
···
579
566
endmenu # "ARC Architecture Configuration"
580
567
581
568
source "mm/Kconfig"
569
+
570
+
config FORCE_MAX_ZONEORDER
571
+
int "Maximum zone order"
572
+
default "12" if ARC_HUGEPAGE_16M
573
+
default "11"
574
+
582
575
source "net/Kconfig"
583
576
source "drivers/Kconfig"
584
577
source "fs/Kconfig"
+1
-1
arch/arc/configs/vdk_hs38_smp_defconfig
+1
-1
arch/arc/configs/vdk_hs38_smp_defconfig
+1
-2
arch/arc/include/asm/arcregs.h
+1
-2
arch/arc/include/asm/arcregs.h
···
349
349
struct cpuinfo_arc_bpu bpu;
350
350
struct bcr_identity core;
351
351
struct bcr_isa isa;
352
-
struct bcr_timer timers;
353
352
unsigned int vec_base;
354
353
struct cpuinfo_arc_ccm iccm, dccm;
355
354
struct {
356
355
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
357
356
fpu_sp:1, fpu_dp:1, pad2:6,
358
357
debug:1, ap:1, smart:1, rtt:1, pad3:4,
359
-
pad4:8;
358
+
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
360
359
} extn;
361
360
struct bcr_mpy extn_mpy;
362
361
struct bcr_extn_xymem extn_xymem;
+5
-2
arch/arc/include/asm/irqflags-arcv2.h
+5
-2
arch/arc/include/asm/irqflags-arcv2.h
···
30
30
/* Was Intr taken in User Mode */
31
31
#define AUX_IRQ_ACT_BIT_U 31
32
32
33
-
/* 0 is highest level, but taken by FIRQs, if present in design */
34
-
#define ARCV2_IRQ_DEF_PRIO 0
33
+
/*
34
+
* User space should be interruptable even by lowest prio interrupt
35
+
* Safe even if actual interrupt priorities is fewer or even one
36
+
*/
37
+
#define ARCV2_IRQ_DEF_PRIO 15
35
38
36
39
/* seed value for status register */
37
40
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
+2
-2
arch/arc/include/asm/mcip.h
+2
-2
arch/arc/include/asm/mcip.h
···
39
39
#define CMD_DEBUG_SET_MASK 0x34
40
40
#define CMD_DEBUG_SET_SELECT 0x36
41
41
42
-
#define CMD_GRTC_READ_LO 0x42
43
-
#define CMD_GRTC_READ_HI 0x43
42
+
#define CMD_GFRC_READ_LO 0x42
43
+
#define CMD_GFRC_READ_HI 0x43
44
44
45
45
#define CMD_IDU_ENABLE 0x71
46
46
#define CMD_IDU_DISABLE 0x72
+26
-19
arch/arc/include/asm/pgtable.h
+26
-19
arch/arc/include/asm/pgtable.h
···
179
179
#define __S111 PAGE_U_X_W_R
180
180
181
181
/****************************************************************
182
-
* Page Table Lookup split
182
+
* 2 tier (PGD:PTE) software page walker
183
183
*
184
-
* We implement 2 tier paging and since this is all software, we are free
185
-
* to customize the span of a PGD / PTE entry to suit us
186
-
*
187
-
* 32 bit virtual address
184
+
* [31] 32 bit virtual address [0]
188
185
* -------------------------------------------------------
189
-
* | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE |
186
+
* | | <------------ PGDIR_SHIFT ----------> |
187
+
* | | |
188
+
* | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
190
189
* -------------------------------------------------------
191
190
* | | |
192
191
* | | --> off in page frame
193
-
* | |
194
192
* | ---> index into Page Table
195
-
* |
196
193
* ----> index into Page Directory
194
+
*
195
+
* In a single page size configuration, only PAGE_SHIFT is fixed
196
+
* So both PGD and PTE sizing can be tweaked
197
+
* e.g. 8K page (PAGE_SHIFT 13) can have
198
+
* - PGDIR_SHIFT 21 -> 11:8:13 address split
199
+
* - PGDIR_SHIFT 24 -> 8:11:13 address split
200
+
*
201
+
* If Super Page is configured, PGDIR_SHIFT becomes fixed too,
202
+
* so the sizing flexibility is gone.
197
203
*/
198
204
199
-
#define BITS_IN_PAGE PAGE_SHIFT
200
-
201
-
/* Optimal Sizing of Pg Tbl - based on MMU page size */
202
-
#if defined(CONFIG_ARC_PAGE_SIZE_8K)
203
-
#define BITS_FOR_PTE 8 /* 11:8:13 */
204
-
#elif defined(CONFIG_ARC_PAGE_SIZE_16K)
205
-
#define BITS_FOR_PTE 8 /* 10:8:14 */
206
-
#elif defined(CONFIG_ARC_PAGE_SIZE_4K)
207
-
#define BITS_FOR_PTE 9 /* 11:9:12 */
205
+
#if defined(CONFIG_ARC_HUGEPAGE_16M)
206
+
#define PGDIR_SHIFT 24
207
+
#elif defined(CONFIG_ARC_HUGEPAGE_2M)
208
+
#define PGDIR_SHIFT 21
209
+
#else
210
+
/*
211
+
* Only Normal page support so "hackable" (see comment above)
212
+
* Default value provides 11:8:13 (8K), 11:9:12 (4K)
213
+
*/
214
+
#define PGDIR_SHIFT 21
208
215
#endif
209
216
210
-
#define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE)
217
+
#define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
218
+
#define BITS_FOR_PGD (32 - PGDIR_SHIFT)
211
219
212
-
#define PGDIR_SHIFT (32 - BITS_FOR_PGD)
213
220
#define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */
214
221
#define PGDIR_MASK (~(PGDIR_SIZE-1))
215
222
+18
-1
arch/arc/kernel/entry-arcv2.S
+18
-1
arch/arc/kernel/entry-arcv2.S
···
211
211
; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
212
212
; entry was via Exception in DS which got preempted in kernel).
213
213
;
214
-
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling
214
+
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
215
+
;
216
+
; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
217
+
; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
218
+
215
219
.Lintr_ret_to_delay_slot:
216
220
debug_marker_ds:
217
221
···
226
222
ld r2, [sp, PT_ret]
227
223
ld r3, [sp, PT_status32]
228
224
225
+
; STAT32 for Int return created from scratch
226
+
; (No delay dlot, disable Further intr in trampoline)
227
+
229
228
bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
230
229
st r0, [sp, PT_status32]
231
230
232
231
mov r1, .Lintr_ret_to_delay_slot_2
233
232
st r1, [sp, PT_ret]
234
233
234
+
; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
235
235
st r2, [sp, 0]
236
236
st r3, [sp, 4]
237
237
238
238
b .Lisr_ret_fast_path
239
239
240
240
.Lintr_ret_to_delay_slot_2:
241
+
; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
241
242
sub sp, sp, SZ_PT_REGS
242
243
st r9, [sp, -4]
243
244
···
252
243
ld r9, [sp, 4]
253
244
sr r9, [erstatus]
254
245
246
+
; restore AUX_USER_SP if returning to U mode
247
+
bbit0 r9, STATUS_U_BIT, 1f
248
+
ld r9, [sp, PT_sp]
249
+
sr r9, [AUX_USER_SP]
250
+
251
+
1:
255
252
ld r9, [sp, 8]
256
253
sr r9, [erbta]
257
254
258
255
ld r9, [sp, -4]
259
256
add sp, sp, SZ_PT_REGS
257
+
258
+
; return from pure kernel mode to delay slot
260
259
rtie
261
260
262
261
END(ret_from_exception)
+24
-17
arch/arc/kernel/intc-arcv2.c
+24
-17
arch/arc/kernel/intc-arcv2.c
···
14
14
#include <linux/irqchip.h>
15
15
#include <asm/irq.h>
16
16
17
+
static int irq_prio;
18
+
17
19
/*
18
20
* Early Hardware specific Interrupt setup
19
21
* -Called very early (start_kernel -> setup_arch -> setup_processor)
···
25
23
void arc_init_IRQ(void)
26
24
{
27
25
unsigned int tmp;
26
+
27
+
struct irq_build {
28
+
#ifdef CONFIG_CPU_BIG_ENDIAN
29
+
unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
30
+
#else
31
+
unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
32
+
#endif
33
+
} irq_bcr;
28
34
29
35
struct aux_irq_ctrl {
30
36
#ifdef CONFIG_CPU_BIG_ENDIAN
···
56
46
57
47
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
58
48
59
-
/* setup status32, don't enable intr yet as kernel doesn't want */
60
-
tmp = read_aux_reg(0xa);
61
-
tmp |= ISA_INIT_STATUS_BITS;
62
-
tmp &= ~STATUS_IE_MASK;
63
-
asm volatile("flag %0 \n"::"r"(tmp));
64
-
65
49
/*
66
50
* ARCv2 core intc provides multiple interrupt priorities (upto 16).
67
51
* Typical builds though have only two levels (0-high, 1-low)
68
52
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
69
53
* NMI style interrupts in future (say perf)
70
-
*
71
-
* Read the intc BCR to confirm that Linux default priority is avail
72
-
* in h/w
73
-
*
74
-
* Note:
75
-
* IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
76
-
* is 0 based.
77
54
*/
78
-
tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
79
-
if (ARCV2_IRQ_DEF_PRIO > tmp)
80
-
panic("Linux default irq prio incorrect\n");
55
+
56
+
READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
57
+
58
+
irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
59
+
pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
60
+
irq_prio + 1, irq_prio,
61
+
irq_bcr.firq ? " FIRQ (not used)":"");
62
+
63
+
/* setup status32, don't enable intr yet as kernel doesn't want */
64
+
tmp = read_aux_reg(0xa);
65
+
tmp |= STATUS_AD_MASK | (irq_prio << 1);
66
+
tmp &= ~STATUS_IE_MASK;
67
+
asm volatile("flag %0 \n"::"r"(tmp));
81
68
}
82
69
83
70
static void arcv2_irq_mask(struct irq_data *data)
···
93
86
{
94
87
/* set default priority */
95
88
write_aux_reg(AUX_IRQ_SELECT, data->irq);
96
-
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
89
+
write_aux_reg(AUX_IRQ_PRIORITY, irq_prio);
97
90
98
91
/*
99
92
* hw auto enables (linux unmask) all by default
+5
-5
arch/arc/kernel/mcip.c
+5
-5
arch/arc/kernel/mcip.c
···
96
96
#ifdef CONFIG_CPU_BIG_ENDIAN
97
97
unsigned int pad3:8,
98
98
idu:1, llm:1, num_cores:6,
99
-
iocoh:1, grtc:1, dbg:1, pad2:1,
99
+
iocoh:1, gfrc:1, dbg:1, pad2:1,
100
100
msg:1, sem:1, ipi:1, pad:1,
101
101
ver:8;
102
102
#else
103
103
unsigned int ver:8,
104
104
pad:1, ipi:1, sem:1, msg:1,
105
-
pad2:1, dbg:1, grtc:1, iocoh:1,
105
+
pad2:1, dbg:1, gfrc:1, iocoh:1,
106
106
num_cores:6, llm:1, idu:1,
107
107
pad3:8;
108
108
#endif
···
116
116
IS_AVAIL1(mp.ipi, "IPI "),
117
117
IS_AVAIL1(mp.idu, "IDU "),
118
118
IS_AVAIL1(mp.dbg, "DEBUG "),
119
-
IS_AVAIL1(mp.grtc, "GRTC"));
119
+
IS_AVAIL1(mp.gfrc, "GFRC"));
120
120
121
121
idu_detected = mp.idu;
122
122
···
125
125
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
126
126
}
127
127
128
-
if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
129
-
panic("kernel trying to use non-existent GRTC\n");
128
+
if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
129
+
panic("kernel trying to use non-existent GFRC\n");
130
130
}
131
131
132
132
struct plat_smp_ops plat_smp_ops = {
+13
-7
arch/arc/kernel/setup.c
+13
-7
arch/arc/kernel/setup.c
···
45
45
static void read_arc_build_cfg_regs(void)
46
46
{
47
47
struct bcr_perip uncached_space;
48
+
struct bcr_timer timer;
48
49
struct bcr_generic bcr;
49
50
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
50
51
unsigned long perip_space;
···
54
53
READ_BCR(AUX_IDENTITY, cpu->core);
55
54
READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
56
55
57
-
READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
56
+
READ_BCR(ARC_REG_TIMERS_BCR, timer);
57
+
cpu->extn.timer0 = timer.t0;
58
+
cpu->extn.timer1 = timer.t1;
59
+
cpu->extn.rtc = timer.rtc;
60
+
58
61
cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
59
62
60
63
READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
···
213
208
(unsigned int)(arc_get_core_freq() / 10000) % 100);
214
209
215
210
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
216
-
IS_AVAIL1(cpu->timers.t0, "Timer0 "),
217
-
IS_AVAIL1(cpu->timers.t1, "Timer1 "),
218
-
IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
211
+
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
212
+
IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
213
+
IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
219
214
CONFIG_ARC_HAS_RTC));
220
215
221
216
n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
···
298
293
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
299
294
int fpu_enabled;
300
295
301
-
if (!cpu->timers.t0)
296
+
if (!cpu->extn.timer0)
302
297
panic("Timer0 is not present!\n");
303
298
304
-
if (!cpu->timers.t1)
299
+
if (!cpu->extn.timer1)
305
300
panic("Timer1 is not present!\n");
306
301
307
-
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
302
+
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
308
303
panic("RTC is not present\n");
309
304
310
305
#ifdef CONFIG_ARC_HAS_DCCM
···
339
334
panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
340
335
341
336
if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic &&
337
+
IS_ENABLED(CONFIG_ARC_HAS_LLSC) &&
342
338
!IS_ENABLED(CONFIG_ARC_STAR_9000923308))
343
339
panic("llock/scond livelock workaround missing\n");
344
340
}
+4
-4
arch/arc/kernel/time.c
+4
-4
arch/arc/kernel/time.c
···
62
62
63
63
/********** Clock Source Device *********/
64
64
65
-
#ifdef CONFIG_ARC_HAS_GRTC
65
+
#ifdef CONFIG_ARC_HAS_GFRC
66
66
67
67
static int arc_counter_setup(void)
68
68
{
···
83
83
84
84
local_irq_save(flags);
85
85
86
-
__mcip_cmd(CMD_GRTC_READ_LO, 0);
86
+
__mcip_cmd(CMD_GFRC_READ_LO, 0);
87
87
stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
88
88
89
-
__mcip_cmd(CMD_GRTC_READ_HI, 0);
89
+
__mcip_cmd(CMD_GFRC_READ_HI, 0);
90
90
stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
91
91
92
92
local_irq_restore(flags);
···
95
95
}
96
96
97
97
static struct clocksource arc_counter = {
98
-
.name = "ARConnect GRTC",
98
+
.name = "ARConnect GFRC",
99
99
.rating = 400,
100
100
.read = arc_counter_read,
101
101
.mask = CLOCKSOURCE_MASK(64),