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dt-bindings: dma: Drop unused QCom hidma binding
The QCom hidma binding was used on a defunct QCom server platform which
mainly used ACPI. DT support in the Linux driver has been broken since
2018, so it seems this binding is unused and can be dropped.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240423161413.481670-2-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Rob Herring (Arm)
and committed by
Vinod Koul
e83cd59d
d100ffe5
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Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
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Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
···
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Qualcomm Technologies HIDMA Management interface
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Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
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memcpy and memset capabilities. It has been designed for virtualized
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environments.
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Each HIDMA HW instance consists of multiple DMA channels. These channels
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share the same bandwidth. The bandwidth utilization can be partitioned
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among channels based on the priority and weight assignments.
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There are only two priority levels and 15 weigh assignments possible.
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Other parameters here determine how much of the system bus this HIDMA
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instance can use like maximum read/write request and number of bytes to
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read/write in a single burst.
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Main node required properties:
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- compatible: "qcom,hidma-mgmt-1.0";
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- reg: Address range for DMA device
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- dma-channels: Number of channels supported by this DMA controller.
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- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
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occupy the bus for in a single transaction. A memcpy requested is
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fragmented to multiples of this amount. This parameter is used while
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writing into destination memory. Setting this value incorrectly can
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starve other peripherals in the system.
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- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
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occupy the bus for in a single transaction. A memcpy request is
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fragmented to multiples of this amount. This parameter is used while
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reading the source memory. Setting this value incorrectly can starve
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other peripherals in the system.
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- max-write-transactions: This value is how many times a write burst is
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applied back to back while writing to the destination before yielding
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the bus.
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- max-read-transactions: This value is how many times a read burst is
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applied back to back while reading the source before yielding the bus.
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- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
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Once a reset is applied to the HW, HW starts a timer for reset operation
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to confirm. If reset is not completed within this time, HW reports reset
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failure.
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Sub-nodes:
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HIDMA has one or more DMA channels that are used to move data from one
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memory location to another.
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When the OS is not in control of the management interface (i.e. it's a guest),
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the channel nodes appear on their own, not under a management node.
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Required properties:
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- compatible: must contain "qcom,hidma-1.0" for initial HW or
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"qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
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- reg: Addresses for the transfer and event channel
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- interrupts: Should contain the event interrupt
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- desc-count: Number of asynchronous requests this channel can handle
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- iommus: required a iommu node
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Optional properties for MSI:
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- msi-parent : See the generic MSI binding described in
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devicetree/bindings/interrupt-controller/msi.txt for a description of the
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msi-parent property.
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Example:
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Hypervisor OS configuration:
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hidma-mgmt@f9984000 = {
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compatible = "qcom,hidma-mgmt-1.0";
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reg = <0xf9984000 0x15000>;
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dma-channels = <6>;
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max-write-burst-bytes = <1024>;
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max-read-burst-bytes = <1024>;
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max-write-transactions = <31>;
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max-read-transactions = <31>;
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channel-reset-timeout-cycles = <0x500>;
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hidma_24: dma-controller@5c050000 {
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compatible = "qcom,hidma-1.0";
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reg = <0 0x5c050000 0x0 0x1000>,
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<0 0x5c0b0000 0x0 0x1000>;
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interrupts = <0 389 0>;
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desc-count = <10>;
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iommus = <&system_mmu>;
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};
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};
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Guest OS configuration:
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hidma_24: dma-controller@5c050000 {
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compatible = "qcom,hidma-1.0";
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reg = <0 0x5c050000 0x0 0x1000>,
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<0 0x5c0b0000 0x0 0x1000>;
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interrupts = <0 389 0>;
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desc-count = <10>;
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iommus = <&system_mmu>;
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};