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crypto: qat - fix virtual channel configuration for GEN6 devices

The TCVCMAP (Traffic Class to Virtual Channel Mapping) field in the
PVC0CTL and PVC1CTL register controls how traffic classes are mapped to
virtual channels in QAT GEN6 hardware.

The driver previously wrote a default TCVCMAP value to this register, but
this configuration was incorrect.

Modify the TCVCMAP configuration to explicitly enable both VC0 and VC1,
and map Traffic Classes 0 to 7 → VC0 and Traffic Class 8 → VC1.
Replace FIELD_PREP() with FIELD_MODIFY() to ensure that only the intended
TCVCMAP field is updated, preserving other bits in the register. This
prevents unintended overwrites of unrelated configuration fields when
modifying TC to VC mappings.

Fixes: 17fd7514ae68 ("crypto: qat - add qat_6xxx driver")
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Suman Kumar Chakraborty and committed by
Herbert Xu e83cfb8f 62842d29

+6 -6
+5 -5
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
··· 532 532 * driver must program the ringmodectl CSRs. 533 533 */ 534 534 value = ADF_CSR_RD(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number)); 535 - value |= FIELD_PREP(ADF_GEN6_RINGMODECTL_TC_MASK, ADF_GEN6_RINGMODECTL_TC_DEFAULT); 536 - value |= FIELD_PREP(ADF_GEN6_RINGMODECTL_TC_EN_MASK, ADF_GEN6_RINGMODECTL_TC_EN_OP1); 535 + FIELD_MODIFY(ADF_GEN6_RINGMODECTL_TC_MASK, &value, ADF_GEN6_RINGMODECTL_TC_DEFAULT); 536 + FIELD_MODIFY(ADF_GEN6_RINGMODECTL_TC_EN_MASK, &value, ADF_GEN6_RINGMODECTL_TC_EN_OP1); 537 537 ADF_CSR_WR(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number), value); 538 538 } 539 539 ··· 549 549 * Read PVC0CTL then write the masked values. 550 550 */ 551 551 pci_read_config_dword(pdev, ADF_GEN6_PVC0CTL_OFFSET, &value); 552 - value |= FIELD_PREP(ADF_GEN6_PVC0CTL_TCVCMAP_MASK, ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT); 552 + FIELD_MODIFY(ADF_GEN6_PVC0CTL_TCVCMAP_MASK, &value, ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT); 553 553 err = pci_write_config_dword(pdev, ADF_GEN6_PVC0CTL_OFFSET, value); 554 554 if (err) { 555 555 dev_err(&GET_DEV(accel_dev), "pci write to PVC0CTL failed\n"); ··· 558 558 559 559 /* Read PVC1CTL then write masked values */ 560 560 pci_read_config_dword(pdev, ADF_GEN6_PVC1CTL_OFFSET, &value); 561 - value |= FIELD_PREP(ADF_GEN6_PVC1CTL_TCVCMAP_MASK, ADF_GEN6_PVC1CTL_TCVCMAP_DEFAULT); 562 - value |= FIELD_PREP(ADF_GEN6_PVC1CTL_VCEN_MASK, ADF_GEN6_PVC1CTL_VCEN_ON); 561 + FIELD_MODIFY(ADF_GEN6_PVC1CTL_TCVCMAP_MASK, &value, ADF_GEN6_PVC1CTL_TCVCMAP_DEFAULT); 562 + FIELD_MODIFY(ADF_GEN6_PVC1CTL_VCEN_MASK, &value, ADF_GEN6_PVC1CTL_VCEN_ON); 563 563 err = pci_write_config_dword(pdev, ADF_GEN6_PVC1CTL_OFFSET, value); 564 564 if (err) 565 565 dev_err(&GET_DEV(accel_dev), "pci write to PVC1CTL failed\n");
+1 -1
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h
··· 99 99 #define ADF_GEN6_PVC0CTL_OFFSET 0x204 100 100 #define ADF_GEN6_PVC0CTL_TCVCMAP_OFFSET 1 101 101 #define ADF_GEN6_PVC0CTL_TCVCMAP_MASK GENMASK(7, 1) 102 - #define ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT 0x7F 102 + #define ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT 0x3F 103 103 104 104 /* VC1 Resource Control Register */ 105 105 #define ADF_GEN6_PVC1CTL_OFFSET 0x210