Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"This is a slightly larger batch of fixes that we've been sitting on a
few -rcs. Most of them are simple oneliners, but there are two sets
that are slightly larger and worth pointing out:
- A set of patches to OMAP to deal with hwmod for RTC on am33xx
(beaglebone SoC, among others). It's the only clock that ever has
a valid offset of 0, so a new flag needed introduction once this
problem was discovered.
- A collection of CCI fixes for performance counters discovered once
people started using it on X-Gene CPUs"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
arm-cci: pmu: Fix typo in event name
Revert "ARM: tegra: fix erroneous address in dts"
ARM: dts: imx6qdl: Fix SPDIF regression
ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx
ARM: dts: imx7d-sdb: fix ti,x-plate-ohms property name
ARM: dts: kirkwood: Fix PCIe label on OpenRD
ARM: kirkwood: ib62x0: fix size of u-boot environment partition
bus: arm-ccn: make event groups reliable
bus: arm-ccn: fix hrtimer registration
bus: arm-ccn: fix PMU interrupt flags
ARM: tegra: Correct polarity for Tegra114 PMIC interrupt
MAINTAINERS: add tree entry for ARM/UniPhier architecture
ARM: sun5i: Fix typo in trip point temperature
MAINTAINERS: Switch to kernel.org account for Krzysztof Kozlowski
ARM: imx6ul: populates platform device at .init_machine
bus: arm-ccn: Add missing event attribute exclusions for host/guest
bus: arm-ccn: Correct required arguments for XP PMU events
bus: arm-ccn: Fix XP watchpoint settings bitmask
bus: arm-ccn: Do not attempt to configure XPs for cycle counter
bus: arm-ccn: Fix PMU handling of MN
...
+172
-109
+1
.mailmap
+1
.mailmap
···
88
88
Kenneth W Chen <kenneth.w.chen@intel.com>
89
89
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
90
90
Koushik <raghavendra.koushik@neterion.com>
91
+
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
91
92
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
92
93
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
93
94
Leonid I Ananiev <leonid.i.ananiev@intel.com>
+10
-6
Documentation/arm/CCN.txt
+10
-6
Documentation/arm/CCN.txt
···
18
18
directory provides configuration templates for all documented
19
19
events, that can be used with perf tool. For example "xp_valid_flit"
20
20
is an equivalent of "type=0x8,event=0x4". Other parameters must be
21
-
explicitly specified. For events originating from device, "node"
22
-
defines its index. All crosspoint events require "xp" (index),
23
-
"port" (device port number) and "vc" (virtual channel ID) and
24
-
"dir" (direction). Watchpoints (special "event" value 0xfe) also
25
-
require comparator values ("cmp_l" and "cmp_h") and "mask", being
26
-
index of the comparator mask.
21
+
explicitly specified.
27
22
23
+
For events originating from device, "node" defines its index.
24
+
25
+
Crosspoint PMU events require "xp" (index), "bus" (bus number)
26
+
and "vc" (virtual channel ID).
27
+
28
+
Crosspoint watchpoint-based events (special "event" value 0xfe)
29
+
require "xp" and "vc" as as above plus "port" (device port index),
30
+
"dir" (transmit/receive direction), comparator values ("cmp_l"
31
+
and "cmp_h") and "mask", being index of the comparator mask.
28
32
Masks are defined separately from the event description
29
33
(due to limited number of the config values) in the "cmp_mask"
30
34
directory, with first 8 configurable by user and additional
+10
-6
MAINTAINERS
+10
-6
MAINTAINERS
···
1624
1624
1625
1625
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
1626
1626
M: Kukjin Kim <kgene@kernel.org>
1627
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
1627
+
M: Krzysztof Kozlowski <krzk@kernel.org>
1628
1628
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1629
1629
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
1630
1630
S: Maintained
···
1831
1831
ARM/UNIPHIER ARCHITECTURE
1832
1832
M: Masahiro Yamada <yamada.masahiro@socionext.com>
1833
1833
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1834
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
1834
1835
S: Maintained
1835
1836
F: arch/arm/boot/dts/uniphier*
1836
1837
F: arch/arm/include/asm/hardware/cache-uniphier.h
···
7465
7464
F: sound/soc/codecs/max9860.*
7466
7465
7467
7466
MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS
7468
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
7467
+
M: Krzysztof Kozlowski <krzk@kernel.org>
7468
+
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
7469
7469
L: linux-pm@vger.kernel.org
7470
7470
S: Supported
7471
7471
F: drivers/power/max14577_charger.c
···
7482
7480
7483
7481
MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS
7484
7482
M: Chanwoo Choi <cw00.choi@samsung.com>
7485
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
7483
+
M: Krzysztof Kozlowski <krzk@kernel.org>
7484
+
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
7486
7485
L: linux-kernel@vger.kernel.org
7487
7486
S: Supported
7488
7487
F: drivers/*/max14577*.c
···
9249
9246
9250
9247
PIN CONTROLLER - SAMSUNG
9251
9248
M: Tomasz Figa <tomasz.figa@gmail.com>
9252
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
9249
+
M: Krzysztof Kozlowski <krzk@kernel.org>
9253
9250
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
9254
9251
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
9255
9252
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
···
10182
10179
F: drivers/platform/x86/samsung-laptop.c
10183
10180
10184
10181
SAMSUNG AUDIO (ASoC) DRIVERS
10185
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
10182
+
M: Krzysztof Kozlowski <krzk@kernel.org>
10186
10183
M: Sangbeom Kim <sbkim73@samsung.com>
10187
10184
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
10188
10185
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
···
10197
10194
10198
10195
SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS
10199
10196
M: Sangbeom Kim <sbkim73@samsung.com>
10200
-
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
10197
+
M: Krzysztof Kozlowski <krzk@kernel.org>
10198
+
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
10201
10199
L: linux-kernel@vger.kernel.org
10202
10200
L: linux-samsung-soc@vger.kernel.org
10203
10201
S: Supported
+1
-1
arch/arm/boot/dts/am335x-baltos.dtsi
+1
-1
arch/arm/boot/dts/am335x-baltos.dtsi
+1
-1
arch/arm/boot/dts/am335x-igep0033.dtsi
+1
-1
arch/arm/boot/dts/am335x-igep0033.dtsi
+1
-1
arch/arm/boot/dts/am335x-phycore-som.dtsi
+1
-1
arch/arm/boot/dts/am335x-phycore-som.dtsi
+4
-4
arch/arm/boot/dts/armada-388-clearfog.dts
+4
-4
arch/arm/boot/dts/armada-388-clearfog.dts
···
390
390
391
391
port@0 {
392
392
reg = <0>;
393
-
label = "lan1";
393
+
label = "lan5";
394
394
};
395
395
396
396
port@1 {
397
397
reg = <1>;
398
-
label = "lan2";
398
+
label = "lan4";
399
399
};
400
400
401
401
port@2 {
···
405
405
406
406
port@3 {
407
407
reg = <3>;
408
-
label = "lan4";
408
+
label = "lan2";
409
409
};
410
410
411
411
port@4 {
412
412
reg = <4>;
413
-
label = "lan5";
413
+
label = "lan1";
414
414
};
415
415
416
416
port@5 {
-3
arch/arm/boot/dts/exynos5410-odroidxu.dts
-3
arch/arm/boot/dts/exynos5410-odroidxu.dts
···
447
447
samsung,dw-mshc-ciu-div = <3>;
448
448
samsung,dw-mshc-sdr-timing = <0 4>;
449
449
samsung,dw-mshc-ddr-timing = <0 2>;
450
-
samsung,dw-mshc-hs400-timing = <0 2>;
451
-
samsung,read-strobe-delay = <90>;
452
450
pinctrl-names = "default";
453
451
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
454
452
bus-width = <8>;
455
453
cap-mmc-highspeed;
456
454
mmc-hs200-1_8v;
457
-
mmc-hs400-1_8v;
458
455
vmmc-supply = <&ldo20_reg>;
459
456
vqmmc-supply = <&ldo11_reg>;
460
457
};
+1
-1
arch/arm/boot/dts/imx6qdl.dtsi
+1
-1
arch/arm/boot/dts/imx6qdl.dtsi
···
243
243
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
244
244
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
245
245
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
246
-
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
246
+
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
247
247
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
248
248
clock-names = "core", "rxtx0",
249
249
"rxtx1", "rxtx2",
+1
-1
arch/arm/boot/dts/imx6sx-sabreauto.dts
+1
-1
arch/arm/boot/dts/imx6sx-sabreauto.dts
+1
-1
arch/arm/boot/dts/imx7d-sdb.dts
+1
-1
arch/arm/boot/dts/imx7d-sdb.dts
+1
-1
arch/arm/boot/dts/kirkwood-ib62x0.dts
+1
-1
arch/arm/boot/dts/kirkwood-ib62x0.dts
+4
arch/arm/boot/dts/kirkwood-openrd.dtsi
+4
arch/arm/boot/dts/kirkwood-openrd.dtsi
+6
-5
arch/arm/boot/dts/logicpd-som-lv.dtsi
+6
-5
arch/arm/boot/dts/logicpd-som-lv.dtsi
···
35
35
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
36
36
37
37
nand@0,0 {
38
-
linux,mtd-name = "micron,mt29f4g16abbda3w";
38
+
compatible = "ti,omap2-nand";
39
39
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
40
+
interrupt-parent = <&gpmc>;
41
+
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
42
+
<1 IRQ_TYPE_NONE>; /* termcount */
43
+
linux,mtd-name = "micron,mt29f4g16abbda3w";
40
44
nand-bus-width = <16>;
41
45
ti,nand-ecc-opt = "bch8";
46
+
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
42
47
gpmc,sync-clk-ps = <0>;
43
48
gpmc,cs-on-ns = <0>;
44
49
gpmc,cs-rd-off-ns = <44>;
···
59
54
gpmc,wr-access-ns = <40>;
60
55
gpmc,wr-data-mux-bus-ns = <0>;
61
56
gpmc,device-width = <2>;
62
-
63
-
gpmc,page-burst-access-ns = <5>;
64
-
gpmc,cycle2cycle-delay-ns = <50>;
65
-
66
57
#address-cells = <1>;
67
58
#size-cells = <1>;
68
59
+1
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+1
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+3
-1
arch/arm/boot/dts/omap3-overo-base.dtsi
+3
-1
arch/arm/boot/dts/omap3-overo-base.dtsi
-2
arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
-2
arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
-2
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
-2
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
-3
arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
-3
arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
+1
-1
arch/arm/boot/dts/sun5i-a13.dtsi
+1
-1
arch/arm/boot/dts/sun5i-a13.dtsi
+1
-1
arch/arm/boot/dts/tegra114-dalmore.dts
+1
-1
arch/arm/boot/dts/tegra114-dalmore.dts
+1
-1
arch/arm/boot/dts/tegra114-roth.dts
+1
-1
arch/arm/boot/dts/tegra114-roth.dts
+1
-1
arch/arm/boot/dts/tegra114-tn7.dts
+1
-1
arch/arm/boot/dts/tegra114-tn7.dts
+2
-2
arch/arm/boot/dts/tegra124-jetson-tk1.dts
+2
-2
arch/arm/boot/dts/tegra124-jetson-tk1.dts
···
1382
1382
* Pin 41: BR_UART1_TXD
1383
1383
* Pin 44: BR_UART1_RXD
1384
1384
*/
1385
-
serial@0,70006000 {
1385
+
serial@70006000 {
1386
1386
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1387
1387
status = "okay";
1388
1388
};
···
1394
1394
* Pin 71: UART2_CTS_L
1395
1395
* Pin 74: UART2_RTS_L
1396
1396
*/
1397
-
serial@0,70006040 {
1397
+
serial@70006040 {
1398
1398
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1399
1399
status = "okay";
1400
1400
};
+1
arch/arm/mach-imx/mach-imx6ul.c
+1
arch/arm/mach-imx/mach-imx6ul.c
+2
-2
arch/arm/mach-imx/pm-imx6.c
+2
-2
arch/arm/mach-imx/pm-imx6.c
···
295
295
val &= ~BM_CLPCR_SBYOS;
296
296
if (cpu_is_imx6sl())
297
297
val |= BM_CLPCR_BYPASS_PMIC_READY;
298
-
if (cpu_is_imx6sl() || cpu_is_imx6sx())
298
+
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
299
299
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
300
300
else
301
301
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
···
310
310
val |= 0x3 << BP_CLPCR_STBY_COUNT;
311
311
val |= BM_CLPCR_VSTBY;
312
312
val |= BM_CLPCR_SBYOS;
313
-
if (cpu_is_imx6sl())
313
+
if (cpu_is_imx6sl() || cpu_is_imx6sx())
314
314
val |= BM_CLPCR_BYPASS_PMIC_READY;
315
315
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
316
316
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-6
arch/arm/mach-omap2/cm33xx.c
-6
arch/arm/mach-omap2/cm33xx.c
···
220
220
{
221
221
int i = 0;
222
222
223
-
if (!clkctrl_offs)
224
-
return 0;
225
-
226
223
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
227
224
MAX_MODULE_READY_TIME, i);
228
225
···
242
245
u8 bit_shift)
243
246
{
244
247
int i = 0;
245
-
246
-
if (!clkctrl_offs)
247
-
return 0;
248
248
249
249
omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
250
250
CLKCTRL_IDLEST_DISABLED),
-6
arch/arm/mach-omap2/cminst44xx.c
-6
arch/arm/mach-omap2/cminst44xx.c
···
278
278
{
279
279
int i = 0;
280
280
281
-
if (!clkctrl_offs)
282
-
return 0;
283
-
284
281
omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
285
282
MAX_MODULE_READY_TIME, i);
286
283
···
300
303
u8 bit_shift)
301
304
{
302
305
int i = 0;
303
-
304
-
if (!clkctrl_offs)
305
-
return 0;
306
306
307
307
omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
308
308
CLKCTRL_IDLEST_DISABLED),
+8
arch/arm/mach-omap2/omap_hwmod.c
+8
arch/arm/mach-omap2/omap_hwmod.c
···
1053
1053
if (oh->flags & HWMOD_NO_IDLEST)
1054
1054
return 0;
1055
1055
1056
+
if (!oh->prcm.omap4.clkctrl_offs &&
1057
+
!(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
1058
+
return 0;
1059
+
1056
1060
return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
1057
1061
oh->clkdm->cm_inst,
1058
1062
oh->prcm.omap4.clkctrl_offs, 0);
···
2973
2969
return 0;
2974
2970
2975
2971
if (!_find_mpu_rt_port(oh))
2972
+
return 0;
2973
+
2974
+
if (!oh->prcm.omap4.clkctrl_offs &&
2975
+
!(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
2976
2976
return 0;
2977
2977
2978
2978
/* XXX check module SIDLEMODE, hardreset status */
+4
arch/arm/mach-omap2/omap_hwmod.h
+4
arch/arm/mach-omap2/omap_hwmod.h
···
443
443
* HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
444
444
* module-level context loss register associated with them; this
445
445
* flag bit should be set in those cases
446
+
* HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL
447
+
* offset of zero; this flag bit should be set in those cases to
448
+
* distinguish from hwmods that have no clkctrl offset.
446
449
*/
447
450
#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0)
451
+
#define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1)
448
452
449
453
/**
450
454
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
+2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
···
29
29
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30
30
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31
31
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32
+
#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
32
33
33
34
/*
34
35
* 'l3' class
···
1297
1296
CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1298
1297
CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1299
1298
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1299
+
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1300
1300
CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1301
1301
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1302
1302
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
+12
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+12
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
···
722
722
* display serial interface controller
723
723
*/
724
724
725
+
static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
726
+
.rev_offs = 0x0000,
727
+
.sysc_offs = 0x0010,
728
+
.syss_offs = 0x0014,
729
+
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
730
+
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
731
+
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
732
+
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
733
+
.sysc_fields = &omap_hwmod_sysc_type1,
734
+
};
735
+
725
736
static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
726
737
.name = "dsi",
738
+
.sysc = &omap3xxx_dsi_sysc,
727
739
};
728
740
729
741
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
+1
-1
drivers/bus/arm-cci.c
+1
-1
drivers/bus/arm-cci.c
···
551
551
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),
552
552
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),
553
553
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),
554
-
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snopp_rq_stall_tt_full, 0xE),
554
+
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_stall_tt_full, 0xE),
555
555
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),
556
556
NULL
557
557
};
+79
-33
drivers/bus/arm-ccn.c
+79
-33
drivers/bus/arm-ccn.c
···
187
187
struct arm_ccn_component *xp;
188
188
189
189
struct arm_ccn_dt dt;
190
+
int mn_id;
190
191
};
191
192
192
193
static DEFINE_MUTEX(arm_ccn_mutex);
···
213
212
#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
214
213
#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
215
214
#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
215
+
#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
216
216
#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
217
217
#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
218
218
#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
···
243
241
static CCN_FORMAT_ATTR(type, "config:8-15");
244
242
static CCN_FORMAT_ATTR(event, "config:16-23");
245
243
static CCN_FORMAT_ATTR(port, "config:24-25");
244
+
static CCN_FORMAT_ATTR(bus, "config:24-25");
246
245
static CCN_FORMAT_ATTR(vc, "config:26-28");
247
246
static CCN_FORMAT_ATTR(dir, "config:29-29");
248
247
static CCN_FORMAT_ATTR(mask, "config:30-33");
···
256
253
&arm_ccn_pmu_format_attr_type.attr.attr,
257
254
&arm_ccn_pmu_format_attr_event.attr.attr,
258
255
&arm_ccn_pmu_format_attr_port.attr.attr,
256
+
&arm_ccn_pmu_format_attr_bus.attr.attr,
259
257
&arm_ccn_pmu_format_attr_vc.attr.attr,
260
258
&arm_ccn_pmu_format_attr_dir.attr.attr,
261
259
&arm_ccn_pmu_format_attr_mask.attr.attr,
···
332
328
static ssize_t arm_ccn_pmu_event_show(struct device *dev,
333
329
struct device_attribute *attr, char *buf)
334
330
{
331
+
struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
335
332
struct arm_ccn_pmu_event *event = container_of(attr,
336
333
struct arm_ccn_pmu_event, attr);
337
334
ssize_t res;
···
354
349
break;
355
350
case CCN_TYPE_XP:
356
351
res += snprintf(buf + res, PAGE_SIZE - res,
357
-
",xp=?,port=?,vc=?,dir=?");
352
+
",xp=?,vc=?");
358
353
if (event->event == CCN_EVENT_WATCHPOINT)
359
354
res += snprintf(buf + res, PAGE_SIZE - res,
360
-
",cmp_l=?,cmp_h=?,mask=?");
355
+
",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
356
+
else
357
+
res += snprintf(buf + res, PAGE_SIZE - res,
358
+
",bus=?");
359
+
360
+
break;
361
+
case CCN_TYPE_MN:
362
+
res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
361
363
break;
362
364
default:
363
365
res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
···
395
383
}
396
384
397
385
static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
398
-
CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
399
-
CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
400
-
CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
386
+
CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
387
+
CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
388
+
CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
401
389
CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
402
390
CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
403
391
CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
···
745
733
746
734
if (has_branch_stack(event) || event->attr.exclude_user ||
747
735
event->attr.exclude_kernel || event->attr.exclude_hv ||
748
-
event->attr.exclude_idle) {
736
+
event->attr.exclude_idle || event->attr.exclude_host ||
737
+
event->attr.exclude_guest) {
749
738
dev_warn(ccn->dev, "Can't exclude execution levels!\n");
750
-
return -EOPNOTSUPP;
739
+
return -EINVAL;
751
740
}
752
741
753
742
if (event->cpu < 0) {
···
772
759
773
760
/* Validate node/xp vs topology */
774
761
switch (type) {
762
+
case CCN_TYPE_MN:
763
+
if (node_xp != ccn->mn_id) {
764
+
dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
765
+
return -EINVAL;
766
+
}
767
+
break;
775
768
case CCN_TYPE_XP:
776
769
if (node_xp >= ccn->num_xps) {
777
770
dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
···
905
886
struct arm_ccn_component *xp;
906
887
u32 val, dt_cfg;
907
888
889
+
/* Nothing to do for cycle counter */
890
+
if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
891
+
return;
892
+
908
893
if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
909
894
xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
910
895
else
···
940
917
arm_ccn_pmu_read_counter(ccn, hw->idx));
941
918
hw->state = 0;
942
919
943
-
/*
944
-
* Pin the timer, so that the overflows are handled by the chosen
945
-
* event->cpu (this is the same one as presented in "cpumask"
946
-
* attribute).
947
-
*/
948
-
if (!ccn->irq)
949
-
hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
950
-
HRTIMER_MODE_REL_PINNED);
951
-
952
920
/* Set the DT bus input, engaging the counter */
953
921
arm_ccn_pmu_xp_dt_config(event, 1);
954
922
}
955
923
956
924
static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
957
925
{
958
-
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
959
926
struct hw_perf_event *hw = &event->hw;
960
-
u64 timeout;
961
927
962
928
/* Disable counting, setting the DT bus to pass-through mode */
963
929
arm_ccn_pmu_xp_dt_config(event, 0);
964
-
965
-
if (!ccn->irq)
966
-
hrtimer_cancel(&ccn->dt.hrtimer);
967
-
968
-
/* Let the DT bus drain */
969
-
timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
970
-
ccn->num_xps;
971
-
while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
972
-
timeout)
973
-
cpu_relax();
974
930
975
931
if (flags & PERF_EF_UPDATE)
976
932
arm_ccn_pmu_event_update(event);
···
990
988
991
989
/* Comparison values */
992
990
writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
993
-
writel((cmp_l >> 32) & 0xefffffff,
991
+
writel((cmp_l >> 32) & 0x7fffffff,
994
992
source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
995
993
writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
996
994
writel((cmp_h >> 32) & 0x0fffffff,
···
998
996
999
997
/* Mask */
1000
998
writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
1001
-
writel((mask_l >> 32) & 0xefffffff,
999
+
writel((mask_l >> 32) & 0x7fffffff,
1002
1000
source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
1003
1001
writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1004
1002
writel((mask_h >> 32) & 0x0fffffff,
···
1016
1014
hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1017
1015
1018
1016
id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1019
-
(CCN_CONFIG_PORT(event->attr.config) << 3) |
1017
+
(CCN_CONFIG_BUS(event->attr.config) << 3) |
1020
1018
(CCN_CONFIG_EVENT(event->attr.config) << 0);
1021
1019
1022
1020
val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
···
1101
1099
spin_unlock(&ccn->dt.config_lock);
1102
1100
}
1103
1101
1102
+
static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1103
+
{
1104
+
return bitmap_weight(ccn->dt.pmu_counters_mask,
1105
+
CCN_NUM_PMU_EVENT_COUNTERS + 1);
1106
+
}
1107
+
1104
1108
static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1105
1109
{
1106
1110
int err;
1107
1111
struct hw_perf_event *hw = &event->hw;
1112
+
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1108
1113
1109
1114
err = arm_ccn_pmu_event_alloc(event);
1110
1115
if (err)
1111
1116
return err;
1117
+
1118
+
/*
1119
+
* Pin the timer, so that the overflows are handled by the chosen
1120
+
* event->cpu (this is the same one as presented in "cpumask"
1121
+
* attribute).
1122
+
*/
1123
+
if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1124
+
hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1125
+
HRTIMER_MODE_REL_PINNED);
1112
1126
1113
1127
arm_ccn_pmu_event_config(event);
1114
1128
···
1138
1120
1139
1121
static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1140
1122
{
1123
+
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1124
+
1141
1125
arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1142
1126
1143
1127
arm_ccn_pmu_event_release(event);
1128
+
1129
+
if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1130
+
hrtimer_cancel(&ccn->dt.hrtimer);
1144
1131
}
1145
1132
1146
1133
static void arm_ccn_pmu_event_read(struct perf_event *event)
1147
1134
{
1148
1135
arm_ccn_pmu_event_update(event);
1136
+
}
1137
+
1138
+
static void arm_ccn_pmu_enable(struct pmu *pmu)
1139
+
{
1140
+
struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1141
+
1142
+
u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1143
+
val |= CCN_DT_PMCR__PMU_EN;
1144
+
writel(val, ccn->dt.base + CCN_DT_PMCR);
1145
+
}
1146
+
1147
+
static void arm_ccn_pmu_disable(struct pmu *pmu)
1148
+
{
1149
+
struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1150
+
1151
+
u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1152
+
val &= ~CCN_DT_PMCR__PMU_EN;
1153
+
writel(val, ccn->dt.base + CCN_DT_PMCR);
1149
1154
}
1150
1155
1151
1156
static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
···
1293
1252
.start = arm_ccn_pmu_event_start,
1294
1253
.stop = arm_ccn_pmu_event_stop,
1295
1254
.read = arm_ccn_pmu_event_read,
1255
+
.pmu_enable = arm_ccn_pmu_enable,
1256
+
.pmu_disable = arm_ccn_pmu_disable,
1296
1257
};
1297
1258
1298
1259
/* No overflow interrupt? Have to use a timer instead. */
···
1404
1361
1405
1362
switch (type) {
1406
1363
case CCN_TYPE_MN:
1364
+
ccn->mn_id = id;
1365
+
return 0;
1407
1366
case CCN_TYPE_DT:
1408
1367
return 0;
1409
1368
case CCN_TYPE_XP:
···
1516
1471
/* Can set 'disable' bits, so can acknowledge interrupts */
1517
1472
writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1518
1473
ccn->base + CCN_MN_ERRINT_STATUS);
1519
-
err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1520
-
dev_name(ccn->dev), ccn);
1474
+
err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1475
+
IRQF_NOBALANCING | IRQF_NO_THREAD,
1476
+
dev_name(ccn->dev), ccn);
1521
1477
if (err)
1522
1478
return err;
1523
1479
+1
drivers/bus/vexpress-config.c
+1
drivers/bus/vexpress-config.c
+3
-2
drivers/firmware/arm_scpi.c
+3
-2
drivers/firmware/arm_scpi.c
···
709
709
struct mbox_client *cl = &pchan->cl;
710
710
struct device_node *shmem = of_parse_phandle(np, "shmem", idx);
711
711
712
-
if (of_address_to_resource(shmem, 0, &res)) {
712
+
ret = of_address_to_resource(shmem, 0, &res);
713
+
of_node_put(shmem);
714
+
if (ret) {
713
715
dev_err(dev, "failed to get SCPI payload mem resource\n");
714
-
ret = -EINVAL;
715
716
goto err;
716
717
}
717
718
+7
-14
drivers/memory/omap-gpmc.c
+7
-14
drivers/memory/omap-gpmc.c
···
2185
2185
return 0;
2186
2186
}
2187
2187
2188
-
static int gpmc_probe_dt_children(struct platform_device *pdev)
2188
+
static void gpmc_probe_dt_children(struct platform_device *pdev)
2189
2189
{
2190
2190
int ret;
2191
2191
struct device_node *child;
···
2200
2200
else
2201
2201
ret = gpmc_probe_generic_child(pdev, child);
2202
2202
2203
-
if (ret)
2204
-
return ret;
2203
+
if (ret) {
2204
+
dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2205
+
child->name, ret);
2206
+
}
2205
2207
}
2206
-
2207
-
return 0;
2208
2208
}
2209
2209
#else
2210
2210
static int gpmc_probe_dt(struct platform_device *pdev)
···
2212
2212
return 0;
2213
2213
}
2214
2214
2215
-
static int gpmc_probe_dt_children(struct platform_device *pdev)
2215
+
static void gpmc_probe_dt_children(struct platform_device *pdev)
2216
2216
{
2217
-
return 0;
2218
2217
}
2219
2218
#endif /* CONFIG_OF */
2220
2219
···
2368
2369
goto setup_irq_failed;
2369
2370
}
2370
2371
2371
-
rc = gpmc_probe_dt_children(pdev);
2372
-
if (rc < 0) {
2373
-
dev_err(gpmc->dev, "failed to probe DT children\n");
2374
-
goto dt_children_failed;
2375
-
}
2372
+
gpmc_probe_dt_children(pdev);
2376
2373
2377
2374
return 0;
2378
2375
2379
-
dt_children_failed:
2380
-
gpmc_free_irq(gpmc);
2381
2376
setup_irq_failed:
2382
2377
gpmc_gpio_exit(gpmc);
2383
2378
gpio_init_failed: