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net: phy: broadcom: Add LPI counter

Add the ability to read the PHY maintained LPI counter which is in the
Clause 45 vendor space, device address 7, offset 0x803F. The counter is
cleared on read.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230531231729.1873932-1-florian.fainelli@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Florian Fainelli and committed by
Jakub Kicinski
e8b6f79b 733b3e27

+14 -7
+12 -7
drivers/net/phy/bcm-phy-lib.c
··· 496 496 497 497 struct bcm_phy_hw_stat { 498 498 const char *string; 499 - u8 reg; 499 + int devad; 500 + u16 reg; 500 501 u8 shift; 501 502 u8 bits; 502 503 }; 503 504 504 505 /* Counters freeze at either 0xffff or 0xff, better than nothing */ 505 506 static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = { 506 - { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 }, 507 - { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 }, 508 - { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 }, 509 - { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 }, 510 - { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 }, 507 + { "phy_receive_errors", -1, MII_BRCM_CORE_BASE12, 0, 16 }, 508 + { "phy_serdes_ber_errors", -1, MII_BRCM_CORE_BASE13, 8, 8 }, 509 + { "phy_false_carrier_sense_errors", -1, MII_BRCM_CORE_BASE13, 0, 8 }, 510 + { "phy_local_rcvr_nok", -1, MII_BRCM_CORE_BASE14, 8, 8 }, 511 + { "phy_remote_rcv_nok", -1, MII_BRCM_CORE_BASE14, 0, 8 }, 512 + { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 }, 511 513 }; 512 514 513 515 int bcm_phy_get_sset_count(struct phy_device *phydev) ··· 538 536 int val; 539 537 u64 ret; 540 538 541 - val = phy_read(phydev, stat.reg); 539 + if (stat.devad < 0) 540 + val = phy_read(phydev, stat.reg); 541 + else 542 + val = phy_read_mmd(phydev, stat.devad, stat.reg); 542 543 if (val < 0) { 543 544 ret = U64_MAX; 544 545 } else {
+2
include/linux/brcmphy.h
··· 359 359 #define LPI_FEATURE_EN 0x8000 360 360 #define LPI_FEATURE_EN_DIG1000X 0x4000 361 361 362 + #define BRCM_CL45VEN_EEE_LPI_CNT 0x803f 363 + 362 364 /* Core register definitions*/ 363 365 #define MII_BRCM_CORE_BASE12 0x12 364 366 #define MII_BRCM_CORE_BASE13 0x13