Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: brcmstb: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from
linux/gpio/generic.h.
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Doug Berger <opendmb@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-7-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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-52
+60
-52
drivers/gpio/gpio-brcmstb.c
+60
-52
drivers/gpio/gpio-brcmstb.c
···
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3
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#include <linux/bitops.h>
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5
#include <linux/gpio/driver.h>
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+
#include <linux/gpio/generic.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
···
38
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struct brcmstb_gpio_bank {
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struct list_head node;
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int id;
41
-
struct gpio_chip gc;
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struct gpio_generic_chip chip;
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struct brcmstb_gpio_priv *parent_priv;
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u32 width;
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u32 wake_active;
···
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{
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void __iomem *reg_base = bank->parent_priv->reg_base;
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74
76
-
return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
77
-
bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
75
+
return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) &
76
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gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id));
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}
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static unsigned long
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brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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{
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unsigned long status;
84
-
unsigned long flags;
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86
-
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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+
guard(gpio_generic_lock_irqsave)(&bank->chip);
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+
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status = __brcmstb_gpio_get_active_irqs(bank);
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raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return status;
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}
···
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static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
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struct brcmstb_gpio_bank *bank)
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{
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-
return hwirq - bank->gc.offset;
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return hwirq - bank->chip.gc.offset;
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}
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static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
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unsigned int hwirq, bool enable)
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{
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struct gpio_chip *gc = &bank->gc;
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
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u32 imask;
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unsigned long flags;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
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guard(gpio_generic_lock_irqsave)(&bank->chip);
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imask = gpio_generic_read_reg(&bank->chip,
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priv->reg_base + GIO_MASK(bank->id));
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if (enable)
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imask |= mask;
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else
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imask &= ~mask;
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gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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gpio_generic_write_reg(&bank->chip,
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priv->reg_base + GIO_MASK(bank->id), imask);
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}
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static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
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gpio_generic_write_reg(&bank->chip,
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priv->reg_base + GIO_STAT(bank->id), mask);
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}
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static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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u32 edge_insensitive, iedge_insensitive;
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u32 edge_config, iedge_config;
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u32 level, ilevel;
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unsigned long flags;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
···
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return -EINVAL;
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}
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-
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(&bank->chip);
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iedge_config = bank->gc.read_reg(priv->reg_base +
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GIO_EC(bank->id)) & ~mask;
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iedge_insensitive = bank->gc.read_reg(priv->reg_base +
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GIO_EI(bank->id)) & ~mask;
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ilevel = bank->gc.read_reg(priv->reg_base +
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GIO_LEVEL(bank->id)) & ~mask;
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iedge_config = gpio_generic_read_reg(&bank->chip,
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priv->reg_base + GIO_EC(bank->id)) & ~mask;
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iedge_insensitive = gpio_generic_read_reg(&bank->chip,
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priv->reg_base + GIO_EI(bank->id)) & ~mask;
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ilevel = gpio_generic_read_reg(&bank->chip,
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priv->reg_base + GIO_LEVEL(bank->id)) & ~mask;
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bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
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iedge_config | edge_config);
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bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
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iedge_insensitive | edge_insensitive);
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bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
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ilevel | level);
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gpio_generic_write_reg(&bank->chip,
207
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priv->reg_base + GIO_EC(bank->id),
208
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iedge_config | edge_config);
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gpio_generic_write_reg(&bank->chip,
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priv->reg_base + GIO_EI(bank->id),
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iedge_insensitive | edge_insensitive);
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gpio_generic_write_reg(&bank->chip,
213
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priv->reg_base + GIO_LEVEL(bank->id),
214
+
ilevel | level);
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215
213
-
raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return 0;
215
217
}
216
218
···
265
263
{
266
264
struct brcmstb_gpio_priv *priv = bank->parent_priv;
267
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struct irq_domain *domain = priv->irq_domain;
268
-
int hwbase = bank->gc.offset;
266
+
int hwbase = bank->chip.gc.offset;
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unsigned long status;
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268
271
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while ((status = brcmstb_gpio_get_active_irqs(bank))) {
···
305
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306
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/* banks are in descending order */
307
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list_for_each_entry_reverse(bank, &priv->bank_list, node) {
308
-
i += bank->gc.ngpio;
306
+
i += bank->chip.gc.ngpio;
309
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if (hwirq < i)
310
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return bank;
311
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}
···
334
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dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
336
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irq, (int)hwirq, bank->id);
337
-
ret = irq_set_chip_data(irq, &bank->gc);
335
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ret = irq_set_chip_data(irq, &bank->chip.gc);
338
336
if (ret < 0)
339
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return ret;
340
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irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
···
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* more important to actually perform all of the steps.
397
395
*/
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list_for_each_entry(bank, &priv->bank_list, node)
399
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gpiochip_remove(&bank->gc);
397
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gpiochip_remove(&bank->chip.gc);
400
398
}
401
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static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
···
414
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if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
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return -EINVAL;
416
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417
-
offset = gpiospec->args[0] - bank->gc.offset;
415
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offset = gpiospec->args[0] - bank->chip.gc.offset;
418
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if (offset >= gc->ngpio || offset < 0)
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return -EINVAL;
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418
···
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static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
496
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struct brcmstb_gpio_bank *bank)
497
495
{
498
-
struct gpio_chip *gc = &bank->gc;
499
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unsigned int i;
500
497
501
498
for (i = 0; i < GIO_REG_STAT; i++)
502
-
bank->saved_regs[i] = gc->read_reg(priv->reg_base +
503
-
GIO_BANK_OFF(bank->id, i));
499
+
bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip,
500
+
priv->reg_base + GIO_BANK_OFF(bank->id, i));
504
501
}
505
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506
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static void brcmstb_gpio_quiesce(struct device *dev, bool save)
507
504
{
508
505
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
509
506
struct brcmstb_gpio_bank *bank;
510
-
struct gpio_chip *gc;
511
507
u32 imask;
512
508
513
509
/* disable non-wake interrupt */
···
513
513
disable_irq(priv->parent_irq);
514
514
515
515
list_for_each_entry(bank, &priv->bank_list, node) {
516
-
gc = &bank->gc;
517
-
518
516
if (save)
519
517
brcmstb_gpio_bank_save(priv, bank);
520
518
···
521
523
imask = bank->wake_active;
522
524
else
523
525
imask = 0;
524
-
gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
525
-
imask);
526
+
gpio_generic_write_reg(&bank->chip,
527
+
priv->reg_base + GIO_MASK(bank->id),
528
+
imask);
526
529
}
527
530
}
528
531
···
537
538
static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
538
539
struct brcmstb_gpio_bank *bank)
539
540
{
540
-
struct gpio_chip *gc = &bank->gc;
541
541
unsigned int i;
542
542
543
543
for (i = 0; i < GIO_REG_STAT; i++)
544
-
gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
545
-
bank->saved_regs[i]);
544
+
gpio_generic_write_reg(&bank->chip,
545
+
priv->reg_base + GIO_BANK_OFF(bank->id, i),
546
+
bank->saved_regs[i]);
546
547
}
547
548
548
549
static int brcmstb_gpio_suspend(struct device *dev)
···
584
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585
586
static int brcmstb_gpio_probe(struct platform_device *pdev)
586
587
{
588
+
struct gpio_generic_chip_config config;
587
589
struct device *dev = &pdev->dev;
588
590
struct device_node *np = dev->of_node;
589
591
void __iomem *reg_base;
···
665
665
bank->width = bank_width;
666
666
}
667
667
668
+
gc = &bank->chip.gc;
669
+
668
670
/*
669
671
* Regs are 4 bytes wide, have data reg, no set/clear regs,
670
672
* and direction bits have 0 = output and 1 = input
671
673
*/
672
-
gc = &bank->gc;
673
-
err = bgpio_init(gc, dev, 4,
674
-
reg_base + GIO_DATA(bank->id),
675
-
NULL, NULL, NULL,
676
-
reg_base + GIO_IODIR(bank->id), flags);
674
+
675
+
config = (struct gpio_generic_chip_config) {
676
+
.dev = dev,
677
+
.sz = 4,
678
+
.dat = reg_base + GIO_DATA(bank->id),
679
+
.dirin = reg_base + GIO_IODIR(bank->id),
680
+
.flags = flags,
681
+
};
682
+
683
+
err = gpio_generic_chip_init(&bank->chip, &config);
677
684
if (err) {
678
-
dev_err(dev, "bgpio_init() failed\n");
685
+
dev_err(dev, "failed to initialize generic GPIO chip\n");
679
686
goto fail;
680
687
}
681
688
···
707
700
* be retained from S5 cold boot
708
701
*/
709
702
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
710
-
gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
703
+
gpio_generic_write_reg(&bank->chip,
704
+
reg_base + GIO_MASK(bank->id), 0);
711
705
712
706
err = gpiochip_add_data(gc, bank);
713
707
if (err) {