Merge tag 'i2c-for-7.1-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+1

.mailmap

··· 338 338 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> 339 339 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> 340 340 Ignat Korchagin <ignat@linux.win> <ignat@cloudflare.com> 341 + Igor Korotin <igor.korotin@linux.dev> <igor.korotin.linux@gmail.com> 341 342 Ike Panhc <ikepanhc@gmail.com> <ike.pan@canonical.com> 342 343 J. Bruce Fields <bfields@fieldses.org> <bfields@redhat.com> 343 344 J. Bruce Fields <bfields@fieldses.org> <bfields@citi.umich.edu>

+49

Documentation/devicetree/bindings/i2c/cnxt,cx92755-i2c.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/cnxt,cx92755-i2c.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Conexant Digicolor I2C controller 8 + 9 + allOf: 10 + - $ref: /schemas/i2c/i2c-controller.yaml# 11 + 12 + maintainers: 13 + - Baruch Siach <baruch@tkos.co.il> 14 + 15 + properties: 16 + compatible: 17 + const: cnxt,cx92755-i2c 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + interrupts: 23 + maxItems: 1 24 + 25 + clocks: 26 + maxItems: 1 27 + 28 + clock-frequency: 29 + default: 100000 30 + 31 + required: 32 + - compatible 33 + - reg 34 + - interrupts 35 + - clocks 36 + 37 + unevaluatedProperties: false 38 + 39 + examples: 40 + - | 41 + i2c@f0000120 { 42 + compatible = "cnxt,cx92755-i2c"; 43 + reg = <0xf0000120 0x10>; 44 + interrupts = <28>; 45 + clocks = <&main_clk>; 46 + clock-frequency = <100000>; 47 + #address-cells = <1>; 48 + #size-cells = <0>; 49 + };

-25

Documentation/devicetree/bindings/i2c/i2c-digicolor.txt

··· 1 - Conexant Digicolor I2C controller 2 - 3 - Required properties: 4 - - compatible: must be "cnxt,cx92755-i2c" 5 - - reg: physical address and length of the device registers 6 - - interrupts: a single interrupt specifier 7 - - clocks: clock for the device 8 - - #address-cells: should be <1> 9 - - #size-cells: should be <0> 10 - 11 - Optional properties: 12 - - clock-frequency: the desired I2C bus clock frequency in Hz; in 13 - absence of this property the default value is used (100 kHz). 14 - 15 - Example: 16 - 17 - i2c: i2c@f0000120 { 18 - compatible = "cnxt,cx92755-i2c"; 19 - reg = <0xf0000120 0x10>; 20 - interrupts = <28>; 21 - clocks = <&main_clk>; 22 - clock-frequency = <100000>; 23 - #address-cells = <1>; 24 - #size-cells = <0>; 25 - };

+2 -1

MAINTAINERS

··· 12115 12115 F: include/uapi/linux/i2c.h 12116 12116 12117 12117 I2C SUBSYSTEM [RUST] 12118 - M: Igor Korotin <igor.korotin.linux@gmail.com> 12118 + M: Igor Korotin <igor.korotin@linux.dev> 12119 12119 R: Danilo Krummrich <dakr@kernel.org> 12120 12120 R: Daniel Almeida <daniel.almeida@collabora.com> 12121 12121 L: rust-for-linux@vger.kernel.org 12122 12122 S: Maintained 12123 + T: git https://github.com/ikrtn/linux.git rust-i2c-next 12123 12124 F: rust/kernel/i2c.rs 12124 12125 F: samples/rust/rust_driver_i2c.rs 12125 12126 F: samples/rust/rust_i2c_client.rs

+12 -1

drivers/i2c/busses/i2c-mt65xx.c

··· 21 21 #include <linux/module.h> 22 22 #include <linux/of.h> 23 23 #include <linux/platform_device.h> 24 + #include <linux/regulator/consumer.h> 24 25 #include <linux/scatterlist.h> 25 26 #include <linux/sched.h> 26 27 #include <linux/slab.h> ··· 1245 1244 bool write_then_read_en = false; 1246 1245 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1247 1246 1247 + if (i2c->adap.bus_regulator) { 1248 + ret = regulator_enable(i2c->adap.bus_regulator); 1249 + if (ret) 1250 + return ret; 1251 + } 1252 + 1248 1253 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1249 1254 if (ret) 1250 - return ret; 1255 + goto err_regulator; 1251 1256 1252 1257 i2c->auto_restart = i2c->dev_comp->auto_restart; 1253 1258 ··· 1308 1301 1309 1302 err_exit: 1310 1303 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1304 + err_regulator: 1305 + if (i2c->adap.bus_regulator) 1306 + regulator_disable(i2c->adap.bus_regulator); 1307 + 1311 1308 return ret; 1312 1309 } 1313 1310

+12 -6

drivers/i2c/busses/i2c-pxa.c

··· 71 71 #define ISR_GCAD (1 << 8) /* general call address detected */ 72 72 #define ISR_SAD (1 << 9) /* slave address detected */ 73 73 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ 74 + #define ISR_A3700_EBB (1 << 11) /* early bus busy for armada 3700 */ 74 75 75 76 #define ILCR_SLV_SHIFT 0 76 77 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT) ··· 264 263 bool highmode_enter; 265 264 u32 fm_mask; 266 265 u32 hs_mask; 266 + u32 busy_mask; 267 267 268 268 struct i2c_bus_recovery_info recovery; 269 269 struct pinctrl *pinctrl; ··· 432 430 433 431 while (1) { 434 432 isr = readl(_ISR(i2c)); 435 - if (!(isr & (ISR_IBB | ISR_UB))) 433 + if (!(isr & i2c->busy_mask)) 436 434 return 0; 437 435 438 436 if (isr & ISR_SAD) ··· 469 467 * quick check of the i2c lines themselves to ensure they've 470 468 * gone high... 471 469 */ 472 - if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && 470 + if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 && 473 471 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) { 474 472 if (i2c_debug > 0) 475 473 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); ··· 490 488 if (i2c_debug) 491 489 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 492 490 493 - if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { 491 + if ((readl(_ISR(i2c)) & i2c->busy_mask) != 0) { 494 492 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 495 493 if (!i2c_pxa_wait_master(i2c)) { 496 494 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); ··· 516 514 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 517 515 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 518 516 519 - if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || 517 + if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 || 520 518 (readl(_ISR(i2c)) & ISR_SAD) != 0 || 521 519 (readl(_ICR(i2c)) & ICR_SCLE) == 0) { 522 520 if (i2c_debug > 1) ··· 1179 1177 /* 1180 1178 * Wait for the bus to become free. 1181 1179 */ 1182 - while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) 1180 + while (timeout-- && readl(_ISR(i2c)) & i2c->busy_mask) 1183 1181 udelay(1000); 1184 1182 1185 1183 if (timeout < 0) { ··· 1324 1322 * handing control of the bus back to avoid the bus changing state. 1325 1323 */ 1326 1324 isr = readl(_ISR(i2c)); 1327 - if (isr & (ISR_UB | ISR_IBB)) { 1325 + if (isr & i2c->busy_mask) { 1328 1326 dev_dbg(&i2c->adap.dev, 1329 1327 "recovery: resetting controller, ISR=0x%08x\n", isr); 1330 1328 i2c_pxa_do_reset(i2c); ··· 1480 1478 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; 1481 1479 i2c->fm_mask = pxa_reg_layout[i2c_type].fm; 1482 1480 i2c->hs_mask = pxa_reg_layout[i2c_type].hs; 1481 + 1482 + i2c->busy_mask = ISR_UB | ISR_IBB; 1483 + if (i2c_type == REGS_A3700) 1484 + i2c->busy_mask |= ISR_A3700_EBB; 1483 1485 1484 1486 if (i2c_type != REGS_CE4100) 1485 1487 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;

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