Merge branch 'lan743x-PCI11010-#PCI11414'

+370 -8

drivers/net/ethernet/microchip/lan743x_ethtool.c

··· 7 7 #include <linux/phy.h> 8 8 #include "lan743x_main.h" 9 9 #include "lan743x_ethtool.h" 10 + #include <linux/sched.h> 11 + #include <linux/iopoll.h> 10 12 11 13 /* eeprom */ 12 14 #define LAN743X_EEPROM_MAGIC (0x74A5) ··· 20 18 #define MAX_OTP_SIZE (1024) 21 19 #define OTP_INDICATOR_1 (0xF3) 22 20 #define OTP_INDICATOR_2 (0xF7) 21 + 22 + #define LOCK_TIMEOUT_MAX_CNT (100) // 1 sec (10 msce * 100) 23 + 24 + #define LAN743X_CSR_READ_OP(offset) lan743x_csr_read(adapter, offset) 23 25 24 26 static int lan743x_otp_power_up(struct lan743x_adapter *adapter) 25 27 { ··· 155 149 return 0; 156 150 } 157 151 152 + static int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, 153 + u16 timeout) 154 + { 155 + u16 timeout_cnt = 0; 156 + u32 val; 157 + 158 + do { 159 + spin_lock(&adapter->eth_syslock_spinlock); 160 + if (adapter->eth_syslock_acquire_cnt == 0) { 161 + lan743x_csr_write(adapter, ETH_SYSTEM_SYS_LOCK_REG, 162 + SYS_LOCK_REG_ENET_SS_LOCK_); 163 + val = lan743x_csr_read(adapter, 164 + ETH_SYSTEM_SYS_LOCK_REG); 165 + if (val & SYS_LOCK_REG_ENET_SS_LOCK_) { 166 + adapter->eth_syslock_acquire_cnt++; 167 + WARN_ON(adapter->eth_syslock_acquire_cnt == 0); 168 + spin_unlock(&adapter->eth_syslock_spinlock); 169 + break; 170 + } 171 + } else { 172 + adapter->eth_syslock_acquire_cnt++; 173 + WARN_ON(adapter->eth_syslock_acquire_cnt == 0); 174 + spin_unlock(&adapter->eth_syslock_spinlock); 175 + break; 176 + } 177 + 178 + spin_unlock(&adapter->eth_syslock_spinlock); 179 + 180 + if (timeout_cnt++ < timeout) 181 + usleep_range(10000, 11000); 182 + else 183 + return -ETIMEDOUT; 184 + } while (true); 185 + 186 + return 0; 187 + } 188 + 189 + static void lan743x_hs_syslock_release(struct lan743x_adapter *adapter) 190 + { 191 + u32 val; 192 + 193 + spin_lock(&adapter->eth_syslock_spinlock); 194 + WARN_ON(adapter->eth_syslock_acquire_cnt == 0); 195 + 196 + if (adapter->eth_syslock_acquire_cnt) { 197 + adapter->eth_syslock_acquire_cnt--; 198 + if (adapter->eth_syslock_acquire_cnt == 0) { 199 + lan743x_csr_write(adapter, ETH_SYSTEM_SYS_LOCK_REG, 0); 200 + val = lan743x_csr_read(adapter, 201 + ETH_SYSTEM_SYS_LOCK_REG); 202 + WARN_ON((val & SYS_LOCK_REG_ENET_SS_LOCK_) != 0); 203 + } 204 + } 205 + 206 + spin_unlock(&adapter->eth_syslock_spinlock); 207 + } 208 + 209 + static void lan743x_hs_otp_power_up(struct lan743x_adapter *adapter) 210 + { 211 + u32 reg_value; 212 + 213 + reg_value = lan743x_csr_read(adapter, HS_OTP_PWR_DN); 214 + if (reg_value & OTP_PWR_DN_PWRDN_N_) { 215 + reg_value &= ~OTP_PWR_DN_PWRDN_N_; 216 + lan743x_csr_write(adapter, HS_OTP_PWR_DN, reg_value); 217 + /* To flush the posted write so the subsequent delay is 218 + * guaranteed to happen after the write at the hardware 219 + */ 220 + lan743x_csr_read(adapter, HS_OTP_PWR_DN); 221 + udelay(1); 222 + } 223 + } 224 + 225 + static void lan743x_hs_otp_power_down(struct lan743x_adapter *adapter) 226 + { 227 + u32 reg_value; 228 + 229 + reg_value = lan743x_csr_read(adapter, HS_OTP_PWR_DN); 230 + if (!(reg_value & OTP_PWR_DN_PWRDN_N_)) { 231 + reg_value |= OTP_PWR_DN_PWRDN_N_; 232 + lan743x_csr_write(adapter, HS_OTP_PWR_DN, reg_value); 233 + /* To flush the posted write so the subsequent delay is 234 + * guaranteed to happen after the write at the hardware 235 + */ 236 + lan743x_csr_read(adapter, HS_OTP_PWR_DN); 237 + udelay(1); 238 + } 239 + } 240 + 241 + static void lan743x_hs_otp_set_address(struct lan743x_adapter *adapter, 242 + u32 address) 243 + { 244 + lan743x_csr_write(adapter, HS_OTP_ADDR_HIGH, (address >> 8) & 0x03); 245 + lan743x_csr_write(adapter, HS_OTP_ADDR_LOW, address & 0xFF); 246 + } 247 + 248 + static void lan743x_hs_otp_read_go(struct lan743x_adapter *adapter) 249 + { 250 + lan743x_csr_write(adapter, HS_OTP_FUNC_CMD, OTP_FUNC_CMD_READ_); 251 + lan743x_csr_write(adapter, HS_OTP_CMD_GO, OTP_CMD_GO_GO_); 252 + } 253 + 254 + static int lan743x_hs_otp_cmd_cmplt_chk(struct lan743x_adapter *adapter) 255 + { 256 + u32 val; 257 + 258 + return readx_poll_timeout(LAN743X_CSR_READ_OP, HS_OTP_STATUS, val, 259 + !(val & OTP_STATUS_BUSY_), 260 + 80, 10000); 261 + } 262 + 263 + static int lan743x_hs_otp_read(struct lan743x_adapter *adapter, u32 offset, 264 + u32 length, u8 *data) 265 + { 266 + int ret; 267 + int i; 268 + 269 + ret = lan743x_hs_syslock_acquire(adapter, LOCK_TIMEOUT_MAX_CNT); 270 + if (ret < 0) 271 + return ret; 272 + 273 + lan743x_hs_otp_power_up(adapter); 274 + 275 + ret = lan743x_hs_otp_cmd_cmplt_chk(adapter); 276 + if (ret < 0) 277 + goto power_down; 278 + 279 + lan743x_hs_syslock_release(adapter); 280 + 281 + for (i = 0; i < length; i++) { 282 + ret = lan743x_hs_syslock_acquire(adapter, 283 + LOCK_TIMEOUT_MAX_CNT); 284 + if (ret < 0) 285 + return ret; 286 + 287 + lan743x_hs_otp_set_address(adapter, offset + i); 288 + 289 + lan743x_hs_otp_read_go(adapter); 290 + ret = lan743x_hs_otp_cmd_cmplt_chk(adapter); 291 + if (ret < 0) 292 + goto power_down; 293 + 294 + data[i] = lan743x_csr_read(adapter, HS_OTP_READ_DATA); 295 + 296 + lan743x_hs_syslock_release(adapter); 297 + } 298 + 299 + ret = lan743x_hs_syslock_acquire(adapter, 300 + LOCK_TIMEOUT_MAX_CNT); 301 + if (ret < 0) 302 + return ret; 303 + 304 + power_down: 305 + lan743x_hs_otp_power_down(adapter); 306 + lan743x_hs_syslock_release(adapter); 307 + 308 + return ret; 309 + } 310 + 311 + static int lan743x_hs_otp_write(struct lan743x_adapter *adapter, u32 offset, 312 + u32 length, u8 *data) 313 + { 314 + int ret; 315 + int i; 316 + 317 + ret = lan743x_hs_syslock_acquire(adapter, LOCK_TIMEOUT_MAX_CNT); 318 + if (ret < 0) 319 + return ret; 320 + 321 + lan743x_hs_otp_power_up(adapter); 322 + 323 + ret = lan743x_hs_otp_cmd_cmplt_chk(adapter); 324 + if (ret < 0) 325 + goto power_down; 326 + 327 + /* set to BYTE program mode */ 328 + lan743x_csr_write(adapter, HS_OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_); 329 + 330 + lan743x_hs_syslock_release(adapter); 331 + 332 + for (i = 0; i < length; i++) { 333 + ret = lan743x_hs_syslock_acquire(adapter, 334 + LOCK_TIMEOUT_MAX_CNT); 335 + if (ret < 0) 336 + return ret; 337 + 338 + lan743x_hs_otp_set_address(adapter, offset + i); 339 + 340 + lan743x_csr_write(adapter, HS_OTP_PRGM_DATA, data[i]); 341 + lan743x_csr_write(adapter, HS_OTP_TST_CMD, 342 + OTP_TST_CMD_PRGVRFY_); 343 + lan743x_csr_write(adapter, HS_OTP_CMD_GO, OTP_CMD_GO_GO_); 344 + 345 + ret = lan743x_hs_otp_cmd_cmplt_chk(adapter); 346 + if (ret < 0) 347 + goto power_down; 348 + 349 + lan743x_hs_syslock_release(adapter); 350 + } 351 + 352 + ret = lan743x_hs_syslock_acquire(adapter, LOCK_TIMEOUT_MAX_CNT); 353 + if (ret < 0) 354 + return ret; 355 + 356 + power_down: 357 + lan743x_hs_otp_power_down(adapter); 358 + lan743x_hs_syslock_release(adapter); 359 + 360 + return ret; 361 + } 362 + 158 363 static int lan743x_eeprom_wait(struct lan743x_adapter *adapter) 159 364 { 160 365 unsigned long start_time = jiffies; ··· 480 263 return 0; 481 264 } 482 265 266 + static int lan743x_hs_eeprom_cmd_cmplt_chk(struct lan743x_adapter *adapter) 267 + { 268 + u32 val; 269 + 270 + return readx_poll_timeout(LAN743X_CSR_READ_OP, HS_E2P_CMD, val, 271 + (!(val & HS_E2P_CMD_EPC_BUSY_) || 272 + (val & HS_E2P_CMD_EPC_TIMEOUT_)), 273 + 50, 10000); 274 + } 275 + 276 + static int lan743x_hs_eeprom_read(struct lan743x_adapter *adapter, 277 + u32 offset, u32 length, u8 *data) 278 + { 279 + int retval; 280 + u32 val; 281 + int i; 282 + 283 + retval = lan743x_hs_syslock_acquire(adapter, LOCK_TIMEOUT_MAX_CNT); 284 + if (retval < 0) 285 + return retval; 286 + 287 + retval = lan743x_hs_eeprom_cmd_cmplt_chk(adapter); 288 + lan743x_hs_syslock_release(adapter); 289 + if (retval < 0) 290 + return retval; 291 + 292 + for (i = 0; i < length; i++) { 293 + retval = lan743x_hs_syslock_acquire(adapter, 294 + LOCK_TIMEOUT_MAX_CNT); 295 + if (retval < 0) 296 + return retval; 297 + 298 + val = HS_E2P_CMD_EPC_BUSY_ | HS_E2P_CMD_EPC_CMD_READ_; 299 + val |= (offset & HS_E2P_CMD_EPC_ADDR_MASK_); 300 + lan743x_csr_write(adapter, HS_E2P_CMD, val); 301 + retval = lan743x_hs_eeprom_cmd_cmplt_chk(adapter); 302 + if (retval < 0) { 303 + lan743x_hs_syslock_release(adapter); 304 + return retval; 305 + } 306 + 307 + val = lan743x_csr_read(adapter, HS_E2P_DATA); 308 + 309 + lan743x_hs_syslock_release(adapter); 310 + 311 + data[i] = val & 0xFF; 312 + offset++; 313 + } 314 + 315 + return 0; 316 + } 317 + 318 + static int lan743x_hs_eeprom_write(struct lan743x_adapter *adapter, 319 + u32 offset, u32 length, u8 *data) 320 + { 321 + int retval; 322 + u32 val; 323 + int i; 324 + 325 + retval = lan743x_hs_syslock_acquire(adapter, LOCK_TIMEOUT_MAX_CNT); 326 + if (retval < 0) 327 + return retval; 328 + 329 + retval = lan743x_hs_eeprom_cmd_cmplt_chk(adapter); 330 + lan743x_hs_syslock_release(adapter); 331 + if (retval < 0) 332 + return retval; 333 + 334 + for (i = 0; i < length; i++) { 335 + retval = lan743x_hs_syslock_acquire(adapter, 336 + LOCK_TIMEOUT_MAX_CNT); 337 + if (retval < 0) 338 + return retval; 339 + 340 + /* Fill data register */ 341 + val = data[i]; 342 + lan743x_csr_write(adapter, HS_E2P_DATA, val); 343 + 344 + /* Send "write" command */ 345 + val = HS_E2P_CMD_EPC_BUSY_ | HS_E2P_CMD_EPC_CMD_WRITE_; 346 + val |= (offset & HS_E2P_CMD_EPC_ADDR_MASK_); 347 + lan743x_csr_write(adapter, HS_E2P_CMD, val); 348 + 349 + retval = lan743x_hs_eeprom_cmd_cmplt_chk(adapter); 350 + lan743x_hs_syslock_release(adapter); 351 + if (retval < 0) 352 + return retval; 353 + 354 + offset++; 355 + } 356 + 357 + return 0; 358 + } 359 + 483 360 static void lan743x_ethtool_get_drvinfo(struct net_device *netdev, 484 361 struct ethtool_drvinfo *info) 485 362 { ··· 615 304 struct lan743x_adapter *adapter = netdev_priv(netdev); 616 305 int ret = 0; 617 306 618 - if (adapter->flags & LAN743X_ADAPTER_FLAG_OTP) 619 - ret = lan743x_otp_read(adapter, ee->offset, ee->len, data); 620 - else 621 - ret = lan743x_eeprom_read(adapter, ee->offset, ee->len, data); 307 + if (adapter->flags & LAN743X_ADAPTER_FLAG_OTP) { 308 + if (adapter->is_pci11x1x) 309 + ret = lan743x_hs_otp_read(adapter, ee->offset, 310 + ee->len, data); 311 + else 312 + ret = lan743x_otp_read(adapter, ee->offset, 313 + ee->len, data); 314 + } else { 315 + if (adapter->is_pci11x1x) 316 + ret = lan743x_hs_eeprom_read(adapter, ee->offset, 317 + ee->len, data); 318 + else 319 + ret = lan743x_eeprom_read(adapter, ee->offset, 320 + ee->len, data); 321 + } 622 322 623 323 return ret; 624 324 } ··· 643 321 if (adapter->flags & LAN743X_ADAPTER_FLAG_OTP) { 644 322 /* Beware! OTP is One Time Programming ONLY! */ 645 323 if (ee->magic == LAN743X_OTP_MAGIC) { 646 - ret = lan743x_otp_write(adapter, ee->offset, 647 - ee->len, data); 324 + if (adapter->is_pci11x1x) 325 + ret = lan743x_hs_otp_write(adapter, ee->offset, 326 + ee->len, data); 327 + else 328 + ret = lan743x_otp_write(adapter, ee->offset, 329 + ee->len, data); 648 330 } 649 331 } else { 650 332 if (ee->magic == LAN743X_EEPROM_MAGIC) { 651 - ret = lan743x_eeprom_write(adapter, ee->offset, 652 - ee->len, data); 333 + if (adapter->is_pci11x1x) 334 + ret = lan743x_hs_eeprom_write(adapter, 335 + ee->offset, 336 + ee->len, data); 337 + else 338 + ret = lan743x_eeprom_write(adapter, ee->offset, 339 + ee->len, data); 653 340 } 654 341 } 655 342 ··· 694 363 "RX Queue 1 Frames", 695 364 "RX Queue 2 Frames", 696 365 "RX Queue 3 Frames", 366 + }; 367 + 368 + static const char lan743x_tx_queue_cnt_strings[][ETH_GSTRING_LEN] = { 369 + "TX Queue 0 Frames", 370 + "TX Queue 1 Frames", 371 + "TX Queue 2 Frames", 372 + "TX Queue 3 Frames", 373 + "TX Total Queue Frames", 697 374 }; 698 375 699 376 static const char lan743x_set2_hw_cnt_strings[][ETH_GSTRING_LEN] = { ··· 801 462 static void lan743x_ethtool_get_strings(struct net_device *netdev, 802 463 u32 stringset, u8 *data) 803 464 { 465 + struct lan743x_adapter *adapter = netdev_priv(netdev); 466 + 804 467 switch (stringset) { 805 468 case ETH_SS_STATS: 806 469 memcpy(data, lan743x_set0_hw_cnt_strings, ··· 814 473 sizeof(lan743x_set1_sw_cnt_strings)], 815 474 lan743x_set2_hw_cnt_strings, 816 475 sizeof(lan743x_set2_hw_cnt_strings)); 476 + if (adapter->is_pci11x1x) { 477 + memcpy(&data[sizeof(lan743x_set0_hw_cnt_strings) + 478 + sizeof(lan743x_set1_sw_cnt_strings) + 479 + sizeof(lan743x_set2_hw_cnt_strings)], 480 + lan743x_tx_queue_cnt_strings, 481 + sizeof(lan743x_tx_queue_cnt_strings)); 482 + } 817 483 break; 818 484 case ETH_SS_PRIV_FLAGS: 819 485 memcpy(data, lan743x_priv_flags_strings, ··· 834 486 u64 *data) 835 487 { 836 488 struct lan743x_adapter *adapter = netdev_priv(netdev); 489 + u64 total_queue_count = 0; 837 490 int data_index = 0; 491 + u64 pkt_cnt; 838 492 u32 buf; 839 493 int i; 840 494 ··· 849 499 for (i = 0; i < ARRAY_SIZE(lan743x_set2_hw_cnt_addr); i++) { 850 500 buf = lan743x_csr_read(adapter, lan743x_set2_hw_cnt_addr[i]); 851 501 data[data_index++] = (u64)buf; 502 + } 503 + if (adapter->is_pci11x1x) { 504 + for (i = 0; i < ARRAY_SIZE(adapter->tx); i++) { 505 + pkt_cnt = (u64)(adapter->tx[i].frame_count); 506 + data[data_index++] = pkt_cnt; 507 + total_queue_count += pkt_cnt; 508 + } 509 + data[data_index++] = total_queue_count; 852 510 } 853 511 } 854 512 ··· 878 520 879 521 static int lan743x_ethtool_get_sset_count(struct net_device *netdev, int sset) 880 522 { 523 + struct lan743x_adapter *adapter = netdev_priv(netdev); 524 + 881 525 switch (sset) { 882 526 case ETH_SS_STATS: 883 527 { ··· 888 528 ret = ARRAY_SIZE(lan743x_set0_hw_cnt_strings); 889 529 ret += ARRAY_SIZE(lan743x_set1_sw_cnt_strings); 890 530 ret += ARRAY_SIZE(lan743x_set2_hw_cnt_strings); 531 + if (adapter->is_pci11x1x) 532 + ret += ARRAY_SIZE(lan743x_tx_queue_cnt_strings); 891 533 return ret; 892 534 } 893 535 case ETH_SS_PRIV_FLAGS:

+2

drivers/net/ethernet/microchip/lan743x_main.c

··· 1776 1776 dev_kfree_skb_irq(skb); 1777 1777 goto unlock; 1778 1778 } 1779 + tx->frame_count++; 1779 1780 1780 1781 if (gso) 1781 1782 lan743x_tx_frame_add_lso(tx, frame_length, nr_frags); ··· 2869 2868 adapter->used_tx_channels = PCI11X1X_USED_TX_CHANNELS; 2870 2869 adapter->max_vector_count = PCI11X1X_MAX_VECTOR_COUNT; 2871 2870 pci11x1x_strap_get_status(adapter); 2871 + spin_lock_init(&adapter->eth_syslock_spinlock); 2872 2872 } else { 2873 2873 adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS; 2874 2874 adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS;

+159

drivers/net/ethernet/microchip/lan743x_main.h

··· 86 86 87 87 #define E2P_DATA (0x044) 88 88 89 + /* Hearthstone top level & System Reg Addresses */ 90 + #define ETH_CTRL_REG_ADDR_BASE (0x0000) 91 + #define ETH_SYS_REG_ADDR_BASE (0x4000) 92 + #define CONFIG_REG_ADDR_BASE (0x0000) 93 + #define ETH_EEPROM_REG_ADDR_BASE (0x0E00) 94 + #define ETH_OTP_REG_ADDR_BASE (0x1000) 95 + #define SYS_LOCK_REG (0x00A0) 96 + #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7) 97 + #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5) 98 + #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4) 99 + #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3) 100 + #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2) 101 + #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1) 102 + #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0) 103 + #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \ 104 + CONFIG_REG_ADDR_BASE + \ 105 + SYS_LOCK_REG) 106 + #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \ 107 + ETH_EEPROM_REG_ADDR_BASE) 108 + #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000) 109 + #define HS_E2P_CMD_EPC_BUSY_ BIT(31) 110 + #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28) 111 + #define HS_E2P_CMD_EPC_CMD_READ_ (0x0) 112 + #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17) 113 + #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0) 114 + #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004) 115 + #define HS_E2P_DATA_MASK_ GENMASK(7, 0) 116 + #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008) 117 + #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16) 118 + #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12) 119 + #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8) 120 + #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0) 121 + #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C) 122 + 89 123 #define GPIO_CFG0 (0x050) 90 124 #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 91 125 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) ··· 336 302 #define INT_MOD_CFG9 (0x7E4) 337 303 338 304 #define PTP_CMD_CTL (0x0A00) 305 + #define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13) 339 306 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 340 307 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 341 308 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) ··· 358 323 (((value) & 0x7) << (1 + ((channel) << 2))) 359 324 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 360 325 326 + #define HS_PTP_GENERAL_CONFIG (0x0A04) 327 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 328 + (0xf << (4 + ((channel) << 2))) 329 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 330 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1) 331 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2) 332 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3) 333 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4) 334 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5) 335 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6) 336 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7) 337 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8) 338 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9) 339 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10) 340 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11) 341 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12) 342 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13) 343 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14) 344 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15) 345 + #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 346 + (((value) & 0xf) << (4 + ((channel) << 2))) 347 + #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) 348 + #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) 349 + 361 350 #define PTP_INT_STS (0x0A08) 351 + #define PTP_INT_IO_FE_MASK_ GENMASK(31, 24) 352 + #define PTP_INT_IO_FE_SHIFT_ (24) 353 + #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) 354 + #define PTP_INT_IO_RE_MASK_ GENMASK(23, 16) 355 + #define PTP_INT_IO_RE_SHIFT_ (16) 356 + #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) 357 + #define PTP_INT_TX_TS_OVRFL_INT_ BIT(14) 358 + #define PTP_INT_TX_SWTS_ERR_INT_ BIT(13) 359 + #define PTP_INT_TX_TS_INT_ BIT(12) 360 + #define PTP_INT_RX_TS_OVRFL_INT_ BIT(9) 361 + #define PTP_INT_RX_TS_INT_ BIT(8) 362 + #define PTP_INT_TIMER_INT_B_ BIT(1) 363 + #define PTP_INT_TIMER_INT_A_ BIT(0) 362 364 #define PTP_INT_EN_SET (0x0A0C) 365 + #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) 366 + #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) 367 + #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) 363 368 #define PTP_INT_EN_CLR (0x0A10) 369 + #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) 370 + #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) 364 371 #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 365 372 #define PTP_INT_BIT_TX_TS_ BIT(12) 366 373 #define PTP_INT_BIT_TIMER_B_ BIT(1) ··· 420 343 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 421 344 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 422 345 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 346 + #define PTP_LTC_SET_SEC_HI (0x0A50) 347 + #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 348 + #define PTP_VERSION (0x0A54) 349 + #define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24) 350 + #define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16) 351 + #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8) 352 + #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0) 353 + #define PTP_IO_SEL (0x0A58) 354 + #define PTP_IO_SEL_MASK_ GENMASK(10, 8) 355 + #define PTP_IO_SEL_SHIFT_ (8) 423 356 #define PTP_LATENCY (0x0A5C) 424 357 #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 425 358 #define PTP_LATENCY_RX_SET_(rx_latency) \ ··· 453 366 #define PTP_TX_MSG_HEADER (0x0AB4) 454 367 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 455 368 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 369 + 370 + #define PTP_TX_CAP_INFO (0x0AB8) 371 + #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0) 372 + #define PTP_TX_DOMAIN (0x0ABC) 373 + #define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16) 374 + #define PTP_TX_DOMAIN_RANGE_EN_ BIT(15) 375 + #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0) 376 + #define PTP_TX_SDOID (0x0AC0) 377 + #define PTP_TX_SDOID_MASK_ GENMASK(23, 16) 378 + #define PTP_TX_SDOID_RANGE_EN_ BIT(15) 379 + #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0) 380 + #define PTP_IO_CAP_CONFIG (0x0AC4) 381 + #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) 382 + #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) 383 + #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) 384 + #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) 385 + #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8) 386 + #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC) 387 + #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0) 388 + #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4) 389 + #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8) 390 + #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) 391 + #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) 392 + #define PTP_IO_PIN_CFG (0x0ADC) 393 + #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) 394 + #define PTP_LTC_RD_SEC_HI (0x0AF0) 395 + #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 396 + #define PTP_LTC_RD_SEC_LO (0x0AF4) 397 + #define PTP_LTC_RD_NS (0x0AF8) 398 + #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0) 399 + #define PTP_LTC_RD_SUBNS (0x0AFC) 400 + #define PTP_RX_USER_MAC_HI (0x0B00) 401 + #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 402 + #define PTP_RX_USER_MAC_LO (0x0B04) 403 + #define PTP_RX_USER_IP_ADDR_0 (0x0B20) 404 + #define PTP_RX_USER_IP_ADDR_1 (0x0B24) 405 + #define PTP_RX_USER_IP_ADDR_2 (0x0B28) 406 + #define PTP_RX_USER_IP_ADDR_3 (0x0B2C) 407 + #define PTP_RX_USER_IP_MASK_0 (0x0B30) 408 + #define PTP_RX_USER_IP_MASK_1 (0x0B34) 409 + #define PTP_RX_USER_IP_MASK_2 (0x0B38) 410 + #define PTP_RX_USER_IP_MASK_3 (0x0B3C) 411 + #define PTP_TX_USER_MAC_HI (0x0B40) 412 + #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 413 + #define PTP_TX_USER_MAC_LO (0x0B44) 414 + #define PTP_TX_USER_IP_ADDR_0 (0x0B60) 415 + #define PTP_TX_USER_IP_ADDR_1 (0x0B64) 416 + #define PTP_TX_USER_IP_ADDR_2 (0x0B68) 417 + #define PTP_TX_USER_IP_ADDR_3 (0x0B6C) 418 + #define PTP_TX_USER_IP_MASK_0 (0x0B70) 419 + #define PTP_TX_USER_IP_MASK_1 (0x0B74) 420 + #define PTP_TX_USER_IP_MASK_2 (0x0B78) 421 + #define PTP_TX_USER_IP_MASK_3 (0x0B7C) 456 422 457 423 #define DMAC_CFG (0xC00) 458 424 #define DMAC_CFG_COAL_EN_ BIT(16) ··· 661 521 662 522 #define OTP_STATUS (0x1030) 663 523 #define OTP_STATUS_BUSY_ BIT(0) 524 + 525 + /* Hearthstone OTP block registers */ 526 + #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \ 527 + ETH_OTP_REG_ADDR_BASE) 528 + #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0) 529 + #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4) 530 + #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8) 531 + #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10) 532 + #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14) 533 + #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18) 534 + #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20) 535 + #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24) 536 + #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28) 537 + #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30) 664 538 665 539 /* MAC statistics registers */ 666 540 #define STAT_RX_FCS_ERRORS (0x1200) ··· 869 715 int last_tail; 870 716 871 717 struct napi_struct napi; 718 + u32 frame_count; 872 719 873 720 struct sk_buff *overflow_skb; 874 721 }; ··· 927 772 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 928 773 bool is_pci11x1x; 929 774 bool is_sgmii_en; 775 + /* protect ethernet syslock */ 776 + spinlock_t eth_syslock_spinlock; 777 + bool eth_syslock_en; 778 + u32 eth_syslock_acquire_cnt; 930 779 u8 max_tx_channels; 931 780 u8 used_tx_channels; 932 781 u8 max_vector_count;

+518 -36

drivers/net/ethernet/microchip/lan743x_ptp.c

··· 25 25 u32 seconds, u32 nano_seconds, 26 26 u32 sub_nano_seconds); 27 27 28 + static int lan743x_get_channel(u32 ch_map) 29 + { 30 + int idx; 31 + 32 + for (idx = 0; idx < 32; idx++) { 33 + if (ch_map & (0x1 << idx)) 34 + return idx; 35 + } 36 + 37 + return -EINVAL; 38 + } 39 + 28 40 int lan743x_gpio_init(struct lan743x_adapter *adapter) 29 41 { 30 42 struct lan743x_gpio *gpio = &adapter->gpio; ··· 191 179 static void lan743x_ptp_clock_get(struct lan743x_adapter *adapter, 192 180 u32 *seconds, u32 *nano_seconds, 193 181 u32 *sub_nano_seconds); 182 + static void lan743x_ptp_io_clock_get(struct lan743x_adapter *adapter, 183 + u32 *sec, u32 *nsec, u32 *sub_nsec); 194 184 static void lan743x_ptp_clock_step(struct lan743x_adapter *adapter, 195 185 s64 time_step_ns); 196 186 ··· 421 407 u32 nano_seconds = 0; 422 408 u32 seconds = 0; 423 409 424 - lan743x_ptp_clock_get(adapter, &seconds, &nano_seconds, NULL); 410 + if (adapter->is_pci11x1x) 411 + lan743x_ptp_io_clock_get(adapter, &seconds, &nano_seconds, 412 + NULL); 413 + else 414 + lan743x_ptp_clock_get(adapter, &seconds, &nano_seconds, NULL); 425 415 ts->tv_sec = seconds; 426 416 ts->tv_nsec = nano_seconds; 427 417 ··· 689 671 return ret; 690 672 } 691 673 674 + static void lan743x_ptp_io_perout_off(struct lan743x_adapter *adapter, 675 + u32 index) 676 + { 677 + struct lan743x_ptp *ptp = &adapter->ptp; 678 + int perout_pin; 679 + int event_ch; 680 + u32 gen_cfg; 681 + int val; 682 + 683 + event_ch = ptp->ptp_io_perout[index]; 684 + if (event_ch >= 0) { 685 + /* set target to far in the future, effectively disabling it */ 686 + lan743x_csr_write(adapter, 687 + PTP_CLOCK_TARGET_SEC_X(event_ch), 688 + 0xFFFF0000); 689 + lan743x_csr_write(adapter, 690 + PTP_CLOCK_TARGET_NS_X(event_ch), 691 + 0); 692 + 693 + gen_cfg = lan743x_csr_read(adapter, HS_PTP_GENERAL_CONFIG); 694 + gen_cfg &= ~(HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_ 695 + (event_ch)); 696 + gen_cfg &= ~(HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(event_ch)); 697 + gen_cfg |= HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(event_ch); 698 + lan743x_csr_write(adapter, HS_PTP_GENERAL_CONFIG, gen_cfg); 699 + if (event_ch) 700 + lan743x_csr_write(adapter, PTP_INT_STS, 701 + PTP_INT_TIMER_INT_B_); 702 + else 703 + lan743x_csr_write(adapter, PTP_INT_STS, 704 + PTP_INT_TIMER_INT_A_); 705 + lan743x_ptp_release_event_ch(adapter, event_ch); 706 + ptp->ptp_io_perout[index] = -1; 707 + } 708 + 709 + perout_pin = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, index); 710 + 711 + /* Deselect Event output */ 712 + val = lan743x_csr_read(adapter, PTP_IO_EVENT_OUTPUT_CFG); 713 + 714 + /* Disables the output of Local Time Target compare events */ 715 + val &= ~PTP_IO_EVENT_OUTPUT_CFG_EN_(perout_pin); 716 + lan743x_csr_write(adapter, PTP_IO_EVENT_OUTPUT_CFG, val); 717 + 718 + /* Configured as an opendrain driver*/ 719 + val = lan743x_csr_read(adapter, PTP_IO_PIN_CFG); 720 + val &= ~PTP_IO_PIN_CFG_OBUF_TYPE_(perout_pin); 721 + lan743x_csr_write(adapter, PTP_IO_PIN_CFG, val); 722 + /* Dummy read to make sure write operation success */ 723 + val = lan743x_csr_read(adapter, PTP_IO_PIN_CFG); 724 + } 725 + 726 + static int lan743x_ptp_io_perout(struct lan743x_adapter *adapter, int on, 727 + struct ptp_perout_request *perout_request) 728 + { 729 + struct lan743x_ptp *ptp = &adapter->ptp; 730 + u32 period_sec, period_nsec; 731 + u32 start_sec, start_nsec; 732 + u32 pulse_sec, pulse_nsec; 733 + int pulse_width; 734 + int perout_pin; 735 + int event_ch; 736 + u32 gen_cfg; 737 + u32 index; 738 + int val; 739 + 740 + index = perout_request->index; 741 + event_ch = ptp->ptp_io_perout[index]; 742 + 743 + if (on) { 744 + perout_pin = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, index); 745 + if (perout_pin < 0) 746 + return -EBUSY; 747 + } else { 748 + lan743x_ptp_io_perout_off(adapter, index); 749 + return 0; 750 + } 751 + 752 + if (event_ch >= LAN743X_PTP_N_EVENT_CHAN) { 753 + /* already on, turn off first */ 754 + lan743x_ptp_io_perout_off(adapter, index); 755 + } 756 + 757 + event_ch = lan743x_ptp_reserve_event_ch(adapter, index); 758 + if (event_ch < 0) { 759 + netif_warn(adapter, drv, adapter->netdev, 760 + "Failed to reserve event channel %d for PEROUT\n", 761 + index); 762 + goto failed; 763 + } 764 + ptp->ptp_io_perout[index] = event_ch; 765 + 766 + if (perout_request->flags & PTP_PEROUT_DUTY_CYCLE) { 767 + pulse_sec = perout_request->on.sec; 768 + pulse_sec += perout_request->on.nsec / 1000000000; 769 + pulse_nsec = perout_request->on.nsec % 1000000000; 770 + } else { 771 + pulse_sec = perout_request->period.sec; 772 + pulse_sec += perout_request->period.nsec / 1000000000; 773 + pulse_nsec = perout_request->period.nsec % 1000000000; 774 + } 775 + 776 + if (pulse_sec == 0) { 777 + if (pulse_nsec >= 400000000) { 778 + pulse_width = PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_; 779 + } else if (pulse_nsec >= 200000000) { 780 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_; 781 + } else if (pulse_nsec >= 100000000) { 782 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_; 783 + } else if (pulse_nsec >= 20000000) { 784 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_; 785 + } else if (pulse_nsec >= 10000000) { 786 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_; 787 + } else if (pulse_nsec >= 2000000) { 788 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_; 789 + } else if (pulse_nsec >= 1000000) { 790 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_; 791 + } else if (pulse_nsec >= 200000) { 792 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_; 793 + } else if (pulse_nsec >= 100000) { 794 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_; 795 + } else if (pulse_nsec >= 20000) { 796 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_; 797 + } else if (pulse_nsec >= 10000) { 798 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_; 799 + } else if (pulse_nsec >= 2000) { 800 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_; 801 + } else if (pulse_nsec >= 1000) { 802 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_; 803 + } else if (pulse_nsec >= 200) { 804 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_; 805 + } else { 806 + netif_warn(adapter, drv, adapter->netdev, 807 + "perout period too small, min is 200nS\n"); 808 + goto failed; 809 + } 810 + } else { 811 + pulse_width = HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_; 812 + } 813 + 814 + /* turn off by setting target far in future */ 815 + lan743x_csr_write(adapter, 816 + PTP_CLOCK_TARGET_SEC_X(event_ch), 817 + 0xFFFF0000); 818 + lan743x_csr_write(adapter, 819 + PTP_CLOCK_TARGET_NS_X(event_ch), 0); 820 + 821 + /* Configure to pulse every period */ 822 + gen_cfg = lan743x_csr_read(adapter, HS_PTP_GENERAL_CONFIG); 823 + gen_cfg &= ~(HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(event_ch)); 824 + gen_cfg |= HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_ 825 + (event_ch, pulse_width); 826 + gen_cfg |= HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(event_ch); 827 + gen_cfg &= ~(HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(event_ch)); 828 + lan743x_csr_write(adapter, HS_PTP_GENERAL_CONFIG, gen_cfg); 829 + 830 + /* set the reload to one toggle cycle */ 831 + period_sec = perout_request->period.sec; 832 + period_sec += perout_request->period.nsec / 1000000000; 833 + period_nsec = perout_request->period.nsec % 1000000000; 834 + lan743x_csr_write(adapter, 835 + PTP_CLOCK_TARGET_RELOAD_SEC_X(event_ch), 836 + period_sec); 837 + lan743x_csr_write(adapter, 838 + PTP_CLOCK_TARGET_RELOAD_NS_X(event_ch), 839 + period_nsec); 840 + 841 + start_sec = perout_request->start.sec; 842 + start_sec += perout_request->start.nsec / 1000000000; 843 + start_nsec = perout_request->start.nsec % 1000000000; 844 + 845 + /* set the start time */ 846 + lan743x_csr_write(adapter, 847 + PTP_CLOCK_TARGET_SEC_X(event_ch), 848 + start_sec); 849 + lan743x_csr_write(adapter, 850 + PTP_CLOCK_TARGET_NS_X(event_ch), 851 + start_nsec); 852 + 853 + /* Enable LTC Target Read */ 854 + val = lan743x_csr_read(adapter, PTP_CMD_CTL); 855 + val |= PTP_CMD_CTL_PTP_LTC_TARGET_READ_; 856 + lan743x_csr_write(adapter, PTP_CMD_CTL, val); 857 + 858 + /* Configure as an push/pull driver */ 859 + val = lan743x_csr_read(adapter, PTP_IO_PIN_CFG); 860 + val |= PTP_IO_PIN_CFG_OBUF_TYPE_(perout_pin); 861 + lan743x_csr_write(adapter, PTP_IO_PIN_CFG, val); 862 + 863 + /* Select Event output */ 864 + val = lan743x_csr_read(adapter, PTP_IO_EVENT_OUTPUT_CFG); 865 + if (event_ch) 866 + /* Channel B as the output */ 867 + val |= PTP_IO_EVENT_OUTPUT_CFG_SEL_(perout_pin); 868 + else 869 + /* Channel A as the output */ 870 + val &= ~PTP_IO_EVENT_OUTPUT_CFG_SEL_(perout_pin); 871 + 872 + /* Enables the output of Local Time Target compare events */ 873 + val |= PTP_IO_EVENT_OUTPUT_CFG_EN_(perout_pin); 874 + lan743x_csr_write(adapter, PTP_IO_EVENT_OUTPUT_CFG, val); 875 + 876 + return 0; 877 + 878 + failed: 879 + lan743x_ptp_io_perout_off(adapter, index); 880 + return -ENODEV; 881 + } 882 + 883 + static void lan743x_ptp_io_extts_off(struct lan743x_adapter *adapter, 884 + u32 index) 885 + { 886 + struct lan743x_ptp *ptp = &adapter->ptp; 887 + struct lan743x_extts *extts; 888 + int val; 889 + 890 + extts = &ptp->extts[index]; 891 + /* PTP Interrupt Enable Clear Register */ 892 + if (extts->flags & PTP_FALLING_EDGE) 893 + val = PTP_INT_EN_FE_EN_CLR_(index); 894 + else 895 + val = PTP_INT_EN_RE_EN_CLR_(index); 896 + lan743x_csr_write(adapter, PTP_INT_EN_CLR, val); 897 + 898 + /* Disables PTP-IO edge lock */ 899 + val = lan743x_csr_read(adapter, PTP_IO_CAP_CONFIG); 900 + if (extts->flags & PTP_FALLING_EDGE) { 901 + val &= ~PTP_IO_CAP_CONFIG_LOCK_FE_(index); 902 + val &= ~PTP_IO_CAP_CONFIG_FE_CAP_EN_(index); 903 + } else { 904 + val &= ~PTP_IO_CAP_CONFIG_LOCK_RE_(index); 905 + val &= ~PTP_IO_CAP_CONFIG_RE_CAP_EN_(index); 906 + } 907 + lan743x_csr_write(adapter, PTP_IO_CAP_CONFIG, val); 908 + 909 + /* PTP-IO De-select register */ 910 + val = lan743x_csr_read(adapter, PTP_IO_SEL); 911 + val &= ~PTP_IO_SEL_MASK_; 912 + lan743x_csr_write(adapter, PTP_IO_SEL, val); 913 + 914 + /* Clear timestamp */ 915 + memset(&extts->ts, 0, sizeof(struct timespec64)); 916 + extts->flags = 0; 917 + } 918 + 919 + static int lan743x_ptp_io_event_cap_en(struct lan743x_adapter *adapter, 920 + u32 flags, u32 channel) 921 + { 922 + struct lan743x_ptp *ptp = &adapter->ptp; 923 + int val; 924 + 925 + if ((flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 926 + return -EOPNOTSUPP; 927 + 928 + mutex_lock(&ptp->command_lock); 929 + /* PTP-IO Event Capture Enable */ 930 + val = lan743x_csr_read(adapter, PTP_IO_CAP_CONFIG); 931 + if (flags & PTP_FALLING_EDGE) { 932 + val &= ~PTP_IO_CAP_CONFIG_LOCK_RE_(channel); 933 + val &= ~PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel); 934 + val |= PTP_IO_CAP_CONFIG_LOCK_FE_(channel); 935 + val |= PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel); 936 + } else { 937 + /* Rising eventing as Default */ 938 + val &= ~PTP_IO_CAP_CONFIG_LOCK_FE_(channel); 939 + val &= ~PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel); 940 + val |= PTP_IO_CAP_CONFIG_LOCK_RE_(channel); 941 + val |= PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel); 942 + } 943 + lan743x_csr_write(adapter, PTP_IO_CAP_CONFIG, val); 944 + 945 + /* PTP-IO Select */ 946 + val = lan743x_csr_read(adapter, PTP_IO_SEL); 947 + val &= ~PTP_IO_SEL_MASK_; 948 + val |= channel << PTP_IO_SEL_SHIFT_; 949 + lan743x_csr_write(adapter, PTP_IO_SEL, val); 950 + 951 + /* PTP Interrupt Enable Register */ 952 + if (flags & PTP_FALLING_EDGE) 953 + val = PTP_INT_EN_FE_EN_SET_(channel); 954 + else 955 + val = PTP_INT_EN_RE_EN_SET_(channel); 956 + lan743x_csr_write(adapter, PTP_INT_EN_SET, val); 957 + 958 + mutex_unlock(&ptp->command_lock); 959 + 960 + return 0; 961 + } 962 + 963 + static int lan743x_ptp_io_extts(struct lan743x_adapter *adapter, int on, 964 + struct ptp_extts_request *extts_request) 965 + { 966 + struct lan743x_ptp *ptp = &adapter->ptp; 967 + u32 flags = extts_request->flags; 968 + u32 index = extts_request->index; 969 + struct lan743x_extts *extts; 970 + int extts_pin; 971 + int ret = 0; 972 + 973 + extts = &ptp->extts[index]; 974 + 975 + if (on) { 976 + extts_pin = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, index); 977 + if (extts_pin < 0) 978 + return -EBUSY; 979 + 980 + ret = lan743x_ptp_io_event_cap_en(adapter, flags, index); 981 + if (!ret) 982 + extts->flags = flags; 983 + } else { 984 + lan743x_ptp_io_extts_off(adapter, index); 985 + } 986 + 987 + return ret; 988 + } 989 + 692 990 static int lan743x_ptpci_enable(struct ptp_clock_info *ptpci, 693 991 struct ptp_clock_request *request, int on) 694 992 { ··· 1016 682 if (request) { 1017 683 switch (request->type) { 1018 684 case PTP_CLK_REQ_EXTTS: 685 + if (request->extts.index < ptpci->n_ext_ts) 686 + return lan743x_ptp_io_extts(adapter, on, 687 + &request->extts); 1019 688 return -EINVAL; 1020 689 case PTP_CLK_REQ_PEROUT: 1021 - if (request->perout.index < ptpci->n_per_out) 1022 - return lan743x_ptp_perout(adapter, on, 690 + if (request->perout.index < ptpci->n_per_out) { 691 + if (adapter->is_pci11x1x) 692 + return lan743x_ptp_io_perout(adapter, on, 693 + &request->perout); 694 + else 695 + return lan743x_ptp_perout(adapter, on, 1023 696 &request->perout); 697 + } 1024 698 return -EINVAL; 1025 699 case PTP_CLK_REQ_PPS: 1026 700 return -EINVAL; ··· 1057 715 switch (func) { 1058 716 case PTP_PF_NONE: 1059 717 case PTP_PF_PEROUT: 1060 - break; 1061 718 case PTP_PF_EXTTS: 719 + break; 1062 720 case PTP_PF_PHYSYNC: 1063 721 default: 1064 722 result = -1; 1065 723 break; 1066 724 } 1067 725 return result; 726 + } 727 + 728 + static void lan743x_ptp_io_event_clock_get(struct lan743x_adapter *adapter, 729 + bool fe, u8 channel, 730 + struct timespec64 *ts) 731 + { 732 + struct lan743x_ptp *ptp = &adapter->ptp; 733 + struct lan743x_extts *extts; 734 + u32 sec, nsec; 735 + 736 + mutex_lock(&ptp->command_lock); 737 + if (fe) { 738 + sec = lan743x_csr_read(adapter, PTP_IO_FE_LTC_SEC_CAP_X); 739 + nsec = lan743x_csr_read(adapter, PTP_IO_FE_LTC_NS_CAP_X); 740 + } else { 741 + sec = lan743x_csr_read(adapter, PTP_IO_RE_LTC_SEC_CAP_X); 742 + nsec = lan743x_csr_read(adapter, PTP_IO_RE_LTC_NS_CAP_X); 743 + } 744 + 745 + mutex_unlock(&ptp->command_lock); 746 + 747 + /* Update Local timestamp */ 748 + extts = &ptp->extts[channel]; 749 + extts->ts.tv_sec = sec; 750 + extts->ts.tv_nsec = nsec; 751 + ts->tv_sec = sec; 752 + ts->tv_nsec = nsec; 1068 753 } 1069 754 1070 755 static long lan743x_ptpci_do_aux_work(struct ptp_clock_info *ptpci) ··· 1102 733 container_of(ptp, struct lan743x_adapter, ptp); 1103 734 u32 cap_info, cause, header, nsec, seconds; 1104 735 bool new_timestamp_available = false; 736 + struct ptp_clock_event ptp_event; 737 + struct timespec64 ts; 738 + int ptp_int_sts; 1105 739 int count = 0; 740 + int channel; 741 + s64 ns; 1106 742 1107 - while ((count < 100) && 1108 - (lan743x_csr_read(adapter, PTP_INT_STS) & PTP_INT_BIT_TX_TS_)) { 743 + ptp_int_sts = lan743x_csr_read(adapter, PTP_INT_STS); 744 + while ((count < 100) && ptp_int_sts) { 1109 745 count++; 1110 - cap_info = lan743x_csr_read(adapter, PTP_CAP_INFO); 1111 746 1112 - if (PTP_CAP_INFO_TX_TS_CNT_GET_(cap_info) > 0) { 1113 - seconds = lan743x_csr_read(adapter, 1114 - PTP_TX_EGRESS_SEC); 1115 - nsec = lan743x_csr_read(adapter, PTP_TX_EGRESS_NS); 1116 - cause = (nsec & 1117 - PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_); 1118 - header = lan743x_csr_read(adapter, 1119 - PTP_TX_MSG_HEADER); 747 + if (ptp_int_sts & PTP_INT_BIT_TX_TS_) { 748 + cap_info = lan743x_csr_read(adapter, PTP_CAP_INFO); 1120 749 1121 - if (cause == PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_) { 1122 - nsec &= PTP_TX_EGRESS_NS_TS_NS_MASK_; 1123 - lan743x_ptp_tx_ts_enqueue_ts(adapter, 1124 - seconds, nsec, 1125 - header); 1126 - new_timestamp_available = true; 1127 - } else if (cause == 1128 - PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_) { 1129 - netif_err(adapter, drv, adapter->netdev, 1130 - "Auto capture cause not supported\n"); 750 + if (PTP_CAP_INFO_TX_TS_CNT_GET_(cap_info) > 0) { 751 + seconds = lan743x_csr_read(adapter, 752 + PTP_TX_EGRESS_SEC); 753 + nsec = lan743x_csr_read(adapter, 754 + PTP_TX_EGRESS_NS); 755 + cause = (nsec & 756 + PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_); 757 + header = lan743x_csr_read(adapter, 758 + PTP_TX_MSG_HEADER); 759 + 760 + if (cause == 761 + PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_) { 762 + nsec &= PTP_TX_EGRESS_NS_TS_NS_MASK_; 763 + lan743x_ptp_tx_ts_enqueue_ts(adapter, 764 + seconds, 765 + nsec, 766 + header); 767 + new_timestamp_available = true; 768 + } else if (cause == 769 + PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_) { 770 + netif_err(adapter, drv, adapter->netdev, 771 + "Auto capture cause not supported\n"); 772 + } else { 773 + netif_warn(adapter, drv, adapter->netdev, 774 + "unknown tx timestamp capture cause\n"); 775 + } 1131 776 } else { 1132 777 netif_warn(adapter, drv, adapter->netdev, 1133 - "unknown tx timestamp capture cause\n"); 778 + "TX TS INT but no TX TS CNT\n"); 1134 779 } 1135 - } else { 1136 - netif_warn(adapter, drv, adapter->netdev, 1137 - "TX TS INT but no TX TS CNT\n"); 780 + lan743x_csr_write(adapter, PTP_INT_STS, 781 + PTP_INT_BIT_TX_TS_); 1138 782 } 1139 - lan743x_csr_write(adapter, PTP_INT_STS, PTP_INT_BIT_TX_TS_); 783 + 784 + if (ptp_int_sts & PTP_INT_IO_FE_MASK_) { 785 + do { 786 + channel = lan743x_get_channel((ptp_int_sts & 787 + PTP_INT_IO_FE_MASK_) >> 788 + PTP_INT_IO_FE_SHIFT_); 789 + if (channel >= 0 && 790 + channel < PCI11X1X_PTP_IO_MAX_CHANNELS) { 791 + lan743x_ptp_io_event_clock_get(adapter, 792 + true, 793 + channel, 794 + &ts); 795 + /* PTP Falling Event post */ 796 + ns = timespec64_to_ns(&ts); 797 + ptp_event.timestamp = ns; 798 + ptp_event.index = channel; 799 + ptp_event.type = PTP_CLOCK_EXTTS; 800 + ptp_clock_event(ptp->ptp_clock, 801 + &ptp_event); 802 + lan743x_csr_write(adapter, PTP_INT_STS, 803 + PTP_INT_IO_FE_SET_ 804 + (channel)); 805 + ptp_int_sts &= ~(1 << 806 + (PTP_INT_IO_FE_SHIFT_ + 807 + channel)); 808 + } else { 809 + /* Clear falling event interrupts */ 810 + lan743x_csr_write(adapter, PTP_INT_STS, 811 + PTP_INT_IO_FE_MASK_); 812 + ptp_int_sts &= ~PTP_INT_IO_FE_MASK_; 813 + } 814 + } while (ptp_int_sts & PTP_INT_IO_FE_MASK_); 815 + } 816 + 817 + if (ptp_int_sts & PTP_INT_IO_RE_MASK_) { 818 + do { 819 + channel = lan743x_get_channel((ptp_int_sts & 820 + PTP_INT_IO_RE_MASK_) >> 821 + PTP_INT_IO_RE_SHIFT_); 822 + if (channel >= 0 && 823 + channel < PCI11X1X_PTP_IO_MAX_CHANNELS) { 824 + lan743x_ptp_io_event_clock_get(adapter, 825 + false, 826 + channel, 827 + &ts); 828 + /* PTP Rising Event post */ 829 + ns = timespec64_to_ns(&ts); 830 + ptp_event.timestamp = ns; 831 + ptp_event.index = channel; 832 + ptp_event.type = PTP_CLOCK_EXTTS; 833 + ptp_clock_event(ptp->ptp_clock, 834 + &ptp_event); 835 + lan743x_csr_write(adapter, PTP_INT_STS, 836 + PTP_INT_IO_RE_SET_ 837 + (channel)); 838 + ptp_int_sts &= ~(1 << 839 + (PTP_INT_IO_RE_SHIFT_ + 840 + channel)); 841 + } else { 842 + /* Clear Rising event interrupt */ 843 + lan743x_csr_write(adapter, PTP_INT_STS, 844 + PTP_INT_IO_RE_MASK_); 845 + ptp_int_sts &= ~PTP_INT_IO_RE_MASK_; 846 + } 847 + } while (ptp_int_sts & PTP_INT_IO_RE_MASK_); 848 + } 849 + 850 + ptp_int_sts = lan743x_csr_read(adapter, PTP_INT_STS); 1140 851 } 1141 852 1142 853 if (new_timestamp_available) ··· 1251 802 mutex_unlock(&ptp->command_lock); 1252 803 } 1253 804 805 + static void lan743x_ptp_io_clock_get(struct lan743x_adapter *adapter, 806 + u32 *sec, u32 *nsec, u32 *sub_nsec) 807 + { 808 + struct lan743x_ptp *ptp = &adapter->ptp; 809 + 810 + mutex_lock(&ptp->command_lock); 811 + lan743x_csr_write(adapter, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_); 812 + lan743x_ptp_wait_till_cmd_done(adapter, PTP_CMD_CTL_PTP_CLOCK_READ_); 813 + 814 + if (sec) 815 + (*sec) = lan743x_csr_read(adapter, PTP_LTC_RD_SEC_LO); 816 + 817 + if (nsec) 818 + (*nsec) = lan743x_csr_read(adapter, PTP_LTC_RD_NS); 819 + 820 + if (sub_nsec) 821 + (*sub_nsec) = 822 + lan743x_csr_read(adapter, PTP_LTC_RD_SUBNS); 823 + 824 + mutex_unlock(&ptp->command_lock); 825 + } 826 + 1254 827 static void lan743x_ptp_clock_step(struct lan743x_adapter *adapter, 1255 828 s64 time_step_ns) 1256 829 { ··· 1286 815 1287 816 if (time_step_ns > 15000000000LL) { 1288 817 /* convert to clock set */ 1289 - lan743x_ptp_clock_get(adapter, &unsigned_seconds, 1290 - &nano_seconds, NULL); 818 + if (adapter->is_pci11x1x) 819 + lan743x_ptp_io_clock_get(adapter, &unsigned_seconds, 820 + &nano_seconds, NULL); 821 + else 822 + lan743x_ptp_clock_get(adapter, &unsigned_seconds, 823 + &nano_seconds, NULL); 1291 824 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL, 1292 825 &remainder); 1293 826 nano_seconds += remainder; ··· 1306 831 /* convert to clock set */ 1307 832 time_step_ns = -time_step_ns; 1308 833 1309 - lan743x_ptp_clock_get(adapter, &unsigned_seconds, 1310 - &nano_seconds, NULL); 834 + if (adapter->is_pci11x1x) { 835 + lan743x_ptp_io_clock_get(adapter, &unsigned_seconds, 836 + &nano_seconds, NULL); 837 + } else { 838 + lan743x_ptp_clock_get(adapter, &unsigned_seconds, 839 + &nano_seconds, NULL); 840 + } 1311 841 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL, 1312 842 &remainder); 1313 843 nano_seconds_step = remainder; ··· 1541 1061 n_pins = LAN7430_N_GPIO; 1542 1062 break; 1543 1063 case ID_REV_ID_LAN7431_: 1064 + case ID_REV_ID_A011_: 1065 + case ID_REV_ID_A041_: 1544 1066 n_pins = LAN7431_N_GPIO; 1545 1067 break; 1546 1068 default: ··· 1570 1088 adapter->netdev->dev_addr); 1571 1089 ptp->ptp_clock_info.max_adj = LAN743X_PTP_MAX_FREQ_ADJ_IN_PPB; 1572 1090 ptp->ptp_clock_info.n_alarm = 0; 1573 - ptp->ptp_clock_info.n_ext_ts = 0; 1091 + ptp->ptp_clock_info.n_ext_ts = LAN743X_PTP_N_EXTTS; 1574 1092 ptp->ptp_clock_info.n_per_out = LAN743X_PTP_N_EVENT_CHAN; 1575 1093 ptp->ptp_clock_info.n_pins = n_pins; 1576 - ptp->ptp_clock_info.pps = 0; 1094 + ptp->ptp_clock_info.pps = LAN743X_PTP_N_PPS; 1577 1095 ptp->ptp_clock_info.pin_config = ptp->pin_config; 1578 1096 ptp->ptp_clock_info.adjfine = lan743x_ptpci_adjfine; 1579 1097 ptp->ptp_clock_info.adjfreq = lan743x_ptpci_adjfreq;

+10

drivers/net/ethernet/microchip/lan743x_ptp.h

··· 18 18 */ 19 19 #define LAN743X_PTP_N_EVENT_CHAN 2 20 20 #define LAN743X_PTP_N_PEROUT LAN743X_PTP_N_EVENT_CHAN 21 + #define LAN743X_PTP_N_EXTTS 4 22 + #define LAN743X_PTP_N_PPS 0 23 + #define PCI11X1X_PTP_IO_MAX_CHANNELS 8 21 24 22 25 struct lan743x_adapter; 23 26 ··· 63 60 int gpio_pin; /* GPIO pin where output appears */ 64 61 }; 65 62 63 + struct lan743x_extts { 64 + int flags; 65 + struct timespec64 ts; 66 + }; 67 + 66 68 struct lan743x_ptp { 67 69 int flags; 68 70 ··· 80 72 81 73 unsigned long used_event_ch; 82 74 struct lan743x_ptp_perout perout[LAN743X_PTP_N_PEROUT]; 75 + int ptp_io_perout[LAN743X_PTP_N_PEROUT]; /* PTP event channel (0=channel A, 1=channel B) */ 76 + struct lan743x_extts extts[LAN743X_PTP_N_EXTTS]; 83 77 84 78 bool leds_multiplexed; 85 79 bool led_enabled[LAN7430_N_LED];

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