+2

arch/loongarch/include/asm/cpu-features.h

reviewed

··· 67 67 #define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR) 68 68 #define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW) 69 69 #define cpu_has_lspw cpu_opt(LOONGARCH_CPU_LSPW) 70 70 + #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) 70 71 #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) 72 72 + #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) 71 73 72 74 #endif /* __ASM_CPU_FEATURES_H */

+5 -1

arch/loongarch/include/asm/cpu.h

reviewed

··· 101 101 #define CPU_FEATURE_HYPERVISOR 26 /* CPU has hypervisor (running in VM) */ 102 102 #define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */ 103 103 #define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */ 104 104 - #define CPU_FEATURE_AVECINT 29 /* CPU has AVEC interrupt */ 104 104 + #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ 105 105 + #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ 106 106 + #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ 105 107 106 108 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) 107 109 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) ··· 134 132 #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR) 135 133 #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW) 136 134 #define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW) 135 135 + #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) 137 136 #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) 137 137 + #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) 138 138 139 139 #endif /* _ASM_CPU_H */

+2 -2

arch/loongarch/include/asm/hw_breakpoint.h

reviewed

··· 134 134 /* Determine number of BRP registers available. */ 135 135 static inline int get_num_brps(void) 136 136 { 137 137 - return csr_read64(LOONGARCH_CSR_FWPC) & CSR_FWPC_NUM; 137 137 + return csr_read32(LOONGARCH_CSR_FWPC) & CSR_FWPC_NUM; 138 138 } 139 139 140 140 /* Determine number of WRP registers available. */ 141 141 static inline int get_num_wrps(void) 142 142 { 143 143 - return csr_read64(LOONGARCH_CSR_MWPC) & CSR_MWPC_NUM; 143 143 + return csr_read32(LOONGARCH_CSR_MWPC) & CSR_MWPC_NUM; 144 144 } 145 145 146 146 #endif /* __KERNEL__ */

+4 -1

arch/loongarch/include/asm/io.h

reviewed

··· 14 14 #include <asm/pgtable-bits.h> 15 15 #include <asm/string.h> 16 16 17 17 - extern void __init __iomem *early_ioremap(u64 phys_addr, unsigned long size); 17 17 + extern void __init __iomem *early_ioremap(phys_addr_t phys_addr, unsigned long size); 18 18 extern void __init early_iounmap(void __iomem *addr, unsigned long size); 19 19 20 20 #define early_memremap early_ioremap ··· 25 25 static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, 26 26 pgprot_t prot) 27 27 { 28 28 + if (offset > TO_PHYS_MASK) 29 29 + return NULL; 30 30 + 28 31 switch (pgprot_val(prot) & _CACHE_MASK) { 29 32 case _CACHE_CC: 30 33 return (void __iomem *)(unsigned long)(CACHE_BASE + offset);

+2

arch/loongarch/include/asm/loongarch.h

reviewed

··· 128 128 #define CPUCFG6_PMNUM GENMASK(7, 4) 129 129 #define CPUCFG6_PMNUM_SHIFT 4 130 130 #define CPUCFG6_PMBITS GENMASK(13, 8) 131 131 + #define CPUCFG6_PMBITS_SHIFT 8 131 132 #define CPUCFG6_UPM BIT(14) 132 133 133 134 #define LOONGARCH_CPUCFG16 0x10 ··· 1138 1137 #define IOCSRF_FLATMODE BIT_ULL(10) 1139 1138 #define IOCSRF_VM BIT_ULL(11) 1140 1139 #define IOCSRF_AVEC BIT_ULL(15) 1140 1140 + #define IOCSRF_REDIRECT BIT_ULL(16) 1141 1141 1142 1142 #define LOONGARCH_IOCSR_VENDOR 0x10 1143 1143

+1 -1

arch/loongarch/include/asm/pgalloc.h

reviewed

··· 88 88 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address) 89 89 { 90 90 pud_t *pud; 91 91 - struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL & ~__GFP_HIGHMEM, 0); 91 91 + struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL, 0); 92 92 93 93 if (!ptdesc) 94 94 return NULL;

+8 -3

arch/loongarch/include/asm/pgtable.h

reviewed

··· 424 424 425 425 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 426 426 { 427 427 + if (pte_val(pte) & _PAGE_DIRTY) 428 428 + pte_val(pte) |= _PAGE_MODIFIED; 429 429 + 427 430 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | 428 431 (pgprot_val(newprot) & ~_PAGE_CHG_MASK)); 429 432 } ··· 550 547 551 548 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 552 549 { 553 553 - pmd_val(pmd) = (pmd_val(pmd) & _HPAGE_CHG_MASK) | 554 554 - (pgprot_val(newprot) & ~_HPAGE_CHG_MASK); 555 555 - return pmd; 550 550 + if (pmd_val(pmd) & _PAGE_DIRTY) 551 551 + pmd_val(pmd) |= _PAGE_MODIFIED; 552 552 + 553 553 + return __pmd((pmd_val(pmd) & _HPAGE_CHG_MASK) | 554 554 + (pgprot_val(newprot) & ~_HPAGE_CHG_MASK)); 556 555 } 557 556 558 557 static inline pmd_t pmd_mkinvalid(pmd_t pmd)

+4

arch/loongarch/kernel/cpu-probe.c

reviewed

··· 157 157 c->options |= LOONGARCH_CPU_TLB; 158 158 if (config & CPUCFG1_IOCSR) 159 159 c->options |= LOONGARCH_CPU_IOCSR; 160 160 + if (config & CPUCFG1_MSGINT) 161 161 + c->options |= LOONGARCH_CPU_MSGINT; 160 162 if (config & CPUCFG1_UAL) { 161 163 c->options |= LOONGARCH_CPU_UAL; 162 164 elf_hwcap |= HWCAP_LOONGARCH_UAL; ··· 333 331 c->options |= LOONGARCH_CPU_EIODECODE; 334 332 if (config & IOCSRF_AVEC) 335 333 c->options |= LOONGARCH_CPU_AVECINT; 334 334 + if (config & IOCSRF_REDIRECT) 335 335 + c->options |= LOONGARCH_CPU_REDIRECTINT; 336 336 if (config & IOCSRF_VM) 337 337 c->options |= LOONGARCH_CPU_HYPERVISOR; 338 338 }

+1 -1

arch/loongarch/kernel/kexec_efi.c

reviewed

··· 42 42 { 43 43 int ret; 44 44 unsigned long text_offset, kernel_segment_number; 45 45 - struct kexec_buf kbuf; 45 45 + struct kexec_buf kbuf = {}; 46 46 struct kexec_segment *kernel_segment; 47 47 struct loongarch_image_header *h; 48 48

+1 -1

arch/loongarch/kernel/kexec_elf.c

reviewed

··· 59 59 int ret; 60 60 unsigned long text_offset, kernel_segment_number; 61 61 struct elfhdr ehdr; 62 62 - struct kexec_buf kbuf; 62 62 + struct kexec_buf kbuf = {}; 63 63 struct kexec_elf_info elf_info; 64 64 struct kexec_segment *kernel_segment; 65 65

-22

arch/loongarch/kernel/machine_kexec.c

reviewed

··· 39 39 static unsigned long start_addr; 40 40 static unsigned long first_ind_entry; 41 41 42 42 - static void kexec_image_info(const struct kimage *kimage) 43 43 - { 44 44 - unsigned long i; 45 45 - 46 46 - pr_debug("kexec kimage info:\n"); 47 47 - pr_debug("\ttype: %d\n", kimage->type); 48 48 - pr_debug("\tstart: %lx\n", kimage->start); 49 49 - pr_debug("\thead: %lx\n", kimage->head); 50 50 - pr_debug("\tnr_segments: %lu\n", kimage->nr_segments); 51 51 - 52 52 - for (i = 0; i < kimage->nr_segments; i++) { 53 53 - pr_debug("\t segment[%lu]: %016lx - %016lx", i, 54 54 - kimage->segment[i].mem, 55 55 - kimage->segment[i].mem + kimage->segment[i].memsz); 56 56 - pr_debug("\t\t0x%lx bytes, %lu pages\n", 57 57 - (unsigned long)kimage->segment[i].memsz, 58 58 - (unsigned long)kimage->segment[i].memsz / PAGE_SIZE); 59 59 - } 60 60 - } 61 61 - 62 42 int machine_kexec_prepare(struct kimage *kimage) 63 43 { 64 44 int i; 65 45 char *bootloader = "kexec"; 66 46 void *cmdline_ptr = (void *)KEXEC_CMDLINE_ADDR; 67 67 - 68 68 - kexec_image_info(kimage); 69 47 70 48 kimage->arch.efi_boot = fw_arg0; 71 49 kimage->arch.systable_ptr = fw_arg2;

+1 -1

arch/loongarch/kernel/machine_kexec_file.c

reviewed

··· 143 143 unsigned long initrd_load_addr = 0; 144 144 unsigned long orig_segments = image->nr_segments; 145 145 char *modified_cmdline = NULL; 146 146 - struct kexec_buf kbuf; 146 146 + struct kexec_buf kbuf = {}; 147 147 148 148 kbuf.image = image; 149 149 /* Don't allocate anything below the kernel */

+3 -4

arch/loongarch/kernel/mem.c

reviewed

··· 13 13 void __init memblock_init(void) 14 14 { 15 15 u32 mem_type; 16 16 - u64 mem_start, mem_end, mem_size; 16 16 + u64 mem_start, mem_size; 17 17 efi_memory_desc_t *md; 18 18 19 19 /* Parse memory information */ ··· 21 21 mem_type = md->type; 22 22 mem_start = md->phys_addr; 23 23 mem_size = md->num_pages << EFI_PAGE_SHIFT; 24 24 - mem_end = mem_start + mem_size; 25 24 26 25 switch (mem_type) { 27 26 case EFI_LOADER_CODE: ··· 30 31 case EFI_PERSISTENT_MEMORY: 31 32 case EFI_CONVENTIONAL_MEMORY: 32 33 memblock_add(mem_start, mem_size); 33 33 - if (max_low_pfn < (mem_end >> PAGE_SHIFT)) 34 34 - max_low_pfn = mem_end >> PAGE_SHIFT; 35 34 break; 36 35 case EFI_PAL_CODE: 37 36 case EFI_UNUSABLE_MEMORY: ··· 46 49 } 47 50 } 48 51 52 52 + max_pfn = PFN_DOWN(memblock_end_of_DRAM()); 53 53 + max_low_pfn = min(PFN_DOWN(HIGHMEM_START), max_pfn); 49 54 memblock_set_current_limit(PFN_PHYS(max_low_pfn)); 50 55 51 56 /* Reserve the first 2MB */

+2 -21

arch/loongarch/kernel/numa.c

reviewed

··· 272 272 node_mem_init(node); 273 273 node_set_online(node); 274 274 } 275 275 - max_low_pfn = PHYS_PFN(memblock_end_of_DRAM()); 275 275 + max_pfn = PFN_DOWN(memblock_end_of_DRAM()); 276 276 + max_low_pfn = min(PFN_DOWN(HIGHMEM_START), max_pfn); 276 277 277 278 setup_nr_node_ids(); 278 279 loongson_sysconf.nr_nodes = nr_node_ids; ··· 283 282 } 284 283 285 284 #endif 286 286 - 287 287 - void __init paging_init(void) 288 288 - { 289 289 - unsigned int node; 290 290 - unsigned long zones_size[MAX_NR_ZONES] = {0, }; 291 291 - 292 292 - for_each_online_node(node) { 293 293 - unsigned long start_pfn, end_pfn; 294 294 - 295 295 - get_pfn_range_for_nid(node, &start_pfn, &end_pfn); 296 296 - 297 297 - if (end_pfn > max_low_pfn) 298 298 - max_low_pfn = end_pfn; 299 299 - } 300 300 - #ifdef CONFIG_ZONE_DMA32 301 301 - zones_size[ZONE_DMA32] = MAX_DMA32_PFN; 302 302 - #endif 303 303 - zones_size[ZONE_NORMAL] = max_low_pfn; 304 304 - free_area_init(zones_size); 305 305 - } 306 285 307 286 int pcibus_to_node(struct pci_bus *bus) 308 287 {

+4 -3

arch/loongarch/kernel/perf_event.c

reviewed

··· 845 845 846 846 static int __init init_hw_perf_events(void) 847 847 { 848 848 - int counters; 848 848 + int bits, counters; 849 849 850 850 if (!cpu_has_pmp) 851 851 return -ENODEV; 852 852 853 853 pr_info("Performance counters: "); 854 854 - counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> 4) + 1; 854 854 + bits = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMBITS) >> CPUCFG6_PMBITS_SHIFT) + 1; 855 855 + counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> CPUCFG6_PMNUM_SHIFT) + 1; 855 856 856 857 loongarch_pmu.num_counters = counters; 857 858 loongarch_pmu.max_period = (1ULL << 63) - 1; ··· 868 867 on_each_cpu(reset_counters, NULL, 1); 869 868 870 869 pr_cont("%s PMU enabled, %d %d-bit counters available to each CPU.\n", 871 871 - loongarch_pmu.name, counters, 64); 870 870 + loongarch_pmu.name, counters, bits); 872 871 873 872 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 874 873

+2 -3

arch/loongarch/kernel/setup.c

reviewed

··· 294 294 295 295 early_init_dt_scan(fdt_pointer, __pa(fdt_pointer)); 296 296 early_init_fdt_reserve_self(); 297 297 - 298 298 - max_low_pfn = PFN_PHYS(memblock_end_of_DRAM()); 299 297 #endif 300 298 } 301 299 ··· 388 390 static void __init arch_mem_init(char **cmdline_p) 389 391 { 390 392 /* Recalculate max_low_pfn for "mem=xxx" */ 391 391 - max_pfn = max_low_pfn = PHYS_PFN(memblock_end_of_DRAM()); 393 393 + max_pfn = PFN_DOWN(memblock_end_of_DRAM()); 394 394 + max_low_pfn = min(PFN_DOWN(HIGHMEM_START), max_pfn); 392 395 393 396 if (usermem) 394 397 pr_info("User-defined physical RAM map overwrite\n");

+2 -2

arch/loongarch/kernel/traps.c

reviewed

··· 1131 1131 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 1132 1132 1133 1133 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 1134 1134 - csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 1135 1135 - csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 1134 1134 + csr_write64(__pa(eentry), LOONGARCH_CSR_MERRENTRY); 1135 1135 + csr_write64(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY); 1136 1136 } 1137 1137 1138 1138 void per_cpu_trap_init(int cpu)

+1 -1

arch/loongarch/kvm/intc/eiointc.c

reviewed

··· 439 439 spin_lock_irqsave(&s->lock, flags); 440 440 switch (type) { 441 441 case KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_NUM_CPU: 442 442 - if (val >= EIOINTC_ROUTE_MAX_VCPUS) 442 442 + if (val > EIOINTC_ROUTE_MAX_VCPUS) 443 443 ret = -EINVAL; 444 444 else 445 445 s->num_cpu = val;

+1 -1

arch/loongarch/kvm/mmu.c

reviewed

··· 857 857 858 858 if (writeable) { 859 859 prot_bits = kvm_pte_mkwriteable(prot_bits); 860 860 - if (write) 860 860 + if (write || !kvm_slot_dirty_track_enabled(memslot)) 861 861 prot_bits = kvm_pte_mkdirty(prot_bits); 862 862 } 863 863

+2

arch/loongarch/kvm/timer.c

reviewed

··· 4 4 */ 5 5 6 6 #include <linux/kvm_host.h> 7 7 + #include <asm/delay.h> 7 8 #include <asm/kvm_csr.h> 8 9 #include <asm/kvm_vcpu.h> 9 10 ··· 96 95 * and set CSR TVAL with -1 97 96 */ 98 97 write_gcsr_timertick(0); 98 98 + __delay(2); /* Wait cycles until timer interrupt injected */ 99 99 100 100 /* 101 101 * Writing CSR_TINTCLR_TI to LOONGARCH_CSR_TINTCLR will clear

+9 -10

arch/loongarch/kvm/vcpu.c

reviewed

··· 132 132 * Clear KVM_LARCH_PMU if the guest is not using PMU CSRs when 133 133 * exiting the guest, so that the next time trap into the guest. 134 134 * We don't need to deal with PMU CSRs contexts. 135 135 + * 136 136 + * Otherwise set the request bit KVM_REQ_PMU to restore guest PMU 137 137 + * before entering guest VM 135 138 */ 136 139 val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); 137 140 val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); ··· 142 139 val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); 143 140 if (!(val & KVM_PMU_EVENT_ENABLED)) 144 141 vcpu->arch.aux_inuse &= ~KVM_LARCH_PMU; 142 142 + else 143 143 + kvm_make_request(KVM_REQ_PMU, vcpu); 145 144 146 145 kvm_restore_host_pmu(vcpu); 147 147 - } 148 148 - 149 149 - static void kvm_restore_pmu(struct kvm_vcpu *vcpu) 150 150 - { 151 151 - if ((vcpu->arch.aux_inuse & KVM_LARCH_PMU)) 152 152 - kvm_make_request(KVM_REQ_PMU, vcpu); 153 146 } 154 147 155 148 static void kvm_check_pmu(struct kvm_vcpu *vcpu) ··· 298 299 vcpu->arch.aux_inuse &= ~KVM_LARCH_SWCSR_LATEST; 299 300 300 301 if (kvm_request_pending(vcpu) || xfer_to_guest_mode_work_pending()) { 301 301 - kvm_lose_pmu(vcpu); 302 302 + if (vcpu->arch.aux_inuse & KVM_LARCH_PMU) { 303 303 + kvm_lose_pmu(vcpu); 304 304 + kvm_make_request(KVM_REQ_PMU, vcpu); 305 305 + } 302 306 /* make sure the vcpu mode has been written */ 303 307 smp_store_mb(vcpu->mode, OUTSIDE_GUEST_MODE); 304 308 local_irq_enable(); ··· 1605 1603 /* Restore timer state regardless */ 1606 1604 kvm_restore_timer(vcpu); 1607 1605 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 1608 1608 - 1609 1609 - /* Restore hardware PMU CSRs */ 1610 1610 - kvm_restore_pmu(vcpu); 1611 1606 1612 1607 /* Don't bother restoring registers multiple times unless necessary */ 1613 1608 if (vcpu->arch.aux_inuse & KVM_LARCH_HWCSR_USABLE)

-2

arch/loongarch/mm/init.c

reviewed

··· 60 60 return memblock_is_memory(addr) && !memblock_is_reserved(addr); 61 61 } 62 62 63 63 - #ifndef CONFIG_NUMA 64 63 void __init paging_init(void) 65 64 { 66 65 unsigned long max_zone_pfns[MAX_NR_ZONES]; ··· 71 72 72 73 free_area_init(max_zone_pfns); 73 74 } 74 74 - #endif /* !CONFIG_NUMA */ 75 75 76 76 void __ref free_initmem(void) 77 77 {

+1 -1

arch/loongarch/mm/ioremap.c

reviewed

··· 6 6 #include <asm/io.h> 7 7 #include <asm-generic/early_ioremap.h> 8 8 9 9 - void __init __iomem *early_ioremap(u64 phys_addr, unsigned long size) 9 9 + void __init __iomem *early_ioremap(phys_addr_t phys_addr, unsigned long size) 10 10 { 11 11 return ((void __iomem *)TO_CACHE(phys_addr)); 12 12 }

+1 -1

rust/Makefile

reviewed

··· 298 298 -fno-inline-functions-called-once -fsanitize=bounds-strict \ 299 299 -fstrict-flex-arrays=% -fmin-function-alignment=% \ 300 300 -fzero-init-padding-bits=% -mno-fdpic \ 301 301 - --param=% --param asan-% 301 301 + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference 302 302 303 303 # Derived from `scripts/Makefile.clang`. 304 304 BINDGEN_TARGET_x86 := x86_64-linux-gnu