Merge tag 'powerpc-5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

+1 -1

arch/powerpc/include/asm/nohash/32/kup-8xx.h

··· 63 63 static inline bool 64 64 bad_kuap_fault(struct pt_regs *regs, unsigned long address, bool is_write) 65 65 { 66 - return WARN(!((regs->kuap ^ MD_APG_KUAP) & 0xf0000000), 66 + return WARN(!((regs->kuap ^ MD_APG_KUAP) & 0xff000000), 67 67 "Bug: fault blocked by AP register !"); 68 68 } 69 69

+14 -31

arch/powerpc/include/asm/nohash/32/mmu-8xx.h

··· 33 33 * respectively NA for All or X for Supervisor and no access for User. 34 34 * Then we use the APG to say whether accesses are according to Page rules or 35 35 * "all Supervisor" rules (Access to all) 36 - * Therefore, we define 2 APG groups. lsb is _PMD_USER 37 - * 0 => Kernel => 01 (all accesses performed according to page definition) 38 - * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 39 - * 2-15 => Not Used 36 + * _PAGE_ACCESSED is also managed via APG. When _PAGE_ACCESSED is not set, say 37 + * "all User" rules, that will lead to NA for all. 38 + * Therefore, we define 4 APG groups. lsb is _PAGE_ACCESSED 39 + * 0 => Kernel => 11 (all accesses performed according as user iaw page definition) 40 + * 1 => Kernel+Accessed => 01 (all accesses performed according to page definition) 41 + * 2 => User => 11 (all accesses performed according as user iaw page definition) 42 + * 3 => User+Accessed => 00 (all accesses performed as supervisor iaw page definition) for INIT 43 + * => 10 (all accesses performed according to swaped page definition) for KUEP 44 + * 4-15 => Not Used 40 45 */ 41 - #define MI_APG_INIT 0x40000000 42 - 43 - /* 44 - * 0 => Kernel => 01 (all accesses performed according to page definition) 45 - * 1 => User => 10 (all accesses performed according to swaped page definition) 46 - * 2-15 => Not Used 47 - */ 48 - #define MI_APG_KUEP 0x60000000 46 + #define MI_APG_INIT 0xdc000000 47 + #define MI_APG_KUEP 0xde000000 49 48 50 49 /* The effective page number register. When read, contains the information 51 50 * about the last instruction TLB miss. When MI_RPN is written, bits in ··· 105 106 #define MD_Ks 0x80000000 /* Should not be set */ 106 107 #define MD_Kp 0x40000000 /* Should always be set */ 107 108 108 - /* 109 - * All pages' PP data bits are set to either 000 or 011 or 001, which means 110 - * respectively RW for Supervisor and no access for User, or RO for 111 - * Supervisor and no access for user and NA for ALL. 112 - * Then we use the APG to say whether accesses are according to Page rules or 113 - * "all Supervisor" rules (Access to all) 114 - * Therefore, we define 2 APG groups. lsb is _PMD_USER 115 - * 0 => Kernel => 01 (all accesses performed according to page definition) 116 - * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 117 - * 2-15 => Not Used 118 - */ 119 - #define MD_APG_INIT 0x40000000 120 - 121 - /* 122 - * 0 => No user => 01 (all accesses performed according to page definition) 123 - * 1 => User => 10 (all accesses performed according to swaped page definition) 124 - * 2-15 => Not Used 125 - */ 126 - #define MD_APG_KUAP 0x60000000 109 + /* See explanation above at the definition of MI_APG_INIT */ 110 + #define MD_APG_INIT 0xdc000000 111 + #define MD_APG_KUAP 0xde000000 127 112 128 113 /* The effective page number register. When read, contains the information 129 114 * about the last instruction TLB miss. When MD_RPN is written, bits in

+5 -4

arch/powerpc/include/asm/nohash/32/pte-8xx.h

··· 39 39 * into the TLB. 40 40 */ 41 41 #define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */ 42 - #define _PAGE_SPECIAL 0x0020 /* SW entry */ 42 + #define _PAGE_ACCESSED 0x0020 /* Copied to L1 APG 1 entry in I/DTLB */ 43 43 #define _PAGE_EXEC 0x0040 /* Copied to PP (bit 21) in ITLB */ 44 - #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ 44 + #define _PAGE_SPECIAL 0x0080 /* SW entry */ 45 45 46 46 #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */ 47 47 #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */ ··· 59 59 60 60 #define _PMD_PRESENT 0x0001 61 61 #define _PMD_PRESENT_MASK _PMD_PRESENT 62 - #define _PMD_BAD 0x0fd0 62 + #define _PMD_BAD 0x0f90 63 63 #define _PMD_PAGE_MASK 0x000c 64 64 #define _PMD_PAGE_8M 0x000c 65 65 #define _PMD_PAGE_512K 0x0004 66 - #define _PMD_USER 0x0020 /* APG 1 */ 66 + #define _PMD_ACCESSED 0x0020 /* APG 1 */ 67 + #define _PMD_USER 0x0040 /* APG 2 */ 67 68 68 69 #define _PTE_NONE_MASK 0 69 70

+9 -3

arch/powerpc/include/asm/topology.h

··· 6 6 7 7 struct device; 8 8 struct device_node; 9 + struct drmem_lmb; 9 10 10 11 #ifdef CONFIG_NUMA 11 12 ··· 62 61 */ 63 62 return (nid < 0) ? 0 : nid; 64 63 } 64 + 65 + int of_drconf_to_nid_single(struct drmem_lmb *lmb); 66 + 65 67 #else 66 68 67 69 static inline int early_cpu_to_node(int cpu) { return 0; } ··· 88 84 return 0; 89 85 } 90 86 91 - #endif /* CONFIG_NUMA */ 87 + static inline int of_drconf_to_nid_single(struct drmem_lmb *lmb) 88 + { 89 + return first_online_node; 90 + } 92 91 93 - struct drmem_lmb; 94 - int of_drconf_to_nid_single(struct drmem_lmb *lmb); 92 + #endif /* CONFIG_NUMA */ 95 93 96 94 #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR) 97 95 extern int find_and_online_cpu_nid(int cpu);

+2 -2

arch/powerpc/include/asm/uaccess.h

··· 178 178 * are no aliasing issues. 179 179 */ 180 180 #define __put_user_asm_goto(x, addr, label, op) \ 181 - asm volatile goto( \ 181 + asm_volatile_goto( \ 182 182 "1: " op "%U1%X1 %0,%1 # put_user\n" \ 183 183 EX_TABLE(1b, %l2) \ 184 184 : \ ··· 191 191 __put_user_asm_goto(x, ptr, label, "std") 192 192 #else /* __powerpc64__ */ 193 193 #define __put_user_asm2_goto(x, addr, label) \ 194 - asm volatile goto( \ 194 + asm_volatile_goto( \ 195 195 "1: stw%X1 %0, %1\n" \ 196 196 "2: stw%X1 %L0, %L1\n" \ 197 197 EX_TABLE(1b, %l2) \

+3 -2

arch/powerpc/kernel/eeh_cache.c

··· 264 264 { 265 265 struct pci_io_addr_range *piar; 266 266 struct rb_node *n; 267 + unsigned long flags; 267 268 268 - spin_lock(&pci_io_addr_cache_root.piar_lock); 269 + spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); 269 270 for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) { 270 271 piar = rb_entry(n, struct pci_io_addr_range, rb_node); 271 272 ··· 274 273 (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", 275 274 &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev)); 276 275 } 277 - spin_unlock(&pci_io_addr_cache_root.piar_lock); 276 + spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); 278 277 279 278 return 0; 280 279 }

-8

arch/powerpc/kernel/head_40x.S

··· 284 284 285 285 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 286 286 lwz r11, 0(r11) /* Get Linux PTE */ 287 - #ifdef CONFIG_SWAP 288 287 li r9, _PAGE_PRESENT | _PAGE_ACCESSED 289 - #else 290 - li r9, _PAGE_PRESENT 291 - #endif 292 288 andc. r9, r9, r11 /* Check permission */ 293 289 bne 5f 294 290 ··· 365 369 366 370 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ 367 371 lwz r11, 0(r11) /* Get Linux PTE */ 368 - #ifdef CONFIG_SWAP 369 372 li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 370 - #else 371 - li r9, _PAGE_PRESENT | _PAGE_EXEC 372 - #endif 373 373 andc. r9, r9, r11 /* Check permission */ 374 374 bne 5f 375 375

+7 -39

arch/powerpc/kernel/head_8xx.S

··· 202 202 203 203 InstructionTLBMiss: 204 204 mtspr SPRN_SPRG_SCRATCH0, r10 205 - #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS) 206 205 mtspr SPRN_SPRG_SCRATCH1, r11 207 - #endif 208 206 209 207 /* If we are faulting a kernel address, we have to use the 210 208 * kernel page tables. ··· 222 224 3: 223 225 mtcr r11 224 226 #endif 225 - #if defined(CONFIG_HUGETLBFS) || !defined(CONFIG_PIN_TLB_TEXT) 226 227 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 227 228 mtspr SPRN_MD_TWC, r11 228 - #else 229 - lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ 230 - mtspr SPRN_MI_TWC, r10 /* Set segment attributes */ 231 - mtspr SPRN_MD_TWC, r10 232 - #endif 233 229 mfspr r10, SPRN_MD_TWC 234 230 lwz r10, 0(r10) /* Get the pte */ 235 - #if defined(CONFIG_HUGETLBFS) || !defined(CONFIG_PIN_TLB_TEXT) 231 + rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 236 232 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 237 233 mtspr SPRN_MI_TWC, r11 238 - #endif 239 - #ifdef CONFIG_SWAP 240 - rlwinm r11, r10, 32-5, _PAGE_PRESENT 241 - and r11, r11, r10 242 - rlwimi r10, r11, 0, _PAGE_PRESENT 243 - #endif 244 234 /* The Linux PTE won't go exactly into the MMU TLB. 245 235 * Software indicator bits 20 and 23 must be clear. 246 236 * Software indicator bits 22, 24, 25, 26, and 27 must be ··· 242 256 243 257 /* Restore registers */ 244 258 0: mfspr r10, SPRN_SPRG_SCRATCH0 245 - #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS) 246 259 mfspr r11, SPRN_SPRG_SCRATCH1 247 - #endif 248 260 rfi 249 261 patch_site 0b, patch__itlbmiss_exit_1 250 262 ··· 252 268 addi r10, r10, 1 253 269 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) 254 270 mfspr r10, SPRN_SPRG_SCRATCH0 255 - #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) 256 271 mfspr r11, SPRN_SPRG_SCRATCH1 257 - #endif 258 272 rfi 259 273 #endif 260 274 ··· 279 297 mfspr r10, SPRN_MD_TWC 280 298 lwz r10, 0(r10) /* Get the pte */ 281 299 282 - /* Insert the Guarded flag into the TWC from the Linux PTE. 300 + /* Insert Guarded and Accessed flags into the TWC from the Linux PTE. 283 301 * It is bit 27 of both the Linux PTE and the TWC (at least 284 302 * I got that right :-). It will be better when we can put 285 303 * this into the Linux pgd/pmd and load it in the operation 286 304 * above. 287 305 */ 288 - rlwimi r11, r10, 0, _PAGE_GUARDED 306 + rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED 289 307 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K 290 308 mtspr SPRN_MD_TWC, r11 291 309 292 - /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 293 - * We also need to know if the insn is a load/store, so: 294 - * Clear _PAGE_PRESENT and load that which will 295 - * trap into DTLB Error with store bit set accordinly. 296 - */ 297 - /* PRESENT=0x1, ACCESSED=0x20 298 - * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 299 - * r10 = (r10 & ~PRESENT) | r11; 300 - */ 301 - #ifdef CONFIG_SWAP 302 - rlwinm r11, r10, 32-5, _PAGE_PRESENT 303 - and r11, r11, r10 304 - rlwimi r10, r11, 0, _PAGE_PRESENT 305 - #endif 306 310 /* The Linux PTE won't go exactly into the MMU TLB. 307 311 * Software indicator bits 24, 25, 26, and 27 must be 308 312 * set. All other Linux PTE bits control the behavior ··· 679 711 li r9, 4 /* up to 4 pages of 8M */ 680 712 mtctr r9 681 713 lis r9, KERNELBASE@h /* Create vaddr for TLB */ 682 - li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */ 714 + li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID 683 715 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 684 716 1: 685 717 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ ··· 743 775 #ifdef CONFIG_PIN_TLB_TEXT 744 776 LOAD_REG_IMMEDIATE(r5, 28 << 8) 745 777 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 746 - LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG) 778 + LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 747 779 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) 748 780 LOAD_REG_ADDR(r9, _sinittext) 749 781 li r0, 4 ··· 765 797 LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM) 766 798 #ifdef CONFIG_PIN_TLB_DATA 767 799 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) 768 - LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG) 800 + LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) 769 801 #ifdef CONFIG_PIN_TLB_IMMR 770 802 li r0, 3 771 803 #else ··· 802 834 #endif 803 835 #ifdef CONFIG_PIN_TLB_IMMR 804 836 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) 805 - LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED) 837 + LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED) 806 838 mfspr r8, SPRN_IMMR 807 839 rlwinm r8, r8, 0, 0xfff80000 808 840 ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \

-12

arch/powerpc/kernel/head_book3s_32.S

··· 457 457 cmplw 0,r1,r3 458 458 #endif 459 459 mfspr r2, SPRN_SPRG_PGDIR 460 - #ifdef CONFIG_SWAP 461 460 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 462 - #else 463 - li r1,_PAGE_PRESENT | _PAGE_EXEC 464 - #endif 465 461 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC) 466 462 bgt- 112f 467 463 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ ··· 519 523 lis r1, TASK_SIZE@h /* check if kernel address */ 520 524 cmplw 0,r1,r3 521 525 mfspr r2, SPRN_SPRG_PGDIR 522 - #ifdef CONFIG_SWAP 523 526 li r1, _PAGE_PRESENT | _PAGE_ACCESSED 524 - #else 525 - li r1, _PAGE_PRESENT 526 - #endif 527 527 bgt- 112f 528 528 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ 529 529 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */ ··· 595 603 lis r1, TASK_SIZE@h /* check if kernel address */ 596 604 cmplw 0,r1,r3 597 605 mfspr r2, SPRN_SPRG_PGDIR 598 - #ifdef CONFIG_SWAP 599 606 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED 600 - #else 601 - li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT 602 - #endif 603 607 bgt- 112f 604 608 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */ 605 609 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */

+2 -1

arch/powerpc/kernel/smp.c

··· 1393 1393 /* Activate a secondary processor. */ 1394 1394 void start_secondary(void *unused) 1395 1395 { 1396 - unsigned int cpu = smp_processor_id(); 1396 + unsigned int cpu = raw_smp_processor_id(); 1397 1397 1398 1398 mmgrab(&init_mm); 1399 1399 current->active_mm = &init_mm; 1400 1400 1401 1401 smp_store_cpu_info(cpu); 1402 1402 set_dec(tb_ticks_per_jiffy); 1403 + rcu_cpu_starting(cpu); 1403 1404 preempt_disable(); 1404 1405 cpu_callin_map[cpu] = 1; 1405 1406

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