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irqchip/gic-common: Remove sync_access callback

The gic_configure_irq(), gic_dist_config(), and gic_cpu_config()
functions each take an optional "sync_access" callback, but in almost
all cases this is not used. The only user is the GICv3 driver's
gic_cpu_init() function, which uses gic_redist_wait_for_rwp() as the
"sync_access" callback for gic_cpu_config().

It would be simpler and clearer to remove the callback and have the
GICv3 driver call gic_redist_wait_for_rwp() explicitly after
gic_cpu_config().

Remove the "sync_access" callback, and call gic_redist_wait_for_rwp()
explicitly in the GICv3 driver.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240617111841.2529370-3-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>

authored by

Mark Rutland and committed by
Catalin Marinas e95c64a7 118d777c

+16 -26
+3 -13
drivers/irqchip/irq-gic-common.c
··· 45 45 } 46 46 47 47 int gic_configure_irq(unsigned int irq, unsigned int type, 48 - void __iomem *base, void (*sync_access)(void)) 48 + void __iomem *base) 49 49 { 50 50 u32 confmask = 0x2 << ((irq % 16) * 2); 51 51 u32 confoff = (irq / 16) * 4; ··· 84 84 85 85 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 86 86 87 - if (sync_access) 88 - sync_access(); 89 - 90 87 return ret; 91 88 } 92 89 93 - void gic_dist_config(void __iomem *base, int gic_irqs, 94 - void (*sync_access)(void)) 90 + void gic_dist_config(void __iomem *base, int gic_irqs) 95 91 { 96 92 unsigned int i; 97 93 ··· 114 118 writel_relaxed(GICD_INT_EN_CLR_X32, 115 119 base + GIC_DIST_ENABLE_CLEAR + i / 8); 116 120 } 117 - 118 - if (sync_access) 119 - sync_access(); 120 121 } 121 122 122 - void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)) 123 + void gic_cpu_config(void __iomem *base, int nr) 123 124 { 124 125 int i; 125 126 ··· 137 144 for (i = 0; i < nr; i += 4) 138 145 writel_relaxed(GICD_INT_DEF_PRI_X4, 139 146 base + GIC_DIST_PRI + i * 4 / 4); 140 - 141 - if (sync_access) 142 - sync_access(); 143 147 }
+3 -4
drivers/irqchip/irq-gic-common.h
··· 20 20 }; 21 21 22 22 int gic_configure_irq(unsigned int irq, unsigned int type, 23 - void __iomem *base, void (*sync_access)(void)); 24 - void gic_dist_config(void __iomem *base, int gic_irqs, 25 - void (*sync_access)(void)); 26 - void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)); 23 + void __iomem *base); 24 + void gic_dist_config(void __iomem *base, int gic_irqs); 25 + void gic_cpu_config(void __iomem *base, int nr); 27 26 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, 28 27 void *data); 29 28 void gic_enable_of_quirks(const struct device_node *np,
+4 -3
drivers/irqchip/irq-gic-v3.c
··· 670 670 671 671 offset = convert_offset_index(d, GICD_ICFGR, &index); 672 672 673 - ret = gic_configure_irq(index, type, base + offset, NULL); 673 + ret = gic_configure_irq(index, type, base + offset); 674 674 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { 675 675 /* Misconfigured PPIs are usually not fatal */ 676 676 pr_warn("GIC: PPI INTID%ld is secure or misconfigured\n", irq); ··· 940 940 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); 941 941 942 942 /* Now do the common stuff */ 943 - gic_dist_config(base, GIC_LINE_NR, NULL); 943 + gic_dist_config(base, GIC_LINE_NR); 944 944 945 945 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 946 946 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { ··· 1282 1282 for (i = 0; i < gic_data.ppi_nr + SGI_NR; i += 32) 1283 1283 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); 1284 1284 1285 - gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); 1285 + gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR); 1286 + gic_redist_wait_for_rwp(); 1286 1287 1287 1288 /* initialise system registers */ 1288 1289 gic_cpu_sys_reg_init();
+3 -3
drivers/irqchip/irq-gic.c
··· 303 303 type != IRQ_TYPE_EDGE_RISING) 304 304 return -EINVAL; 305 305 306 - ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); 306 + ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG); 307 307 if (ret && gicirq < 32) { 308 308 /* Misconfigured PPIs are usually not fatal */ 309 309 pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); ··· 479 479 for (i = 32; i < gic_irqs; i += 4) 480 480 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 481 481 482 - gic_dist_config(base, gic_irqs, NULL); 482 + gic_dist_config(base, gic_irqs); 483 483 484 484 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 485 485 } ··· 516 516 gic_cpu_map[i] &= ~cpu_mask; 517 517 } 518 518 519 - gic_cpu_config(dist_base, 32, NULL); 519 + gic_cpu_config(dist_base, 32); 520 520 521 521 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 522 522 gic_cpu_if_up(gic);
+3 -3
drivers/irqchip/irq-hip04.c
··· 130 130 131 131 raw_spin_lock(&irq_controller_lock); 132 132 133 - ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL); 133 + ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG); 134 134 if (ret && irq < 32) { 135 135 /* Misconfigured PPIs are usually not fatal */ 136 136 pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); ··· 260 260 for (i = 32; i < nr_irqs; i += 2) 261 261 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); 262 262 263 - gic_dist_config(base, nr_irqs, NULL); 263 + gic_dist_config(base, nr_irqs); 264 264 265 265 writel_relaxed(1, base + GIC_DIST_CTRL); 266 266 } ··· 287 287 if (i != cpu) 288 288 hip04_cpu_map[i] &= ~cpu_mask; 289 289 290 - gic_cpu_config(dist_base, 32, NULL); 290 + gic_cpu_config(dist_base, 32); 291 291 292 292 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); 293 293 writel_relaxed(1, base + GIC_CPU_CTRL);