Merge tag 'drm-fixes-2025-10-17' of https://gitlab.freedesktop.org/drm/kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull drm fixes from Dave Airlie:
"As per usual xe/amdgpu are the leaders, with some i915 and then a
bunch of scattered fixes. There are a bunch of stability fixes for
some older amdgpu cards.

draw:
- Avoid color truncation

gpuvm:
- Avoid kernel-doc warning

sched:
- Avoid double free

i915:
- Skip GuC communication warning if reset is in progress
- Couple frontbuffer related fixes
- Deactivate PSR only on LNL and when selective fetch enabled

xe:
- Increase global invalidation timeout to handle some workloads
- Fix NPD while evicting BOs in an array of VM binds
- Fix resizable BAR to account for possibly needing to move BARs
other than the LMEMBAR
- Fix error handling in xe_migrate_init()
- Fix atomic fault handling with mixed mappings or if the page is
already in VRAM
- Enable media samplers power gating for platforms before Xe2
- Fix de-registering exec queue from GuC when unbinding
- Ensure data migration to system if indicated by madvise with SVM
- Fix kerneldoc for kunit change
- Always account for cacheline alignment on migration
- Drop bogus assertion on eviction

amdgpu:
- Backlight fix
- SI fixes
- CIK fix
- Make CE support debug only
- IP discovery fix
- Ring reset fixes
- GPUVM fault memory barrier fix
- Drop unused structures in amdgpu_drm.h
- JPEG debugfs fix
- VRAM handling fixes for GPUs without VRAM
- GC 12 MES fixes

amdkfd:
- MES fix

ast:
- Fix display output after reboot

bridge:
- lt9211: Fix version check

panthor:
- Fix MCU suspend

qaic:
- Init bootlog in correct order
- Treat remaining == 0 as error in find_and_map_user_pages()
- Lock access to DBC request queue

rockchip:
- vop2: Fix destination size in atomic check"

* tag 'drm-fixes-2025-10-17' of https://gitlab.freedesktop.org/drm/kernel: (44 commits)
drm/sched: Fix potential double free in drm_sched_job_add_resv_dependencies
drm/xe/evict: drop bogus assert
drm/xe/migrate: don't misalign current bytes
drm/xe/kunit: Fix kerneldoc for parameterized tests
drm/xe/svm: Ensure data will be migrated to system if indicated by madvise.
drm/gpuvm: Fix kernel-doc warning for drm_gpuvm_map_req.map
drm/i915/psr: Deactivate PSR only on LNL and when selective fetch enabled
drm/ast: Blank with VGACR17 sync enable, always clear VGACRB6 sync off
accel/qaic: Synchronize access to DBC request queue head & tail pointer
accel/qaic: Treat remaining == 0 as error in find_and_map_user_pages()
accel/qaic: Fix bootlog initialization ordering
drm/rockchip: vop2: use correct destination rectangle height check
drm/draw: fix color truncation in drm_draw_fill24
drm/xe/guc: Check GuC running state before deregistering exec queue
drm/xe: Enable media sampler power gating
drm/xe: Handle mixed mappings and existing VRAM on atomic faults
drm/xe/migrate: Fix an error path
drm/xe: Move rebar to be done earlier
drm/xe: Don't allow evicting of BOs in same VM in array of VM binds
drm/xe: Increase global invalidation timeout to 1000us
...

Linus Torvalds 6 months ago e96687c6 389dfd9d

+355 -224

60 changed files

expand all

drivers

accel

qaic

qaic.h

qaic_control.c

qaic_data.c

qaic_debugfs.c

qaic_drv.c

gpu

drm

amd

amdgpu

amdgpu.h

amdgpu_amdkfd_gpuvm.c

amdgpu_cs.c

amdgpu_device.c

amdgpu_discovery.c

amdgpu_drv.c

amdgpu_fence.c

amdgpu_jpeg.c

amdgpu_kms.c

amdgpu_mes.c

amdgpu_mes.h

amdgpu_ring.c

amdgpu_ring.h

amdgpu_virt.c

amdgpu_vram_mgr.c

gfx_v11_0.c

gfx_v12_0.c

gmc_v7_0.c

gmc_v8_0.c

mes_userqueue.c

mes_v11_0.c

mes_v12_0.c

amdkfd

kfd_device_queue_manager.c

display

amdgpu_dm

amdgpu_dm.c

amdgpu_dm.h

legacy-dpm

si_dpm.c

powerplay

hwmgr

smu7_hwmgr.c

ast

ast_mode.c

ast_reg.h

bridge

lontium-lt9211.c

drm_draw.c

drm_draw_internal.h

i915

display

intel_fb.c

intel_frontbuffer.c

intel_psr.c

gem

i915_gem_object_frontbuffer.h

intel_guc_ct.c

panthor

panthor_fw.c

rockchip

rockchip_drm_vop2.c

scheduler

sched_main.c

regs

xe_gt_regs.h

tests

xe_pci.c

xe_bo_evict.c

xe_device.c

xe_gt_idle.c

xe_guc_submit.c

xe_migrate.c

xe_pci.c

xe_svm.c

xe_vm.c

xe_vm_types.h

xe_vram.c

xe_vram.h

include

drm

drm_gpuvm.h

uapi

drm

amdgpu_drm.h

drivers/accel/qaic/qaic.h

··· 97 97 * response queue's head and tail pointer of this DBC. 98 98 */ 99 99 void __iomem *dbc_base; 100 + /* Synchronizes access to Request queue's head and tail pointer */ 101 + struct mutex req_lock; 100 102 /* Head of list where each node is a memory handle queued in request queue */ 101 103 struct list_head xfer_list; 102 104 /* Synchronizes DBC readers during cleanup */

+1 -1

drivers/accel/qaic/qaic_control.c

··· 407 407 return -EINVAL; 408 408 remaining = in_trans->size - resources->xferred_dma_size; 409 409 if (remaining == 0) 410 - return 0; 410 + return -EINVAL; 411 411 412 412 if (check_add_overflow(xfer_start_addr, remaining, &end)) 413 413 return -EINVAL;

+10 -2

drivers/accel/qaic/qaic_data.c

··· 1356 1356 goto release_ch_rcu; 1357 1357 } 1358 1358 1359 + ret = mutex_lock_interruptible(&dbc->req_lock); 1360 + if (ret) 1361 + goto release_ch_rcu; 1362 + 1359 1363 head = readl(dbc->dbc_base + REQHP_OFF); 1360 1364 tail = readl(dbc->dbc_base + REQTP_OFF); 1361 1365 1362 1366 if (head == U32_MAX || tail == U32_MAX) { 1363 1367 /* PCI link error */ 1364 1368 ret = -ENODEV; 1365 - goto release_ch_rcu; 1369 + goto unlock_req_lock; 1366 1370 } 1367 1371 1368 1372 queue_level = head <= tail ? tail - head : dbc->nelem - (head - tail); ··· 1374 1370 ret = send_bo_list_to_device(qdev, file_priv, exec, args->hdr.count, is_partial, dbc, 1375 1371 head, &tail); 1376 1372 if (ret) 1377 - goto release_ch_rcu; 1373 + goto unlock_req_lock; 1378 1374 1379 1375 /* Finalize commit to hardware */ 1380 1376 submit_ts = ktime_get_ns(); 1381 1377 writel(tail, dbc->dbc_base + REQTP_OFF); 1378 + mutex_unlock(&dbc->req_lock); 1382 1379 1383 1380 update_profiling_data(file_priv, exec, args->hdr.count, is_partial, received_ts, 1384 1381 submit_ts, queue_level); ··· 1387 1382 if (datapath_polling) 1388 1383 schedule_work(&dbc->poll_work); 1389 1384 1385 + unlock_req_lock: 1386 + if (ret) 1387 + mutex_unlock(&dbc->req_lock); 1390 1388 release_ch_rcu: 1391 1389 srcu_read_unlock(&dbc->ch_lock, rcu_id); 1392 1390 unlock_dev_srcu:

+3 -2

drivers/accel/qaic/qaic_debugfs.c

··· 218 218 if (ret) 219 219 goto destroy_workqueue; 220 220 221 + dev_set_drvdata(&mhi_dev->dev, qdev); 222 + qdev->bootlog_ch = mhi_dev; 223 + 221 224 for (i = 0; i < BOOTLOG_POOL_SIZE; i++) { 222 225 msg = devm_kzalloc(&qdev->pdev->dev, sizeof(*msg), GFP_KERNEL); 223 226 if (!msg) { ··· 236 233 goto mhi_unprepare; 237 234 } 238 235 239 - dev_set_drvdata(&mhi_dev->dev, qdev); 240 - qdev->bootlog_ch = mhi_dev; 241 236 return 0; 242 237 243 238 mhi_unprepare:

drivers/accel/qaic/qaic_drv.c

··· 454 454 return NULL; 455 455 init_waitqueue_head(&qdev->dbc[i].dbc_release); 456 456 INIT_LIST_HEAD(&qdev->dbc[i].bo_lists); 457 + ret = drmm_mutex_init(drm, &qdev->dbc[i].req_lock); 458 + if (ret) 459 + return NULL; 457 460 } 458 461 459 462 return qdev;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1290 1290 bool debug_disable_gpu_ring_reset; 1291 1291 bool debug_vm_userptr; 1292 1292 bool debug_disable_ce_logs; 1293 + bool debug_enable_ce_cs; 1293 1294 1294 1295 /* Protection for the following isolation structure */ 1295 1296 struct mutex enforce_isolation_mutex;

+2 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

··· 2329 2329 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 2330 2330 struct kfd_vm_fault_info *mem) 2331 2331 { 2332 - if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { 2332 + if (atomic_read_acquire(&adev->gmc.vm_fault_info_updated) == 1) { 2333 2333 *mem = *adev->gmc.vm_fault_info; 2334 - mb(); /* make sure read happened */ 2335 - atomic_set(&adev->gmc.vm_fault_info_updated, 0); 2334 + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 2336 2335 } 2337 2336 return 0; 2338 2337 }

+7 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

··· 364 364 if (p->uf_bo && ring->funcs->no_user_fence) 365 365 return -EINVAL; 366 366 367 + if (!p->adev->debug_enable_ce_cs && 368 + chunk_ib->flags & AMDGPU_IB_FLAG_CE) { 369 + dev_err_ratelimited(p->adev->dev, "CE CS is blocked, use debug=0x400 to override\n"); 370 + return -EINVAL; 371 + } 372 + 367 373 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && 368 374 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 369 375 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) ··· 708 702 */ 709 703 const s64 us_upper_bound = 200000; 710 704 711 - if (!adev->mm_stats.log2_max_MBps) { 705 + if ((!adev->mm_stats.log2_max_MBps) || !ttm_resource_manager_used(&adev->mman.vram_mgr.manager)) { 712 706 *max_bytes = 0; 713 707 *max_vis_bytes = 0; 714 708 return;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 1882 1882 1883 1883 static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) 1884 1884 { 1885 + /* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. 1886 + * It's unclear if this is a platform-specific or GPU-specific issue. 1887 + * Disable ASPM on SI for the time being. 1888 + */ 1889 + if (adev->family == AMDGPU_FAMILY_SI) 1890 + return true; 1891 + 1885 1892 #if IS_ENABLED(CONFIG_X86) 1886 1893 struct cpuinfo_x86 *c = &cpu_data(0); 1887 1894

+17 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

··· 1033 1033 /* Until a uniform way is figured, get mask based on hwid */ 1034 1034 switch (hw_id) { 1035 1035 case VCN_HWID: 1036 - harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1036 + /* VCN vs UVD+VCE */ 1037 + if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1038 + harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1037 1039 break; 1038 1040 case DMU_HWID: 1039 1041 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) ··· 2567 2565 amdgpu_discovery_init(adev); 2568 2566 vega10_reg_base_init(adev); 2569 2567 adev->sdma.num_instances = 2; 2568 + adev->sdma.sdma_mask = 3; 2570 2569 adev->gmc.num_umc = 4; 2570 + adev->gfx.xcc_mask = 1; 2571 2571 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2572 2572 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2573 2573 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); ··· 2596 2592 amdgpu_discovery_init(adev); 2597 2593 vega10_reg_base_init(adev); 2598 2594 adev->sdma.num_instances = 2; 2595 + adev->sdma.sdma_mask = 3; 2599 2596 adev->gmc.num_umc = 4; 2597 + adev->gfx.xcc_mask = 1; 2600 2598 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2601 2599 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2602 2600 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); ··· 2625 2619 amdgpu_discovery_init(adev); 2626 2620 vega10_reg_base_init(adev); 2627 2621 adev->sdma.num_instances = 1; 2622 + adev->sdma.sdma_mask = 1; 2628 2623 adev->vcn.num_vcn_inst = 1; 2629 2624 adev->gmc.num_umc = 2; 2625 + adev->gfx.xcc_mask = 1; 2630 2626 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2631 2627 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2632 2628 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); ··· 2673 2665 amdgpu_discovery_init(adev); 2674 2666 vega20_reg_base_init(adev); 2675 2667 adev->sdma.num_instances = 2; 2668 + adev->sdma.sdma_mask = 3; 2676 2669 adev->gmc.num_umc = 8; 2670 + adev->gfx.xcc_mask = 1; 2677 2671 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2678 2672 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2679 2673 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); ··· 2703 2693 amdgpu_discovery_init(adev); 2704 2694 arct_reg_base_init(adev); 2705 2695 adev->sdma.num_instances = 8; 2696 + adev->sdma.sdma_mask = 0xff; 2706 2697 adev->vcn.num_vcn_inst = 2; 2707 2698 adev->gmc.num_umc = 8; 2699 + adev->gfx.xcc_mask = 1; 2708 2700 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2709 2701 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2710 2702 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); ··· 2738 2726 amdgpu_discovery_init(adev); 2739 2727 aldebaran_reg_base_init(adev); 2740 2728 adev->sdma.num_instances = 5; 2729 + adev->sdma.sdma_mask = 0x1f; 2741 2730 adev->vcn.num_vcn_inst = 2; 2742 2731 adev->gmc.num_umc = 4; 2732 + adev->gfx.xcc_mask = 1; 2743 2733 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2744 2734 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2745 2735 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); ··· 2776 2762 } else { 2777 2763 cyan_skillfish_reg_base_init(adev); 2778 2764 adev->sdma.num_instances = 2; 2765 + adev->sdma.sdma_mask = 3; 2766 + adev->gfx.xcc_mask = 1; 2779 2767 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2780 2768 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2781 2769 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);

+7 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 144 144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 145 145 AMDGPU_DEBUG_SMU_POOL = BIT(7), 146 146 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 147 - AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9) 147 + AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 148 + AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10) 148 149 }; 149 150 150 151 unsigned int amdgpu_vram_limit = UINT_MAX; ··· 2289 2288 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2290 2289 pr_info("debug: disable kernel logs of correctable errors\n"); 2291 2290 adev->debug_disable_ce_logs = true; 2291 + } 2292 + 2293 + if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2294 + pr_info("debug: allowing command submission to CE engine\n"); 2295 + adev->debug_enable_ce_cs = true; 2292 2296 } 2293 2297 } 2294 2298

+45 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

··· 758 758 * @fence: fence of the ring to signal 759 759 * 760 760 */ 761 - void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence) 761 + void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) 762 762 { 763 - dma_fence_set_error(&fence->base, -ETIME); 764 - amdgpu_fence_write(fence->ring, fence->seq); 765 - amdgpu_fence_process(fence->ring); 763 + struct dma_fence *unprocessed; 764 + struct dma_fence __rcu **ptr; 765 + struct amdgpu_fence *fence; 766 + struct amdgpu_ring *ring = af->ring; 767 + unsigned long flags; 768 + u32 seq, last_seq; 769 + 770 + last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; 771 + seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; 772 + 773 + /* mark all fences from the guilty context with an error */ 774 + spin_lock_irqsave(&ring->fence_drv.lock, flags); 775 + do { 776 + last_seq++; 777 + last_seq &= ring->fence_drv.num_fences_mask; 778 + 779 + ptr = &ring->fence_drv.fences[last_seq]; 780 + rcu_read_lock(); 781 + unprocessed = rcu_dereference(*ptr); 782 + 783 + if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) { 784 + fence = container_of(unprocessed, struct amdgpu_fence, base); 785 + 786 + if (fence == af) 787 + dma_fence_set_error(&fence->base, -ETIME); 788 + else if (fence->context == af->context) 789 + dma_fence_set_error(&fence->base, -ECANCELED); 790 + } 791 + rcu_read_unlock(); 792 + } while (last_seq != seq); 793 + spin_unlock_irqrestore(&ring->fence_drv.lock, flags); 794 + /* signal the guilty fence */ 795 + amdgpu_fence_write(ring, af->seq); 796 + amdgpu_fence_process(ring); 766 797 } 767 798 768 799 void amdgpu_fence_save_wptr(struct dma_fence *fence) ··· 821 790 struct dma_fence *unprocessed; 822 791 struct dma_fence __rcu **ptr; 823 792 struct amdgpu_fence *fence; 824 - u64 wptr, i, seqno; 793 + u64 wptr; 794 + u32 seq, last_seq; 825 795 826 - seqno = amdgpu_fence_read(ring); 796 + last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; 797 + seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; 827 798 wptr = ring->fence_drv.signalled_wptr; 828 799 ring->ring_backup_entries_to_copy = 0; 829 800 830 - for (i = seqno + 1; i <= ring->fence_drv.sync_seq; ++i) { 831 - ptr = &ring->fence_drv.fences[i & ring->fence_drv.num_fences_mask]; 801 + do { 802 + last_seq++; 803 + last_seq &= ring->fence_drv.num_fences_mask; 804 + 805 + ptr = &ring->fence_drv.fences[last_seq]; 832 806 rcu_read_lock(); 833 807 unprocessed = rcu_dereference(*ptr); 834 808 ··· 849 813 wptr = fence->wptr; 850 814 } 851 815 rcu_read_unlock(); 852 - } 816 + } while (last_seq != seq); 853 817 } 854 818 855 819 /*

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

··· 371 371 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 372 372 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 373 373 ring = &adev->jpeg.inst[i].ring_dec[j]; 374 - if (val & (BIT_ULL(1) << ((i * adev->jpeg.num_jpeg_rings) + j))) 374 + if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j))) 375 375 ring->sched.ready = true; 376 376 else 377 377 ring->sched.ready = false;

+4 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

··· 758 758 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 759 759 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 760 760 case AMDGPU_INFO_VRAM_USAGE: 761 - ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 761 + ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 762 + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 762 763 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 763 764 case AMDGPU_INFO_VIS_VRAM_USAGE: 764 765 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); ··· 805 804 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 806 805 atomic64_read(&adev->vram_pin_size) - 807 806 AMDGPU_VM_RESERVED_VRAM; 808 - mem.vram.heap_usage = 809 - ttm_resource_manager_usage(vram_man); 807 + mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 808 + ttm_resource_manager_usage(vram_man) : 0; 810 809 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 811 810 812 811 mem.cpu_accessible_vram.total_heap_size =

+11 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

··· 409 409 return -EINVAL; 410 410 411 411 /* Clear the doorbell array before detection */ 412 - memset(adev->mes.hung_queue_db_array_cpu_addr, 0, 412 + memset(adev->mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET, 413 413 adev->mes.hung_queue_db_array_size * sizeof(u32)); 414 414 input.queue_type = queue_type; 415 415 input.detect_only = detect_only; ··· 420 420 dev_err(adev->dev, "failed to detect and reset\n"); 421 421 } else { 422 422 *hung_db_num = 0; 423 - for (i = 0; i < adev->mes.hung_queue_db_array_size; i++) { 423 + for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { 424 424 if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { 425 425 hung_db_array[i] = db_array[i]; 426 426 *hung_db_num += 1; 427 427 } 428 428 } 429 + 430 + /* 431 + * TODO: return HQD info for MES scheduled user compute queue reset cases 432 + * stored in hung_db_array hqd info offset to full array size 433 + */ 429 434 } 430 435 431 436 return r; ··· 691 686 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) 692 687 { 693 688 uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 694 - bool is_supported = false; 695 689 696 - if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && 697 - amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && 698 - mes_rev >= 0x63) 699 - is_supported = true; 700 - 701 - return is_supported; 690 + return ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && 691 + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && 692 + mes_rev >= 0x63) || 693 + amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); 702 694 } 703 695 704 696 /* Fix me -- node_id is used to identify the correct MES instances in the future */

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

··· 149 149 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 150 150 151 151 int hung_queue_db_array_size; 152 + int hung_queue_hqd_info_offset; 152 153 struct amdgpu_bo *hung_queue_db_array_gpu_obj; 153 154 uint64_t hung_queue_db_array_gpu_addr; 154 155 void *hung_queue_db_array_cpu_addr;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

··· 811 811 if (r) 812 812 return r; 813 813 814 - /* signal the fence of the bad job */ 814 + /* signal the guilty fence and set an error on all fences from the context */ 815 815 if (guilty_fence) 816 816 amdgpu_fence_driver_guilty_force_completion(guilty_fence); 817 817 /* Re-emit the non-guilty commands */

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

··· 155 155 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); 156 156 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 157 157 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 158 - void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence); 158 + void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); 159 159 void amdgpu_fence_save_wptr(struct dma_fence *fence); 160 160 161 161 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

··· 598 598 vf2pf_info->driver_cert = 0; 599 599 vf2pf_info->os_info.all = 0; 600 600 601 - vf2pf_info->fb_usage = 602 - ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; 601 + vf2pf_info->fb_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 602 + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20 : 0; 603 603 vf2pf_info->fb_vis_usage = 604 604 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; 605 605 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

··· 234 234 !adev->gmc.vram_vendor) 235 235 return 0; 236 236 237 + if (!ttm_resource_manager_used(&adev->mman.vram_mgr.manager)) 238 + return 0; 239 + 237 240 return attr->mode; 238 241 } 239 242

-2

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 5862 5862 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5863 5863 u32 header, control = 0; 5864 5864 5865 - BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5866 - 5867 5865 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5868 5866 5869 5867 control |= ib->length_dw | (vmid << 24);

-2

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 4419 4419 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4420 4420 u32 header, control = 0; 4421 4421 4422 - BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4423 - 4424 4422 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4425 4423 4426 4424 control |= ib->length_dw | (vmid << 24);

+3 -4

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

··· 1068 1068 GFP_KERNEL); 1069 1069 if (!adev->gmc.vm_fault_info) 1070 1070 return -ENOMEM; 1071 - atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1071 + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 1072 1072 1073 1073 return 0; 1074 1074 } ··· 1290 1290 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1291 1291 VMID); 1292 1292 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1293 - && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1293 + && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { 1294 1294 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1295 1295 u32 protections = REG_GET_FIELD(status, 1296 1296 VM_CONTEXT1_PROTECTION_FAULT_STATUS, ··· 1306 1306 info->prot_read = protections & 0x8 ? true : false; 1307 1307 info->prot_write = protections & 0x10 ? true : false; 1308 1308 info->prot_exec = protections & 0x20 ? true : false; 1309 - mb(); 1310 - atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1309 + atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); 1311 1310 } 1312 1311 1313 1312 return 0;

+3 -4

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

··· 1183 1183 GFP_KERNEL); 1184 1184 if (!adev->gmc.vm_fault_info) 1185 1185 return -ENOMEM; 1186 - atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1186 + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 1187 1187 1188 1188 return 0; 1189 1189 } ··· 1478 1478 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1479 1479 VMID); 1480 1480 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1481 - && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1481 + && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { 1482 1482 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1483 1483 u32 protections = REG_GET_FIELD(status, 1484 1484 VM_CONTEXT1_PROTECTION_FAULT_STATUS, ··· 1494 1494 info->prot_read = protections & 0x8 ? true : false; 1495 1495 info->prot_write = protections & 0x10 ? true : false; 1496 1496 info->prot_exec = protections & 0x20 ? true : false; 1497 - mb(); 1498 - atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1497 + atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); 1499 1498 } 1500 1499 1501 1500 return 0;

+3 -3

drivers/gpu/drm/amd/amdgpu/mes_userqueue.c

··· 208 208 struct amdgpu_userq_mgr *uqm, *tmp; 209 209 unsigned int hung_db_num = 0; 210 210 int queue_id, r, i; 211 - u32 db_array[4]; 211 + u32 db_array[8]; 212 212 213 - if (db_array_size > 4) { 214 - dev_err(adev->dev, "DB array size (%d vs 4) too small\n", 213 + if (db_array_size > 8) { 214 + dev_err(adev->dev, "DB array size (%d vs 8) too small\n", 215 215 db_array_size); 216 216 return -EINVAL; 217 217 }

+5 -3

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

··· 66 66 #define GFX_MES_DRAM_SIZE 0x80000 67 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 68 69 - #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 4 69 + #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 70 + #define MES11_HUNG_HQD_INFO_OFFSET 4 70 71 71 72 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 72 73 { ··· 1721 1720 struct amdgpu_device *adev = ip_block->adev; 1722 1721 int pipe, r; 1723 1722 1724 - adev->mes.hung_queue_db_array_size = 1725 - MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1723 + adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1724 + adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1725 + 1726 1726 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1727 1727 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1728 1728 continue;

+11 -4

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

··· 47 47 48 48 #define MES_EOP_SIZE 2048 49 49 50 - #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 4 50 + #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 + #define MES12_HUNG_HQD_INFO_OFFSET 4 51 52 52 53 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 53 54 { ··· 229 228 pipe, x_pkt->header.opcode); 230 229 231 230 r = amdgpu_fence_wait_polling(ring, seq, timeout); 232 - if (r < 1 || !*status_ptr) { 231 + 232 + /* 233 + * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). 234 + * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. 235 + */ 236 + if (r < 1 || !(lower_32_bits(*status_ptr))) { 233 237 234 238 if (misc_op_str) 235 239 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", ··· 1905 1899 struct amdgpu_device *adev = ip_block->adev; 1906 1900 int pipe, r; 1907 1901 1908 - adev->mes.hung_queue_db_array_size = 1909 - MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1902 + adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1903 + adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1904 + 1910 1905 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1911 1906 r = amdgpu_mes_init_microcode(adev, pipe); 1912 1907 if (r)

+21 -52

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

··· 1209 1209 pr_debug_ratelimited("Evicting process pid %d queues\n", 1210 1210 pdd->process->lead_thread->pid); 1211 1211 1212 + if (dqm->dev->kfd->shared_resources.enable_mes) { 1213 + pdd->last_evict_timestamp = get_jiffies_64(); 1214 + retval = suspend_all_queues_mes(dqm); 1215 + if (retval) { 1216 + dev_err(dev, "Suspending all queues failed"); 1217 + goto out; 1218 + } 1219 + } 1220 + 1212 1221 /* Mark all queues as evicted. Deactivate all active queues on 1213 1222 * the qpd. 1214 1223 */ ··· 1230 1221 decrement_queue_count(dqm, qpd, q); 1231 1222 1232 1223 if (dqm->dev->kfd->shared_resources.enable_mes) { 1233 - int err; 1234 - 1235 - err = remove_queue_mes(dqm, q, qpd); 1236 - if (err) { 1224 + retval = remove_queue_mes(dqm, q, qpd); 1225 + if (retval) { 1237 1226 dev_err(dev, "Failed to evict queue %d\n", 1238 1227 q->properties.queue_id); 1239 - retval = err; 1228 + goto out; 1240 1229 } 1241 1230 } 1242 1231 } 1243 - pdd->last_evict_timestamp = get_jiffies_64(); 1244 - if (!dqm->dev->kfd->shared_resources.enable_mes) 1232 + 1233 + if (!dqm->dev->kfd->shared_resources.enable_mes) { 1234 + pdd->last_evict_timestamp = get_jiffies_64(); 1245 1235 retval = execute_queues_cpsch(dqm, 1246 1236 qpd->is_debug ? 1247 1237 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1248 1238 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1249 1239 USE_DEFAULT_GRACE_PERIOD); 1240 + } else { 1241 + retval = resume_all_queues_mes(dqm); 1242 + if (retval) 1243 + dev_err(dev, "Resuming all queues failed"); 1244 + } 1250 1245 1251 1246 out: 1252 1247 dqm_unlock(dqm); ··· 3111 3098 return ret; 3112 3099 } 3113 3100 3114 - static int kfd_dqm_evict_pasid_mes(struct device_queue_manager *dqm, 3115 - struct qcm_process_device *qpd) 3116 - { 3117 - struct device *dev = dqm->dev->adev->dev; 3118 - int ret = 0; 3119 - 3120 - /* Check if process is already evicted */ 3121 - dqm_lock(dqm); 3122 - if (qpd->evicted) { 3123 - /* Increment the evicted count to make sure the 3124 - * process stays evicted before its terminated. 3125 - */ 3126 - qpd->evicted++; 3127 - dqm_unlock(dqm); 3128 - goto out; 3129 - } 3130 - dqm_unlock(dqm); 3131 - 3132 - ret = suspend_all_queues_mes(dqm); 3133 - if (ret) { 3134 - dev_err(dev, "Suspending all queues failed"); 3135 - goto out; 3136 - } 3137 - 3138 - ret = dqm->ops.evict_process_queues(dqm, qpd); 3139 - if (ret) { 3140 - dev_err(dev, "Evicting process queues failed"); 3141 - goto out; 3142 - } 3143 - 3144 - ret = resume_all_queues_mes(dqm); 3145 - if (ret) 3146 - dev_err(dev, "Resuming all queues failed"); 3147 - 3148 - out: 3149 - return ret; 3150 - } 3151 - 3152 3101 int kfd_evict_process_device(struct kfd_process_device *pdd) 3153 3102 { 3154 3103 struct device_queue_manager *dqm; 3155 3104 struct kfd_process *p; 3156 - int ret = 0; 3157 3105 3158 3106 p = pdd->process; 3159 3107 dqm = pdd->dev->dqm; 3160 3108 3161 3109 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 3162 3110 3163 - if (dqm->dev->kfd->shared_resources.enable_mes) 3164 - ret = kfd_dqm_evict_pasid_mes(dqm, &pdd->qpd); 3165 - else 3166 - ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 3167 - 3168 - return ret; 3111 + return dqm->ops.evict_process_queues(dqm, &pdd->qpd); 3169 3112 } 3170 3113 3171 3114 int reserve_debug_trap_vmid(struct device_queue_manager *dqm,

+4 -8

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 2085 2085 2086 2086 dc_hardware_init(adev->dm.dc); 2087 2087 2088 - adev->dm.restore_backlight = true; 2089 - 2090 2088 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev); 2091 2089 if (!adev->dm.hpd_rx_offload_wq) { 2092 2090 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); ··· 3440 3442 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3441 3443 3442 3444 dc_resume(dm->dc); 3443 - adev->dm.restore_backlight = true; 3444 3445 3445 3446 amdgpu_dm_irq_resume_early(adev); 3446 3447 ··· 9966 9969 bool mode_set_reset_required = false; 9967 9970 u32 i; 9968 9971 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 9972 + bool set_backlight_level = false; 9969 9973 9970 9974 /* Disable writeback */ 9971 9975 for_each_old_connector_in_state(state, connector, old_con_state, i) { ··· 10086 10088 acrtc->hw_mode = new_crtc_state->mode; 10087 10089 crtc->hwmode = new_crtc_state->mode; 10088 10090 mode_set_reset_required = true; 10091 + set_backlight_level = true; 10089 10092 } else if (modereset_required(new_crtc_state)) { 10090 10093 drm_dbg_atomic(dev, 10091 10094 "Atomic commit: RESET. crtc id %d:[%p]\n", ··· 10143 10144 * to fix a flicker issue. 10144 10145 * It will cause the dm->actual_brightness is not the current panel brightness 10145 10146 * level. (the dm->brightness is the correct panel level) 10146 - * So we set the backlight level with dm->brightness value after initial 10147 - * set mode. Use restore_backlight flag to avoid setting backlight level 10148 - * for every subsequent mode set. 10147 + * So we set the backlight level with dm->brightness value after set mode 10149 10148 */ 10150 - if (dm->restore_backlight) { 10149 + if (set_backlight_level) { 10151 10150 for (i = 0; i < dm->num_of_edps; i++) { 10152 10151 if (dm->backlight_dev[i]) 10153 10152 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 10154 10153 } 10155 - dm->restore_backlight = false; 10156 10154 } 10157 10155 } 10158 10156

-7

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

··· 631 631 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 632 632 633 633 /** 634 - * @restore_backlight: 635 - * 636 - * Flag to indicate whether to restore backlight after modeset. 637 - */ 638 - bool restore_backlight; 639 - 640 - /** 641 634 * @aux_hpd_discon_quirk: 642 635 * 643 636 * quirk for hpd discon while aux is on-going.

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

··· 3500 3500 * for these GPUs to calculate bandwidth requirements. 3501 3501 */ 3502 3502 if (high_pixelclock_count) { 3503 + /* Work around flickering lines at the bottom edge 3504 + * of the screen when using a single 4K 60Hz monitor. 3505 + */ 3506 + disable_mclk_switching = true; 3507 + 3503 3508 /* On Oland, we observe some flickering when two 4K 60Hz 3504 3509 * displays are connected, possibly because voltage is too low. 3505 3510 * Raise the voltage by requiring a higher SCLK.

+1 -2

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

··· 5444 5444 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * 5445 5445 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5446 5446 else if (hwmgr->pp_table_version == PP_TABLE_V0) 5447 - thermal_data->max = data->thermal_temp_setting.temperature_shutdown * 5448 - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5447 + thermal_data->max = data->thermal_temp_setting.temperature_shutdown; 5449 5448 5450 5449 thermal_data->sw_ctf_threshold = thermal_data->max; 5451 5450

+10 -8

drivers/gpu/drm/ast/ast_mode.c

··· 836 836 static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) 837 837 { 838 838 struct ast_device *ast = to_ast_device(crtc->dev); 839 + u8 vgacr17 = 0x00; 840 + u8 vgacrb6 = 0xff; 839 841 840 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, 0x00); 841 - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, 0x00); 842 + vgacr17 |= AST_IO_VGACR17_SYNC_ENABLE; 843 + vgacrb6 &= ~(AST_IO_VGACRB6_VSYNC_OFF | AST_IO_VGACRB6_HSYNC_OFF); 844 + 845 + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); 846 + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); 842 847 } 843 848 844 849 static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) 845 850 { 846 851 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 847 852 struct ast_device *ast = to_ast_device(crtc->dev); 848 - u8 vgacrb6; 853 + u8 vgacr17 = 0xff; 849 854 850 - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, AST_IO_VGASR1_SD); 851 - 852 - vgacrb6 = AST_IO_VGACRB6_VSYNC_OFF | 853 - AST_IO_VGACRB6_HSYNC_OFF; 854 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); 855 + vgacr17 &= ~AST_IO_VGACR17_SYNC_ENABLE; 856 + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); 855 857 856 858 /* 857 859 * HW cursors require the underlying primary plane and CRTC to

drivers/gpu/drm/ast/ast_reg.h

··· 29 29 #define AST_IO_VGAGRI (0x4E) 30 30 31 31 #define AST_IO_VGACRI (0x54) 32 + #define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in docs */ 32 33 #define AST_IO_VGACR80_PASSWORD (0xa8) 33 34 #define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) 34 35 #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1)

+1 -2

drivers/gpu/drm/bridge/lontium-lt9211.c

··· 121 121 } 122 122 123 123 /* Test for known Chip ID. */ 124 - if (chipid[0] != REG_CHIPID0_VALUE || chipid[1] != REG_CHIPID1_VALUE || 125 - chipid[2] != REG_CHIPID2_VALUE) { 124 + if (chipid[0] != REG_CHIPID0_VALUE || chipid[1] != REG_CHIPID1_VALUE) { 126 125 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n", 127 126 chipid[0], chipid[1], chipid[2]); 128 127 return -EINVAL;

+1 -1

drivers/gpu/drm/drm_draw.c

··· 127 127 128 128 void drm_draw_fill24(struct iosys_map *dmap, unsigned int dpitch, 129 129 unsigned int height, unsigned int width, 130 - u16 color) 130 + u32 color) 131 131 { 132 132 unsigned int y, x; 133 133

+1 -1

drivers/gpu/drm/drm_draw_internal.h

··· 47 47 48 48 void drm_draw_fill24(struct iosys_map *dmap, unsigned int dpitch, 49 49 unsigned int height, unsigned int width, 50 - u16 color); 50 + u32 color); 51 51 52 52 void drm_draw_fill32(struct iosys_map *dmap, unsigned int dpitch, 53 53 unsigned int height, unsigned int width,

+20 -18

drivers/gpu/drm/i915/display/intel_fb.c

··· 2113 2113 if (intel_fb_uses_dpt(fb)) 2114 2114 intel_dpt_destroy(intel_fb->dpt_vm); 2115 2115 2116 - intel_frontbuffer_put(intel_fb->frontbuffer); 2117 - 2118 2116 intel_fb_bo_framebuffer_fini(intel_fb_bo(fb)); 2117 + 2118 + intel_frontbuffer_put(intel_fb->frontbuffer); 2119 2119 2120 2120 kfree(intel_fb); 2121 2121 } ··· 2218 2218 int ret = -EINVAL; 2219 2219 int i; 2220 2220 2221 + /* 2222 + * intel_frontbuffer_get() must be done before 2223 + * intel_fb_bo_framebuffer_init() to avoid set_tiling vs. addfb race. 2224 + */ 2225 + intel_fb->frontbuffer = intel_frontbuffer_get(obj); 2226 + if (!intel_fb->frontbuffer) 2227 + return -ENOMEM; 2228 + 2221 2229 ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); 2222 2230 if (ret) 2223 - return ret; 2224 - 2225 - intel_fb->frontbuffer = intel_frontbuffer_get(obj); 2226 - if (!intel_fb->frontbuffer) { 2227 - ret = -ENOMEM; 2228 - goto err; 2229 - } 2231 + goto err_frontbuffer_put; 2230 2232 2231 2233 ret = -EINVAL; 2232 2234 if (!drm_any_plane_has_format(display->drm, ··· 2237 2235 drm_dbg_kms(display->drm, 2238 2236 "unsupported pixel format %p4cc / modifier 0x%llx\n", 2239 2237 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 2240 - goto err_frontbuffer_put; 2238 + goto err_bo_framebuffer_fini; 2241 2239 } 2242 2240 2243 2241 max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, ··· 2248 2246 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 2249 2247 "tiled" : "linear", 2250 2248 mode_cmd->pitches[0], max_stride); 2251 - goto err_frontbuffer_put; 2249 + goto err_bo_framebuffer_fini; 2252 2250 } 2253 2251 2254 2252 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ ··· 2256 2254 drm_dbg_kms(display->drm, 2257 2255 "plane 0 offset (0x%08x) must be 0\n", 2258 2256 mode_cmd->offsets[0]); 2259 - goto err_frontbuffer_put; 2257 + goto err_bo_framebuffer_fini; 2260 2258 } 2261 2259 2262 2260 drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd); ··· 2266 2264 2267 2265 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 2268 2266 drm_dbg_kms(display->drm, "bad plane %d handle\n", i); 2269 - goto err_frontbuffer_put; 2267 + goto err_bo_framebuffer_fini; 2270 2268 } 2271 2269 2272 2270 stride_alignment = intel_fb_stride_alignment(fb, i); ··· 2274 2272 drm_dbg_kms(display->drm, 2275 2273 "plane %d pitch (%d) must be at least %u byte aligned\n", 2276 2274 i, fb->pitches[i], stride_alignment); 2277 - goto err_frontbuffer_put; 2275 + goto err_bo_framebuffer_fini; 2278 2276 } 2279 2277 2280 2278 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { ··· 2284 2282 drm_dbg_kms(display->drm, 2285 2283 "ccs aux plane %d pitch (%d) must be %d\n", 2286 2284 i, fb->pitches[i], ccs_aux_stride); 2287 - goto err_frontbuffer_put; 2285 + goto err_bo_framebuffer_fini; 2288 2286 } 2289 2287 } 2290 2288 ··· 2293 2291 2294 2292 ret = intel_fill_fb_info(display, intel_fb); 2295 2293 if (ret) 2296 - goto err_frontbuffer_put; 2294 + goto err_bo_framebuffer_fini; 2297 2295 2298 2296 if (intel_fb_uses_dpt(fb)) { 2299 2297 struct i915_address_space *vm; ··· 2319 2317 err_free_dpt: 2320 2318 if (intel_fb_uses_dpt(fb)) 2321 2319 intel_dpt_destroy(intel_fb->dpt_vm); 2320 + err_bo_framebuffer_fini: 2321 + intel_fb_bo_framebuffer_fini(obj); 2322 2322 err_frontbuffer_put: 2323 2323 intel_frontbuffer_put(intel_fb->frontbuffer); 2324 - err: 2325 - intel_fb_bo_framebuffer_fini(obj); 2326 2324 return ret; 2327 2325 } 2328 2326

+9 -1

drivers/gpu/drm/i915/display/intel_frontbuffer.c

··· 270 270 spin_unlock(&display->fb_tracking.lock); 271 271 272 272 i915_active_fini(&front->write); 273 + 274 + drm_gem_object_put(obj); 273 275 kfree_rcu(front, rcu); 274 276 } 275 277 ··· 289 287 if (!front) 290 288 return NULL; 291 289 290 + drm_gem_object_get(obj); 291 + 292 292 front->obj = obj; 293 293 kref_init(&front->ref); 294 294 atomic_set(&front->bits, 0); ··· 303 299 spin_lock(&display->fb_tracking.lock); 304 300 cur = intel_bo_set_frontbuffer(obj, front); 305 301 spin_unlock(&display->fb_tracking.lock); 306 - if (cur != front) 302 + 303 + if (cur != front) { 304 + drm_gem_object_put(obj); 307 305 kfree(front); 306 + } 307 + 308 308 return cur; 309 309 } 310 310

+10 -2

drivers/gpu/drm/i915/display/intel_psr.c

··· 3402 3402 struct intel_display *display = to_intel_display(intel_dp); 3403 3403 3404 3404 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3405 + /* Selective fetch prior LNL */ 3405 3406 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3406 3407 /* can we turn CFF off? */ 3407 3408 if (intel_dp->psr.busy_frontbuffer_bits == 0) ··· 3421 3420 intel_psr_configure_full_frame_update(intel_dp); 3422 3421 3423 3422 intel_psr_force_update(intel_dp); 3423 + } else if (!intel_dp->psr.psr2_sel_fetch_enabled) { 3424 + /* 3425 + * PSR1 on all platforms 3426 + * PSR2 HW tracking 3427 + * Panel Replay Full frame update 3428 + */ 3429 + intel_psr_force_update(intel_dp); 3424 3430 } else { 3431 + /* Selective update LNL onwards */ 3425 3432 intel_psr_exit(intel_dp); 3426 3433 } 3427 3434 3428 - if ((!intel_dp->psr.psr2_sel_fetch_enabled || DISPLAY_VER(display) >= 20) && 3429 - !intel_dp->psr.busy_frontbuffer_bits) 3435 + if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3430 3436 queue_work(display->wq.unordered, &intel_dp->psr.work); 3431 3437 } 3432 3438

-2

drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h

··· 89 89 90 90 if (!front) { 91 91 RCU_INIT_POINTER(obj->frontbuffer, NULL); 92 - drm_gem_object_put(intel_bo_to_drm_bo(obj)); 93 92 } else if (rcu_access_pointer(obj->frontbuffer)) { 94 93 cur = rcu_dereference_protected(obj->frontbuffer, true); 95 94 kref_get(&cur->ref); 96 95 } else { 97 - drm_gem_object_get(intel_bo_to_drm_bo(obj)); 98 96 rcu_assign_pointer(obj->frontbuffer, front); 99 97 } 100 98

+8 -1

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

··· 1325 1325 1326 1326 static void ct_try_receive_message(struct intel_guc_ct *ct) 1327 1327 { 1328 + struct intel_guc *guc = ct_to_guc(ct); 1328 1329 int ret; 1329 1330 1330 - if (GEM_WARN_ON(!ct->enabled)) 1331 + if (!ct->enabled) { 1332 + GEM_WARN_ON(!guc_to_gt(guc)->uc.reset_in_progress); 1333 + return; 1334 + } 1335 + 1336 + /* When interrupt disabled, message handling is not expected */ 1337 + if (!guc->interrupts.enabled) 1331 1338 return; 1332 1339 1333 1340 ret = ct_receive(ct);

drivers/gpu/drm/panthor/panthor_fw.c

··· 1099 1099 } 1100 1100 1101 1101 panthor_job_irq_suspend(&ptdev->fw->irq); 1102 + panthor_fw_stop(ptdev); 1102 1103 } 1103 1104 1104 1105 /**

+1 -1

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

··· 1031 1031 return format; 1032 1032 1033 1033 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || 1034 - drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { 1034 + drm_rect_width(dest) < 4 || drm_rect_height(dest) < 4) { 1035 1035 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", 1036 1036 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, 1037 1037 drm_rect_width(dest), drm_rect_height(dest));

+7 -6

drivers/gpu/drm/scheduler/sched_main.c

··· 965 965 dma_resv_assert_held(resv); 966 966 967 967 dma_resv_for_each_fence(&cursor, resv, usage, fence) { 968 - /* Make sure to grab an additional ref on the added fence */ 969 - dma_fence_get(fence); 970 - ret = drm_sched_job_add_dependency(job, fence); 971 - if (ret) { 972 - dma_fence_put(fence); 968 + /* 969 + * As drm_sched_job_add_dependency always consumes the fence 970 + * reference (even when it fails), and dma_resv_for_each_fence 971 + * is not obtaining one, we need to grab one before calling. 972 + */ 973 + ret = drm_sched_job_add_dependency(job, dma_fence_get(fence)); 974 + if (ret) 973 975 return ret; 974 - } 975 976 } 976 977 return 0; 977 978 }

drivers/gpu/drm/xe/regs/xe_gt_regs.h

··· 342 342 #define POWERGATE_ENABLE XE_REG(0xa210) 343 343 #define RENDER_POWERGATE_ENABLE REG_BIT(0) 344 344 #define MEDIA_POWERGATE_ENABLE REG_BIT(1) 345 + #define MEDIA_SAMPLERS_POWERGATE_ENABLE REG_BIT(2) 345 346 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 346 347 #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 347 348

drivers/gpu/drm/xe/tests/xe_pci.c

··· 66 66 67 67 /** 68 68 * xe_pci_fake_data_gen_params - Generate struct xe_pci_fake_data parameters 69 + * @test: test context object 69 70 * @prev: the pointer to the previous parameter to iterate from or NULL 70 71 * @desc: output buffer with minimum size of KUNIT_PARAM_DESC_SIZE 71 72 * ··· 243 242 244 243 /** 245 244 * xe_pci_graphics_ip_gen_param - Generate graphics struct xe_ip parameters 245 + * @test: test context object 246 246 * @prev: the pointer to the previous parameter to iterate from or NULL 247 247 * @desc: output buffer with minimum size of KUNIT_PARAM_DESC_SIZE 248 248 * ··· 268 266 269 267 /** 270 268 * xe_pci_media_ip_gen_param - Generate media struct xe_ip parameters 269 + * @test: test context object 271 270 * @prev: the pointer to the previous parameter to iterate from or NULL 272 271 * @desc: output buffer with minimum size of KUNIT_PARAM_DESC_SIZE 273 272 * ··· 293 290 294 291 /** 295 292 * xe_pci_id_gen_param - Generate struct pci_device_id parameters 293 + * @test: test context object 296 294 * @prev: the pointer to the previous parameter to iterate from or NULL 297 295 * @desc: output buffer with minimum size of KUNIT_PARAM_DESC_SIZE 298 296 * ··· 380 376 381 377 /** 382 378 * xe_pci_live_device_gen_param - Helper to iterate Xe devices as KUnit parameters 379 + * @test: test context object 383 380 * @prev: the previously returned value, or NULL for the first iteration 384 381 * @desc: the buffer for a parameter name 385 382 *

-8

drivers/gpu/drm/xe/xe_bo_evict.c

··· 182 182 183 183 static int xe_bo_restore_and_map_ggtt(struct xe_bo *bo) 184 184 { 185 - struct xe_device *xe = xe_bo_device(bo); 186 185 int ret; 187 186 188 187 ret = xe_bo_restore_pinned(bo); ··· 199 200 xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo); 200 201 } 201 202 } 202 - 203 - /* 204 - * We expect validate to trigger a move VRAM and our move code 205 - * should setup the iosys map. 206 - */ 207 - xe_assert(xe, !(bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE) || 208 - !iosys_map_is_null(&bo->vmap)); 209 203 210 204 return 0; 211 205 }

+1 -1

drivers/gpu/drm/xe/xe_device.c

··· 1070 1070 spin_lock(&gt->global_invl_lock); 1071 1071 1072 1072 xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1); 1073 - if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) 1073 + if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 1000, NULL, true)) 1074 1074 xe_gt_err_once(gt, "Global invalidation timeout\n"); 1075 1075 1076 1076 spin_unlock(&gt->global_invl_lock);

drivers/gpu/drm/xe/xe_gt_idle.c

··· 124 124 if (xe_gt_is_main_type(gt)) 125 125 gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE; 126 126 127 + if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1255) 128 + gtidle->powergate_enable |= MEDIA_SAMPLERS_POWERGATE_ENABLE; 129 + 127 130 if (xe->info.platform != XE_DG1) { 128 131 for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) { 129 132 if ((gt->info.engine_mask & BIT(i))) ··· 249 246 drm_printf(p, "Media Slice%d Power Gate Status: %s\n", n, 250 247 str_up_down(pg_status & media_slices[n].status_bit)); 251 248 } 249 + 250 + if (MEDIA_VERx100(xe) >= 1100 && MEDIA_VERx100(xe) < 1255) 251 + drm_printf(p, "Media Samplers Power Gating Enabled: %s\n", 252 + str_yes_no(pg_enabled & MEDIA_SAMPLERS_POWERGATE_ENABLE)); 253 + 252 254 return 0; 253 255 } 254 256

+12 -1

drivers/gpu/drm/xe/xe_guc_submit.c

··· 44 44 #include "xe_ring_ops_types.h" 45 45 #include "xe_sched_job.h" 46 46 #include "xe_trace.h" 47 + #include "xe_uc_fw.h" 47 48 #include "xe_vm.h" 48 49 49 50 static struct xe_guc * ··· 1490 1489 xe_gt_assert(guc_to_gt(guc), !(q->flags & EXEC_QUEUE_FLAG_PERMANENT)); 1491 1490 trace_xe_exec_queue_cleanup_entity(q); 1492 1491 1493 - if (exec_queue_registered(q)) 1492 + /* 1493 + * Expected state transitions for cleanup: 1494 + * - If the exec queue is registered and GuC firmware is running, we must first 1495 + * disable scheduling and deregister the queue to ensure proper teardown and 1496 + * resource release in the GuC, then destroy the exec queue on driver side. 1497 + * - If the GuC is already stopped (e.g., during driver unload or GPU reset), 1498 + * we cannot expect a response for the deregister request. In this case, 1499 + * it is safe to directly destroy the exec queue on driver side, as the GuC 1500 + * will not process further requests and all resources must be cleaned up locally. 1501 + */ 1502 + if (exec_queue_registered(q) && xe_uc_fw_is_running(&guc->fw)) 1494 1503 disable_scheduling_deregister(guc, q); 1495 1504 else 1496 1505 __guc_exec_queue_destroy(guc, q);

+4 -2

drivers/gpu/drm/xe/xe_migrate.c

··· 434 434 435 435 err = xe_migrate_lock_prepare_vm(tile, m, vm); 436 436 if (err) 437 - return err; 437 + goto err_out; 438 438 439 439 if (xe->info.has_usm) { 440 440 struct xe_hw_engine *hwe = xe_gt_hw_engine(primary_gt, ··· 2113 2113 if (current_bytes & ~PAGE_MASK) { 2114 2114 int pitch = 4; 2115 2115 2116 - current_bytes = min_t(int, current_bytes, S16_MAX * pitch); 2116 + current_bytes = min_t(int, current_bytes, 2117 + round_down(S16_MAX * pitch, 2118 + XE_CACHELINE_BYTES)); 2117 2119 } 2118 2120 2119 2121 __fence = xe_migrate_vram(m, current_bytes,

drivers/gpu/drm/xe/xe_pci.c

··· 867 867 if (err) 868 868 return err; 869 869 870 + xe_vram_resize_bar(xe); 871 + 870 872 err = xe_device_probe_early(xe); 871 873 /* 872 874 * In Boot Survivability mode, no drm card is exposed and driver

+15 -2

drivers/gpu/drm/xe/xe_svm.c

··· 1034 1034 if (err) 1035 1035 return err; 1036 1036 1037 + dpagemap = xe_vma_resolve_pagemap(vma, tile); 1038 + if (!dpagemap && !ctx.devmem_only) 1039 + ctx.device_private_page_owner = NULL; 1037 1040 range = xe_svm_range_find_or_insert(vm, fault_addr, vma, &ctx); 1038 1041 1039 1042 if (IS_ERR(range)) ··· 1057 1054 1058 1055 range_debug(range, "PAGE FAULT"); 1059 1056 1060 - dpagemap = xe_vma_resolve_pagemap(vma, tile); 1061 1057 if (--migrate_try_count >= 0 && 1062 1058 xe_svm_range_needs_migrate_to_vram(range, vma, !!dpagemap || ctx.devmem_only)) { 1063 1059 ktime_t migrate_start = xe_svm_stats_ktime_get(); ··· 1075 1073 drm_dbg(&vm->xe->drm, 1076 1074 "VRAM allocation failed, falling back to retrying fault, asid=%u, errno=%pe\n", 1077 1075 vm->usm.asid, ERR_PTR(err)); 1078 - goto retry; 1076 + 1077 + /* 1078 + * In the devmem-only case, mixed mappings may 1079 + * be found. The get_pages function will fix 1080 + * these up to a single location, allowing the 1081 + * page fault handler to make forward progress. 1082 + */ 1083 + if (ctx.devmem_only) 1084 + goto get_pages; 1085 + else 1086 + goto retry; 1079 1087 } else { 1080 1088 drm_err(&vm->xe->drm, 1081 1089 "VRAM allocation failed, retry count exceeded, asid=%u, errno=%pe\n", ··· 1095 1083 } 1096 1084 } 1097 1085 1086 + get_pages: 1098 1087 get_pages_start = xe_svm_stats_ktime_get(); 1099 1088 1100 1089 range_debug(range, "GET PAGES");

+23 -9

drivers/gpu/drm/xe/xe_vm.c

··· 2832 2832 } 2833 2833 2834 2834 static int vma_lock_and_validate(struct drm_exec *exec, struct xe_vma *vma, 2835 - bool validate) 2835 + bool res_evict, bool validate) 2836 2836 { 2837 2837 struct xe_bo *bo = xe_vma_bo(vma); 2838 2838 struct xe_vm *vm = xe_vma_vm(vma); ··· 2843 2843 err = drm_exec_lock_obj(exec, &bo->ttm.base); 2844 2844 if (!err && validate) 2845 2845 err = xe_bo_validate(bo, vm, 2846 - !xe_vm_in_preempt_fence_mode(vm), exec); 2846 + !xe_vm_in_preempt_fence_mode(vm) && 2847 + res_evict, exec); 2847 2848 } 2848 2849 2849 2850 return err; ··· 2914 2913 } 2915 2914 2916 2915 static int op_lock_and_prep(struct drm_exec *exec, struct xe_vm *vm, 2917 - struct xe_vma_op *op) 2916 + struct xe_vma_ops *vops, struct xe_vma_op *op) 2918 2917 { 2919 2918 int err = 0; 2919 + bool res_evict; 2920 + 2921 + /* 2922 + * We only allow evicting a BO within the VM if it is not part of an 2923 + * array of binds, as an array of binds can evict another BO within the 2924 + * bind. 2925 + */ 2926 + res_evict = !(vops->flags & XE_VMA_OPS_ARRAY_OF_BINDS); 2920 2927 2921 2928 switch (op->base.op) { 2922 2929 case DRM_GPUVA_OP_MAP: 2923 2930 if (!op->map.invalidate_on_bind) 2924 2931 err = vma_lock_and_validate(exec, op->map.vma, 2932 + res_evict, 2925 2933 !xe_vm_in_fault_mode(vm) || 2926 2934 op->map.immediate); 2927 2935 break; ··· 2941 2931 2942 2932 err = vma_lock_and_validate(exec, 2943 2933 gpuva_to_vma(op->base.remap.unmap->va), 2944 - false); 2934 + res_evict, false); 2945 2935 if (!err && op->remap.prev) 2946 - err = vma_lock_and_validate(exec, op->remap.prev, true); 2936 + err = vma_lock_and_validate(exec, op->remap.prev, 2937 + res_evict, true); 2947 2938 if (!err && op->remap.next) 2948 - err = vma_lock_and_validate(exec, op->remap.next, true); 2939 + err = vma_lock_and_validate(exec, op->remap.next, 2940 + res_evict, true); 2949 2941 break; 2950 2942 case DRM_GPUVA_OP_UNMAP: 2951 2943 err = check_ufence(gpuva_to_vma(op->base.unmap.va)); ··· 2956 2944 2957 2945 err = vma_lock_and_validate(exec, 2958 2946 gpuva_to_vma(op->base.unmap.va), 2959 - false); 2947 + res_evict, false); 2960 2948 break; 2961 2949 case DRM_GPUVA_OP_PREFETCH: 2962 2950 { ··· 2971 2959 2972 2960 err = vma_lock_and_validate(exec, 2973 2961 gpuva_to_vma(op->base.prefetch.va), 2974 - false); 2962 + res_evict, false); 2975 2963 if (!err && !xe_vma_has_no_bo(vma)) 2976 2964 err = xe_bo_migrate(xe_vma_bo(vma), 2977 2965 region_to_mem_type[region], ··· 3017 3005 return err; 3018 3006 3019 3007 list_for_each_entry(op, &vops->list, link) { 3020 - err = op_lock_and_prep(exec, vm, op); 3008 + err = op_lock_and_prep(exec, vm, vops, op); 3021 3009 if (err) 3022 3010 return err; 3023 3011 } ··· 3650 3638 } 3651 3639 3652 3640 xe_vma_ops_init(&vops, vm, q, syncs, num_syncs); 3641 + if (args->num_binds > 1) 3642 + vops.flags |= XE_VMA_OPS_ARRAY_OF_BINDS; 3653 3643 for (i = 0; i < args->num_binds; ++i) { 3654 3644 u64 range = bind_ops[i].range; 3655 3645 u64 addr = bind_ops[i].addr;

drivers/gpu/drm/xe/xe_vm_types.h

··· 476 476 /** @flag: signify the properties within xe_vma_ops*/ 477 477 #define XE_VMA_OPS_FLAG_HAS_SVM_PREFETCH BIT(0) 478 478 #define XE_VMA_OPS_FLAG_MADVISE BIT(1) 479 + #define XE_VMA_OPS_ARRAY_OF_BINDS BIT(2) 479 480 u32 flags; 480 481 #ifdef TEST_VM_OPS_ERROR 481 482 /** @inject_error: inject error to test error handling */

+26 -8

drivers/gpu/drm/xe/xe_vram.c

··· 26 26 27 27 #define BAR_SIZE_SHIFT 20 28 28 29 - static void 30 - _resize_bar(struct xe_device *xe, int resno, resource_size_t size) 29 + /* 30 + * Release all the BARs that could influence/block LMEMBAR resizing, i.e. 31 + * assigned IORESOURCE_MEM_64 BARs 32 + */ 33 + static void release_bars(struct pci_dev *pdev) 34 + { 35 + struct resource *res; 36 + int i; 37 + 38 + pci_dev_for_each_resource(pdev, res, i) { 39 + /* Resource already un-assigned, do not reset it */ 40 + if (!res->parent) 41 + continue; 42 + 43 + /* No need to release unrelated BARs */ 44 + if (!(res->flags & IORESOURCE_MEM_64)) 45 + continue; 46 + 47 + pci_release_resource(pdev, i); 48 + } 49 + } 50 + 51 + static void resize_bar(struct xe_device *xe, int resno, resource_size_t size) 31 52 { 32 53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 33 54 int bar_size = pci_rebar_bytes_to_size(size); 34 55 int ret; 35 56 36 - if (pci_resource_len(pdev, resno)) 37 - pci_release_resource(pdev, resno); 57 + release_bars(pdev); 38 58 39 59 ret = pci_resize_resource(pdev, resno, bar_size); 40 60 if (ret) { ··· 70 50 * if force_vram_bar_size is set, attempt to set to the requested size 71 51 * else set to maximum possible size 72 52 */ 73 - static void resize_vram_bar(struct xe_device *xe) 53 + void xe_vram_resize_bar(struct xe_device *xe) 74 54 { 75 55 int force_vram_bar_size = xe_modparam.force_vram_bar_size; 76 56 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); ··· 139 119 pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); 140 120 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); 141 121 142 - _resize_bar(xe, LMEM_BAR, rebar_size); 122 + resize_bar(xe, LMEM_BAR, rebar_size); 143 123 144 124 pci_assign_unassigned_bus_resources(pdev->bus); 145 125 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); ··· 167 147 drm_err(&xe->drm, "pci resource is not valid\n"); 168 148 return -ENXIO; 169 149 } 170 - 171 - resize_vram_bar(xe); 172 150 173 151 lmem_bar->io_start = pci_resource_start(pdev, LMEM_BAR); 174 152 lmem_bar->io_size = pci_resource_len(pdev, LMEM_BAR);

drivers/gpu/drm/xe/xe_vram.h

··· 11 11 struct xe_device; 12 12 struct xe_vram_region; 13 13 14 + void xe_vram_resize_bar(struct xe_device *xe); 14 15 int xe_vram_probe(struct xe_device *xe); 15 16 16 17 struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement);

+1 -1

include/drm/drm_gpuvm.h

··· 1078 1078 */ 1079 1079 struct drm_gpuvm_map_req { 1080 1080 /** 1081 - * @op_map: struct drm_gpuva_op_map 1081 + * @map: struct drm_gpuva_op_map 1082 1082 */ 1083 1083 struct drm_gpuva_op_map map; 1084 1084 };

-21

include/uapi/drm/amdgpu_drm.h

··· 1555 1555 __u32 userq_num_slots; 1556 1556 }; 1557 1557 1558 - /* GFX metadata BO sizes and alignment info (in bytes) */ 1559 - struct drm_amdgpu_info_uq_fw_areas_gfx { 1560 - /* shadow area size */ 1561 - __u32 shadow_size; 1562 - /* shadow area base virtual mem alignment */ 1563 - __u32 shadow_alignment; 1564 - /* context save area size */ 1565 - __u32 csa_size; 1566 - /* context save area base virtual mem alignment */ 1567 - __u32 csa_alignment; 1568 - }; 1569 - 1570 - /* IP specific fw related information used in the 1571 - * subquery AMDGPU_INFO_UQ_FW_AREAS 1572 - */ 1573 - struct drm_amdgpu_info_uq_fw_areas { 1574 - union { 1575 - struct drm_amdgpu_info_uq_fw_areas_gfx gfx; 1576 - }; 1577 - }; 1578 - 1579 1558 struct drm_amdgpu_info_num_handles { 1580 1559 /** Max handles as supported by firmware for UVD */ 1581 1560 __u32 uvd_max_handles;

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