drm/v3d: Fix performance counter source settings on V3D 7.x

When the new register addresses were introduced for V3D 7.x, we added
new masks for performance counter sources on V3D 7.x. Nevertheless,
we never apply these new masks when setting the sources.

Fix the performance counter source settings on V3D 7.x by introducing
a new macro, `V3D_SET_FIELD_VER`, which allows fields setting to vary
by version. Using this macro, we can provide different values for
source mask based on the V3D version, ensuring that sources are
correctly configure on V3D 7.x.

Fixes: 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106121736.5707-1-mcanal@igalia.com

Maíra Canal 2 years ago e987e22e 4f537776

+27 -21

3 changed files

expand all

drivers

gpu

drm

v3d

v3d_debugfs.c

v3d_perfmon.c

v3d_regs.h

+2 -2

drivers/gpu/drm/v3d/v3d_debugfs.c

··· 237 237 if (v3d->ver >= 40) { 238 238 int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver); 239 239 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, 240 - V3D_SET_FIELD(cycle_count_reg, 241 - V3D_PCTR_S0)); 240 + V3D_SET_FIELD_VER(cycle_count_reg, 241 + V3D_PCTR_S0, v3d->ver)); 242 242 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1); 243 243 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1); 244 244 } else {

+8 -7

drivers/gpu/drm/v3d/v3d_perfmon.c

··· 240 240 241 241 for (i = 0; i < ncounters; i++) { 242 242 u32 source = i / 4; 243 - u32 channel = V3D_SET_FIELD(perfmon->counters[i], V3D_PCTR_S0); 243 + u32 channel = V3D_SET_FIELD_VER(perfmon->counters[i], V3D_PCTR_S0, 244 + v3d->ver); 244 245 245 246 i++; 246 - channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0, 247 - V3D_PCTR_S1); 247 + channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 248 + V3D_PCTR_S1, v3d->ver); 248 249 i++; 249 - channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0, 250 - V3D_PCTR_S2); 250 + channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 251 + V3D_PCTR_S2, v3d->ver); 251 252 i++; 252 - channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0, 253 - V3D_PCTR_S3); 253 + channel |= V3D_SET_FIELD_VER(i < ncounters ? perfmon->counters[i] : 0, 254 + V3D_PCTR_S3, v3d->ver); 254 255 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_SRC_X(source), channel); 255 256 } 256 257

+17 -12

drivers/gpu/drm/v3d/v3d_regs.h

··· 15 15 fieldval & field##_MASK; \ 16 16 }) 17 17 18 + #define V3D_SET_FIELD_VER(value, field, ver) \ 19 + ({ \ 20 + typeof(ver) _ver = (ver); \ 21 + u32 fieldval = (value) << field##_SHIFT(_ver); \ 22 + WARN_ON((fieldval & ~field##_MASK(_ver)) != 0); \ 23 + fieldval & field##_MASK(_ver); \ 24 + }) 25 + 18 26 #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 19 27 field##_SHIFT) 20 28 ··· 362 354 #define V3D_V4_PCTR_0_SRC_28_31 0x0067c 363 355 #define V3D_V4_PCTR_0_SRC_X(x) (V3D_V4_PCTR_0_SRC_0_3 + \ 364 356 4 * (x)) 365 - # define V3D_PCTR_S0_MASK V3D_MASK(6, 0) 366 - # define V3D_V7_PCTR_S0_MASK V3D_MASK(7, 0) 367 - # define V3D_PCTR_S0_SHIFT 0 368 - # define V3D_PCTR_S1_MASK V3D_MASK(14, 8) 369 - # define V3D_V7_PCTR_S1_MASK V3D_MASK(15, 8) 370 - # define V3D_PCTR_S1_SHIFT 8 371 - # define V3D_PCTR_S2_MASK V3D_MASK(22, 16) 372 - # define V3D_V7_PCTR_S2_MASK V3D_MASK(23, 16) 373 - # define V3D_PCTR_S2_SHIFT 16 374 - # define V3D_PCTR_S3_MASK V3D_MASK(30, 24) 375 - # define V3D_V7_PCTR_S3_MASK V3D_MASK(31, 24) 376 - # define V3D_PCTR_S3_SHIFT 24 357 + # define V3D_PCTR_S0_MASK(ver) (((ver) >= 71) ? V3D_MASK(7, 0) : V3D_MASK(6, 0)) 358 + # define V3D_PCTR_S0_SHIFT(ver) 0 359 + # define V3D_PCTR_S1_MASK(ver) (((ver) >= 71) ? V3D_MASK(15, 8) : V3D_MASK(14, 8)) 360 + # define V3D_PCTR_S1_SHIFT(ver) 8 361 + # define V3D_PCTR_S2_MASK(ver) (((ver) >= 71) ? V3D_MASK(23, 16) : V3D_MASK(22, 16)) 362 + # define V3D_PCTR_S2_SHIFT(ver) 16 363 + # define V3D_PCTR_S3_MASK(ver) (((ver) >= 71) ? V3D_MASK(31, 24) : V3D_MASK(30, 24)) 364 + # define V3D_PCTR_S3_SHIFT(ver) 24 365 + 377 366 #define V3D_PCTR_CYCLE_COUNT(ver) ((ver >= 71) ? 0 : 32) 378 367 379 368 /* Output values of the counters. */

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