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drm/amdgpu: simplify VM update tracking a bit

Store the 64bit sequence directly. Makes it simpler to use and saves a bit
of fence reference counting overhead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Christian König and committed by
Alex Deucher
e997b827 184a69ca

+16 -37
+11 -29
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
··· 276 276 struct amdgpu_device *adev = ring->adev; 277 277 unsigned vmhub = ring->funcs->vmhub; 278 278 uint64_t fence_context = adev->fence_context + ring->idx; 279 - struct dma_fence *updates = sync->last_vm_update; 280 279 bool needs_flush = vm->use_cpu_for_update; 281 - int r = 0; 280 + uint64_t updates = sync->last_vm_update; 281 + int r; 282 282 283 283 *id = vm->reserved_vmid[vmhub]; 284 - if (updates && (*id)->flushed_updates && 285 - updates->context == (*id)->flushed_updates->context && 286 - !dma_fence_is_later(updates, (*id)->flushed_updates)) 287 - updates = NULL; 288 - 289 284 if ((*id)->owner != vm->immediate.fence_context || 290 - job->vm_pd_addr != (*id)->pd_gpu_addr || 291 - updates || !(*id)->last_flush || 285 + (*id)->pd_gpu_addr != job->vm_pd_addr || 286 + (*id)->flushed_updates < updates || 287 + !(*id)->last_flush || 292 288 ((*id)->last_flush->context != fence_context && 293 289 !dma_fence_is_signaled((*id)->last_flush))) { 294 290 struct dma_fence *tmp; ··· 298 302 tmp = amdgpu_sync_peek_fence(&(*id)->active, ring); 299 303 if (tmp) { 300 304 *id = NULL; 301 - r = amdgpu_sync_fence(sync, tmp); 302 - return r; 305 + return amdgpu_sync_fence(sync, tmp); 303 306 } 304 307 needs_flush = true; 305 308 } ··· 310 315 if (r) 311 316 return r; 312 317 313 - if (updates) { 314 - dma_fence_put((*id)->flushed_updates); 315 - (*id)->flushed_updates = dma_fence_get(updates); 316 - } 318 + (*id)->flushed_updates = updates; 317 319 job->vm_needs_flush = needs_flush; 318 320 return 0; 319 321 } ··· 338 346 unsigned vmhub = ring->funcs->vmhub; 339 347 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; 340 348 uint64_t fence_context = adev->fence_context + ring->idx; 341 - struct dma_fence *updates = sync->last_vm_update; 349 + uint64_t updates = sync->last_vm_update; 342 350 int r; 343 351 344 352 job->vm_needs_flush = vm->use_cpu_for_update; ··· 346 354 /* Check if we can use a VMID already assigned to this VM */ 347 355 list_for_each_entry_reverse((*id), &id_mgr->ids_lru, list) { 348 356 bool needs_flush = vm->use_cpu_for_update; 349 - struct dma_fence *flushed; 350 357 351 358 /* Check all the prerequisites to using this VMID */ 352 359 if ((*id)->owner != vm->immediate.fence_context) ··· 359 368 !dma_fence_is_signaled((*id)->last_flush))) 360 369 needs_flush = true; 361 370 362 - flushed = (*id)->flushed_updates; 363 - if (updates && (!flushed || dma_fence_is_later(updates, flushed))) 371 + if ((*id)->flushed_updates < updates) 364 372 needs_flush = true; 365 373 366 374 if (needs_flush && !adev->vm_manager.concurrent_flush) ··· 372 382 if (r) 373 383 return r; 374 384 375 - if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { 376 - dma_fence_put((*id)->flushed_updates); 377 - (*id)->flushed_updates = dma_fence_get(updates); 378 - } 379 - 385 + (*id)->flushed_updates = updates; 380 386 job->vm_needs_flush |= needs_flush; 381 387 return 0; 382 388 } ··· 418 432 goto error; 419 433 420 434 if (!id) { 421 - struct dma_fence *updates = sync->last_vm_update; 422 - 423 435 /* Still no ID to use? Then use the idle one found earlier */ 424 436 id = idle; 425 437 ··· 426 442 if (r) 427 443 goto error; 428 444 429 - dma_fence_put(id->flushed_updates); 430 - id->flushed_updates = dma_fence_get(updates); 445 + id->flushed_updates = sync->last_vm_update; 431 446 job->vm_needs_flush = true; 432 447 } 433 448 ··· 593 610 struct amdgpu_vmid *id = &id_mgr->ids[j]; 594 611 595 612 amdgpu_sync_free(&id->active); 596 - dma_fence_put(id->flushed_updates); 597 613 dma_fence_put(id->last_flush); 598 614 dma_fence_put(id->pasid_mapping); 599 615 }
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
··· 47 47 48 48 uint64_t pd_gpu_addr; 49 49 /* last flushed PD/PT update */ 50 - struct dma_fence *flushed_updates; 50 + uint64_t flushed_updates; 51 51 52 52 uint32_t current_gpu_reset_count; 53 53
+3 -6
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
··· 51 51 void amdgpu_sync_create(struct amdgpu_sync *sync) 52 52 { 53 53 hash_init(sync->fences); 54 - sync->last_vm_update = NULL; 54 + sync->last_vm_update = 0; 55 55 } 56 56 57 57 /** ··· 184 184 if (!fence) 185 185 return 0; 186 186 187 - amdgpu_sync_keep_later(&sync->last_vm_update, fence); 187 + sync->last_vm_update = max(sync->last_vm_update, fence->seqno); 188 188 return amdgpu_sync_fence(sync, fence); 189 189 } 190 190 ··· 376 376 } 377 377 } 378 378 379 - dma_fence_put(clone->last_vm_update); 380 - clone->last_vm_update = dma_fence_get(source->last_vm_update); 379 + clone->last_vm_update = source->last_vm_update; 381 380 382 381 return 0; 383 382 } ··· 418 419 dma_fence_put(e->fence); 419 420 kmem_cache_free(amdgpu_sync_slab, e); 420 421 } 421 - 422 - dma_fence_put(sync->last_vm_update); 423 422 } 424 423 425 424 /**
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
··· 43 43 */ 44 44 struct amdgpu_sync { 45 45 DECLARE_HASHTABLE(fences, 4); 46 - struct dma_fence *last_vm_update; 46 + uint64_t last_vm_update; 47 47 }; 48 48 49 49 void amdgpu_sync_create(struct amdgpu_sync *sync);