tjh.dev / kernel
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EDAC/amd64: Generate ctl_name string at runtime

Currently, the ctl_name string is statically assigned based on the family and
model of the SOC when the amd64_edac module is loaded.

The same, however, is not exactly needed as the string can be generated and
assigned at runtime through scnprintf().

Remove all static assignments and generate the string at runtime. Also,
cleanup the switch cases which became defunct and consolidate identical cases.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20251106015727.1987246-1-avadhut.naik@amd.com

authored by

Avadhut Naik and committed by
Borislav Petkov (AMD) e9abd990 3a866087

+13 -47
+10 -46
drivers/edac/amd64_edac.c
··· 3766 3766 pvt->stepping = boot_cpu_data.x86_stepping; 3767 3767 pvt->model = boot_cpu_data.x86_model; 3768 3768 pvt->fam = boot_cpu_data.x86; 3769 + char *tmp_name = NULL; 3769 3770 pvt->max_mcs = 2; 3770 3771 3771 3772 /* ··· 3780 3779 3781 3780 switch (pvt->fam) { 3782 3781 case 0xf: 3783 - pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? 3782 + tmp_name = (pvt->ext_model >= K8_REV_F) ? 3784 3783 "K8 revF or later" : "K8 revE or earlier"; 3785 3784 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; 3786 3785 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; ··· 3789 3788 break; 3790 3789 3791 3790 case 0x10: 3792 - pvt->ctl_name = "F10h"; 3793 3791 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; 3794 3792 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; 3795 3793 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; ··· 3797 3797 case 0x15: 3798 3798 switch (pvt->model) { 3799 3799 case 0x30: 3800 - pvt->ctl_name = "F15h_M30h"; 3801 3800 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; 3802 3801 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; 3803 3802 break; 3804 3803 case 0x60: 3805 - pvt->ctl_name = "F15h_M60h"; 3806 3804 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; 3807 3805 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; 3808 3806 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; ··· 3809 3811 /* Richland is only client */ 3810 3812 return -ENODEV; 3811 3813 default: 3812 - pvt->ctl_name = "F15h"; 3813 3814 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; 3814 3815 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; 3815 3816 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; ··· 3819 3822 case 0x16: 3820 3823 switch (pvt->model) { 3821 3824 case 0x30: 3822 - pvt->ctl_name = "F16h_M30h"; 3823 3825 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; 3824 3826 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; 3825 3827 break; 3826 3828 default: 3827 - pvt->ctl_name = "F16h"; 3828 3829 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; 3829 3830 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; 3830 3831 break; ··· 3831 3836 3832 3837 case 0x17: 3833 3838 switch (pvt->model) { 3834 - case 0x10 ... 0x2f: 3835 - pvt->ctl_name = "F17h_M10h"; 3836 - break; 3837 3839 case 0x30 ... 0x3f: 3838 - pvt->ctl_name = "F17h_M30h"; 3839 3840 pvt->max_mcs = 8; 3840 3841 break; 3841 - case 0x60 ... 0x6f: 3842 - pvt->ctl_name = "F17h_M60h"; 3843 - break; 3844 - case 0x70 ... 0x7f: 3845 - pvt->ctl_name = "F17h_M70h"; 3846 - break; 3847 3842 default: 3848 - pvt->ctl_name = "F17h"; 3849 3843 break; 3850 3844 } 3851 3845 break; 3852 3846 3853 3847 case 0x18: 3854 - pvt->ctl_name = "F18h"; 3855 3848 break; 3856 3849 3857 3850 case 0x19: 3858 3851 switch (pvt->model) { 3859 3852 case 0x00 ... 0x0f: 3860 - pvt->ctl_name = "F19h"; 3861 3853 pvt->max_mcs = 8; 3862 3854 break; 3863 3855 case 0x10 ... 0x1f: 3864 - pvt->ctl_name = "F19h_M10h"; 3865 3856 pvt->max_mcs = 12; 3866 3857 pvt->flags.zn_regs_v2 = 1; 3867 3858 break; 3868 - case 0x20 ... 0x2f: 3869 - pvt->ctl_name = "F19h_M20h"; 3870 - break; 3871 3859 case 0x30 ... 0x3f: 3872 3860 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { 3873 - pvt->ctl_name = "MI200"; 3861 + tmp_name = "MI200"; 3874 3862 pvt->max_mcs = 4; 3875 3863 pvt->dram_type = MEM_HBM2; 3876 3864 pvt->gpu_umc_base = 0x50000; 3877 3865 pvt->ops = &gpu_ops; 3878 3866 } else { 3879 - pvt->ctl_name = "F19h_M30h"; 3880 3867 pvt->max_mcs = 8; 3881 3868 } 3882 3869 break; 3883 - case 0x50 ... 0x5f: 3884 - pvt->ctl_name = "F19h_M50h"; 3885 - break; 3886 3870 case 0x60 ... 0x6f: 3887 - pvt->ctl_name = "F19h_M60h"; 3888 3871 pvt->flags.zn_regs_v2 = 1; 3889 3872 break; 3890 3873 case 0x70 ... 0x7f: 3891 - pvt->ctl_name = "F19h_M70h"; 3892 3874 pvt->max_mcs = 4; 3893 3875 pvt->flags.zn_regs_v2 = 1; 3894 3876 break; 3895 3877 case 0x90 ... 0x9f: 3896 - pvt->ctl_name = "F19h_M90h"; 3897 3878 pvt->max_mcs = 4; 3898 3879 pvt->dram_type = MEM_HBM3; 3899 3880 pvt->gpu_umc_base = 0x90000; 3900 3881 pvt->ops = &gpu_ops; 3901 3882 break; 3902 3883 case 0xa0 ... 0xaf: 3903 - pvt->ctl_name = "F19h_MA0h"; 3904 3884 pvt->max_mcs = 12; 3905 3885 pvt->flags.zn_regs_v2 = 1; 3906 3886 break; ··· 3885 3915 case 0x1A: 3886 3916 switch (pvt->model) { 3887 3917 case 0x00 ... 0x1f: 3888 - pvt->ctl_name = "F1Ah"; 3889 3918 pvt->max_mcs = 12; 3890 3919 pvt->flags.zn_regs_v2 = 1; 3891 3920 break; 3892 3921 case 0x40 ... 0x4f: 3893 - pvt->ctl_name = "F1Ah_M40h"; 3894 3922 pvt->flags.zn_regs_v2 = 1; 3895 3923 break; 3896 3924 case 0x50 ... 0x57: 3897 - pvt->ctl_name = "F1Ah_M50h"; 3925 + case 0xc0 ... 0xc7: 3898 3926 pvt->max_mcs = 16; 3899 3927 pvt->flags.zn_regs_v2 = 1; 3900 3928 break; 3901 3929 case 0x90 ... 0x9f: 3902 - pvt->ctl_name = "F1Ah_M90h"; 3903 - pvt->max_mcs = 8; 3904 - pvt->flags.zn_regs_v2 = 1; 3905 - break; 3906 3930 case 0xa0 ... 0xaf: 3907 - pvt->ctl_name = "F1Ah_MA0h"; 3908 3931 pvt->max_mcs = 8; 3909 - pvt->flags.zn_regs_v2 = 1; 3910 - break; 3911 - case 0xc0 ... 0xc7: 3912 - pvt->ctl_name = "F1Ah_MC0h"; 3913 - pvt->max_mcs = 16; 3914 3932 pvt->flags.zn_regs_v2 = 1; 3915 3933 break; 3916 3934 } ··· 3908 3950 amd64_err("Unsupported family!\n"); 3909 3951 return -ENODEV; 3910 3952 } 3953 + 3954 + if (tmp_name) 3955 + scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), tmp_name); 3956 + else 3957 + scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "F%02Xh_M%02Xh", 3958 + pvt->fam, pvt->model); 3911 3959 3912 3960 return 0; 3913 3961 }
+3 -1
drivers/edac/amd64_edac.h
··· 101 101 #define ON true 102 102 #define OFF false 103 103 104 + #define MAX_CTL_NAMELEN 19 105 + 104 106 /* 105 107 * PCI-defined configuration space registers 106 108 */ ··· 364 362 /* x4, x8, or x16 syndromes in use */ 365 363 u8 ecc_sym_sz; 366 364 367 - const char *ctl_name; 365 + char ctl_name[MAX_CTL_NAMELEN]; 368 366 u16 f1_id, f2_id; 369 367 /* Maximum number of memory controllers per die/node. */ 370 368 u8 max_mcs;