+3

drivers/net/ethernet/intel/Kconfig

reviewed

··· 231 231 depends on PCI 232 232 select AUXILIARY_BUS 233 233 select LIBIE 234 234 + select LIBIE_ADMINQ 234 235 select NET_DEVLINK 235 236 help 236 237 This driver supports Intel(R) Ethernet Controller XL710 Family of ··· 261 260 config IAVF 262 261 tristate 263 262 select LIBIE 263 263 + select LIBIE_ADMINQ 264 264 select NET_SHAPER 265 265 266 266 config I40EVF ··· 296 294 select AUXILIARY_BUS 297 295 select DIMLIB 298 296 select LIBIE 297 297 + select LIBIE_ADMINQ 299 298 select NET_DEVLINK 300 299 select PACKING 301 300 select PLDMFW

+34 -34

drivers/net/ethernet/intel/i40e/i40e_adminq.c

reviewed

··· 18 18 19 19 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 20 20 (hw->aq.num_asq_entries * 21 21 - sizeof(struct i40e_aq_desc)), 21 21 + sizeof(struct libie_aq_desc)), 22 22 I40E_ADMINQ_DESC_ALIGNMENT); 23 23 if (ret_code) 24 24 return ret_code; ··· 44 44 45 45 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 46 46 (hw->aq.num_arq_entries * 47 47 - sizeof(struct i40e_aq_desc)), 47 47 + sizeof(struct libie_aq_desc)), 48 48 I40E_ADMINQ_DESC_ALIGNMENT); 49 49 50 50 return ret_code; ··· 80 80 **/ 81 81 static int i40e_alloc_arq_bufs(struct i40e_hw *hw) 82 82 { 83 83 - struct i40e_aq_desc *desc; 83 83 + struct libie_aq_desc *desc; 84 84 struct i40e_dma_mem *bi; 85 85 int ret_code; 86 86 int i; ··· 108 108 /* now configure the descriptors for use */ 109 109 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 110 110 111 111 - desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 111 111 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 112 112 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 113 113 - desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 113 113 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 114 114 desc->opcode = 0; 115 115 /* This is in accordance with Admin queue design, there is no 116 116 * register for buffer size configuration ··· 119 119 desc->retval = 0; 120 120 desc->cookie_high = 0; 121 121 desc->cookie_low = 0; 122 122 - desc->params.external.addr_high = 122 122 + desc->params.generic.addr_high = 123 123 cpu_to_le32(upper_32_bits(bi->pa)); 124 124 - desc->params.external.addr_low = 124 124 + desc->params.generic.addr_low = 125 125 cpu_to_le32(lower_32_bits(bi->pa)); 126 126 - desc->params.external.param0 = 0; 127 127 - desc->params.external.param1 = 0; 126 126 + desc->params.generic.param0 = 0; 127 127 + desc->params.generic.param1 = 0; 128 128 } 129 129 130 130 alloc_arq_bufs: ··· 691 691 struct i40e_adminq_ring *asq = &(hw->aq.asq); 692 692 struct i40e_asq_cmd_details *details; 693 693 u16 ntc = asq->next_to_clean; 694 694 - struct i40e_aq_desc desc_cb; 695 695 - struct i40e_aq_desc *desc; 694 694 + struct libie_aq_desc desc_cb; 695 695 + struct libie_aq_desc *desc; 696 696 697 697 desc = I40E_ADMINQ_DESC(*asq, ntc); 698 698 details = I40E_ADMINQ_DETAILS(*asq, ntc); ··· 750 750 **/ 751 751 static int 752 752 i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 753 753 - struct i40e_aq_desc *desc, 753 753 + struct libie_aq_desc *desc, 754 754 void *buff, /* can be NULL */ 755 755 u16 buff_size, 756 756 struct i40e_asq_cmd_details *cmd_details, ··· 758 758 { 759 759 struct i40e_dma_mem *dma_buff = NULL; 760 760 struct i40e_asq_cmd_details *details; 761 761 - struct i40e_aq_desc *desc_on_ring; 761 761 + struct libie_aq_desc *desc_on_ring; 762 762 bool cmd_completed = false; 763 763 u16 retval = 0; 764 764 int status = 0; ··· 771 771 goto asq_send_command_error; 772 772 } 773 773 774 774 - hw->aq.asq_last_status = I40E_AQ_RC_OK; 774 774 + hw->aq.asq_last_status = LIBIE_AQ_RC_OK; 775 775 776 776 val = rd32(hw, I40E_PF_ATQH); 777 777 if (val >= hw->aq.num_asq_entries) { ··· 851 851 /* Update the address values in the desc with the pa value 852 852 * for respective buffer 853 853 */ 854 854 - desc_on_ring->params.external.addr_high = 854 854 + desc_on_ring->params.generic.addr_high = 855 855 cpu_to_le32(upper_32_bits(dma_buff->pa)); 856 856 - desc_on_ring->params.external.addr_low = 856 856 + desc_on_ring->params.generic.addr_low = 857 857 cpu_to_le32(lower_32_bits(dma_buff->pa)); 858 858 } 859 859 ··· 905 905 retval &= 0xff; 906 906 } 907 907 cmd_completed = true; 908 908 - if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 908 908 + if ((enum libie_aq_err)retval == LIBIE_AQ_RC_OK) 909 909 status = 0; 910 910 - else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY) 910 910 + else if ((enum libie_aq_err)retval == LIBIE_AQ_RC_EBUSY) 911 911 status = -EBUSY; 912 912 else 913 913 status = -EIO; 914 914 - hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 914 914 + hw->aq.asq_last_status = (enum libie_aq_err)retval; 915 915 } 916 916 917 917 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, ··· 954 954 **/ 955 955 int 956 956 i40e_asq_send_command_atomic(struct i40e_hw *hw, 957 957 - struct i40e_aq_desc *desc, 957 957 + struct libie_aq_desc *desc, 958 958 void *buff, /* can be NULL */ 959 959 u16 buff_size, 960 960 struct i40e_asq_cmd_details *cmd_details, ··· 972 972 } 973 973 974 974 int 975 975 - i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc, 975 975 + i40e_asq_send_command(struct i40e_hw *hw, struct libie_aq_desc *desc, 976 976 void *buff, /* can be NULL */ u16 buff_size, 977 977 struct i40e_asq_cmd_details *cmd_details) 978 978 { ··· 996 996 **/ 997 997 int 998 998 i40e_asq_send_command_atomic_v2(struct i40e_hw *hw, 999 999 - struct i40e_aq_desc *desc, 999 999 + struct libie_aq_desc *desc, 1000 1000 void *buff, /* can be NULL */ 1001 1001 u16 buff_size, 1002 1002 struct i40e_asq_cmd_details *cmd_details, 1003 1003 bool is_atomic_context, 1004 1004 - enum i40e_admin_queue_err *aq_status) 1004 1004 + enum libie_aq_err *aq_status) 1005 1005 { 1006 1006 int status; 1007 1007 ··· 1023 1023 * 1024 1024 * Fill the desc with default values 1025 1025 **/ 1026 1026 - void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 1026 1026 + void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, 1027 1027 u16 opcode) 1028 1028 { 1029 1029 /* zero out the desc */ 1030 1030 - memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 1030 1030 + memset((void *)desc, 0, sizeof(struct libie_aq_desc)); 1031 1031 desc->opcode = cpu_to_le16(opcode); 1032 1032 - desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); 1032 1032 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 1033 1033 } 1034 1034 1035 1035 /** ··· 1047 1047 u16 *pending) 1048 1048 { 1049 1049 u16 ntc = hw->aq.arq.next_to_clean; 1050 1050 - struct i40e_aq_desc *desc; 1050 1050 + struct libie_aq_desc *desc; 1051 1051 struct i40e_dma_mem *bi; 1052 1052 int ret_code = 0; 1053 1053 u16 desc_idx; ··· 1081 1081 desc_idx = ntc; 1082 1082 1083 1083 hw->aq.arq_last_status = 1084 1084 - (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 1084 1084 + (enum libie_aq_err)le16_to_cpu(desc->retval); 1085 1085 flags = le16_to_cpu(desc->flags); 1086 1086 - if (flags & I40E_AQ_FLAG_ERR) { 1086 1086 + if (flags & LIBIE_AQ_FLAG_ERR) { 1087 1087 ret_code = -EIO; 1088 1088 i40e_debug(hw, 1089 1089 I40E_DEBUG_AQ_MESSAGE, ··· 1107 1107 * size 1108 1108 */ 1109 1109 bi = &hw->aq.arq.r.arq_bi[ntc]; 1110 1110 - memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 1110 1110 + memset((void *)desc, 0, sizeof(struct libie_aq_desc)); 1111 1111 1112 1112 - desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 1112 1112 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 1113 1113 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 1114 1114 - desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 1114 1114 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 1115 1115 desc->datalen = cpu_to_le16((u16)bi->size); 1116 1116 - desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1117 1117 - desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1116 1116 + desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1117 1117 + desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1118 1118 1119 1119 /* set tail = the last cleaned desc index. */ 1120 1120 wr32(hw, I40E_PF_ARQT, ntc);

+6 -6

drivers/net/ethernet/intel/i40e/i40e_adminq.h

reviewed

··· 9 9 #include "i40e_adminq_cmd.h" 10 10 11 11 #define I40E_ADMINQ_DESC(R, i) \ 12 12 - (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i])) 12 12 + (&(((struct libie_aq_desc *)((R).desc_buf.va))[i])) 13 13 14 14 #define I40E_ADMINQ_DESC_ALIGNMENT 4096 15 15 ··· 39 39 u16 flags_dis; 40 40 bool async; 41 41 bool postpone; 42 42 - struct i40e_aq_desc *wb_desc; 42 42 + struct libie_aq_desc *wb_desc; 43 43 }; 44 44 45 45 #define I40E_ADMINQ_DETAILS(R, i) \ ··· 47 47 48 48 /* ARQ event information */ 49 49 struct i40e_arq_event_info { 50 50 - struct i40e_aq_desc desc; 50 50 + struct libie_aq_desc desc; 51 51 u16 msg_len; 52 52 u16 buf_len; 53 53 u8 *msg_buf; ··· 72 72 struct mutex arq_mutex; /* Receive queue lock */ 73 73 74 74 /* last status values on send and receive queues */ 75 75 - enum i40e_admin_queue_err asq_last_status; 76 76 - enum i40e_admin_queue_err arq_last_status; 75 75 + enum libie_aq_err asq_last_status; 76 76 + enum libie_aq_err arq_last_status; 77 77 }; 78 78 79 79 /** ··· 119 119 #define I40E_AQ_LARGE_BUF 512 120 120 #define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */ 121 121 122 122 - void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 122 122 + void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, 123 123 u16 opcode); 124 124 125 125 #endif /* _I40E_ADMINQ_H_ */

+2 -153

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

reviewed

··· 4 4 #ifndef _I40E_ADMINQ_CMD_H_ 5 5 #define _I40E_ADMINQ_CMD_H_ 6 6 7 7 + #include <linux/net/intel/libie/adminq.h> 8 8 + 7 9 #include <linux/bits.h> 8 10 #include <linux/types.h> 9 11 ··· 31 29 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 32 30 /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 33 31 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 34 34 - 35 35 - struct i40e_aq_desc { 36 36 - __le16 flags; 37 37 - __le16 opcode; 38 38 - __le16 datalen; 39 39 - __le16 retval; 40 40 - __le32 cookie_high; 41 41 - __le32 cookie_low; 42 42 - union { 43 43 - struct { 44 44 - __le32 param0; 45 45 - __le32 param1; 46 46 - __le32 param2; 47 47 - __le32 param3; 48 48 - } internal; 49 49 - struct { 50 50 - __le32 param0; 51 51 - __le32 param1; 52 52 - __le32 addr_high; 53 53 - __le32 addr_low; 54 54 - } external; 55 55 - u8 raw[16]; 56 56 - } params; 57 57 - }; 58 58 - 59 59 - /* Flags sub-structure 60 60 - * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 61 61 - * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 62 62 - */ 63 63 - 64 64 - /* command flags and offsets*/ 65 65 - #define I40E_AQ_FLAG_ERR_SHIFT 2 66 66 - #define I40E_AQ_FLAG_LB_SHIFT 9 67 67 - #define I40E_AQ_FLAG_RD_SHIFT 10 68 68 - #define I40E_AQ_FLAG_BUF_SHIFT 12 69 69 - #define I40E_AQ_FLAG_SI_SHIFT 13 70 70 - 71 71 - #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 72 72 - #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 73 73 - #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 74 74 - #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 75 75 - #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 76 76 - 77 77 - /* error codes */ 78 78 - enum i40e_admin_queue_err { 79 79 - I40E_AQ_RC_OK = 0, /* success */ 80 80 - I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 81 81 - I40E_AQ_RC_ENOENT = 2, /* No such element */ 82 82 - I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 83 83 - I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 84 84 - I40E_AQ_RC_EIO = 5, /* I/O error */ 85 85 - I40E_AQ_RC_ENXIO = 6, /* No such resource */ 86 86 - I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 87 87 - I40E_AQ_RC_EAGAIN = 8, /* Try again */ 88 88 - I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 89 89 - I40E_AQ_RC_EACCES = 10, /* Permission denied */ 90 90 - I40E_AQ_RC_EFAULT = 11, /* Bad address */ 91 91 - I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 92 92 - I40E_AQ_RC_EEXIST = 13, /* object already exists */ 93 93 - I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 94 94 - I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 95 95 - I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 96 96 - I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 97 97 - I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 98 98 - I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 99 99 - I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 100 100 - I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 101 101 - I40E_AQ_RC_EFBIG = 22, /* File too large */ 102 102 - }; 103 32 104 33 /* Admin Queue command opcodes */ 105 34 enum i40e_admin_queue_opc { ··· 253 320 __le16 api_minor; 254 321 }; 255 322 256 256 - I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 257 257 - 258 258 - /* Send driver version (indirect 0x0002) */ 259 259 - struct i40e_aqc_driver_version { 260 260 - u8 driver_major_ver; 261 261 - u8 driver_minor_ver; 262 262 - u8 driver_build_ver; 263 263 - u8 driver_subbuild_ver; 264 264 - u8 reserved[4]; 265 265 - __le32 address_high; 266 266 - __le32 address_low; 267 267 - }; 268 268 - 269 269 - I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 270 270 - 271 323 /* Queue Shutdown (direct 0x0003) */ 272 324 struct i40e_aqc_queue_shutdown { 273 325 __le32 driver_unloading; ··· 269 351 }; 270 352 271 353 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 272 272 - 273 273 - /* Request resource ownership (direct 0x0008) 274 274 - * Release resource ownership (direct 0x0009) 275 275 - */ 276 276 - struct i40e_aqc_request_resource { 277 277 - __le16 resource_id; 278 278 - __le16 access_type; 279 279 - __le32 timeout; 280 280 - __le32 resource_number; 281 281 - u8 reserved[4]; 282 282 - }; 283 283 - 284 284 - I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 285 285 - 286 286 - /* Get function capabilities (indirect 0x000A) 287 287 - * Get device capabilities (indirect 0x000B) 288 288 - */ 289 289 - struct i40e_aqc_list_capabilites { 290 290 - u8 command_flags; 291 291 - u8 pf_index; 292 292 - u8 reserved[2]; 293 293 - __le32 count; 294 294 - __le32 addr_high; 295 295 - __le32 addr_low; 296 296 - }; 297 297 - 298 298 - I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 299 299 - 300 300 - struct i40e_aqc_list_capabilities_element_resp { 301 301 - __le16 id; 302 302 - u8 major_rev; 303 303 - u8 minor_rev; 304 304 - __le32 number; 305 305 - __le32 logical_id; 306 306 - __le32 phys_id; 307 307 - u8 reserved[16]; 308 308 - }; 309 309 - 310 310 - /* list of caps */ 311 311 - 312 312 - #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 313 313 - #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 314 314 - #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 315 315 - #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 316 316 - #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 317 317 - #define I40E_AQ_CAP_ID_SRIOV 0x0012 318 318 - #define I40E_AQ_CAP_ID_VF 0x0013 319 319 - #define I40E_AQ_CAP_ID_VMDQ 0x0014 320 320 - #define I40E_AQ_CAP_ID_8021QBG 0x0015 321 321 - #define I40E_AQ_CAP_ID_8021QBR 0x0016 322 322 - #define I40E_AQ_CAP_ID_VSI 0x0017 323 323 - #define I40E_AQ_CAP_ID_DCB 0x0018 324 324 - #define I40E_AQ_CAP_ID_FCOE 0x0021 325 325 - #define I40E_AQ_CAP_ID_ISCSI 0x0022 326 326 - #define I40E_AQ_CAP_ID_RSS 0x0040 327 327 - #define I40E_AQ_CAP_ID_RXQ 0x0041 328 328 - #define I40E_AQ_CAP_ID_TXQ 0x0042 329 329 - #define I40E_AQ_CAP_ID_MSIX 0x0043 330 330 - #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 331 331 - #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 332 332 - #define I40E_AQ_CAP_ID_1588 0x0046 333 333 - #define I40E_AQ_CAP_ID_IWARP 0x0051 334 334 - #define I40E_AQ_CAP_ID_LED 0x0061 335 335 - #define I40E_AQ_CAP_ID_SDP 0x0062 336 336 - #define I40E_AQ_CAP_ID_MDIO 0x0063 337 337 - #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 338 338 - #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 339 339 - #define I40E_AQ_CAP_ID_FLEX10 0x00F1 340 340 - #define I40E_AQ_CAP_ID_CEM 0x00F2 341 354 342 355 /* Set CPPM Configuration (direct 0x0103) */ 343 356 struct i40e_aqc_cppm_configuration {

+2 -5

drivers/net/ethernet/intel/i40e/i40e_client.c

reviewed

··· 682 682 if (err) { 683 683 dev_info(&pf->pdev->dev, 684 684 "couldn't get PF vsi config, err %pe aq_err %s\n", 685 685 - ERR_PTR(err), 686 686 - i40e_aq_str(&pf->hw, 687 687 - pf->hw.aq.asq_last_status)); 685 685 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 688 686 return -ENOENT; 689 687 } 690 688 ··· 709 711 dev_info(&pf->pdev->dev, 710 712 "update VSI ctxt for PE failed, err %pe aq_err %s\n", 711 713 ERR_PTR(err), 712 712 - i40e_aq_str(&pf->hw, 713 713 - pf->hw.aq.asq_last_status)); 714 714 + libie_aq_str(pf->hw.aq.asq_last_status)); 714 715 } 715 716 } 716 717 return err;

+330 -400

drivers/net/ethernet/intel/i40e/i40e_common.c

reviewed

··· 69 69 } 70 70 71 71 /** 72 72 - * i40e_aq_str - convert AQ err code to a string 73 73 - * @hw: pointer to the HW structure 74 74 - * @aq_err: the AQ error code to convert 75 75 - **/ 76 76 - const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 77 77 - { 78 78 - switch (aq_err) { 79 79 - case I40E_AQ_RC_OK: 80 80 - return "OK"; 81 81 - case I40E_AQ_RC_EPERM: 82 82 - return "I40E_AQ_RC_EPERM"; 83 83 - case I40E_AQ_RC_ENOENT: 84 84 - return "I40E_AQ_RC_ENOENT"; 85 85 - case I40E_AQ_RC_ESRCH: 86 86 - return "I40E_AQ_RC_ESRCH"; 87 87 - case I40E_AQ_RC_EINTR: 88 88 - return "I40E_AQ_RC_EINTR"; 89 89 - case I40E_AQ_RC_EIO: 90 90 - return "I40E_AQ_RC_EIO"; 91 91 - case I40E_AQ_RC_ENXIO: 92 92 - return "I40E_AQ_RC_ENXIO"; 93 93 - case I40E_AQ_RC_E2BIG: 94 94 - return "I40E_AQ_RC_E2BIG"; 95 95 - case I40E_AQ_RC_EAGAIN: 96 96 - return "I40E_AQ_RC_EAGAIN"; 97 97 - case I40E_AQ_RC_ENOMEM: 98 98 - return "I40E_AQ_RC_ENOMEM"; 99 99 - case I40E_AQ_RC_EACCES: 100 100 - return "I40E_AQ_RC_EACCES"; 101 101 - case I40E_AQ_RC_EFAULT: 102 102 - return "I40E_AQ_RC_EFAULT"; 103 103 - case I40E_AQ_RC_EBUSY: 104 104 - return "I40E_AQ_RC_EBUSY"; 105 105 - case I40E_AQ_RC_EEXIST: 106 106 - return "I40E_AQ_RC_EEXIST"; 107 107 - case I40E_AQ_RC_EINVAL: 108 108 - return "I40E_AQ_RC_EINVAL"; 109 109 - case I40E_AQ_RC_ENOTTY: 110 110 - return "I40E_AQ_RC_ENOTTY"; 111 111 - case I40E_AQ_RC_ENOSPC: 112 112 - return "I40E_AQ_RC_ENOSPC"; 113 113 - case I40E_AQ_RC_ENOSYS: 114 114 - return "I40E_AQ_RC_ENOSYS"; 115 115 - case I40E_AQ_RC_ERANGE: 116 116 - return "I40E_AQ_RC_ERANGE"; 117 117 - case I40E_AQ_RC_EFLUSHED: 118 118 - return "I40E_AQ_RC_EFLUSHED"; 119 119 - case I40E_AQ_RC_BAD_ADDR: 120 120 - return "I40E_AQ_RC_BAD_ADDR"; 121 121 - case I40E_AQ_RC_EMODE: 122 122 - return "I40E_AQ_RC_EMODE"; 123 123 - case I40E_AQ_RC_EFBIG: 124 124 - return "I40E_AQ_RC_EFBIG"; 125 125 - } 126 126 - 127 127 - snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 128 128 - return hw->err_str; 129 129 - } 130 130 - 131 131 - /** 132 72 * i40e_debug_aq 133 73 * @hw: debug mask related to admin queue 134 74 * @mask: debug mask ··· 81 141 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 82 142 void *buffer, u16 buf_len) 83 143 { 84 84 - struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 144 144 + struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc; 85 145 u32 effective_mask = hw->debug_mask & mask; 86 146 char prefix[27]; 87 147 u16 len; ··· 104 164 le32_to_cpu(aq_desc->cookie_low)); 105 165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 106 166 "\tparam (0,1) 0x%08X 0x%08X\n", 107 107 - le32_to_cpu(aq_desc->params.internal.param0), 108 108 - le32_to_cpu(aq_desc->params.internal.param1)); 167 167 + le32_to_cpu(aq_desc->params.generic.param0), 168 168 + le32_to_cpu(aq_desc->params.generic.param1)); 109 169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 110 170 "\taddr (h,l) 0x%08X 0x%08X\n", 111 111 - le32_to_cpu(aq_desc->params.external.addr_high), 112 112 - le32_to_cpu(aq_desc->params.external.addr_low)); 171 171 + le32_to_cpu(aq_desc->params.generic.addr_high), 172 172 + le32_to_cpu(aq_desc->params.generic.addr_low)); 113 173 114 174 if (buffer && buf_len != 0 && len != 0 && 115 175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { ··· 154 214 int i40e_aq_queue_shutdown(struct i40e_hw *hw, 155 215 bool unloading) 156 216 { 157 157 - struct i40e_aq_desc desc; 158 158 - struct i40e_aqc_queue_shutdown *cmd = 159 159 - (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 217 217 + struct i40e_aqc_queue_shutdown *cmd; 218 218 + struct libie_aq_desc desc; 160 219 int status; 161 220 162 221 i40e_fill_default_direct_cmd_desc(&desc, 163 222 i40e_aqc_opc_queue_shutdown); 164 223 224 224 + cmd = libie_aq_raw(&desc); 165 225 if (unloading) 166 226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 167 227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); ··· 185 245 u8 *lut, u16 lut_size, 186 246 bool set) 187 247 { 188 188 - struct i40e_aq_desc desc; 189 189 - struct i40e_aqc_get_set_rss_lut *cmd_resp = 190 190 - (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 248 248 + struct i40e_aqc_get_set_rss_lut *cmd_resp; 249 249 + struct libie_aq_desc desc; 191 250 int status; 192 251 u16 flags; 193 252 ··· 197 258 i40e_fill_default_direct_cmd_desc(&desc, 198 259 i40e_aqc_opc_get_rss_lut); 199 260 261 261 + cmd_resp = libie_aq_raw(&desc); 200 262 /* Indirect command */ 201 201 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 202 202 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 263 263 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 264 264 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 203 265 204 266 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 205 267 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); ··· 266 326 struct i40e_aqc_get_set_rss_key_data *key, 267 327 bool set) 268 328 { 269 269 - struct i40e_aq_desc desc; 270 270 - struct i40e_aqc_get_set_rss_key *cmd_resp = 271 271 - (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 272 329 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 330 330 + struct i40e_aqc_get_set_rss_key *cmd_resp; 331 331 + struct libie_aq_desc desc; 273 332 int status; 274 333 275 334 if (set) ··· 278 339 i40e_fill_default_direct_cmd_desc(&desc, 279 340 i40e_aqc_opc_get_rss_key); 280 341 342 342 + cmd_resp = libie_aq_raw(&desc); 281 343 /* Indirect command */ 282 282 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 283 283 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 344 344 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 345 345 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 284 346 285 347 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 286 348 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); ··· 379 439 struct i40e_aqc_mac_address_read_data *addrs, 380 440 struct i40e_asq_cmd_details *cmd_details) 381 441 { 382 382 - struct i40e_aq_desc desc; 383 383 - struct i40e_aqc_mac_address_read *cmd_data = 384 384 - (struct i40e_aqc_mac_address_read *)&desc.params.raw; 442 442 + struct i40e_aqc_mac_address_read *cmd_data; 443 443 + struct libie_aq_desc desc; 385 444 int status; 386 445 387 446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 388 388 - desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 447 447 + cmd_data = libie_aq_raw(&desc); 448 448 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 389 449 390 450 status = i40e_asq_send_command(hw, &desc, addrs, 391 451 sizeof(*addrs), cmd_details); ··· 405 465 u16 flags, u8 *mac_addr, 406 466 struct i40e_asq_cmd_details *cmd_details) 407 467 { 408 408 - struct i40e_aq_desc desc; 409 409 - struct i40e_aqc_mac_address_write *cmd_data = 410 410 - (struct i40e_aqc_mac_address_write *)&desc.params.raw; 468 468 + struct i40e_aqc_mac_address_write *cmd_data; 469 469 + struct libie_aq_desc desc; 411 470 int status; 412 471 413 472 i40e_fill_default_direct_cmd_desc(&desc, 414 473 i40e_aqc_opc_mac_address_write); 474 474 + cmd_data = libie_aq_raw(&desc); 415 475 cmd_data->command_flags = cpu_to_le16(flags); 416 476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 417 477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | ··· 1001 1061 { 1002 1062 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1003 1063 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1004 1004 - struct i40e_aq_desc desc; 1064 1064 + struct libie_aq_desc desc; 1005 1065 int status; 1006 1066 1007 1067 if (!abilities) ··· 1011 1071 i40e_fill_default_direct_cmd_desc(&desc, 1012 1072 i40e_aqc_opc_get_phy_abilities); 1013 1073 1014 1014 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1074 1074 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1015 1075 if (abilities_size > I40E_AQ_LARGE_BUF) 1016 1016 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1076 1076 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1017 1077 1018 1078 if (qualified_modules) 1019 1019 - desc.params.external.param0 |= 1079 1079 + desc.params.generic.param0 |= 1020 1080 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1021 1081 1022 1082 if (report_init) 1023 1023 - desc.params.external.param0 |= 1083 1083 + desc.params.generic.param0 |= 1024 1084 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1025 1085 1026 1086 status = i40e_asq_send_command(hw, &desc, abilities, 1027 1087 abilities_size, cmd_details); 1028 1088 1029 1089 switch (hw->aq.asq_last_status) { 1030 1030 - case I40E_AQ_RC_EIO: 1090 1090 + case LIBIE_AQ_RC_EIO: 1031 1091 status = -EIO; 1032 1092 break; 1033 1033 - case I40E_AQ_RC_EAGAIN: 1093 1093 + case LIBIE_AQ_RC_EAGAIN: 1034 1094 usleep_range(1000, 2000); 1035 1095 total_delay++; 1036 1096 status = -EIO; 1037 1097 break; 1038 1038 - /* also covers I40E_AQ_RC_OK */ 1098 1098 + /* also covers LIBIE_AQ_RC_OK */ 1039 1099 default: 1040 1100 break; 1041 1101 } 1042 1102 1043 1043 - } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1103 1103 + } while ((hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN) && 1044 1104 (total_delay < max_delay)); 1045 1105 1046 1106 if (status) ··· 1077 1137 struct i40e_aq_set_phy_config *config, 1078 1138 struct i40e_asq_cmd_details *cmd_details) 1079 1139 { 1080 1080 - struct i40e_aq_desc desc; 1081 1081 - struct i40e_aq_set_phy_config *cmd = 1082 1082 - (struct i40e_aq_set_phy_config *)&desc.params.raw; 1140 1140 + struct i40e_aq_set_phy_config *cmd; 1141 1141 + struct libie_aq_desc desc; 1083 1142 int status; 1084 1143 1085 1144 if (!config) ··· 1087 1148 i40e_fill_default_direct_cmd_desc(&desc, 1088 1149 i40e_aqc_opc_set_phy_config); 1089 1150 1151 1151 + cmd = libie_aq_raw(&desc); 1090 1152 *cmd = *config; 1091 1153 1092 1154 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 1199 1259 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1200 1260 struct i40e_asq_cmd_details *cmd_details) 1201 1261 { 1202 1202 - struct i40e_aq_desc desc; 1203 1203 - struct i40e_aqc_clear_pxe *cmd = 1204 1204 - (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1262 1262 + struct i40e_aqc_clear_pxe *cmd; 1263 1263 + struct libie_aq_desc desc; 1205 1264 int status; 1206 1265 1207 1266 i40e_fill_default_direct_cmd_desc(&desc, 1208 1267 i40e_aqc_opc_clear_pxe_mode); 1209 1268 1269 1269 + cmd = libie_aq_raw(&desc); 1210 1270 cmd->rx_cnt = 0x2; 1211 1271 1212 1272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 1228 1288 bool enable_link, 1229 1289 struct i40e_asq_cmd_details *cmd_details) 1230 1290 { 1231 1231 - struct i40e_aq_desc desc; 1232 1232 - struct i40e_aqc_set_link_restart_an *cmd = 1233 1233 - (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1291 1291 + struct i40e_aqc_set_link_restart_an *cmd; 1292 1292 + struct libie_aq_desc desc; 1234 1293 int status; 1235 1294 1236 1295 i40e_fill_default_direct_cmd_desc(&desc, 1237 1296 i40e_aqc_opc_set_link_restart_an); 1238 1297 1298 1298 + cmd = libie_aq_raw(&desc); 1239 1299 cmd->command = I40E_AQ_PHY_RESTART_AN; 1240 1300 if (enable_link) 1241 1301 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; ··· 1260 1320 bool enable_lse, struct i40e_link_status *link, 1261 1321 struct i40e_asq_cmd_details *cmd_details) 1262 1322 { 1263 1263 - struct i40e_aq_desc desc; 1264 1264 - struct i40e_aqc_get_link_status *resp = 1265 1265 - (struct i40e_aqc_get_link_status *)&desc.params.raw; 1266 1323 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1324 1324 + struct i40e_aqc_get_link_status *resp; 1325 1325 + struct libie_aq_desc desc; 1267 1326 bool tx_pause, rx_pause; 1268 1327 u16 command_flags; 1269 1328 int status; 1270 1329 1271 1330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1272 1331 1332 1332 + resp = libie_aq_raw(&desc); 1273 1333 if (enable_lse) 1274 1334 command_flags = I40E_AQ_LSE_ENABLE; 1275 1335 else ··· 1355 1415 u16 mask, 1356 1416 struct i40e_asq_cmd_details *cmd_details) 1357 1417 { 1358 1358 - struct i40e_aq_desc desc; 1359 1359 - struct i40e_aqc_set_phy_int_mask *cmd = 1360 1360 - (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1418 1418 + struct i40e_aqc_set_phy_int_mask *cmd; 1419 1419 + struct libie_aq_desc desc; 1361 1420 int status; 1362 1421 1363 1422 i40e_fill_default_direct_cmd_desc(&desc, 1364 1423 i40e_aqc_opc_set_phy_int_mask); 1365 1424 1425 1425 + cmd = libie_aq_raw(&desc); 1366 1426 cmd->event_mask = cpu_to_le16(mask); 1367 1427 1368 1428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 1381 1441 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1382 1442 struct i40e_asq_cmd_details *cmd_details) 1383 1443 { 1384 1384 - struct i40e_aq_desc desc; 1385 1385 - struct i40e_aqc_set_lb_mode *cmd = 1386 1386 - (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1444 1444 + struct i40e_aqc_set_lb_mode *cmd; 1445 1445 + struct libie_aq_desc desc; 1387 1446 1388 1447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1448 1448 + cmd = libie_aq_raw(&desc); 1389 1449 if (ena_lpbk) { 1390 1450 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1391 1451 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); ··· 1407 1467 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1408 1468 struct i40e_asq_cmd_details *cmd_details) 1409 1469 { 1410 1410 - struct i40e_aq_desc desc; 1411 1411 - struct i40e_aqc_set_phy_debug *cmd = 1412 1412 - (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1470 1470 + struct i40e_aqc_set_phy_debug *cmd; 1471 1471 + struct libie_aq_desc desc; 1413 1472 int status; 1414 1473 1415 1474 i40e_fill_default_direct_cmd_desc(&desc, 1416 1475 i40e_aqc_opc_set_phy_debug); 1417 1476 1477 1477 + cmd = libie_aq_raw(&desc); 1418 1478 cmd->command_flags = cmd_flags; 1419 1479 1420 1480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 1434 1494 struct i40e_vsi_context *vsi_ctx, 1435 1495 struct i40e_asq_cmd_details *cmd_details) 1436 1496 { 1437 1437 - struct i40e_aq_desc desc; 1438 1438 - struct i40e_aqc_add_get_update_vsi *cmd = 1439 1439 - (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1440 1440 - struct i40e_aqc_add_get_update_vsi_completion *resp = 1441 1441 - (struct i40e_aqc_add_get_update_vsi_completion *) 1442 1442 - &desc.params.raw; 1497 1497 + struct i40e_aqc_add_get_update_vsi_completion *resp; 1498 1498 + struct i40e_aqc_add_get_update_vsi *cmd; 1499 1499 + struct libie_aq_desc desc; 1443 1500 int status; 1444 1501 1445 1502 i40e_fill_default_direct_cmd_desc(&desc, 1446 1503 i40e_aqc_opc_add_vsi); 1447 1504 1505 1505 + resp = libie_aq_raw(&desc); 1506 1506 + cmd = libie_aq_raw(&desc); 1448 1507 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1449 1508 cmd->connection_type = vsi_ctx->connection_type; 1450 1509 cmd->vf_id = vsi_ctx->vf_num; 1451 1510 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1452 1511 1453 1453 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1512 1512 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1454 1513 1455 1514 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1456 1515 sizeof(vsi_ctx->info), ··· 1477 1538 u16 seid, 1478 1539 struct i40e_asq_cmd_details *cmd_details) 1479 1540 { 1480 1480 - struct i40e_aq_desc desc; 1481 1481 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1482 1482 - (struct i40e_aqc_set_vsi_promiscuous_modes *) 1483 1483 - &desc.params.raw; 1541 1541 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1542 1542 + struct libie_aq_desc desc; 1484 1543 int status; 1485 1544 1486 1545 i40e_fill_default_direct_cmd_desc(&desc, 1487 1546 i40e_aqc_opc_set_vsi_promiscuous_modes); 1488 1547 1548 1548 + cmd = libie_aq_raw(&desc); 1489 1549 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1490 1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1491 1551 cmd->seid = cpu_to_le16(seid); ··· 1504 1566 u16 seid, 1505 1567 struct i40e_asq_cmd_details *cmd_details) 1506 1568 { 1507 1507 - struct i40e_aq_desc desc; 1508 1508 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1509 1509 - (struct i40e_aqc_set_vsi_promiscuous_modes *) 1510 1510 - &desc.params.raw; 1569 1569 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1570 1570 + struct libie_aq_desc desc; 1511 1571 int status; 1512 1572 1513 1573 i40e_fill_default_direct_cmd_desc(&desc, 1514 1574 i40e_aqc_opc_set_vsi_promiscuous_modes); 1515 1575 1576 1576 + cmd = libie_aq_raw(&desc); 1516 1577 cmd->promiscuous_flags = cpu_to_le16(0); 1517 1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1518 1579 cmd->seid = cpu_to_le16(seid); ··· 1534 1597 struct i40e_asq_cmd_details *cmd_details, 1535 1598 bool rx_only_promisc) 1536 1599 { 1537 1537 - struct i40e_aq_desc desc; 1538 1538 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1539 1539 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1600 1600 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1601 1601 + struct libie_aq_desc desc; 1540 1602 u16 flags = 0; 1541 1603 int status; 1542 1604 1543 1605 i40e_fill_default_direct_cmd_desc(&desc, 1544 1606 i40e_aqc_opc_set_vsi_promiscuous_modes); 1545 1607 1608 1608 + cmd = libie_aq_raw(&desc); 1546 1609 if (set) { 1547 1610 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1548 1611 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) ··· 1573 1636 u16 seid, bool set, 1574 1637 struct i40e_asq_cmd_details *cmd_details) 1575 1638 { 1576 1576 - struct i40e_aq_desc desc; 1577 1577 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1578 1578 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1639 1639 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1640 1640 + struct libie_aq_desc desc; 1579 1641 u16 flags = 0; 1580 1642 int status; 1581 1643 1582 1644 i40e_fill_default_direct_cmd_desc(&desc, 1583 1645 i40e_aqc_opc_set_vsi_promiscuous_modes); 1584 1646 1647 1647 + cmd = libie_aq_raw(&desc); 1585 1648 if (set) 1586 1649 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1587 1650 ··· 1608 1671 u16 vid, 1609 1672 struct i40e_asq_cmd_details *cmd_details) 1610 1673 { 1611 1611 - struct i40e_aq_desc desc; 1612 1612 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1613 1613 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1674 1674 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1675 1675 + struct libie_aq_desc desc; 1614 1676 u16 flags = 0; 1615 1677 int status; 1616 1678 1617 1679 i40e_fill_default_direct_cmd_desc(&desc, 1618 1680 i40e_aqc_opc_set_vsi_promiscuous_modes); 1619 1681 1682 1682 + cmd = libie_aq_raw(&desc); 1620 1683 if (enable) 1621 1684 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1622 1685 ··· 1644 1707 u16 vid, 1645 1708 struct i40e_asq_cmd_details *cmd_details) 1646 1709 { 1647 1647 - struct i40e_aq_desc desc; 1648 1648 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1649 1649 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1710 1710 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1711 1711 + struct libie_aq_desc desc; 1650 1712 u16 flags = 0; 1651 1713 int status; 1652 1714 1653 1715 i40e_fill_default_direct_cmd_desc(&desc, 1654 1716 i40e_aqc_opc_set_vsi_promiscuous_modes); 1655 1717 1718 1718 + cmd = libie_aq_raw(&desc); 1656 1719 if (enable) { 1657 1720 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1658 1721 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) ··· 1685 1748 u16 seid, bool enable, u16 vid, 1686 1749 struct i40e_asq_cmd_details *cmd_details) 1687 1750 { 1688 1688 - struct i40e_aq_desc desc; 1689 1689 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1690 1690 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1751 1751 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1752 1752 + struct libie_aq_desc desc; 1691 1753 u16 flags = 0; 1692 1754 int status; 1693 1755 ··· 1696 1760 if (enable) 1697 1761 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1698 1762 1763 1763 + cmd = libie_aq_raw(&desc); 1699 1764 cmd->promiscuous_flags = cpu_to_le16(flags); 1700 1765 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1701 1766 cmd->seid = cpu_to_le16(seid); ··· 1720 1783 u16 seid, bool set_filter, 1721 1784 struct i40e_asq_cmd_details *cmd_details) 1722 1785 { 1723 1723 - struct i40e_aq_desc desc; 1724 1724 - struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1725 1725 - (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1786 1786 + struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1787 1787 + struct libie_aq_desc desc; 1726 1788 int status; 1727 1789 1728 1790 i40e_fill_default_direct_cmd_desc(&desc, 1729 1791 i40e_aqc_opc_set_vsi_promiscuous_modes); 1730 1792 1793 1793 + cmd = libie_aq_raw(&desc); 1731 1794 if (set_filter) 1732 1795 cmd->promiscuous_flags 1733 1796 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); ··· 1752 1815 struct i40e_vsi_context *vsi_ctx, 1753 1816 struct i40e_asq_cmd_details *cmd_details) 1754 1817 { 1755 1755 - struct i40e_aq_desc desc; 1756 1756 - struct i40e_aqc_add_get_update_vsi *cmd = 1757 1757 - (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1758 1758 - struct i40e_aqc_add_get_update_vsi_completion *resp = 1759 1759 - (struct i40e_aqc_add_get_update_vsi_completion *) 1760 1760 - &desc.params.raw; 1818 1818 + struct i40e_aqc_add_get_update_vsi_completion *resp; 1819 1819 + struct i40e_aqc_add_get_update_vsi *cmd; 1820 1820 + struct libie_aq_desc desc; 1761 1821 int status; 1762 1822 1763 1823 i40e_fill_default_direct_cmd_desc(&desc, 1764 1824 i40e_aqc_opc_get_vsi_parameters); 1765 1825 1826 1826 + resp = libie_aq_raw(&desc); 1827 1827 + cmd = libie_aq_raw(&desc); 1766 1828 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1767 1829 1768 1768 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1830 1830 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1769 1831 1770 1832 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1771 1833 sizeof(vsi_ctx->info), NULL); ··· 1793 1857 struct i40e_vsi_context *vsi_ctx, 1794 1858 struct i40e_asq_cmd_details *cmd_details) 1795 1859 { 1796 1796 - struct i40e_aq_desc desc; 1797 1797 - struct i40e_aqc_add_get_update_vsi *cmd = 1798 1798 - (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1799 1799 - struct i40e_aqc_add_get_update_vsi_completion *resp = 1800 1800 - (struct i40e_aqc_add_get_update_vsi_completion *) 1801 1801 - &desc.params.raw; 1860 1860 + struct i40e_aqc_add_get_update_vsi_completion *resp; 1861 1861 + struct i40e_aqc_add_get_update_vsi *cmd; 1862 1862 + struct libie_aq_desc desc; 1802 1863 int status; 1803 1864 1804 1865 i40e_fill_default_direct_cmd_desc(&desc, 1805 1866 i40e_aqc_opc_update_vsi_parameters); 1867 1867 + resp = libie_aq_raw(&desc); 1868 1868 + cmd = libie_aq_raw(&desc); 1806 1869 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1807 1870 1808 1808 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1871 1871 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1809 1872 1810 1873 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1811 1874 sizeof(vsi_ctx->info), ··· 1831 1896 u16 buf_size, u16 *start_seid, 1832 1897 struct i40e_asq_cmd_details *cmd_details) 1833 1898 { 1834 1834 - struct i40e_aq_desc desc; 1835 1835 - struct i40e_aqc_switch_seid *scfg = 1836 1836 - (struct i40e_aqc_switch_seid *)&desc.params.raw; 1899 1899 + struct i40e_aqc_switch_seid *scfg; 1900 1900 + struct libie_aq_desc desc; 1837 1901 int status; 1838 1902 1839 1903 i40e_fill_default_direct_cmd_desc(&desc, 1840 1904 i40e_aqc_opc_get_switch_config); 1841 1841 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1905 1905 + scfg = libie_aq_raw(&desc); 1906 1906 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1842 1907 if (buf_size > I40E_AQ_LARGE_BUF) 1843 1843 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1908 1908 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1844 1909 scfg->seid = cpu_to_le16(*start_seid); 1845 1910 1846 1911 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); ··· 1865 1930 u16 valid_flags, u8 mode, 1866 1931 struct i40e_asq_cmd_details *cmd_details) 1867 1932 { 1868 1868 - struct i40e_aq_desc desc; 1869 1869 - struct i40e_aqc_set_switch_config *scfg = 1870 1870 - (struct i40e_aqc_set_switch_config *)&desc.params.raw; 1933 1933 + struct i40e_aqc_set_switch_config *scfg; 1934 1934 + struct libie_aq_desc desc; 1871 1935 int status; 1872 1936 1873 1937 i40e_fill_default_direct_cmd_desc(&desc, 1874 1938 i40e_aqc_opc_set_switch_config); 1939 1939 + scfg = libie_aq_raw(&desc); 1875 1940 scfg->flags = cpu_to_le16(flags); 1876 1941 scfg->valid_flags = cpu_to_le16(valid_flags); 1877 1942 scfg->mode = mode; ··· 1903 1968 u16 *api_major_version, u16 *api_minor_version, 1904 1969 struct i40e_asq_cmd_details *cmd_details) 1905 1970 { 1906 1906 - struct i40e_aq_desc desc; 1907 1907 - struct i40e_aqc_get_version *resp = 1908 1908 - (struct i40e_aqc_get_version *)&desc.params.raw; 1971 1971 + struct i40e_aqc_get_version *resp; 1972 1972 + struct libie_aq_desc desc; 1909 1973 int status; 1910 1974 1975 1975 + resp = libie_aq_raw(&desc); 1911 1976 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1912 1977 1913 1978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 1940 2005 struct i40e_driver_version *dv, 1941 2006 struct i40e_asq_cmd_details *cmd_details) 1942 2007 { 1943 1943 - struct i40e_aq_desc desc; 1944 1944 - struct i40e_aqc_driver_version *cmd = 1945 1945 - (struct i40e_aqc_driver_version *)&desc.params.raw; 2008 2008 + struct libie_aqc_driver_ver *cmd; 2009 2009 + struct libie_aq_desc desc; 1946 2010 int status; 1947 2011 u16 len; 1948 2012 1949 2013 if (dv == NULL) 1950 2014 return -EINVAL; 1951 2015 2016 2016 + cmd = libie_aq_raw(&desc); 1952 2017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1953 2018 1954 1954 - desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 1955 1955 - cmd->driver_major_ver = dv->major_version; 1956 1956 - cmd->driver_minor_ver = dv->minor_version; 1957 1957 - cmd->driver_build_ver = dv->build_version; 1958 1958 - cmd->driver_subbuild_ver = dv->subbuild_version; 2019 2019 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 2020 2020 + cmd->major_ver = dv->major_version; 2021 2021 + cmd->minor_ver = dv->minor_version; 2022 2022 + cmd->build_ver = dv->build_version; 2023 2023 + cmd->subbuild_ver = dv->subbuild_version; 1959 2024 1960 2025 len = 0; 1961 2026 while (len < sizeof(dv->driver_string) && ··· 2055 2120 bool enable_stats, 2056 2121 struct i40e_asq_cmd_details *cmd_details) 2057 2122 { 2058 2058 - struct i40e_aq_desc desc; 2059 2059 - struct i40e_aqc_add_veb *cmd = 2060 2060 - (struct i40e_aqc_add_veb *)&desc.params.raw; 2061 2061 - struct i40e_aqc_add_veb_completion *resp = 2062 2062 - (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2123 2123 + struct i40e_aqc_add_veb_completion *resp; 2124 2124 + struct i40e_aqc_add_veb *cmd; 2125 2125 + struct libie_aq_desc desc; 2063 2126 u16 veb_flags = 0; 2064 2127 int status; 2065 2128 ··· 2065 2132 if (!!uplink_seid != !!downlink_seid) 2066 2133 return -EINVAL; 2067 2134 2135 2135 + resp = libie_aq_raw(&desc); 2136 2136 + cmd = libie_aq_raw(&desc); 2068 2137 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2069 2138 2070 2139 cmd->uplink_seid = cpu_to_le16(uplink_seid); ··· 2113 2178 u16 *vebs_used, u16 *vebs_free, 2114 2179 struct i40e_asq_cmd_details *cmd_details) 2115 2180 { 2116 2116 - struct i40e_aq_desc desc; 2117 2117 - struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2118 2118 - (struct i40e_aqc_get_veb_parameters_completion *) 2119 2119 - &desc.params.raw; 2181 2181 + struct i40e_aqc_get_veb_parameters_completion *cmd_resp; 2182 2182 + struct libie_aq_desc desc; 2120 2183 int status; 2121 2184 2122 2185 if (veb_seid == 0) 2123 2186 return -EINVAL; 2124 2187 2188 2188 + cmd_resp = libie_aq_raw(&desc); 2125 2189 i40e_fill_default_direct_cmd_desc(&desc, 2126 2190 i40e_aqc_opc_get_veb_parameters); 2127 2191 cmd_resp->seid = cpu_to_le16(veb_seid); ··· 2162 2228 **/ 2163 2229 static u16 2164 2230 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2165 2165 - struct i40e_aq_desc *desc, u16 count, u16 seid) 2231 2231 + struct libie_aq_desc *desc, u16 count, u16 seid) 2166 2232 { 2167 2167 - struct i40e_aqc_macvlan *cmd = 2168 2168 - (struct i40e_aqc_macvlan *)&desc->params.raw; 2233 2233 + struct i40e_aqc_macvlan *cmd = libie_aq_raw(desc); 2169 2234 u16 buf_size; 2170 2235 int i; 2171 2236 ··· 2182 2249 mv_list[i].flags |= 2183 2250 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2184 2251 2185 2185 - desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2252 2252 + desc->flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2186 2253 if (buf_size > I40E_AQ_LARGE_BUF) 2187 2187 - desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2254 2254 + desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2188 2255 2189 2256 return buf_size; 2190 2257 } ··· 2204 2271 struct i40e_aqc_add_macvlan_element_data *mv_list, 2205 2272 u16 count, struct i40e_asq_cmd_details *cmd_details) 2206 2273 { 2207 2207 - struct i40e_aq_desc desc; 2274 2274 + struct libie_aq_desc desc; 2208 2275 u16 buf_size; 2209 2276 2210 2277 if (count == 0 || !mv_list || !hw) ··· 2235 2302 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2236 2303 struct i40e_aqc_add_macvlan_element_data *mv_list, 2237 2304 u16 count, struct i40e_asq_cmd_details *cmd_details, 2238 2238 - enum i40e_admin_queue_err *aq_status) 2305 2305 + enum libie_aq_err *aq_status) 2239 2306 { 2240 2240 - struct i40e_aq_desc desc; 2307 2307 + struct libie_aq_desc desc; 2241 2308 u16 buf_size; 2242 2309 2243 2310 if (count == 0 || !mv_list || !hw) ··· 2264 2331 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2265 2332 u16 count, struct i40e_asq_cmd_details *cmd_details) 2266 2333 { 2267 2267 - struct i40e_aq_desc desc; 2268 2268 - struct i40e_aqc_macvlan *cmd = 2269 2269 - (struct i40e_aqc_macvlan *)&desc.params.raw; 2334 2334 + struct i40e_aqc_macvlan *cmd; 2335 2335 + struct libie_aq_desc desc; 2270 2336 u16 buf_size; 2271 2337 int status; 2272 2338 ··· 2276 2344 2277 2345 /* prep the rest of the request */ 2278 2346 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2347 2347 + cmd = libie_aq_raw(&desc); 2279 2348 cmd->num_addresses = cpu_to_le16(count); 2280 2349 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2281 2350 cmd->seid[1] = 0; 2282 2351 cmd->seid[2] = 0; 2283 2352 2284 2284 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2353 2353 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2285 2354 if (buf_size > I40E_AQ_LARGE_BUF) 2286 2286 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2355 2355 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2287 2356 2288 2357 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2289 2358 cmd_details, true); ··· 2311 2378 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2312 2379 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2313 2380 u16 count, struct i40e_asq_cmd_details *cmd_details, 2314 2314 - enum i40e_admin_queue_err *aq_status) 2381 2381 + enum libie_aq_err *aq_status) 2315 2382 { 2316 2383 struct i40e_aqc_macvlan *cmd; 2317 2317 - struct i40e_aq_desc desc; 2384 2384 + struct libie_aq_desc desc; 2318 2385 u16 buf_size; 2319 2386 2320 2387 if (count == 0 || !mv_list || !hw) ··· 2324 2391 2325 2392 /* prep the rest of the request */ 2326 2393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2327 2327 - cmd = (struct i40e_aqc_macvlan *)&desc.params.raw; 2394 2394 + cmd = libie_aq_raw(&desc); 2328 2395 cmd->num_addresses = cpu_to_le16(count); 2329 2396 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2330 2397 cmd->seid[1] = 0; 2331 2398 cmd->seid[2] = 0; 2332 2399 2333 2333 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2400 2400 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2334 2401 if (buf_size > I40E_AQ_LARGE_BUF) 2335 2335 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2402 2402 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2336 2403 2337 2404 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2338 2405 cmd_details, true, aq_status); ··· 2354 2421 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2355 2422 struct i40e_asq_cmd_details *cmd_details) 2356 2423 { 2357 2357 - struct i40e_aq_desc desc; 2358 2358 - struct i40e_aqc_pf_vf_message *cmd = 2359 2359 - (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2424 2424 + struct i40e_aqc_pf_vf_message *cmd; 2425 2425 + struct libie_aq_desc desc; 2360 2426 int status; 2361 2427 2362 2428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2429 2429 + cmd = libie_aq_raw(&desc); 2363 2430 cmd->id = cpu_to_le32(vfid); 2364 2431 desc.cookie_high = cpu_to_le32(v_opcode); 2365 2432 desc.cookie_low = cpu_to_le32(v_retval); 2366 2366 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2433 2433 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI); 2367 2434 if (msglen) { 2368 2368 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2369 2369 - I40E_AQ_FLAG_RD)); 2435 2435 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 2436 2436 + LIBIE_AQ_FLAG_RD)); 2370 2437 if (msglen > I40E_AQ_LARGE_BUF) 2371 2371 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2438 2438 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2372 2439 desc.datalen = cpu_to_le16(msglen); 2373 2440 } 2374 2441 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); ··· 2389 2456 u32 reg_addr, u64 *reg_val, 2390 2457 struct i40e_asq_cmd_details *cmd_details) 2391 2458 { 2392 2392 - struct i40e_aq_desc desc; 2393 2393 - struct i40e_aqc_debug_reg_read_write *cmd_resp = 2394 2394 - (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2459 2459 + struct i40e_aqc_debug_reg_read_write *cmd_resp; 2460 2460 + struct libie_aq_desc desc; 2395 2461 int status; 2396 2462 2397 2463 if (reg_val == NULL) ··· 2398 2466 2399 2467 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2400 2468 2469 2469 + cmd_resp = libie_aq_raw(&desc); 2401 2470 cmd_resp->address = cpu_to_le32(reg_addr); 2402 2471 2403 2472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 2424 2491 u32 reg_addr, u64 reg_val, 2425 2492 struct i40e_asq_cmd_details *cmd_details) 2426 2493 { 2427 2427 - struct i40e_aq_desc desc; 2428 2428 - struct i40e_aqc_debug_reg_read_write *cmd = 2429 2429 - (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2494 2494 + struct i40e_aqc_debug_reg_read_write *cmd; 2495 2495 + struct libie_aq_desc desc; 2430 2496 int status; 2431 2497 2432 2498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2433 2499 2500 2500 + cmd = libie_aq_raw(&desc); 2434 2501 cmd->address = cpu_to_le32(reg_addr); 2435 2502 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2436 2503 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); ··· 2457 2524 u8 sdp_number, u64 *timeout, 2458 2525 struct i40e_asq_cmd_details *cmd_details) 2459 2526 { 2460 2460 - struct i40e_aq_desc desc; 2461 2461 - struct i40e_aqc_request_resource *cmd_resp = 2462 2462 - (struct i40e_aqc_request_resource *)&desc.params.raw; 2527 2527 + struct libie_aqc_req_res *cmd_resp; 2528 2528 + struct libie_aq_desc desc; 2463 2529 int status; 2464 2530 2465 2531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2466 2532 2467 2467 - cmd_resp->resource_id = cpu_to_le16(resource); 2533 2533 + cmd_resp = libie_aq_raw(&desc); 2534 2534 + cmd_resp->res_id = cpu_to_le16(resource); 2468 2535 cmd_resp->access_type = cpu_to_le16(access); 2469 2469 - cmd_resp->resource_number = cpu_to_le32(sdp_number); 2536 2536 + cmd_resp->res_number = cpu_to_le32(sdp_number); 2470 2537 2471 2538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2472 2539 /* The completion specifies the maximum time in ms that the driver ··· 2475 2542 * busy return value and the timeout field indicates the maximum time 2476 2543 * the current owner of the resource has to free it. 2477 2544 */ 2478 2478 - if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2545 2545 + if (!status || hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY) 2479 2546 *timeout = le32_to_cpu(cmd_resp->timeout); 2480 2547 2481 2548 return status; ··· 2495 2562 u8 sdp_number, 2496 2563 struct i40e_asq_cmd_details *cmd_details) 2497 2564 { 2498 2498 - struct i40e_aq_desc desc; 2499 2499 - struct i40e_aqc_request_resource *cmd = 2500 2500 - (struct i40e_aqc_request_resource *)&desc.params.raw; 2565 2565 + struct libie_aqc_req_res *cmd; 2566 2566 + struct libie_aq_desc desc; 2501 2567 int status; 2502 2568 2503 2569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2504 2570 2505 2505 - cmd->resource_id = cpu_to_le16(resource); 2506 2506 - cmd->resource_number = cpu_to_le32(sdp_number); 2571 2571 + cmd = libie_aq_raw(&desc); 2572 2572 + cmd->res_id = cpu_to_le16(resource); 2573 2573 + cmd->res_number = cpu_to_le32(sdp_number); 2507 2574 2508 2575 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2509 2576 ··· 2527 2594 bool last_command, 2528 2595 struct i40e_asq_cmd_details *cmd_details) 2529 2596 { 2530 2530 - struct i40e_aq_desc desc; 2531 2531 - struct i40e_aqc_nvm_update *cmd = 2532 2532 - (struct i40e_aqc_nvm_update *)&desc.params.raw; 2597 2597 + struct i40e_aqc_nvm_update *cmd; 2598 2598 + struct libie_aq_desc desc; 2533 2599 int status; 2534 2600 2535 2601 /* In offset the highest byte must be zeroed. */ ··· 2539 2607 2540 2608 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2541 2609 2610 2610 + cmd = libie_aq_raw(&desc); 2542 2611 /* If this is the last command in a series, set the proper flag. */ 2543 2612 if (last_command) 2544 2613 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; ··· 2547 2614 cmd->offset = cpu_to_le32(offset); 2548 2615 cmd->length = cpu_to_le16(length); 2549 2616 2550 2550 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2617 2617 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2551 2618 if (length > I40E_AQ_LARGE_BUF) 2552 2552 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2619 2619 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2553 2620 2554 2621 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2555 2622 ··· 2572 2639 u32 offset, u16 length, bool last_command, 2573 2640 struct i40e_asq_cmd_details *cmd_details) 2574 2641 { 2575 2575 - struct i40e_aq_desc desc; 2576 2576 - struct i40e_aqc_nvm_update *cmd = 2577 2577 - (struct i40e_aqc_nvm_update *)&desc.params.raw; 2642 2642 + struct i40e_aqc_nvm_update *cmd; 2643 2643 + struct libie_aq_desc desc; 2578 2644 int status; 2579 2645 2580 2646 /* In offset the highest byte must be zeroed. */ ··· 2584 2652 2585 2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2586 2654 2655 2655 + cmd = libie_aq_raw(&desc); 2587 2656 /* If this is the last command in a series, set the proper flag. */ 2588 2657 if (last_command) 2589 2658 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; ··· 2611 2678 u32 cap_count, 2612 2679 enum i40e_admin_queue_opc list_type_opc) 2613 2680 { 2614 2614 - struct i40e_aqc_list_capabilities_element_resp *cap; 2681 2681 + struct libie_aqc_list_caps_elem *cap; 2615 2682 u32 valid_functions, num_functions; 2616 2683 u32 number, logical_id, phys_id; 2617 2684 struct i40e_hw_capabilities *p; ··· 2620 2687 int status; 2621 2688 u32 i = 0; 2622 2689 2623 2623 - cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2690 2690 + cap = (struct libie_aqc_list_caps_elem *)buff; 2624 2691 2625 2692 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2626 2693 p = &hw->dev_caps; ··· 2630 2697 return; 2631 2698 2632 2699 for (i = 0; i < cap_count; i++, cap++) { 2633 2633 - id = le16_to_cpu(cap->id); 2700 2700 + id = le16_to_cpu(cap->cap); 2634 2701 number = le32_to_cpu(cap->number); 2635 2702 logical_id = le32_to_cpu(cap->logical_id); 2636 2703 phys_id = le32_to_cpu(cap->phys_id); 2637 2637 - major_rev = cap->major_rev; 2704 2704 + major_rev = cap->major_ver; 2638 2705 2639 2706 switch (id) { 2640 2640 - case I40E_AQ_CAP_ID_SWITCH_MODE: 2707 2707 + case LIBIE_AQC_CAPS_SWITCH_MODE: 2641 2708 p->switch_mode = number; 2642 2709 break; 2643 2643 - case I40E_AQ_CAP_ID_MNG_MODE: 2710 2710 + case LIBIE_AQC_CAPS_MNG_MODE: 2644 2711 p->management_mode = number; 2645 2712 if (major_rev > 1) { 2646 2713 p->mng_protocols_over_mctp = logical_id; ··· 2651 2718 p->mng_protocols_over_mctp = 0; 2652 2719 } 2653 2720 break; 2654 2654 - case I40E_AQ_CAP_ID_NPAR_ACTIVE: 2721 2721 + case LIBIE_AQC_CAPS_NPAR_ACTIVE: 2655 2722 p->npar_enable = number; 2656 2723 break; 2657 2657 - case I40E_AQ_CAP_ID_OS2BMC_CAP: 2724 2724 + case LIBIE_AQC_CAPS_OS2BMC_CAP: 2658 2725 p->os2bmc = number; 2659 2726 break; 2660 2660 - case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 2727 2727 + case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2661 2728 p->valid_functions = number; 2662 2729 break; 2663 2663 - case I40E_AQ_CAP_ID_SRIOV: 2730 2730 + case LIBIE_AQC_CAPS_SRIOV: 2664 2731 if (number == 1) 2665 2732 p->sr_iov_1_1 = true; 2666 2733 break; 2667 2667 - case I40E_AQ_CAP_ID_VF: 2734 2734 + case LIBIE_AQC_CAPS_VF: 2668 2735 p->num_vfs = number; 2669 2736 p->vf_base_id = logical_id; 2670 2737 break; 2671 2671 - case I40E_AQ_CAP_ID_VMDQ: 2738 2738 + case LIBIE_AQC_CAPS_VMDQ: 2672 2739 if (number == 1) 2673 2740 p->vmdq = true; 2674 2741 break; 2675 2675 - case I40E_AQ_CAP_ID_8021QBG: 2742 2742 + case LIBIE_AQC_CAPS_8021QBG: 2676 2743 if (number == 1) 2677 2744 p->evb_802_1_qbg = true; 2678 2745 break; 2679 2679 - case I40E_AQ_CAP_ID_8021QBR: 2746 2746 + case LIBIE_AQC_CAPS_8021QBR: 2680 2747 if (number == 1) 2681 2748 p->evb_802_1_qbh = true; 2682 2749 break; 2683 2683 - case I40E_AQ_CAP_ID_VSI: 2750 2750 + case LIBIE_AQC_CAPS_VSI: 2684 2751 p->num_vsis = number; 2685 2752 break; 2686 2686 - case I40E_AQ_CAP_ID_DCB: 2753 2753 + case LIBIE_AQC_CAPS_DCB: 2687 2754 if (number == 1) { 2688 2755 p->dcb = true; 2689 2756 p->enabled_tcmap = logical_id; 2690 2757 p->maxtc = phys_id; 2691 2758 } 2692 2759 break; 2693 2693 - case I40E_AQ_CAP_ID_FCOE: 2760 2760 + case LIBIE_AQC_CAPS_FCOE: 2694 2761 if (number == 1) 2695 2762 p->fcoe = true; 2696 2763 break; 2697 2697 - case I40E_AQ_CAP_ID_ISCSI: 2764 2764 + case LIBIE_AQC_CAPS_ISCSI: 2698 2765 if (number == 1) 2699 2766 p->iscsi = true; 2700 2767 break; 2701 2701 - case I40E_AQ_CAP_ID_RSS: 2768 2768 + case LIBIE_AQC_CAPS_RSS: 2702 2769 p->rss = true; 2703 2770 p->rss_table_size = number; 2704 2771 p->rss_table_entry_width = logical_id; 2705 2772 break; 2706 2706 - case I40E_AQ_CAP_ID_RXQ: 2773 2773 + case LIBIE_AQC_CAPS_RXQS: 2707 2774 p->num_rx_qp = number; 2708 2775 p->base_queue = phys_id; 2709 2776 break; 2710 2710 - case I40E_AQ_CAP_ID_TXQ: 2777 2777 + case LIBIE_AQC_CAPS_TXQS: 2711 2778 p->num_tx_qp = number; 2712 2779 p->base_queue = phys_id; 2713 2780 break; 2714 2714 - case I40E_AQ_CAP_ID_MSIX: 2781 2781 + case LIBIE_AQC_CAPS_MSIX: 2715 2782 p->num_msix_vectors = number; 2716 2783 i40e_debug(hw, I40E_DEBUG_INIT, 2717 2784 "HW Capability: MSIX vector count = %d\n", 2718 2785 p->num_msix_vectors); 2719 2786 break; 2720 2720 - case I40E_AQ_CAP_ID_VF_MSIX: 2787 2787 + case LIBIE_AQC_CAPS_VF_MSIX: 2721 2788 p->num_msix_vectors_vf = number; 2722 2789 break; 2723 2723 - case I40E_AQ_CAP_ID_FLEX10: 2790 2790 + case LIBIE_AQC_CAPS_FLEX10: 2724 2791 if (major_rev == 1) { 2725 2792 if (number == 1) { 2726 2793 p->flex10_enable = true; ··· 2736 2803 p->flex10_mode = logical_id; 2737 2804 p->flex10_status = phys_id; 2738 2805 break; 2739 2739 - case I40E_AQ_CAP_ID_CEM: 2806 2806 + case LIBIE_AQC_CAPS_CEM: 2740 2807 if (number == 1) 2741 2808 p->mgmt_cem = true; 2742 2809 break; 2743 2743 - case I40E_AQ_CAP_ID_IWARP: 2810 2810 + case LIBIE_AQC_CAPS_RDMA: 2744 2811 if (number == 1) 2745 2812 p->iwarp = true; 2746 2813 break; 2747 2747 - case I40E_AQ_CAP_ID_LED: 2814 2814 + case LIBIE_AQC_CAPS_LED: 2748 2815 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2749 2816 p->led[phys_id] = true; 2750 2817 break; 2751 2751 - case I40E_AQ_CAP_ID_SDP: 2818 2818 + case LIBIE_AQC_CAPS_SDP: 2752 2819 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2753 2820 p->sdp[phys_id] = true; 2754 2821 break; 2755 2755 - case I40E_AQ_CAP_ID_MDIO: 2822 2822 + case LIBIE_AQC_CAPS_MDIO: 2756 2823 if (number == 1) { 2757 2824 p->mdio_port_num = phys_id; 2758 2825 p->mdio_port_mode = logical_id; 2759 2826 } 2760 2827 break; 2761 2761 - case I40E_AQ_CAP_ID_1588: 2828 2828 + case LIBIE_AQC_CAPS_1588: 2762 2829 if (number == 1) 2763 2830 p->ieee_1588 = true; 2764 2831 break; 2765 2765 - case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 2832 2832 + case LIBIE_AQC_CAPS_FD: 2766 2833 p->fd = true; 2767 2834 p->fd_filters_guaranteed = number; 2768 2835 p->fd_filters_best_effort = logical_id; 2769 2836 break; 2770 2770 - case I40E_AQ_CAP_ID_WSR_PROT: 2837 2837 + case LIBIE_AQC_CAPS_WSR_PROT: 2771 2838 p->wr_csr_prot = (u64)number; 2772 2839 p->wr_csr_prot |= (u64)logical_id << 32; 2773 2840 break; 2774 2774 - case I40E_AQ_CAP_ID_NVM_MGMT: 2841 2841 + case LIBIE_AQC_CAPS_NVM_MGMT: 2775 2842 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 2776 2843 p->sec_rev_disabled = true; 2777 2844 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) ··· 2863 2930 enum i40e_admin_queue_opc list_type_opc, 2864 2931 struct i40e_asq_cmd_details *cmd_details) 2865 2932 { 2866 2866 - struct i40e_aqc_list_capabilites *cmd; 2867 2867 - struct i40e_aq_desc desc; 2933 2933 + struct libie_aqc_list_caps *cmd; 2934 2934 + struct libie_aq_desc desc; 2868 2935 int status = 0; 2869 2936 2870 2870 - cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2937 2937 + cmd = libie_aq_raw(&desc); 2871 2938 2872 2939 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2873 2940 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { ··· 2877 2944 2878 2945 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2879 2946 2880 2880 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2947 2947 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2881 2948 if (buff_size > I40E_AQ_LARGE_BUF) 2882 2882 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2949 2949 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2883 2950 2884 2951 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2885 2952 *data_size = le16_to_cpu(desc.datalen); ··· 2912 2979 bool last_command, u8 preservation_flags, 2913 2980 struct i40e_asq_cmd_details *cmd_details) 2914 2981 { 2915 2915 - struct i40e_aq_desc desc; 2916 2916 - struct i40e_aqc_nvm_update *cmd = 2917 2917 - (struct i40e_aqc_nvm_update *)&desc.params.raw; 2982 2982 + struct i40e_aqc_nvm_update *cmd; 2983 2983 + struct libie_aq_desc desc; 2918 2984 int status; 2919 2985 2920 2986 /* In offset the highest byte must be zeroed. */ ··· 2924 2992 2925 2993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2926 2994 2995 2995 + cmd = libie_aq_raw(&desc); 2927 2996 /* If this is the last command in a series, set the proper flag. */ 2928 2997 if (last_command) 2929 2998 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; ··· 2942 3009 cmd->offset = cpu_to_le32(offset); 2943 3010 cmd->length = cpu_to_le16(length); 2944 3011 2945 2945 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3012 3012 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2946 3013 if (length > I40E_AQ_LARGE_BUF) 2947 2947 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3014 3014 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2948 3015 2949 3016 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2950 3017 ··· 2970 3037 u16 *local_len, u16 *remote_len, 2971 3038 struct i40e_asq_cmd_details *cmd_details) 2972 3039 { 2973 2973 - struct i40e_aq_desc desc; 2974 2974 - struct i40e_aqc_lldp_get_mib *cmd = 2975 2975 - (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2976 2976 - struct i40e_aqc_lldp_get_mib *resp = 2977 2977 - (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3040 3040 + struct i40e_aqc_lldp_get_mib *resp; 3041 3041 + struct i40e_aqc_lldp_get_mib *cmd; 3042 3042 + struct libie_aq_desc desc; 2978 3043 int status; 2979 3044 2980 3045 if (buff_size == 0 || !buff) ··· 2980 3049 2981 3050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2982 3051 /* Indirect Command */ 2983 2983 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3052 3052 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2984 3053 3054 3054 + resp = libie_aq_raw(&desc); 3055 3055 + cmd = libie_aq_raw(&desc); 2985 3056 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2986 3057 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 2987 3058 2988 3059 desc.datalen = cpu_to_le16(buff_size); 2989 3060 2990 2990 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3061 3061 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2991 3062 if (buff_size > I40E_AQ_LARGE_BUF) 2992 2992 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3063 3063 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2993 3064 2994 3065 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2995 3066 if (!status) { ··· 3020 3087 struct i40e_asq_cmd_details *cmd_details) 3021 3088 { 3022 3089 struct i40e_aqc_lldp_set_local_mib *cmd; 3023 3023 - struct i40e_aq_desc desc; 3090 3090 + struct libie_aq_desc desc; 3024 3091 int status; 3025 3092 3026 3026 - cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3093 3093 + cmd = libie_aq_raw(&desc); 3027 3094 if (buff_size == 0 || !buff) 3028 3095 return -EINVAL; 3029 3096 3030 3097 i40e_fill_default_direct_cmd_desc(&desc, 3031 3098 i40e_aqc_opc_lldp_set_local_mib); 3032 3099 /* Indirect Command */ 3033 3033 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3100 3100 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 3034 3101 if (buff_size > I40E_AQ_LARGE_BUF) 3035 3035 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3102 3102 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3036 3103 desc.datalen = cpu_to_le16(buff_size); 3037 3104 3038 3105 cmd->type = mib_type; ··· 3057 3124 bool enable_update, 3058 3125 struct i40e_asq_cmd_details *cmd_details) 3059 3126 { 3060 3060 - struct i40e_aq_desc desc; 3061 3061 - struct i40e_aqc_lldp_update_mib *cmd = 3062 3062 - (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3127 3127 + struct i40e_aqc_lldp_update_mib *cmd; 3128 3128 + struct libie_aq_desc desc; 3063 3129 int status; 3064 3130 3065 3131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3066 3132 3133 3133 + cmd = libie_aq_raw(&desc); 3067 3134 if (!enable_update) 3068 3135 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3069 3136 ··· 3085 3152 bool persist, 3086 3153 struct i40e_asq_cmd_details *cmd_details) 3087 3154 { 3088 3088 - struct i40e_aq_desc desc; 3089 3089 - struct i40e_aqc_lldp_stop *cmd = 3090 3090 - (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3155 3155 + struct i40e_aqc_lldp_stop *cmd; 3156 3156 + struct libie_aq_desc desc; 3091 3157 int status; 3092 3158 3093 3159 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3094 3160 3161 3161 + cmd = libie_aq_raw(&desc); 3095 3162 if (shutdown_agent) 3096 3163 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3097 3164 ··· 3119 3186 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3120 3187 struct i40e_asq_cmd_details *cmd_details) 3121 3188 { 3122 3122 - struct i40e_aq_desc desc; 3123 3123 - struct i40e_aqc_lldp_start *cmd = 3124 3124 - (struct i40e_aqc_lldp_start *)&desc.params.raw; 3189 3189 + struct i40e_aqc_lldp_start *cmd; 3190 3190 + struct libie_aq_desc desc; 3125 3191 int status; 3126 3192 3127 3193 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3128 3194 3195 3195 + cmd = libie_aq_raw(&desc); 3129 3196 cmd->command = I40E_AQ_LLDP_AGENT_START; 3130 3197 3131 3198 if (persist) { ··· 3152 3219 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3153 3220 struct i40e_asq_cmd_details *cmd_details) 3154 3221 { 3155 3155 - struct i40e_aq_desc desc; 3156 3156 - struct i40e_aqc_set_dcb_parameters *cmd = 3157 3157 - (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3222 3222 + struct i40e_aqc_set_dcb_parameters *cmd; 3223 3223 + struct libie_aq_desc desc; 3158 3224 int status; 3159 3225 3160 3226 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) ··· 3162 3230 i40e_fill_default_direct_cmd_desc(&desc, 3163 3231 i40e_aqc_opc_set_dcb_parameters); 3164 3232 3233 3233 + cmd = libie_aq_raw(&desc); 3165 3234 if (dcb_enable) { 3166 3235 cmd->valid_flags = I40E_DCB_VALID; 3167 3236 cmd->command = I40E_AQ_DCB_SET_AGENT; ··· 3185 3252 void *buff, u16 buff_size, 3186 3253 struct i40e_asq_cmd_details *cmd_details) 3187 3254 { 3188 3188 - struct i40e_aq_desc desc; 3255 3255 + struct libie_aq_desc desc; 3189 3256 int status; 3190 3257 3191 3258 if (buff_size == 0 || !buff) ··· 3193 3260 3194 3261 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3195 3262 3196 3196 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3263 3263 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3197 3264 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3198 3265 cmd_details); 3199 3266 ··· 3217 3284 u8 *filter_index, 3218 3285 struct i40e_asq_cmd_details *cmd_details) 3219 3286 { 3220 3220 - struct i40e_aq_desc desc; 3221 3221 - struct i40e_aqc_add_udp_tunnel *cmd = 3222 3222 - (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3223 3223 - struct i40e_aqc_del_udp_tunnel_completion *resp = 3224 3224 - (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3287 3287 + struct i40e_aqc_del_udp_tunnel_completion *resp; 3288 3288 + struct i40e_aqc_add_udp_tunnel *cmd; 3289 3289 + struct libie_aq_desc desc; 3225 3290 int status; 3226 3291 3227 3292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3228 3293 3294 3294 + resp = libie_aq_raw(&desc); 3295 3295 + cmd = libie_aq_raw(&desc); 3229 3296 cmd->udp_port = cpu_to_le16(udp_port); 3230 3297 cmd->protocol_type = protocol_index; 3231 3298 ··· 3246 3313 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3247 3314 struct i40e_asq_cmd_details *cmd_details) 3248 3315 { 3249 3249 - struct i40e_aq_desc desc; 3250 3250 - struct i40e_aqc_remove_udp_tunnel *cmd = 3251 3251 - (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3316 3316 + struct i40e_aqc_remove_udp_tunnel *cmd; 3317 3317 + struct libie_aq_desc desc; 3252 3318 int status; 3253 3319 3254 3320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3255 3321 3322 3322 + cmd = libie_aq_raw(&desc); 3256 3323 cmd->index = index; 3257 3324 3258 3325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 3271 3338 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3272 3339 struct i40e_asq_cmd_details *cmd_details) 3273 3340 { 3274 3274 - struct i40e_aq_desc desc; 3275 3275 - struct i40e_aqc_switch_seid *cmd = 3276 3276 - (struct i40e_aqc_switch_seid *)&desc.params.raw; 3341 3341 + struct i40e_aqc_switch_seid *cmd; 3342 3342 + struct libie_aq_desc desc; 3277 3343 int status; 3278 3344 3279 3345 if (seid == 0) ··· 3280 3348 3281 3349 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3282 3350 3351 3351 + cmd = libie_aq_raw(&desc); 3283 3352 cmd->seid = cpu_to_le16(seid); 3284 3353 3285 3354 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, ··· 3301 3368 int i40e_aq_dcb_updated(struct i40e_hw *hw, 3302 3369 struct i40e_asq_cmd_details *cmd_details) 3303 3370 { 3304 3304 - struct i40e_aq_desc desc; 3371 3371 + struct libie_aq_desc desc; 3305 3372 int status; 3306 3373 3307 3374 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); ··· 3327 3394 enum i40e_admin_queue_opc opcode, 3328 3395 struct i40e_asq_cmd_details *cmd_details) 3329 3396 { 3330 3330 - struct i40e_aq_desc desc; 3331 3331 - struct i40e_aqc_tx_sched_ind *cmd = 3332 3332 - (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3397 3397 + struct i40e_aqc_tx_sched_ind *cmd; 3398 3398 + struct libie_aq_desc desc; 3333 3399 int status; 3334 3400 bool cmd_param_flag = false; 3335 3401 ··· 3355 3423 3356 3424 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3357 3425 3426 3426 + cmd = libie_aq_raw(&desc); 3358 3427 /* Indirect command */ 3359 3359 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3428 3428 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3360 3429 if (cmd_param_flag) 3361 3361 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3430 3430 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 3362 3431 if (buff_size > I40E_AQ_LARGE_BUF) 3363 3363 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3432 3432 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3364 3433 3365 3434 desc.datalen = cpu_to_le16(buff_size); 3366 3435 ··· 3384 3451 u16 seid, u16 credit, u8 max_credit, 3385 3452 struct i40e_asq_cmd_details *cmd_details) 3386 3453 { 3387 3387 - struct i40e_aq_desc desc; 3388 3388 - struct i40e_aqc_configure_vsi_bw_limit *cmd = 3389 3389 - (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3454 3454 + struct i40e_aqc_configure_vsi_bw_limit *cmd; 3455 3455 + struct libie_aq_desc desc; 3390 3456 int status; 3391 3457 3392 3458 i40e_fill_default_direct_cmd_desc(&desc, 3393 3459 i40e_aqc_opc_configure_vsi_bw_limit); 3394 3460 3461 3461 + cmd = libie_aq_raw(&desc); 3395 3462 cmd->vsi_seid = cpu_to_le16(seid); 3396 3463 cmd->credit = cpu_to_le16(credit); 3397 3464 cmd->max_credit = max_credit; ··· 3719 3786 struct i40e_control_filter_stats *stats, 3720 3787 struct i40e_asq_cmd_details *cmd_details) 3721 3788 { 3722 3722 - struct i40e_aq_desc desc; 3723 3723 - struct i40e_aqc_add_remove_control_packet_filter *cmd = 3724 3724 - (struct i40e_aqc_add_remove_control_packet_filter *) 3725 3725 - &desc.params.raw; 3726 3726 - struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3727 3727 - (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3728 3728 - &desc.params.raw; 3789 3789 + struct i40e_aqc_add_remove_control_packet_filter_completion *resp; 3790 3790 + struct i40e_aqc_add_remove_control_packet_filter *cmd; 3791 3791 + struct libie_aq_desc desc; 3729 3792 int status; 3730 3793 3731 3794 if (vsi_seid == 0) 3732 3795 return -EINVAL; 3733 3796 3797 3797 + resp = libie_aq_raw(&desc); 3798 3798 + cmd = libie_aq_raw(&desc); 3734 3799 if (is_add) { 3735 3800 i40e_fill_default_direct_cmd_desc(&desc, 3736 3801 i40e_aqc_opc_add_control_packet_filter); ··· 3796 3865 u32 reg_addr0, u32 *reg_val0, 3797 3866 u32 reg_addr1, u32 *reg_val1) 3798 3867 { 3799 3799 - struct i40e_aq_desc desc; 3800 3800 - struct i40e_aqc_alternate_write *cmd_resp = 3801 3801 - (struct i40e_aqc_alternate_write *)&desc.params.raw; 3868 3868 + struct i40e_aqc_alternate_write *cmd_resp; 3869 3869 + struct libie_aq_desc desc; 3802 3870 int status; 3803 3871 3804 3872 if (!reg_val0) 3805 3873 return -EINVAL; 3806 3874 3807 3875 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3876 3876 + cmd_resp = libie_aq_raw(&desc); 3808 3877 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3809 3878 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3810 3879 ··· 3832 3901 struct i40e_asq_cmd_details *cmd_details) 3833 3902 { 3834 3903 struct i40e_aqc_tx_sched_ind *cmd; 3835 3835 - struct i40e_aq_desc desc; 3904 3904 + struct libie_aq_desc desc; 3836 3905 int status; 3837 3906 3838 3838 - cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3907 3907 + cmd = libie_aq_raw(&desc); 3839 3908 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 3840 3909 cmd->vsi_seid = cpu_to_le16(seid); 3841 3910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 3853 3922 int i40e_aq_resume_port_tx(struct i40e_hw *hw, 3854 3923 struct i40e_asq_cmd_details *cmd_details) 3855 3924 { 3856 3856 - struct i40e_aq_desc desc; 3925 3925 + struct libie_aq_desc desc; 3857 3926 int status; 3858 3927 3859 3928 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); ··· 3930 3999 u8 *ret_next_table, u32 *ret_next_index, 3931 4000 struct i40e_asq_cmd_details *cmd_details) 3932 4001 { 3933 3933 - struct i40e_aq_desc desc; 3934 3934 - struct i40e_aqc_debug_dump_internals *cmd = 3935 3935 - (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 3936 3936 - struct i40e_aqc_debug_dump_internals *resp = 3937 3937 - (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4002 4002 + struct i40e_aqc_debug_dump_internals *resp; 4003 4003 + struct i40e_aqc_debug_dump_internals *cmd; 4004 4004 + struct libie_aq_desc desc; 3938 4005 int status; 3939 4006 3940 4007 if (buff_size == 0 || !buff) ··· 3940 4011 3941 4012 i40e_fill_default_direct_cmd_desc(&desc, 3942 4013 i40e_aqc_opc_debug_dump_internals); 4014 4014 + resp = libie_aq_raw(&desc); 4015 4015 + cmd = libie_aq_raw(&desc); 3943 4016 /* Indirect Command */ 3944 3944 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4017 4017 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3945 4018 if (buff_size > I40E_AQ_LARGE_BUF) 3946 3946 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4019 4019 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3947 4020 3948 4021 cmd->cluster_id = cluster_id; 3949 4022 cmd->table_id = table_id; ··· 4022 4091 struct i40e_asq_cmd_details *cmd_details) 4023 4092 { 4024 4093 u16 bwd_size = sizeof(*bw_data); 4025 4025 - struct i40e_aq_desc desc; 4094 4094 + struct libie_aq_desc desc; 4026 4095 int status; 4027 4096 4028 4097 i40e_fill_default_direct_cmd_desc(&desc, 4029 4098 i40e_aqc_opc_configure_partition_bw); 4030 4099 4031 4100 /* Indirect command */ 4032 4032 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4033 4033 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4101 4101 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4102 4102 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 4034 4103 4035 4104 if (bwd_size > I40E_AQ_LARGE_BUF) 4036 4036 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4105 4105 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4037 4106 4038 4107 desc.datalen = cpu_to_le16(bwd_size); 4039 4108 ··· 4465 4534 u32 reg_addr, u32 *reg_val, 4466 4535 struct i40e_asq_cmd_details *cmd_details) 4467 4536 { 4468 4468 - struct i40e_aq_desc desc; 4469 4469 - struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4470 4470 - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4537 4537 + struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp; 4538 4538 + struct libie_aq_desc desc; 4471 4539 int status; 4472 4540 4473 4541 if (!reg_val) ··· 4474 4544 4475 4545 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4476 4546 4547 4547 + cmd_resp = libie_aq_raw(&desc); 4477 4548 cmd_resp->address = cpu_to_le32(reg_addr); 4478 4549 4479 4550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); ··· 4503 4572 if (!use_register) { 4504 4573 do_retry: 4505 4574 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4506 4506 - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4575 4575 + if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4507 4576 usleep_range(1000, 2000); 4508 4577 retry--; 4509 4578 goto do_retry; ··· 4531 4600 u32 reg_addr, u32 reg_val, 4532 4601 struct i40e_asq_cmd_details *cmd_details) 4533 4602 { 4534 4534 - struct i40e_aq_desc desc; 4535 4535 - struct i40e_aqc_rx_ctl_reg_read_write *cmd = 4536 4536 - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4603 4603 + struct i40e_aqc_rx_ctl_reg_read_write *cmd; 4604 4604 + struct libie_aq_desc desc; 4537 4605 int status; 4538 4606 4539 4607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4540 4608 4609 4609 + cmd = libie_aq_raw(&desc); 4541 4610 cmd->address = cpu_to_le32(reg_addr); 4542 4611 cmd->value = cpu_to_le32(reg_val); 4543 4612 ··· 4565 4634 do_retry: 4566 4635 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4567 4636 reg_val, NULL); 4568 4568 - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4637 4637 + if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4569 4638 usleep_range(1000, 2000); 4570 4639 retry--; 4571 4640 goto do_retry; ··· 4624 4693 u32 reg_addr, u32 reg_val, 4625 4694 struct i40e_asq_cmd_details *cmd_details) 4626 4695 { 4627 4627 - struct i40e_aq_desc desc; 4628 4628 - struct i40e_aqc_phy_register_access *cmd = 4629 4629 - (struct i40e_aqc_phy_register_access *)&desc.params.raw; 4696 4696 + struct i40e_aqc_phy_register_access *cmd; 4697 4697 + struct libie_aq_desc desc; 4630 4698 int status; 4631 4699 4632 4700 i40e_fill_default_direct_cmd_desc(&desc, 4633 4701 i40e_aqc_opc_set_phy_register); 4634 4702 4703 4703 + cmd = libie_aq_raw(&desc); 4635 4704 cmd->phy_interface = phy_select; 4636 4705 cmd->dev_address = dev_addr; 4637 4706 cmd->reg_address = cpu_to_le32(reg_addr); ··· 4669 4738 u32 reg_addr, u32 *reg_val, 4670 4739 struct i40e_asq_cmd_details *cmd_details) 4671 4740 { 4672 4672 - struct i40e_aq_desc desc; 4673 4673 - struct i40e_aqc_phy_register_access *cmd = 4674 4674 - (struct i40e_aqc_phy_register_access *)&desc.params.raw; 4741 4741 + struct i40e_aqc_phy_register_access *cmd; 4742 4742 + struct libie_aq_desc desc; 4675 4743 int status; 4676 4744 4677 4745 i40e_fill_default_direct_cmd_desc(&desc, 4678 4746 i40e_aqc_opc_get_phy_register); 4679 4747 4748 4748 + cmd = libie_aq_raw(&desc); 4680 4749 cmd->phy_interface = phy_select; 4681 4750 cmd->dev_address = dev_addr; 4682 4751 cmd->reg_address = cpu_to_le32(reg_addr); ··· 4708 4777 u32 *error_offset, u32 *error_info, 4709 4778 struct i40e_asq_cmd_details *cmd_details) 4710 4779 { 4711 4711 - struct i40e_aq_desc desc; 4712 4712 - struct i40e_aqc_write_personalization_profile *cmd = 4713 4713 - (struct i40e_aqc_write_personalization_profile *) 4714 4714 - &desc.params.raw; 4780 4780 + struct i40e_aqc_write_personalization_profile *cmd; 4715 4781 struct i40e_aqc_write_ddp_resp *resp; 4782 4782 + struct libie_aq_desc desc; 4716 4783 int status; 4717 4784 4718 4785 i40e_fill_default_direct_cmd_desc(&desc, 4719 4786 i40e_aqc_opc_write_personalization_profile); 4720 4787 4721 4721 - desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 4788 4788 + cmd = libie_aq_raw(&desc); 4789 4789 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 4722 4790 if (buff_size > I40E_AQ_LARGE_BUF) 4723 4723 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4791 4791 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4724 4792 4725 4793 desc.datalen = cpu_to_le16(buff_size); 4726 4794 ··· 4727 4797 4728 4798 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4729 4799 if (!status) { 4730 4730 - resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 4800 4800 + resp = libie_aq_raw(&desc); 4731 4801 if (error_offset) 4732 4802 *error_offset = le32_to_cpu(resp->error_offset); 4733 4803 if (error_info) ··· 4749 4819 u16 buff_size, u8 flags, 4750 4820 struct i40e_asq_cmd_details *cmd_details) 4751 4821 { 4752 4752 - struct i40e_aq_desc desc; 4753 4753 - struct i40e_aqc_get_applied_profiles *cmd = 4754 4754 - (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 4822 4822 + struct i40e_aqc_get_applied_profiles *cmd; 4823 4823 + struct libie_aq_desc desc; 4755 4824 int status; 4756 4825 4757 4826 i40e_fill_default_direct_cmd_desc(&desc, 4758 4827 i40e_aqc_opc_get_personalization_profile_list); 4759 4828 4760 4760 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4829 4829 + cmd = libie_aq_raw(&desc); 4830 4830 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4761 4831 if (buff_size > I40E_AQ_LARGE_BUF) 4762 4762 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4832 4832 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4763 4833 desc.datalen = cpu_to_le16(buff_size); 4764 4834 4765 4835 cmd->flags = flags; ··· 4821 4891 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 4822 4892 struct i40e_profile_aq_section *aq) 4823 4893 { 4824 4824 - struct i40e_aq_desc desc; 4894 4894 + struct libie_aq_desc desc; 4825 4895 u8 *msg = NULL; 4826 4896 u16 msglen; 4827 4897 int status; ··· 4832 4902 4833 4903 msglen = aq->datalen; 4834 4904 if (msglen) { 4835 4835 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 4836 4836 - I40E_AQ_FLAG_RD)); 4905 4905 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 4906 4906 + LIBIE_AQ_FLAG_RD)); 4837 4907 if (msglen > I40E_AQ_LARGE_BUF) 4838 4838 - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4908 4908 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4839 4909 desc.datalen = cpu_to_le16(msglen); 4840 4910 msg = &aq->data[0]; 4841 4911 } ··· 5052 5122 struct i40e_aqc_cloud_filters_element_data *filters, 5053 5123 u8 filter_count) 5054 5124 { 5055 5055 - struct i40e_aq_desc desc; 5056 5056 - struct i40e_aqc_add_remove_cloud_filters *cmd = 5057 5057 - (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5125 5125 + struct i40e_aqc_add_remove_cloud_filters *cmd; 5126 5126 + struct libie_aq_desc desc; 5058 5127 u16 buff_len; 5059 5128 int status; 5060 5129 5061 5130 i40e_fill_default_direct_cmd_desc(&desc, 5062 5131 i40e_aqc_opc_add_cloud_filters); 5063 5132 5133 5133 + cmd = libie_aq_raw(&desc); 5064 5134 buff_len = filter_count * sizeof(*filters); 5065 5135 desc.datalen = cpu_to_le16(buff_len); 5066 5066 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5136 5136 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5067 5137 cmd->num_filters = filter_count; 5068 5138 cmd->seid = cpu_to_le16(seid); 5069 5139 ··· 5089 5159 struct i40e_aqc_cloud_filters_element_bb *filters, 5090 5160 u8 filter_count) 5091 5161 { 5092 5092 - struct i40e_aq_desc desc; 5093 5093 - struct i40e_aqc_add_remove_cloud_filters *cmd = 5094 5094 - (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5162 5162 + struct i40e_aqc_add_remove_cloud_filters *cmd; 5163 5163 + struct libie_aq_desc desc; 5095 5164 u16 buff_len; 5096 5165 int status; 5097 5166 int i; ··· 5098 5169 i40e_fill_default_direct_cmd_desc(&desc, 5099 5170 i40e_aqc_opc_add_cloud_filters); 5100 5171 5172 5172 + cmd = libie_aq_raw(&desc); 5101 5173 buff_len = filter_count * sizeof(*filters); 5102 5174 desc.datalen = cpu_to_le16(buff_len); 5103 5103 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5175 5175 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5104 5176 cmd->num_filters = filter_count; 5105 5177 cmd->seid = cpu_to_le16(seid); 5106 5178 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; ··· 5145 5215 struct i40e_aqc_cloud_filters_element_data *filters, 5146 5216 u8 filter_count) 5147 5217 { 5148 5148 - struct i40e_aq_desc desc; 5149 5149 - struct i40e_aqc_add_remove_cloud_filters *cmd = 5150 5150 - (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5218 5218 + struct i40e_aqc_add_remove_cloud_filters *cmd; 5219 5219 + struct libie_aq_desc desc; 5151 5220 u16 buff_len; 5152 5221 int status; 5153 5222 5154 5223 i40e_fill_default_direct_cmd_desc(&desc, 5155 5224 i40e_aqc_opc_remove_cloud_filters); 5156 5225 5226 5226 + cmd = libie_aq_raw(&desc); 5157 5227 buff_len = filter_count * sizeof(*filters); 5158 5228 desc.datalen = cpu_to_le16(buff_len); 5159 5159 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5229 5229 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5160 5230 cmd->num_filters = filter_count; 5161 5231 cmd->seid = cpu_to_le16(seid); 5162 5232 ··· 5182 5252 struct i40e_aqc_cloud_filters_element_bb *filters, 5183 5253 u8 filter_count) 5184 5254 { 5185 5185 - struct i40e_aq_desc desc; 5186 5186 - struct i40e_aqc_add_remove_cloud_filters *cmd = 5187 5187 - (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5255 5255 + struct i40e_aqc_add_remove_cloud_filters *cmd; 5256 5256 + struct libie_aq_desc desc; 5188 5257 u16 buff_len; 5189 5258 int status; 5190 5259 int i; ··· 5191 5262 i40e_fill_default_direct_cmd_desc(&desc, 5192 5263 i40e_aqc_opc_remove_cloud_filters); 5193 5264 5265 5265 + cmd = libie_aq_raw(&desc); 5194 5266 buff_len = filter_count * sizeof(*filters); 5195 5267 desc.datalen = cpu_to_le16(buff_len); 5196 5196 - desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5268 5268 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5197 5269 cmd->num_filters = filter_count; 5198 5270 cmd->seid = cpu_to_le16(seid); 5199 5271 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;

+5 -5

drivers/net/ethernet/intel/i40e/i40e_dcb.c

reviewed

··· 750 750 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 751 751 &hw->remote_dcbx_config); 752 752 /* Don't treat ENOENT as an error for Remote MIBs */ 753 753 - if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 753 753 + if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) 754 754 ret = 0; 755 755 756 756 out: ··· 799 799 } 800 800 801 801 /* CEE mode not enabled try querying IEEE data */ 802 802 - if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 802 802 + if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) 803 803 return i40e_get_ieee_dcb_config(hw); 804 804 805 805 if (ret) ··· 816 816 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 817 817 &hw->remote_dcbx_config); 818 818 /* Don't treat ENOENT as an error for Remote MIBs */ 819 819 - if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 819 819 + if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) 820 820 ret = 0; 821 821 822 822 out: ··· 925 925 926 926 if (!ret) { 927 927 *lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED; 928 928 - } else if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) { 928 928 + } else if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) { 929 929 /* MIB is not available yet but the agent is running */ 930 930 *lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED; 931 931 ret = 0; 932 932 - } else if (hw->aq.asq_last_status == I40E_AQ_RC_EPERM) { 932 932 + } else if (hw->aq.asq_last_status == LIBIE_AQ_RC_EPERM) { 933 933 *lldp_status = I40E_GET_FW_LLDP_STATUS_DISABLED; 934 934 ret = 0; 935 935 }

+4 -4

drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c

reviewed

··· 136 136 dev_info(&pf->pdev->dev, 137 137 "Failed setting DCB ETS configuration err %pe aq_err %s\n", 138 138 ERR_PTR(ret), 139 139 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 139 139 + libie_aq_str(pf->hw.aq.asq_last_status)); 140 140 return -EINVAL; 141 141 } 142 142 ··· 175 175 dev_info(&pf->pdev->dev, 176 176 "Failed setting DCB PFC configuration err %pe aq_err %s\n", 177 177 ERR_PTR(ret), 178 178 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 178 178 + libie_aq_str(pf->hw.aq.asq_last_status)); 179 179 return -EINVAL; 180 180 } 181 181 ··· 226 226 dev_info(&pf->pdev->dev, 227 227 "Failed setting DCB configuration err %pe aq_err %s\n", 228 228 ERR_PTR(ret), 229 229 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 229 229 + libie_aq_str(pf->hw.aq.asq_last_status)); 230 230 return -EINVAL; 231 231 } 232 232 ··· 291 291 dev_info(&pf->pdev->dev, 292 292 "Failed setting DCB configuration err %pe aq_err %s\n", 293 293 ERR_PTR(ret), 294 294 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 294 294 + libie_aq_str(pf->hw.aq.asq_last_status)); 295 295 return -EINVAL; 296 296 } 297 297

+23 -23

drivers/net/ethernet/intel/i40e/i40e_debugfs.c

reviewed

··· 489 489 dev_info(&pf->pdev->dev, "AdminQ Tx Ring\n"); 490 490 ring = &(hw->aq.asq); 491 491 for (i = 0; i < ring->count; i++) { 492 492 - struct i40e_aq_desc *d = I40E_ADMINQ_DESC(*ring, i); 492 492 + struct libie_aq_desc *d = I40E_ADMINQ_DESC(*ring, i); 493 493 494 494 dev_info(&pf->pdev->dev, 495 495 " at[%02d] flags=0x%04x op=0x%04x dlen=0x%04x ret=0x%04x cookie_h=0x%08x cookie_l=0x%08x\n", ··· 502 502 dev_info(&pf->pdev->dev, "AdminQ Rx Ring\n"); 503 503 ring = &(hw->aq.arq); 504 504 for (i = 0; i < ring->count; i++) { 505 505 - struct i40e_aq_desc *d = I40E_ADMINQ_DESC(*ring, i); 505 505 + struct libie_aq_desc *d = I40E_ADMINQ_DESC(*ring, i); 506 506 507 507 dev_info(&pf->pdev->dev, 508 508 " ar[%02d] flags=0x%04x op=0x%04x dlen=0x%04x ret=0x%04x cookie_h=0x%08x cookie_l=0x%08x\n", ··· 1268 1268 dev_info(&pf->pdev->dev, "clear_stats vsi [seid] or clear_stats port\n"); 1269 1269 } 1270 1270 } else if (strncmp(cmd_buf, "send aq_cmd", 11) == 0) { 1271 1271 - struct i40e_aq_desc *desc; 1271 1271 + struct libie_aq_desc *desc; 1272 1272 int ret; 1273 1273 1274 1274 - desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL); 1274 1274 + desc = kzalloc(sizeof(*desc), GFP_KERNEL); 1275 1275 if (!desc) 1276 1276 goto command_write_done; 1277 1277 cnt = sscanf(&cmd_buf[11], ··· 1279 1279 &desc->flags, 1280 1280 &desc->opcode, &desc->datalen, &desc->retval, 1281 1281 &desc->cookie_high, &desc->cookie_low, 1282 1282 - &desc->params.internal.param0, 1283 1283 - &desc->params.internal.param1, 1284 1284 - &desc->params.internal.param2, 1285 1285 - &desc->params.internal.param3); 1282 1282 + &desc->params.generic.param0, 1283 1283 + &desc->params.generic.param1, 1284 1284 + &desc->params.generic.addr_high, 1285 1285 + &desc->params.generic.addr_low); 1286 1286 if (cnt != 10) { 1287 1287 dev_info(&pf->pdev->dev, 1288 1288 "send aq_cmd: bad command string, cnt=%d\n", ··· 1307 1307 "AQ desc WB 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1308 1308 desc->flags, desc->opcode, desc->datalen, desc->retval, 1309 1309 desc->cookie_high, desc->cookie_low, 1310 1310 - desc->params.internal.param0, 1311 1311 - desc->params.internal.param1, 1312 1312 - desc->params.internal.param2, 1313 1313 - desc->params.internal.param3); 1310 1310 + desc->params.generic.param0, 1311 1311 + desc->params.generic.param1, 1312 1312 + desc->params.generic.addr_high, 1313 1313 + desc->params.generic.addr_low); 1314 1314 kfree(desc); 1315 1315 desc = NULL; 1316 1316 } else if (strncmp(cmd_buf, "send indirect aq_cmd", 20) == 0) { 1317 1317 - struct i40e_aq_desc *desc; 1317 1317 + struct libie_aq_desc *desc; 1318 1318 u16 buffer_len; 1319 1319 u8 *buff; 1320 1320 int ret; 1321 1321 1322 1322 - desc = kzalloc(sizeof(struct i40e_aq_desc), GFP_KERNEL); 1322 1322 + desc = kzalloc(sizeof(*desc), GFP_KERNEL); 1323 1323 if (!desc) 1324 1324 goto command_write_done; 1325 1325 cnt = sscanf(&cmd_buf[20], ··· 1327 1327 &desc->flags, 1328 1328 &desc->opcode, &desc->datalen, &desc->retval, 1329 1329 &desc->cookie_high, &desc->cookie_low, 1330 1330 - &desc->params.internal.param0, 1331 1331 - &desc->params.internal.param1, 1332 1332 - &desc->params.internal.param2, 1333 1333 - &desc->params.internal.param3, 1330 1330 + &desc->params.generic.param0, 1331 1331 + &desc->params.generic.param1, 1332 1332 + &desc->params.generic.addr_high, 1333 1333 + &desc->params.generic.addr_low, 1334 1334 &buffer_len); 1335 1335 if (cnt != 11) { 1336 1336 dev_info(&pf->pdev->dev, ··· 1350 1350 desc = NULL; 1351 1351 goto command_write_done; 1352 1352 } 1353 1353 - desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1353 1353 + desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1354 1354 ret = i40e_asq_send_command(&pf->hw, desc, buff, 1355 1355 buffer_len, NULL); 1356 1356 if (!ret) { ··· 1368 1368 "AQ desc WB 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1369 1369 desc->flags, desc->opcode, desc->datalen, desc->retval, 1370 1370 desc->cookie_high, desc->cookie_low, 1371 1371 - desc->params.internal.param0, 1372 1372 - desc->params.internal.param1, 1373 1373 - desc->params.internal.param2, 1374 1374 - desc->params.internal.param3); 1371 1371 + desc->params.generic.param0, 1372 1372 + desc->params.generic.param1, 1373 1373 + desc->params.generic.addr_high, 1374 1374 + desc->params.generic.addr_low); 1375 1375 print_hex_dump(KERN_INFO, "AQ buffer WB: ", 1376 1376 DUMP_PREFIX_OFFSET, 16, 1, 1377 1377 buff, buffer_len, true);

+17 -19

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

reviewed

··· 1462 1462 netdev_info(netdev, 1463 1463 "Set phy config failed, err %pe aq_err %s\n", 1464 1464 ERR_PTR(status), 1465 1465 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1465 1465 + libie_aq_str(hw->aq.asq_last_status)); 1466 1466 err = -EAGAIN; 1467 1467 goto done; 1468 1468 } ··· 1472 1472 netdev_dbg(netdev, 1473 1473 "Updating link info failed with err %pe aq_err %s\n", 1474 1474 ERR_PTR(status), 1475 1475 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1475 1475 + libie_aq_str(hw->aq.asq_last_status)); 1476 1476 1477 1477 } else { 1478 1478 netdev_info(netdev, "Nothing changed, exiting without setting anything.\n"); ··· 1520 1520 netdev_info(netdev, 1521 1521 "Set phy config failed, err %pe aq_err %s\n", 1522 1522 ERR_PTR(status), 1523 1523 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1523 1523 + libie_aq_str(hw->aq.asq_last_status)); 1524 1524 err = -EAGAIN; 1525 1525 goto done; 1526 1526 } ··· 1534 1534 netdev_dbg(netdev, 1535 1535 "Updating link info failed with err %pe aq_err %s\n", 1536 1536 ERR_PTR(status), 1537 1537 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1537 1537 + libie_aq_str(hw->aq.asq_last_status)); 1538 1538 } 1539 1539 1540 1540 done: ··· 1641 1641 if (ret) { 1642 1642 netdev_info(netdev, "link restart failed, err %pe aq_err %s\n", 1643 1643 ERR_PTR(ret), 1644 1644 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1644 1644 + libie_aq_str(hw->aq.asq_last_status)); 1645 1645 return -EIO; 1646 1646 } 1647 1647 ··· 1758 1758 if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) { 1759 1759 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %pe aq_err %s\n", 1760 1760 ERR_PTR(status), 1761 1761 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1761 1761 + libie_aq_str(hw->aq.asq_last_status)); 1762 1762 err = -EAGAIN; 1763 1763 } 1764 1764 if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) { 1765 1765 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %pe aq_err %s\n", 1766 1766 ERR_PTR(status), 1767 1767 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1767 1767 + libie_aq_str(hw->aq.asq_last_status)); 1768 1768 err = -EAGAIN; 1769 1769 } 1770 1770 if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) { 1771 1771 netdev_info(netdev, "Set fc failed on the get_link_info call with err %pe aq_err %s\n", 1772 1772 ERR_PTR(status), 1773 1773 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1773 1773 + libie_aq_str(hw->aq.asq_last_status)); 1774 1774 err = -EAGAIN; 1775 1775 } 1776 1776 ··· 1918 1918 ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len, 1919 1919 (u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i), 1920 1920 last, NULL); 1921 1921 - if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) { 1921 1921 + if (ret_val && hw->aq.asq_last_status == LIBIE_AQ_RC_EPERM) { 1922 1922 dev_info(&pf->pdev->dev, 1923 1923 "read NVM failed, invalid offset 0x%x\n", 1924 1924 offset); 1925 1925 break; 1926 1926 } else if (ret_val && 1927 1927 - hw->aq.asq_last_status == I40E_AQ_RC_EACCES) { 1927 1927 + hw->aq.asq_last_status == LIBIE_AQ_RC_EACCES) { 1928 1928 dev_info(&pf->pdev->dev, 1929 1929 "read NVM failed, access, offset 0x%x\n", 1930 1930 offset); ··· 5249 5249 DECLARE_BITMAP(orig_flags, I40E_PF_FLAGS_NBITS); 5250 5250 DECLARE_BITMAP(new_flags, I40E_PF_FLAGS_NBITS); 5251 5251 struct i40e_netdev_priv *np = netdev_priv(dev); 5252 5252 - enum i40e_admin_queue_err adq_err; 5253 5252 struct i40e_vsi *vsi = np->vsi; 5254 5253 struct i40e_pf *pf = vsi->back; 5254 5254 + enum libie_aq_err adq_err; 5255 5255 u32 reset_needed = 0; 5256 5256 int status; 5257 5257 u32 i, j; ··· 5371 5371 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; 5372 5372 ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags, 5373 5373 0, NULL); 5374 5374 - if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { 5374 5374 + if (ret && pf->hw.aq.asq_last_status != LIBIE_AQ_RC_ESRCH) { 5375 5375 dev_info(&pf->pdev->dev, 5376 5376 "couldn't set switch config bits, err %pe aq_err %s\n", 5377 5377 ERR_PTR(ret), 5378 5378 - i40e_aq_str(&pf->hw, 5379 5379 - pf->hw.aq.asq_last_status)); 5378 5378 + libie_aq_str(pf->hw.aq.asq_last_status)); 5380 5379 /* not a fatal problem, just keep going */ 5381 5380 } 5382 5381 } ··· 5437 5438 if (status) { 5438 5439 adq_err = pf->hw.aq.asq_last_status; 5439 5440 switch (adq_err) { 5440 5440 - case I40E_AQ_RC_EEXIST: 5441 5441 + case LIBIE_AQ_RC_EEXIST: 5441 5442 dev_warn(&pf->pdev->dev, 5442 5443 "FW LLDP agent is already running\n"); 5443 5444 reset_needed = 0; 5444 5445 break; 5445 5445 - case I40E_AQ_RC_EPERM: 5446 5446 + case LIBIE_AQ_RC_EPERM: 5446 5447 dev_warn(&pf->pdev->dev, 5447 5448 "Device configuration forbids SW from starting the LLDP agent.\n"); 5448 5449 return -EINVAL; 5449 5449 - case I40E_AQ_RC_EAGAIN: 5450 5450 + case LIBIE_AQ_RC_EAGAIN: 5450 5451 dev_warn(&pf->pdev->dev, 5451 5452 "Stop FW LLDP agent command is still being processed, please try again in a second.\n"); 5452 5453 return -EBUSY; ··· 5454 5455 dev_warn(&pf->pdev->dev, 5455 5456 "Starting FW LLDP agent failed: error: %pe, %s\n", 5456 5457 ERR_PTR(status), 5457 5457 - i40e_aq_str(&pf->hw, 5458 5458 - adq_err)); 5458 5458 + libie_aq_str(adq_err)); 5459 5459 return -EINVAL; 5460 5460 } 5461 5461 }

+90 -150

drivers/net/ethernet/intel/i40e/i40e_main.c

reviewed

··· 101 101 102 102 MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); 103 103 MODULE_IMPORT_NS("LIBIE"); 104 104 + MODULE_IMPORT_NS("LIBIE_ADMINQ"); 104 105 MODULE_LICENSE("GPL v2"); 105 106 106 107 static struct workqueue_struct *i40e_wq; ··· 1815 1814 if (ret) 1816 1815 netdev_info(netdev, "Ignoring error from firmware on LAA update, status %pe, AQ ret %s\n", 1817 1816 ERR_PTR(ret), 1818 1818 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1817 1817 + libie_aq_str(hw->aq.asq_last_status)); 1819 1818 } 1820 1819 1821 1820 /* schedule our worker thread which will take care of ··· 1847 1846 dev_info(&pf->pdev->dev, 1848 1847 "Cannot set RSS key, err %pe aq_err %s\n", 1849 1848 ERR_PTR(ret), 1850 1850 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1849 1849 + libie_aq_str(hw->aq.asq_last_status)); 1851 1850 return ret; 1852 1851 } 1853 1852 } ··· 1859 1858 dev_info(&pf->pdev->dev, 1860 1859 "Cannot set RSS lut, err %pe aq_err %s\n", 1861 1860 ERR_PTR(ret), 1862 1862 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1861 1861 + libie_aq_str(hw->aq.asq_last_status)); 1863 1862 return ret; 1864 1863 } 1865 1864 } ··· 2341 2340 int num_del, int *retval) 2342 2341 { 2343 2342 struct i40e_hw *hw = &vsi->back->hw; 2344 2344 - enum i40e_admin_queue_err aq_status; 2343 2343 + enum libie_aq_err aq_status; 2345 2344 int aq_ret; 2346 2345 2347 2346 aq_ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, list, num_del, NULL, 2348 2347 &aq_status); 2349 2348 2350 2349 /* Explicitly ignore and do not report when firmware returns ENOENT */ 2351 2351 - if (aq_ret && !(aq_status == I40E_AQ_RC_ENOENT)) { 2350 2350 + if (aq_ret && !(aq_status == LIBIE_AQ_RC_ENOENT)) { 2352 2351 *retval = -EIO; 2353 2352 dev_info(&vsi->back->pdev->dev, 2354 2353 "ignoring delete macvlan error on %s, err %pe, aq_err %s\n", 2355 2355 - vsi_name, ERR_PTR(aq_ret), 2356 2356 - i40e_aq_str(hw, aq_status)); 2354 2354 + vsi_name, ERR_PTR(aq_ret), libie_aq_str(aq_status)); 2357 2355 } 2358 2356 } 2359 2357 ··· 2375 2375 int num_add) 2376 2376 { 2377 2377 struct i40e_hw *hw = &vsi->back->hw; 2378 2378 - enum i40e_admin_queue_err aq_status; 2378 2378 + enum libie_aq_err aq_status; 2379 2379 int fcnt; 2380 2380 2381 2381 i40e_aq_add_macvlan_v2(hw, vsi->seid, list, num_add, NULL, &aq_status); ··· 2386 2386 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); 2387 2387 dev_warn(&vsi->back->pdev->dev, 2388 2388 "Error %s adding RX filters on %s, promiscuous mode forced on\n", 2389 2389 - i40e_aq_str(hw, aq_status), vsi_name); 2389 2389 + libie_aq_str(aq_status), vsi_name); 2390 2390 } else if (vsi->type == I40E_VSI_SRIOV || 2391 2391 vsi->type == I40E_VSI_VMDQ1 || 2392 2392 vsi->type == I40E_VSI_VMDQ2) { 2393 2393 dev_warn(&vsi->back->pdev->dev, 2394 2394 "Error %s adding RX filters on %s, please set promiscuous on manually for %s\n", 2395 2395 - i40e_aq_str(hw, aq_status), vsi_name, 2396 2396 - vsi_name); 2395 2395 + libie_aq_str(aq_status), vsi_name, vsi_name); 2397 2396 } else { 2398 2397 dev_warn(&vsi->back->pdev->dev, 2399 2398 "Error %s adding RX filters on %s, incorrect VSI type: %i.\n", 2400 2400 - i40e_aq_str(hw, aq_status), vsi_name, 2401 2401 - vsi->type); 2399 2399 + libie_aq_str(aq_status), vsi_name, vsi->type); 2402 2400 } 2403 2401 } 2404 2402 } ··· 2439 2441 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); 2440 2442 dev_warn(&vsi->back->pdev->dev, 2441 2443 "Error %s, forcing overflow promiscuous on %s\n", 2442 2442 - i40e_aq_str(hw, hw->aq.asq_last_status), 2443 2443 - vsi_name); 2444 2444 + libie_aq_str(hw->aq.asq_last_status), vsi_name); 2444 2445 } 2445 2446 2446 2447 return aq_ret; ··· 2480 2483 dev_info(&pf->pdev->dev, 2481 2484 "Set default VSI failed, err %pe, aq_err %s\n", 2482 2485 ERR_PTR(aq_ret), 2483 2483 - i40e_aq_str(hw, hw->aq.asq_last_status)); 2486 2486 + libie_aq_str(hw->aq.asq_last_status)); 2484 2487 } 2485 2488 } else { 2486 2489 aq_ret = i40e_aq_set_vsi_unicast_promiscuous( ··· 2492 2495 dev_info(&pf->pdev->dev, 2493 2496 "set unicast promisc failed, err %pe, aq_err %s\n", 2494 2497 ERR_PTR(aq_ret), 2495 2495 - i40e_aq_str(hw, hw->aq.asq_last_status)); 2498 2498 + libie_aq_str(hw->aq.asq_last_status)); 2496 2499 } 2497 2500 aq_ret = i40e_aq_set_vsi_multicast_promiscuous( 2498 2501 hw, ··· 2502 2505 dev_info(&pf->pdev->dev, 2503 2506 "set multicast promisc failed, err %pe, aq_err %s\n", 2504 2507 ERR_PTR(aq_ret), 2505 2505 - i40e_aq_str(hw, hw->aq.asq_last_status)); 2508 2508 + libie_aq_str(hw->aq.asq_last_status)); 2506 2509 } 2507 2510 } 2508 2511 ··· 2810 2813 "set multi promisc failed on %s, err %pe aq_err %s\n", 2811 2814 vsi_name, 2812 2815 ERR_PTR(aq_ret), 2813 2813 - i40e_aq_str(hw, hw->aq.asq_last_status)); 2816 2816 + libie_aq_str(hw->aq.asq_last_status)); 2814 2817 } else { 2815 2818 dev_info(&pf->pdev->dev, "%s allmulti mode.\n", 2816 2819 cur_multipromisc ? "entering" : "leaving"); ··· 2831 2834 cur_promisc ? "on" : "off", 2832 2835 vsi_name, 2833 2836 ERR_PTR(aq_ret), 2834 2834 - i40e_aq_str(hw, hw->aq.asq_last_status)); 2837 2837 + libie_aq_str(hw->aq.asq_last_status)); 2835 2838 } 2836 2839 } 2837 2840 out: ··· 2980 2983 dev_info(&vsi->back->pdev->dev, 2981 2984 "update vlan stripping failed, err %pe aq_err %s\n", 2982 2985 ERR_PTR(ret), 2983 2983 - i40e_aq_str(&vsi->back->hw, 2984 2984 - vsi->back->hw.aq.asq_last_status)); 2986 2986 + libie_aq_str(vsi->back->hw.aq.asq_last_status)); 2985 2987 } 2986 2988 } 2987 2989 ··· 3014 3018 dev_info(&vsi->back->pdev->dev, 3015 3019 "update vlan stripping failed, err %pe aq_err %s\n", 3016 3020 ERR_PTR(ret), 3017 3017 - i40e_aq_str(&vsi->back->hw, 3018 3018 - vsi->back->hw.aq.asq_last_status)); 3021 3021 + libie_aq_str(vsi->back->hw.aq.asq_last_status)); 3019 3022 } 3020 3023 } 3021 3024 ··· 3258 3263 dev_info(&vsi->back->pdev->dev, 3259 3264 "add pvid failed, err %pe aq_err %s\n", 3260 3265 ERR_PTR(ret), 3261 3261 - i40e_aq_str(&vsi->back->hw, 3262 3262 - vsi->back->hw.aq.asq_last_status)); 3266 3266 + libie_aq_str(vsi->back->hw.aq.asq_last_status)); 3263 3267 return -ENOENT; 3264 3268 } 3265 3269 ··· 5528 5534 dev_info(&pf->pdev->dev, 5529 5535 "couldn't get PF vsi bw config, err %pe aq_err %s\n", 5530 5536 ERR_PTR(ret), 5531 5531 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5537 5537 + libie_aq_str(pf->hw.aq.asq_last_status)); 5532 5538 return -EINVAL; 5533 5539 } 5534 5540 ··· 5539 5545 dev_info(&pf->pdev->dev, 5540 5546 "couldn't get PF vsi ets bw config, err %pe aq_err %s\n", 5541 5547 ERR_PTR(ret), 5542 5542 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5548 5548 + libie_aq_str(pf->hw.aq.asq_last_status)); 5543 5549 return -EINVAL; 5544 5550 } 5545 5551 ··· 5729 5735 if (ret) { 5730 5736 dev_info(&pf->pdev->dev, "Update vsi config failed, err %pe aq_err %s\n", 5731 5737 ERR_PTR(ret), 5732 5732 - i40e_aq_str(hw, hw->aq.asq_last_status)); 5738 5738 + libie_aq_str(hw->aq.asq_last_status)); 5733 5739 return ret; 5734 5740 } 5735 5741 /* update the local VSI info with updated queue map */ ··· 5785 5791 dev_info(&pf->pdev->dev, 5786 5792 "Failed querying vsi bw info, err %pe aq_err %s\n", 5787 5793 ERR_PTR(ret), 5788 5788 - i40e_aq_str(hw, hw->aq.asq_last_status)); 5794 5794 + libie_aq_str(hw->aq.asq_last_status)); 5789 5795 goto out; 5790 5796 } 5791 5797 if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) { ··· 5852 5858 dev_info(&pf->pdev->dev, 5853 5859 "Update vsi tc config failed, err %pe aq_err %s\n", 5854 5860 ERR_PTR(ret), 5855 5855 - i40e_aq_str(hw, hw->aq.asq_last_status)); 5861 5861 + libie_aq_str(hw->aq.asq_last_status)); 5856 5862 goto out; 5857 5863 } 5858 5864 /* update the local VSI info with updated queue map */ ··· 5865 5871 dev_info(&pf->pdev->dev, 5866 5872 "Failed updating vsi bw info, err %pe aq_err %s\n", 5867 5873 ERR_PTR(ret), 5868 5868 - i40e_aq_str(hw, hw->aq.asq_last_status)); 5874 5874 + libie_aq_str(hw->aq.asq_last_status)); 5869 5875 goto out; 5870 5876 } 5871 5877 ··· 5979 5985 dev_err(&pf->pdev->dev, 5980 5986 "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %pe aq_err %s\n", 5981 5987 max_tx_rate, seid, ERR_PTR(ret), 5982 5982 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5988 5988 + libie_aq_str(pf->hw.aq.asq_last_status)); 5983 5989 return ret; 5984 5990 } 5985 5991 ··· 5991 5997 **/ 5992 5998 static void i40e_remove_queue_channels(struct i40e_vsi *vsi) 5993 5999 { 5994 5994 - enum i40e_admin_queue_err last_aq_status; 5995 6000 struct i40e_cloud_filter *cfilter; 6001 6001 + enum libie_aq_err last_aq_status; 5996 6002 struct i40e_channel *ch, *ch_tmp; 5997 6003 struct i40e_pf *pf = vsi->back; 5998 6004 struct hlist_node *node; ··· 6055 6061 dev_info(&pf->pdev->dev, 6056 6062 "Failed to delete cloud filter, err %pe aq_err %s\n", 6057 6063 ERR_PTR(ret), 6058 6058 - i40e_aq_str(&pf->hw, last_aq_status)); 6064 6064 + libie_aq_str(last_aq_status)); 6059 6065 kfree(cfilter); 6060 6066 } 6061 6067 ··· 6190 6196 dev_info(&pf->pdev->dev, 6191 6197 "Cannot set RSS lut, err %pe aq_err %s\n", 6192 6198 ERR_PTR(ret), 6193 6193 - i40e_aq_str(hw, hw->aq.asq_last_status)); 6199 6199 + libie_aq_str(hw->aq.asq_last_status)); 6194 6200 kfree(lut); 6195 6201 return ret; 6196 6202 } ··· 6289 6295 dev_info(&pf->pdev->dev, 6290 6296 "add new vsi failed, err %pe aq_err %s\n", 6291 6297 ERR_PTR(ret), 6292 6292 - i40e_aq_str(&pf->hw, 6293 6293 - pf->hw.aq.asq_last_status)); 6298 6298 + libie_aq_str(pf->hw.aq.asq_last_status)); 6294 6299 return -ENOENT; 6295 6300 } 6296 6301 ··· 6532 6539 ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags, 6533 6540 pf->last_sw_conf_valid_flags, 6534 6541 mode, NULL); 6535 6535 - if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH) 6542 6542 + if (ret && hw->aq.asq_last_status != LIBIE_AQ_RC_ESRCH) 6536 6543 dev_err(&pf->pdev->dev, 6537 6544 "couldn't set switch config bits, err %pe aq_err %s\n", 6538 6538 - ERR_PTR(ret), 6539 6539 - i40e_aq_str(hw, 6540 6540 - hw->aq.asq_last_status)); 6545 6545 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 6541 6546 6542 6547 return ret; 6543 6548 } ··· 6734 6743 if (ret) { 6735 6744 dev_info(&pf->pdev->dev, 6736 6745 "VEB bw config failed, err %pe aq_err %s\n", 6737 6737 - ERR_PTR(ret), 6738 6738 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6746 6746 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 6739 6747 goto out; 6740 6748 } 6741 6749 ··· 6743 6753 if (ret) { 6744 6754 dev_info(&pf->pdev->dev, 6745 6755 "Failed getting veb bw config, err %pe aq_err %s\n", 6746 6746 - ERR_PTR(ret), 6747 6747 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6756 6756 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 6748 6757 } 6749 6758 6750 6759 out: ··· 6824 6835 dev_info(&pf->pdev->dev, 6825 6836 "Resume Port Tx failed, err %pe aq_err %s\n", 6826 6837 ERR_PTR(ret), 6827 6827 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6838 6838 + libie_aq_str(pf->hw.aq.asq_last_status)); 6828 6839 /* Schedule PF reset to recover */ 6829 6840 set_bit(__I40E_PF_RESET_REQUESTED, pf->state); 6830 6841 i40e_service_event_schedule(pf); ··· 6848 6859 if (ret) { 6849 6860 dev_info(&pf->pdev->dev, 6850 6861 "Suspend Port Tx failed, err %pe aq_err %s\n", 6851 6851 - ERR_PTR(ret), 6852 6852 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6862 6862 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 6853 6863 /* Schedule PF reset to recover */ 6854 6864 set_bit(__I40E_PF_RESET_REQUESTED, pf->state); 6855 6865 i40e_service_event_schedule(pf); ··· 6887 6899 if (ret) { 6888 6900 dev_info(&pf->pdev->dev, 6889 6901 "Set DCB Config failed, err %pe aq_err %s\n", 6890 6890 - ERR_PTR(ret), 6891 6891 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6902 6902 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 6892 6903 goto out; 6893 6904 } 6894 6905 ··· 7003 7016 if (ret) { 7004 7017 dev_info(&pf->pdev->dev, 7005 7018 "Modify Port ETS failed, err %pe aq_err %s\n", 7006 7006 - ERR_PTR(ret), 7007 7007 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 7019 7019 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 7008 7020 goto out; 7009 7021 } 7010 7022 ··· 7042 7056 if (ret) { 7043 7057 dev_info(&pf->pdev->dev, 7044 7058 "DCB Updated failed, err %pe aq_err %s\n", 7045 7045 - ERR_PTR(ret), 7046 7046 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 7059 7059 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 7047 7060 goto out; 7048 7061 } 7049 7062 ··· 7125 7140 if (err) { 7126 7141 dev_info(&pf->pdev->dev, 7127 7142 "Enable Port ETS failed, err %pe aq_err %s\n", 7128 7128 - ERR_PTR(err), 7129 7129 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 7143 7143 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 7130 7144 err = -ENOENT; 7131 7145 goto out; 7132 7146 } ··· 7198 7214 dev_dbg(&pf->pdev->dev, 7199 7215 "DCBX offload is supported for this PF.\n"); 7200 7216 } 7201 7201 - } else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) { 7217 7217 + } else if (pf->hw.aq.asq_last_status == LIBIE_AQ_RC_EPERM) { 7202 7218 dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n"); 7203 7219 set_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags); 7204 7220 } else { 7205 7221 dev_info(&pf->pdev->dev, 7206 7222 "Query for DCB configuration failed, err %pe aq_err %s\n", 7207 7207 - ERR_PTR(err), 7208 7208 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 7223 7223 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 7209 7224 } 7210 7225 7211 7226 out: ··· 7460 7477 if (err) { 7461 7478 dev_err(&pf->pdev->dev, 7462 7479 "failed to get phy cap., ret = %pe last_status = %s\n", 7463 7463 - ERR_PTR(err), 7464 7464 - i40e_aq_str(hw, hw->aq.asq_last_status)); 7480 7480 + ERR_PTR(err), libie_aq_str(hw->aq.asq_last_status)); 7465 7481 return err; 7466 7482 } 7467 7483 speed = abilities.link_speed; ··· 7471 7489 if (err) { 7472 7490 dev_err(&pf->pdev->dev, 7473 7491 "failed to get phy cap., ret = %pe last_status = %s\n", 7474 7474 - ERR_PTR(err), 7475 7475 - i40e_aq_str(hw, hw->aq.asq_last_status)); 7492 7492 + ERR_PTR(err), libie_aq_str(hw->aq.asq_last_status)); 7476 7493 return err; 7477 7494 } 7478 7495 ··· 7515 7534 if (err) { 7516 7535 dev_err(&pf->pdev->dev, 7517 7536 "set phy config ret = %pe last_status = %s\n", 7518 7518 - ERR_PTR(err), 7519 7519 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 7537 7537 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 7520 7538 return err; 7521 7539 } 7522 7540 ··· 7855 7875 } 7856 7876 dev_info(&pf->pdev->dev, 7857 7877 "Error adding mac filter on macvlan err %pe, aq_err %s\n", 7858 7858 - ERR_PTR(ret), 7859 7859 - i40e_aq_str(hw, aq_err)); 7878 7878 + ERR_PTR(ret), libie_aq_str(aq_err)); 7860 7879 netdev_err(vdev, "L2fwd offload disabled to L2 filter error\n"); 7861 7880 } 7862 7881 ··· 7927 7948 if (ret) { 7928 7949 dev_info(&pf->pdev->dev, 7929 7950 "Update vsi tc config failed, err %pe aq_err %s\n", 7930 7930 - ERR_PTR(ret), 7931 7931 - i40e_aq_str(hw, hw->aq.asq_last_status)); 7951 7951 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 7932 7952 return ret; 7933 7953 } 7934 7954 /* update the local VSI info with updated queue map */ ··· 8142 8164 } else { 8143 8165 dev_info(&pf->pdev->dev, 8144 8166 "Error deleting mac filter on macvlan err %pe, aq_err %s\n", 8145 8145 - ERR_PTR(ret), 8146 8146 - i40e_aq_str(hw, aq_err)); 8167 8167 + ERR_PTR(ret), libie_aq_str(aq_err)); 8147 8168 } 8148 8169 break; 8149 8170 } ··· 9396 9419 static int i40e_handle_lldp_event(struct i40e_pf *pf, 9397 9420 struct i40e_arq_event_info *e) 9398 9421 { 9399 9399 - struct i40e_aqc_lldp_get_mib *mib = 9400 9400 - (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; 9422 9422 + struct i40e_aqc_lldp_get_mib *mib = libie_aq_raw(&e->desc); 9401 9423 struct i40e_hw *hw = &pf->hw; 9402 9424 struct i40e_dcbx_config tmp_dcbx_cfg; 9403 9425 bool need_reconfig = false; ··· 9453 9477 dev_info(&pf->pdev->dev, 9454 9478 "Failed querying DCB configuration data from firmware, err %pe aq_err %s\n", 9455 9479 ERR_PTR(ret), 9456 9456 - i40e_aq_str(&pf->hw, 9457 9457 - pf->hw.aq.asq_last_status)); 9480 9480 + libie_aq_str(pf->hw.aq.asq_last_status)); 9458 9481 } 9459 9482 goto exit; 9460 9483 } ··· 9534 9559 static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, 9535 9560 struct i40e_arq_event_info *e) 9536 9561 { 9537 9537 - struct i40e_aqc_lan_overflow *data = 9538 9538 - (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; 9562 9562 + struct i40e_aqc_lan_overflow *data = libie_aq_raw(&e->desc); 9539 9563 u32 queue = le32_to_cpu(data->prtdcb_rupto); 9540 9564 u32 qtx_ctl = le32_to_cpu(data->otx_ctl); 9541 9565 struct i40e_hw *hw = &pf->hw; ··· 10054 10080 static void i40e_handle_link_event(struct i40e_pf *pf, 10055 10081 struct i40e_arq_event_info *e) 10056 10082 { 10057 10057 - struct i40e_aqc_get_link_status *status = 10058 10058 - (struct i40e_aqc_get_link_status *)&e->desc.params.raw; 10083 10083 + struct i40e_aqc_get_link_status *status = libie_aq_raw(&e->desc); 10059 10084 10060 10085 /* Do a new status request to re-enable LSE reporting 10061 10086 * and load new status information into the hw struct ··· 10262 10289 if (ret) { 10263 10290 dev_info(&pf->pdev->dev, 10264 10291 "couldn't get PF vsi config, err %pe aq_err %s\n", 10265 10265 - ERR_PTR(ret), 10266 10266 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10292 10292 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10267 10293 return; 10268 10294 } 10269 10295 ctxt.flags = I40E_AQ_VSI_TYPE_PF; ··· 10273 10301 if (ret) { 10274 10302 dev_info(&pf->pdev->dev, 10275 10303 "update vsi switch failed, err %pe aq_err %s\n", 10276 10276 - ERR_PTR(ret), 10277 10277 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10304 10304 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10278 10305 } 10279 10306 } 10280 10307 ··· 10296 10325 if (ret) { 10297 10326 dev_info(&pf->pdev->dev, 10298 10327 "couldn't get PF vsi config, err %pe aq_err %s\n", 10299 10299 - ERR_PTR(ret), 10300 10300 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10328 10328 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10301 10329 return; 10302 10330 } 10303 10331 ctxt.flags = I40E_AQ_VSI_TYPE_PF; ··· 10307 10337 if (ret) { 10308 10338 dev_info(&pf->pdev->dev, 10309 10339 "update vsi switch failed, err %pe aq_err %s\n", 10310 10310 - ERR_PTR(ret), 10311 10311 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10340 10340 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10312 10341 } 10313 10342 } 10314 10343 ··· 10422 10453 static int i40e_get_capabilities(struct i40e_pf *pf, 10423 10454 enum i40e_admin_queue_opc list_type) 10424 10455 { 10425 10425 - struct i40e_aqc_list_capabilities_element_resp *cap_buf; 10456 10456 + struct libie_aqc_list_caps_elem *cap_buf; 10426 10457 u16 data_size; 10427 10458 int buf_len; 10428 10459 int err; 10429 10460 10430 10430 - buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 10461 10461 + buf_len = 40 * sizeof(struct libie_aqc_list_caps_elem); 10431 10462 do { 10432 10463 cap_buf = kzalloc(buf_len, GFP_KERNEL); 10433 10464 if (!cap_buf) ··· 10440 10471 /* data loaded, buffer no longer needed */ 10441 10472 kfree(cap_buf); 10442 10473 10443 10443 - if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { 10474 10474 + if (pf->hw.aq.asq_last_status == LIBIE_AQ_RC_ENOMEM) { 10444 10475 /* retry with a larger buffer */ 10445 10476 buf_len = data_size; 10446 10446 - } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK || err) { 10477 10477 + } else if (pf->hw.aq.asq_last_status != LIBIE_AQ_RC_OK || err) { 10447 10478 dev_info(&pf->pdev->dev, 10448 10479 "capability discovery failed, err %pe aq_err %s\n", 10449 10480 ERR_PTR(err), 10450 10450 - i40e_aq_str(&pf->hw, 10451 10451 - pf->hw.aq.asq_last_status)); 10481 10481 + libie_aq_str(pf->hw.aq.asq_last_status)); 10452 10482 return -ENODEV; 10453 10483 } 10454 10484 } while (err); ··· 10584 10616 dev_dbg(&pf->pdev->dev, 10585 10617 "Failed to rebuild cloud filter, err %pe aq_err %s\n", 10586 10618 ERR_PTR(ret), 10587 10587 - i40e_aq_str(&pf->hw, 10588 10588 - pf->hw.aq.asq_last_status)); 10619 10619 + libie_aq_str(pf->hw.aq.asq_last_status)); 10589 10620 return ret; 10590 10621 } 10591 10622 } ··· 10825 10858 ret = i40e_init_adminq(&pf->hw); 10826 10859 if (ret) { 10827 10860 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %pe aq_err %s\n", 10828 10828 - ERR_PTR(ret), 10829 10829 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10861 10861 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10830 10862 goto clear_recovery; 10831 10863 } 10832 10864 i40e_get_oem_version(&pf->hw); ··· 10936 10970 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); 10937 10971 if (ret) 10938 10972 dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n", 10939 10939 - ERR_PTR(ret), 10940 10940 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10973 10973 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 10941 10974 10942 10975 /* Rebuild the VSIs and VEBs that existed before reset. 10943 10976 * They are still in our local switch element arrays, so only ··· 11034 11069 if (ret) 11035 11070 dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n", 11036 11071 ERR_PTR(ret), 11037 11037 - i40e_aq_str(&pf->hw, 11038 11038 - pf->hw.aq.asq_last_status)); 11072 11072 + libie_aq_str(pf->hw.aq.asq_last_status)); 11039 11073 } 11040 11074 /* reinit the misc interrupt */ 11041 11075 if (test_bit(I40E_FLAG_MSIX_ENA, pf->flags)) { ··· 11065 11101 dev_warn(&pf->pdev->dev, 11066 11102 "Failed to restore promiscuous setting: %s, err %pe aq_err %s\n", 11067 11103 pf->cur_promisc ? "on" : "off", 11068 11068 - ERR_PTR(ret), 11069 11069 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 11104 11104 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 11070 11105 11071 11106 i40e_reset_all_vfs(pf, true); 11072 11107 ··· 12271 12308 dev_info(&pf->pdev->dev, 12272 12309 "Cannot get RSS key, err %pe aq_err %s\n", 12273 12310 ERR_PTR(ret), 12274 12274 - i40e_aq_str(&pf->hw, 12275 12275 - pf->hw.aq.asq_last_status)); 12311 12311 + libie_aq_str(pf->hw.aq.asq_last_status)); 12276 12312 return ret; 12277 12313 } 12278 12314 } ··· 12284 12322 dev_info(&pf->pdev->dev, 12285 12323 "Cannot get RSS lut, err %pe aq_err %s\n", 12286 12324 ERR_PTR(ret), 12287 12287 - i40e_aq_str(&pf->hw, 12288 12288 - pf->hw.aq.asq_last_status)); 12325 12325 + libie_aq_str(pf->hw.aq.asq_last_status)); 12289 12326 return ret; 12290 12327 } 12291 12328 } ··· 12945 12984 NULL); 12946 12985 if (ret) { 12947 12986 netdev_info(netdev, "add UDP port failed, err %pe aq_err %s\n", 12948 12948 - ERR_PTR(ret), 12949 12949 - i40e_aq_str(hw, hw->aq.asq_last_status)); 12987 12987 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 12950 12988 return -EIO; 12951 12989 } 12952 12990 ··· 12964 13004 ret = i40e_aq_del_udp_tunnel(hw, ti->hw_priv, NULL); 12965 13005 if (ret) { 12966 13006 netdev_info(netdev, "delete UDP port failed, err %pe aq_err %s\n", 12967 12967 - ERR_PTR(ret), 12968 12968 - i40e_aq_str(hw, hw->aq.asq_last_status)); 13007 13007 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 12969 13008 return -EIO; 12970 13009 } 12971 13010 ··· 13854 13895 dev_info(&pf->pdev->dev, 13855 13896 "couldn't get PF vsi config, err %pe aq_err %s\n", 13856 13897 ERR_PTR(ret), 13857 13857 - i40e_aq_str(&pf->hw, 13858 13858 - pf->hw.aq.asq_last_status)); 13898 13898 + libie_aq_str(pf->hw.aq.asq_last_status)); 13859 13899 return -ENOENT; 13860 13900 } 13861 13901 vsi->info = ctxt.info; ··· 13883 13925 dev_info(&pf->pdev->dev, 13884 13926 "update vsi failed, err %d aq_err %s\n", 13885 13927 ret, 13886 13886 - i40e_aq_str(&pf->hw, 13887 13887 - pf->hw.aq.asq_last_status)); 13928 13928 + libie_aq_str(pf->hw.aq.asq_last_status)); 13888 13929 ret = -ENOENT; 13889 13930 goto err; 13890 13931 } ··· 13902 13945 dev_info(&pf->pdev->dev, 13903 13946 "update vsi failed, err %pe aq_err %s\n", 13904 13947 ERR_PTR(ret), 13905 13905 - i40e_aq_str(&pf->hw, 13906 13906 - pf->hw.aq.asq_last_status)); 13948 13948 + libie_aq_str(pf->hw.aq.asq_last_status)); 13907 13949 ret = -ENOENT; 13908 13950 goto err; 13909 13951 } ··· 13925 13969 "failed to configure TCs for main VSI tc_map 0x%08x, err %pe aq_err %s\n", 13926 13970 enabled_tc, 13927 13971 ERR_PTR(ret), 13928 13928 - i40e_aq_str(&pf->hw, 13929 13929 - pf->hw.aq.asq_last_status)); 13972 13972 + libie_aq_str(pf->hw.aq.asq_last_status)); 13930 13973 } 13931 13974 } 13932 13975 break; ··· 14019 14064 dev_info(&vsi->back->pdev->dev, 14020 14065 "add vsi failed, err %pe aq_err %s\n", 14021 14066 ERR_PTR(ret), 14022 14022 - i40e_aq_str(&pf->hw, 14023 14023 - pf->hw.aq.asq_last_status)); 14067 14067 + libie_aq_str(pf->hw.aq.asq_last_status)); 14024 14068 ret = -ENOENT; 14025 14069 goto err; 14026 14070 } ··· 14049 14095 if (ret) { 14050 14096 dev_info(&pf->pdev->dev, 14051 14097 "couldn't get vsi bw info, err %pe aq_err %s\n", 14052 14052 - ERR_PTR(ret), 14053 14053 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 14098 14098 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 14054 14099 /* VSI is already added so not tearing that up */ 14055 14100 ret = 0; 14056 14101 } ··· 14497 14544 if (ret) { 14498 14545 dev_info(&pf->pdev->dev, 14499 14546 "query veb bw config failed, err %pe aq_err %s\n", 14500 14500 - ERR_PTR(ret), 14501 14501 - i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); 14547 14547 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 14502 14548 goto out; 14503 14549 } 14504 14550 ··· 14506 14554 if (ret) { 14507 14555 dev_info(&pf->pdev->dev, 14508 14556 "query veb bw ets config failed, err %pe aq_err %s\n", 14509 14509 - ERR_PTR(ret), 14510 14510 - i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); 14557 14557 + ERR_PTR(ret), libie_aq_str(hw->aq.asq_last_status)); 14511 14558 goto out; 14512 14559 } 14513 14560 ··· 14694 14743 if (ret) { 14695 14744 dev_info(&pf->pdev->dev, 14696 14745 "couldn't add VEB, err %pe aq_err %s\n", 14697 14697 - ERR_PTR(ret), 14698 14698 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 14746 14746 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 14699 14747 return -EPERM; 14700 14748 } 14701 14749 ··· 14704 14754 if (ret) { 14705 14755 dev_info(&pf->pdev->dev, 14706 14756 "couldn't get VEB statistics idx, err %pe aq_err %s\n", 14707 14707 - ERR_PTR(ret), 14708 14708 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 14757 14757 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 14709 14758 return -EPERM; 14710 14759 } 14711 14760 ret = i40e_veb_get_bw_info(veb); 14712 14761 if (ret) { 14713 14762 dev_info(&pf->pdev->dev, 14714 14763 "couldn't get VEB bw info, err %pe aq_err %s\n", 14715 14715 - ERR_PTR(ret), 14716 14716 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 14764 14764 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 14717 14765 i40e_aq_delete_element(&pf->hw, veb->seid, NULL); 14718 14766 return -ENOENT; 14719 14767 } ··· 14906 14958 if (ret) { 14907 14959 dev_info(&pf->pdev->dev, 14908 14960 "get switch config failed err %d aq_err %s\n", 14909 14909 - ret, 14910 14910 - i40e_aq_str(&pf->hw, 14911 14911 - pf->hw.aq.asq_last_status)); 14961 14961 + ret, libie_aq_str(pf->hw.aq.asq_last_status)); 14912 14962 kfree(aq_buf); 14913 14963 return -ENOENT; 14914 14964 } ··· 14951 15005 if (ret) { 14952 15006 dev_info(&pf->pdev->dev, 14953 15007 "couldn't fetch switch config, err %pe aq_err %s\n", 14954 14954 - ERR_PTR(ret), 14955 14955 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 15008 15008 + ERR_PTR(ret), libie_aq_str(pf->hw.aq.asq_last_status)); 14956 15009 return ret; 14957 15010 } 14958 15011 i40e_pf_reset_stats(pf); ··· 14974 15029 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; 14975 15030 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0, 14976 15031 NULL); 14977 14977 - if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { 15032 15032 + if (ret && pf->hw.aq.asq_last_status != LIBIE_AQ_RC_ESRCH) { 14978 15033 dev_info(&pf->pdev->dev, 14979 15034 "couldn't set switch config bits, err %pe aq_err %s\n", 14980 15035 ERR_PTR(ret), 14981 14981 - i40e_aq_str(&pf->hw, 14982 14982 - pf->hw.aq.asq_last_status)); 15036 15036 + libie_aq_str(pf->hw.aq.asq_last_status)); 14983 15037 /* not a fatal problem, just keep going */ 14984 15038 } 14985 15039 pf->last_sw_conf_valid_flags = valid_flags; ··· 15880 15936 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); 15881 15937 if (err) 15882 15938 dev_info(&pf->pdev->dev, "set phy mask fail, err %pe aq_err %s\n", 15883 15883 - ERR_PTR(err), 15884 15884 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 15939 15939 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 15885 15940 15886 15941 /* VF MDD event logs are rate limited to one second intervals */ 15887 15942 ratelimit_state_init(&pf->mdd_message_rate_limit, 1 * HZ, 1); ··· 15902 15959 if (err) 15903 15960 dev_info(&pf->pdev->dev, "link restart failed, err %pe aq_err %s\n", 15904 15961 ERR_PTR(err), 15905 15905 - i40e_aq_str(&pf->hw, 15906 15906 - pf->hw.aq.asq_last_status)); 15962 15962 + libie_aq_str(pf->hw.aq.asq_last_status)); 15907 15963 } 15908 15964 /* The main driver is (mostly) up and happy. We need to set this state 15909 15965 * before setting up the misc vector or we get a race and the vector ··· 16033 16091 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); 16034 16092 if (err) 16035 16093 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %pe last_status = %s\n", 16036 16036 - ERR_PTR(err), 16037 16037 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 16094 16094 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 16038 16095 pf->hw.phy.link_info.requested_speeds = abilities.link_speed; 16039 16096 16040 16097 /* set the FEC config due to the board capabilities */ ··· 16043 16102 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); 16044 16103 if (err) 16045 16104 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %pe last_status = %s\n", 16046 16046 - ERR_PTR(err), 16047 16047 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 16105 16105 + ERR_PTR(err), libie_aq_str(pf->hw.aq.asq_last_status)); 16048 16106 16049 16107 /* make sure the MFS hasn't been set lower than the default */ 16050 16108 #define MAX_FRAME_SIZE_DEFAULT 0x2600

+9 -9

drivers/net/ethernet/intel/i40e/i40e_nvm.c

reviewed

··· 997 997 u8 *bytes, int *perrno) 998 998 { 999 999 struct i40e_asq_cmd_details cmd_details; 1000 1000 - struct i40e_aq_desc *aq_desc; 1000 1000 + struct libie_aq_desc *aq_desc; 1001 1001 u32 buff_size = 0; 1002 1002 u8 *buff = NULL; 1003 1003 u32 aq_desc_len; ··· 1011 1011 memset(&cmd_details, 0, sizeof(cmd_details)); 1012 1012 cmd_details.wb_desc = &hw->nvm_wb_desc; 1013 1013 1014 1014 - aq_desc_len = sizeof(struct i40e_aq_desc); 1014 1014 + aq_desc_len = sizeof(struct libie_aq_desc); 1015 1015 memset(&hw->nvm_wb_desc, 0, aq_desc_len); 1016 1016 1017 1017 /* get the aq descriptor */ ··· 1022 1022 *perrno = -EINVAL; 1023 1023 return -EINVAL; 1024 1024 } 1025 1025 - aq_desc = (struct i40e_aq_desc *)bytes; 1025 1025 + aq_desc = (struct libie_aq_desc *)bytes; 1026 1026 1027 1027 /* if data buffer needed, make sure it's ready */ 1028 1028 aq_data_len = cmd->data_size - aq_desc_len; ··· 1053 1053 i40e_debug(hw, I40E_DEBUG_NVM, 1054 1054 "%s err %pe aq_err %s\n", 1055 1055 __func__, ERR_PTR(status), 1056 1056 - i40e_aq_str(hw, hw->aq.asq_last_status)); 1056 1056 + libie_aq_str(hw->aq.asq_last_status)); 1057 1057 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1058 1058 return status; 1059 1059 } ··· 1087 1087 1088 1088 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1089 1089 1090 1090 - aq_desc_len = sizeof(struct i40e_aq_desc); 1090 1090 + aq_desc_len = sizeof(struct libie_aq_desc); 1091 1091 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); 1092 1092 1093 1093 /* check offset range */ ··· 1154 1154 1155 1155 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1156 1156 1157 1157 - aq_desc_len = sizeof(struct i40e_aq_desc); 1157 1157 + aq_desc_len = sizeof(struct libie_aq_desc); 1158 1158 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen); 1159 1159 1160 1160 /* check copylength range */ ··· 1442 1442 * so here we try to reacquire the semaphore then retry the write. 1443 1443 * We only do one retry, then give up. 1444 1444 */ 1445 1445 - if (status && hw->aq.asq_last_status == I40E_AQ_RC_EBUSY && 1445 1445 + if (status && hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY && 1446 1446 !retry_attempt) { 1447 1447 u32 old_asq_status = hw->aq.asq_last_status; 1448 1448 int old_status = status; ··· 1628 1628 * @desc: AdminQ descriptor 1629 1629 **/ 1630 1630 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 1631 1631 - struct i40e_aq_desc *desc) 1631 1631 + struct libie_aq_desc *desc) 1632 1632 { 1633 1633 - u32 aq_desc_len = sizeof(struct i40e_aq_desc); 1633 1633 + u32 aq_desc_len = sizeof(struct libie_aq_desc); 1634 1634 1635 1635 if (opcode == hw->nvm_wait_opcode) { 1636 1636 memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len);

+7 -8

drivers/net/ethernet/intel/i40e/i40e_prototype.h

reviewed

··· 23 23 struct i40e_arq_event_info *e, 24 24 u16 *events_pending); 25 25 int 26 26 - i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc, 26 26 + i40e_asq_send_command(struct i40e_hw *hw, struct libie_aq_desc *desc, 27 27 void *buff, /* can be NULL */ u16 buff_size, 28 28 struct i40e_asq_cmd_details *cmd_details); 29 29 int 30 30 - i40e_asq_send_command_atomic(struct i40e_hw *hw, struct i40e_aq_desc *desc, 30 30 + i40e_asq_send_command_atomic(struct i40e_hw *hw, struct libie_aq_desc *desc, 31 31 void *buff, /* can be NULL */ u16 buff_size, 32 32 struct i40e_asq_cmd_details *cmd_details, 33 33 bool is_atomic_context); 34 34 int 35 35 i40e_asq_send_command_atomic_v2(struct i40e_hw *hw, 36 36 - struct i40e_aq_desc *desc, 36 36 + struct libie_aq_desc *desc, 37 37 void *buff, /* can be NULL */ 38 38 u16 buff_size, 39 39 struct i40e_asq_cmd_details *cmd_details, 40 40 bool is_atomic_context, 41 41 - enum i40e_admin_queue_err *aq_status); 41 41 + enum libie_aq_err *aq_status); 42 42 43 43 /* debug function for adminq */ 44 44 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, ··· 46 46 47 47 bool i40e_check_asq_alive(struct i40e_hw *hw); 48 48 int i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading); 49 49 - const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err); 50 49 51 50 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid, 52 51 bool pf_lut, u8 *lut, u16 lut_size); ··· 154 155 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 155 156 struct i40e_aqc_add_macvlan_element_data *mv_list, 156 157 u16 count, struct i40e_asq_cmd_details *cmd_details, 157 157 - enum i40e_admin_queue_err *aq_status); 158 158 + enum libie_aq_err *aq_status); 158 159 int i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id, 159 160 struct i40e_aqc_remove_macvlan_element_data *mv_list, 160 161 u16 count, struct i40e_asq_cmd_details *cmd_details); ··· 162 163 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 163 164 struct i40e_aqc_remove_macvlan_element_data *mv_list, 164 165 u16 count, struct i40e_asq_cmd_details *cmd_details, 165 165 - enum i40e_admin_queue_err *aq_status); 166 166 + enum libie_aq_err *aq_status); 166 167 167 168 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 168 169 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, ··· 338 339 struct i40e_nvm_access *cmd, 339 340 u8 *bytes, int *errno); 340 341 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 341 341 - struct i40e_aq_desc *desc); 342 342 + struct libie_aq_desc *desc); 342 343 void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw); 343 344 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status); 344 345

+3 -3

drivers/net/ethernet/intel/i40e/i40e_type.h

reviewed

··· 24 24 25 25 /* forward declaration */ 26 26 struct i40e_hw; 27 27 - typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 27 27 + typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct libie_aq_desc *); 28 28 29 29 /* Data type manipulation macros. */ 30 30 ··· 555 555 556 556 /* state of nvm update process */ 557 557 enum i40e_nvmupd_state nvmupd_state; 558 558 - struct i40e_aq_desc nvm_wb_desc; 559 559 - struct i40e_aq_desc nvm_aq_event_desc; 558 558 + struct libie_aq_desc nvm_wb_desc; 559 559 + struct libie_aq_desc nvm_aq_event_desc; 560 560 struct i40e_virt_mem nvm_buff; 561 561 bool nvm_release_on_done; 562 562 u16 nvm_wait_opcode;

+11 -16

drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c

reviewed

··· 1290 1290 1291 1291 dev_err(&pf->pdev->dev, 1292 1292 "VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n", 1293 1293 - vf->vf_id, 1294 1294 - ERR_PTR(aq_ret), 1295 1295 - i40e_aq_str(&pf->hw, aq_err)); 1293 1293 + vf->vf_id, ERR_PTR(aq_ret), 1294 1294 + libie_aq_str(aq_err)); 1296 1295 1297 1296 return aq_ret; 1298 1297 } ··· 1305 1306 1306 1307 dev_err(&pf->pdev->dev, 1307 1308 "VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n", 1308 1308 - vf->vf_id, 1309 1309 - ERR_PTR(aq_ret), 1310 1310 - i40e_aq_str(&pf->hw, aq_err)); 1309 1309 + vf->vf_id, ERR_PTR(aq_ret), 1310 1310 + libie_aq_str(aq_err)); 1311 1311 } 1312 1312 1313 1313 return aq_ret; ··· 1321 1323 1322 1324 dev_err(&pf->pdev->dev, 1323 1325 "VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n", 1324 1324 - vf->vf_id, 1325 1325 - ERR_PTR(aq_ret), 1326 1326 - i40e_aq_str(&pf->hw, aq_err)); 1326 1326 + vf->vf_id, ERR_PTR(aq_ret), 1327 1327 + libie_aq_str(aq_err)); 1327 1328 1328 1329 if (!aq_tmp) 1329 1330 aq_tmp = aq_ret; ··· 1336 1339 1337 1340 dev_err(&pf->pdev->dev, 1338 1341 "VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n", 1339 1339 - vf->vf_id, 1340 1340 - ERR_PTR(aq_ret), 1341 1341 - i40e_aq_str(&pf->hw, aq_err)); 1342 1342 + vf->vf_id, ERR_PTR(aq_ret), 1343 1343 + libie_aq_str(aq_err)); 1342 1344 1343 1345 if (!aq_tmp) 1344 1346 aq_tmp = aq_ret; ··· 3744 3748 dev_err(&pf->pdev->dev, 3745 3749 "VF %d: Failed to delete cloud filter, err %pe aq_err %s\n", 3746 3750 vf->vf_id, ERR_PTR(ret), 3747 3747 - i40e_aq_str(&pf->hw, 3748 3748 - pf->hw.aq.asq_last_status)); 3751 3751 + libie_aq_str(pf->hw.aq.asq_last_status)); 3749 3752 3750 3753 hlist_del(&cfilter->cloud_node); 3751 3754 kfree(cfilter); ··· 3846 3851 dev_err(&pf->pdev->dev, 3847 3852 "VF %d: Failed to delete cloud filter, err %pe aq_err %s\n", 3848 3853 vf->vf_id, ERR_PTR(ret), 3849 3849 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 3854 3854 + libie_aq_str(pf->hw.aq.asq_last_status)); 3850 3855 goto err; 3851 3856 } 3852 3857 ··· 3982 3987 dev_err(&pf->pdev->dev, 3983 3988 "VF %d: Failed to add cloud filter, err %pe aq_err %s\n", 3984 3989 vf->vf_id, ERR_PTR(aq_ret), 3985 3985 - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 3990 3990 + libie_aq_str(pf->hw.aq.asq_last_status)); 3986 3991 goto err_free; 3987 3992 } 3988 3993

+31 -31

drivers/net/ethernet/intel/iavf/iavf_adminq.c

reviewed

··· 18 18 ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 19 19 iavf_mem_atq_ring, 20 20 (hw->aq.num_asq_entries * 21 21 - sizeof(struct iavf_aq_desc)), 21 21 + sizeof(struct libie_aq_desc)), 22 22 IAVF_ADMINQ_DESC_ALIGNMENT); 23 23 if (ret_code) 24 24 return ret_code; ··· 45 45 ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 46 46 iavf_mem_arq_ring, 47 47 (hw->aq.num_arq_entries * 48 48 - sizeof(struct iavf_aq_desc)), 48 48 + sizeof(struct libie_aq_desc)), 49 49 IAVF_ADMINQ_DESC_ALIGNMENT); 50 50 51 51 return ret_code; ··· 81 81 **/ 82 82 static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw) 83 83 { 84 84 - struct iavf_aq_desc *desc; 84 84 + struct libie_aq_desc *desc; 85 85 struct iavf_dma_mem *bi; 86 86 enum iavf_status ret_code; 87 87 int i; ··· 111 111 /* now configure the descriptors for use */ 112 112 desc = IAVF_ADMINQ_DESC(hw->aq.arq, i); 113 113 114 114 - desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF); 114 114 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 115 115 if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF) 116 116 - desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB); 116 116 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 117 117 desc->opcode = 0; 118 118 /* This is in accordance with Admin queue design, there is no 119 119 * register for buffer size configuration ··· 122 122 desc->retval = 0; 123 123 desc->cookie_high = 0; 124 124 desc->cookie_low = 0; 125 125 - desc->params.external.addr_high = 125 125 + desc->params.generic.addr_high = 126 126 cpu_to_le32(upper_32_bits(bi->pa)); 127 127 - desc->params.external.addr_low = 127 127 + desc->params.generic.addr_low = 128 128 cpu_to_le32(lower_32_bits(bi->pa)); 129 129 - desc->params.external.param0 = 0; 130 130 - desc->params.external.param1 = 0; 129 129 + desc->params.generic.param0 = 0; 130 130 + desc->params.generic.param1 = 0; 131 131 } 132 132 133 133 alloc_arq_bufs: ··· 558 558 struct iavf_adminq_ring *asq = &hw->aq.asq; 559 559 struct iavf_asq_cmd_details *details; 560 560 u16 ntc = asq->next_to_clean; 561 561 - struct iavf_aq_desc desc_cb; 562 562 - struct iavf_aq_desc *desc; 561 561 + struct libie_aq_desc desc_cb; 562 562 + struct libie_aq_desc *desc; 563 563 564 564 desc = IAVF_ADMINQ_DESC(*asq, ntc); 565 565 details = IAVF_ADMINQ_DETAILS(*asq, ntc); ··· 573 573 desc_cb = *desc; 574 574 cb_func(hw, &desc_cb); 575 575 } 576 576 - memset((void *)desc, 0, sizeof(struct iavf_aq_desc)); 576 576 + memset((void *)desc, 0, sizeof(struct libie_aq_desc)); 577 577 memset((void *)details, 0, 578 578 sizeof(struct iavf_asq_cmd_details)); 579 579 ntc++; ··· 615 615 * queue. It runs the queue, cleans the queue, etc 616 616 **/ 617 617 enum iavf_status iavf_asq_send_command(struct iavf_hw *hw, 618 618 - struct iavf_aq_desc *desc, 618 618 + struct libie_aq_desc *desc, 619 619 void *buff, /* can be NULL */ 620 620 u16 buff_size, 621 621 struct iavf_asq_cmd_details *cmd_details) 622 622 { 623 623 struct iavf_dma_mem *dma_buff = NULL; 624 624 struct iavf_asq_cmd_details *details; 625 625 - struct iavf_aq_desc *desc_on_ring; 625 625 + struct libie_aq_desc *desc_on_ring; 626 626 bool cmd_completed = false; 627 627 enum iavf_status status = 0; 628 628 u16 retval = 0; ··· 637 637 goto asq_send_command_error; 638 638 } 639 639 640 640 - hw->aq.asq_last_status = IAVF_AQ_RC_OK; 640 640 + hw->aq.asq_last_status = LIBIE_AQ_RC_OK; 641 641 642 642 val = rd32(hw, IAVF_VF_ATQH1); 643 643 if (val >= hw->aq.num_asq_entries) { ··· 717 717 /* Update the address values in the desc with the pa value 718 718 * for respective buffer 719 719 */ 720 720 - desc_on_ring->params.external.addr_high = 720 720 + desc_on_ring->params.generic.addr_high = 721 721 cpu_to_le32(upper_32_bits(dma_buff->pa)); 722 722 - desc_on_ring->params.external.addr_low = 722 722 + desc_on_ring->params.generic.addr_low = 723 723 cpu_to_le32(lower_32_bits(dma_buff->pa)); 724 724 } 725 725 ··· 766 766 retval &= 0xff; 767 767 } 768 768 cmd_completed = true; 769 769 - if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK) 769 769 + if ((enum libie_aq_err)retval == LIBIE_AQ_RC_OK) 770 770 status = 0; 771 771 - else if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY) 771 771 + else if ((enum libie_aq_err)retval == LIBIE_AQ_RC_EBUSY) 772 772 status = IAVF_ERR_NOT_READY; 773 773 else 774 774 status = IAVF_ERR_ADMIN_QUEUE_ERROR; 775 775 - hw->aq.asq_last_status = (enum iavf_admin_queue_err)retval; 775 775 + hw->aq.asq_last_status = (enum libie_aq_err)retval; 776 776 } 777 777 778 778 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, ··· 809 809 * 810 810 * Fill the desc with default values 811 811 **/ 812 812 - void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode) 812 812 + void iavf_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode) 813 813 { 814 814 /* zero out the desc */ 815 815 - memset((void *)desc, 0, sizeof(struct iavf_aq_desc)); 815 815 + memset((void *)desc, 0, sizeof(struct libie_aq_desc)); 816 816 desc->opcode = cpu_to_le16(opcode); 817 817 - desc->flags = cpu_to_le16(IAVF_AQ_FLAG_SI); 817 817 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 818 818 } 819 819 820 820 /** ··· 832 832 u16 *pending) 833 833 { 834 834 u16 ntc = hw->aq.arq.next_to_clean; 835 835 - struct iavf_aq_desc *desc; 835 835 + struct libie_aq_desc *desc; 836 836 enum iavf_status ret_code = 0; 837 837 struct iavf_dma_mem *bi; 838 838 u16 desc_idx; ··· 866 866 desc_idx = ntc; 867 867 868 868 hw->aq.arq_last_status = 869 869 - (enum iavf_admin_queue_err)le16_to_cpu(desc->retval); 869 869 + (enum libie_aq_err)le16_to_cpu(desc->retval); 870 870 flags = le16_to_cpu(desc->flags); 871 871 - if (flags & IAVF_AQ_FLAG_ERR) { 871 871 + if (flags & LIBIE_AQ_FLAG_ERR) { 872 872 ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR; 873 873 iavf_debug(hw, 874 874 IAVF_DEBUG_AQ_MESSAGE, ··· 892 892 * size 893 893 */ 894 894 bi = &hw->aq.arq.r.arq_bi[ntc]; 895 895 - memset((void *)desc, 0, sizeof(struct iavf_aq_desc)); 895 895 + memset((void *)desc, 0, sizeof(struct libie_aq_desc)); 896 896 897 897 - desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF); 897 897 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 898 898 if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF) 899 899 - desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB); 899 899 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 900 900 desc->datalen = cpu_to_le16((u16)bi->size); 901 901 - desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 902 902 - desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 901 901 + desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 902 902 + desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 903 903 904 904 /* set tail = the last cleaned desc index. */ 905 905 wr32(hw, IAVF_VF_ARQT1, ntc);

+6 -6

drivers/net/ethernet/intel/iavf/iavf_adminq.h

reviewed

··· 9 9 #include "iavf_adminq_cmd.h" 10 10 11 11 #define IAVF_ADMINQ_DESC(R, i) \ 12 12 - (&(((struct iavf_aq_desc *)((R).desc_buf.va))[i])) 12 12 + (&(((struct libie_aq_desc *)((R).desc_buf.va))[i])) 13 13 14 14 #define IAVF_ADMINQ_DESC_ALIGNMENT 4096 15 15 ··· 39 39 u16 flags_dis; 40 40 bool async; 41 41 bool postpone; 42 42 - struct iavf_aq_desc *wb_desc; 42 42 + struct libie_aq_desc *wb_desc; 43 43 }; 44 44 45 45 #define IAVF_ADMINQ_DETAILS(R, i) \ ··· 47 47 48 48 /* ARQ event information */ 49 49 struct iavf_arq_event_info { 50 50 - struct iavf_aq_desc desc; 50 50 + struct libie_aq_desc desc; 51 51 u16 msg_len; 52 52 u16 buf_len; 53 53 u8 *msg_buf; ··· 72 72 struct mutex arq_mutex; /* Receive queue lock */ 73 73 74 74 /* last status values on send and receive queues */ 75 75 - enum iavf_admin_queue_err asq_last_status; 76 76 - enum iavf_admin_queue_err arq_last_status; 75 75 + enum libie_aq_err asq_last_status; 76 76 + enum libie_aq_err arq_last_status; 77 77 }; 78 78 79 79 /** ··· 123 123 #define IAVF_AQ_LARGE_BUF 512 124 124 #define IAVF_ASQ_CMD_TIMEOUT 250000 /* usecs */ 125 125 126 126 - void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode); 126 126 + void iavf_fill_default_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode); 127 127 128 128 #endif /* _IAVF_ADMINQ_H_ */

+2 -81

drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h

reviewed

··· 4 4 #ifndef _IAVF_ADMINQ_CMD_H_ 5 5 #define _IAVF_ADMINQ_CMD_H_ 6 6 7 7 + #include <linux/net/intel/libie/adminq.h> 8 8 + 7 9 /* This header file defines the iavf Admin Queue commands and is shared between 8 10 * iavf Firmware and Software. 9 11 * ··· 22 20 23 21 /* API version 1.7 implements additional link and PHY-specific APIs */ 24 22 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007 25 25 - 26 26 - struct iavf_aq_desc { 27 27 - __le16 flags; 28 28 - __le16 opcode; 29 29 - __le16 datalen; 30 30 - __le16 retval; 31 31 - __le32 cookie_high; 32 32 - __le32 cookie_low; 33 33 - union { 34 34 - struct { 35 35 - __le32 param0; 36 36 - __le32 param1; 37 37 - __le32 param2; 38 38 - __le32 param3; 39 39 - } internal; 40 40 - struct { 41 41 - __le32 param0; 42 42 - __le32 param1; 43 43 - __le32 addr_high; 44 44 - __le32 addr_low; 45 45 - } external; 46 46 - u8 raw[16]; 47 47 - } params; 48 48 - }; 49 49 - 50 50 - /* Flags sub-structure 51 51 - * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 52 52 - * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 53 53 - */ 54 54 - 55 55 - /* command flags and offsets*/ 56 56 - #define IAVF_AQ_FLAG_DD_SHIFT 0 57 57 - #define IAVF_AQ_FLAG_CMP_SHIFT 1 58 58 - #define IAVF_AQ_FLAG_ERR_SHIFT 2 59 59 - #define IAVF_AQ_FLAG_VFE_SHIFT 3 60 60 - #define IAVF_AQ_FLAG_LB_SHIFT 9 61 61 - #define IAVF_AQ_FLAG_RD_SHIFT 10 62 62 - #define IAVF_AQ_FLAG_VFC_SHIFT 11 63 63 - #define IAVF_AQ_FLAG_BUF_SHIFT 12 64 64 - #define IAVF_AQ_FLAG_SI_SHIFT 13 65 65 - #define IAVF_AQ_FLAG_EI_SHIFT 14 66 66 - #define IAVF_AQ_FLAG_FE_SHIFT 15 67 67 - 68 68 - #define IAVF_AQ_FLAG_DD BIT(IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */ 69 69 - #define IAVF_AQ_FLAG_CMP BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 70 70 - #define IAVF_AQ_FLAG_ERR BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 71 71 - #define IAVF_AQ_FLAG_VFE BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 72 72 - #define IAVF_AQ_FLAG_LB BIT(IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */ 73 73 - #define IAVF_AQ_FLAG_RD BIT(IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */ 74 74 - #define IAVF_AQ_FLAG_VFC BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 75 75 - #define IAVF_AQ_FLAG_BUF BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 76 76 - #define IAVF_AQ_FLAG_SI BIT(IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 77 77 - #define IAVF_AQ_FLAG_EI BIT(IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 78 78 - #define IAVF_AQ_FLAG_FE BIT(IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 79 79 - 80 80 - /* error codes */ 81 81 - enum iavf_admin_queue_err { 82 82 - IAVF_AQ_RC_OK = 0, /* success */ 83 83 - IAVF_AQ_RC_EPERM = 1, /* Operation not permitted */ 84 84 - IAVF_AQ_RC_ENOENT = 2, /* No such element */ 85 85 - IAVF_AQ_RC_ESRCH = 3, /* Bad opcode */ 86 86 - IAVF_AQ_RC_EINTR = 4, /* operation interrupted */ 87 87 - IAVF_AQ_RC_EIO = 5, /* I/O error */ 88 88 - IAVF_AQ_RC_ENXIO = 6, /* No such resource */ 89 89 - IAVF_AQ_RC_E2BIG = 7, /* Arg too long */ 90 90 - IAVF_AQ_RC_EAGAIN = 8, /* Try again */ 91 91 - IAVF_AQ_RC_ENOMEM = 9, /* Out of memory */ 92 92 - IAVF_AQ_RC_EACCES = 10, /* Permission denied */ 93 93 - IAVF_AQ_RC_EFAULT = 11, /* Bad address */ 94 94 - IAVF_AQ_RC_EBUSY = 12, /* Device or resource busy */ 95 95 - IAVF_AQ_RC_EEXIST = 13, /* object already exists */ 96 96 - IAVF_AQ_RC_EINVAL = 14, /* Invalid argument */ 97 97 - IAVF_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 98 98 - IAVF_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 99 99 - IAVF_AQ_RC_ENOSYS = 17, /* Function not implemented */ 100 100 - IAVF_AQ_RC_ERANGE = 18, /* Parameter out of range */ 101 101 - IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 102 102 - IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 103 103 - IAVF_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 104 104 - IAVF_AQ_RC_EFBIG = 22, /* File too large */ 105 105 - }; 106 23 107 24 /* Admin Queue command opcodes */ 108 25 enum iavf_admin_queue_opc {

+26 -84

drivers/net/ethernet/intel/iavf/iavf_common.c

reviewed

··· 8 8 #include "iavf_prototype.h" 9 9 10 10 /** 11 11 - * iavf_aq_str - convert AQ err code to a string 12 12 - * @hw: pointer to the HW structure 13 13 - * @aq_err: the AQ error code to convert 14 14 - **/ 15 15 - const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err) 16 16 - { 17 17 - switch (aq_err) { 18 18 - case IAVF_AQ_RC_OK: 19 19 - return "OK"; 20 20 - case IAVF_AQ_RC_EPERM: 21 21 - return "IAVF_AQ_RC_EPERM"; 22 22 - case IAVF_AQ_RC_ENOENT: 23 23 - return "IAVF_AQ_RC_ENOENT"; 24 24 - case IAVF_AQ_RC_ESRCH: 25 25 - return "IAVF_AQ_RC_ESRCH"; 26 26 - case IAVF_AQ_RC_EINTR: 27 27 - return "IAVF_AQ_RC_EINTR"; 28 28 - case IAVF_AQ_RC_EIO: 29 29 - return "IAVF_AQ_RC_EIO"; 30 30 - case IAVF_AQ_RC_ENXIO: 31 31 - return "IAVF_AQ_RC_ENXIO"; 32 32 - case IAVF_AQ_RC_E2BIG: 33 33 - return "IAVF_AQ_RC_E2BIG"; 34 34 - case IAVF_AQ_RC_EAGAIN: 35 35 - return "IAVF_AQ_RC_EAGAIN"; 36 36 - case IAVF_AQ_RC_ENOMEM: 37 37 - return "IAVF_AQ_RC_ENOMEM"; 38 38 - case IAVF_AQ_RC_EACCES: 39 39 - return "IAVF_AQ_RC_EACCES"; 40 40 - case IAVF_AQ_RC_EFAULT: 41 41 - return "IAVF_AQ_RC_EFAULT"; 42 42 - case IAVF_AQ_RC_EBUSY: 43 43 - return "IAVF_AQ_RC_EBUSY"; 44 44 - case IAVF_AQ_RC_EEXIST: 45 45 - return "IAVF_AQ_RC_EEXIST"; 46 46 - case IAVF_AQ_RC_EINVAL: 47 47 - return "IAVF_AQ_RC_EINVAL"; 48 48 - case IAVF_AQ_RC_ENOTTY: 49 49 - return "IAVF_AQ_RC_ENOTTY"; 50 50 - case IAVF_AQ_RC_ENOSPC: 51 51 - return "IAVF_AQ_RC_ENOSPC"; 52 52 - case IAVF_AQ_RC_ENOSYS: 53 53 - return "IAVF_AQ_RC_ENOSYS"; 54 54 - case IAVF_AQ_RC_ERANGE: 55 55 - return "IAVF_AQ_RC_ERANGE"; 56 56 - case IAVF_AQ_RC_EFLUSHED: 57 57 - return "IAVF_AQ_RC_EFLUSHED"; 58 58 - case IAVF_AQ_RC_BAD_ADDR: 59 59 - return "IAVF_AQ_RC_BAD_ADDR"; 60 60 - case IAVF_AQ_RC_EMODE: 61 61 - return "IAVF_AQ_RC_EMODE"; 62 62 - case IAVF_AQ_RC_EFBIG: 63 63 - return "IAVF_AQ_RC_EFBIG"; 64 64 - } 65 65 - 66 66 - snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 67 67 - return hw->err_str; 68 68 - } 69 69 - 70 70 - /** 71 11 * iavf_stat_str - convert status err code to a string 72 12 * @hw: pointer to the HW structure 73 13 * @stat_err: the status error code to convert ··· 168 228 void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc, 169 229 void *buffer, u16 buf_len) 170 230 { 171 171 - struct iavf_aq_desc *aq_desc = (struct iavf_aq_desc *)desc; 231 231 + struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc; 172 232 u8 *buf = (u8 *)buffer; 173 233 174 234 if ((!(mask & hw->debug_mask)) || !desc) ··· 184 244 le32_to_cpu(aq_desc->cookie_high), 185 245 le32_to_cpu(aq_desc->cookie_low)); 186 246 iavf_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 187 187 - le32_to_cpu(aq_desc->params.internal.param0), 188 188 - le32_to_cpu(aq_desc->params.internal.param1)); 247 247 + le32_to_cpu(aq_desc->params.generic.param0), 248 248 + le32_to_cpu(aq_desc->params.generic.param1)); 189 249 iavf_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 190 190 - le32_to_cpu(aq_desc->params.external.addr_high), 191 191 - le32_to_cpu(aq_desc->params.external.addr_low)); 250 250 + le32_to_cpu(aq_desc->params.generic.addr_high), 251 251 + le32_to_cpu(aq_desc->params.generic.addr_low)); 192 252 193 253 if (buffer && aq_desc->datalen) { 194 254 u16 len = le16_to_cpu(aq_desc->datalen); ··· 237 297 **/ 238 298 enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading) 239 299 { 240 240 - struct iavf_aq_desc desc; 241 241 - struct iavf_aqc_queue_shutdown *cmd = 242 242 - (struct iavf_aqc_queue_shutdown *)&desc.params.raw; 300 300 + struct iavf_aqc_queue_shutdown *cmd; 301 301 + struct libie_aq_desc desc; 243 302 enum iavf_status status; 244 303 304 304 + cmd = libie_aq_raw(&desc); 245 305 iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_queue_shutdown); 246 306 247 307 if (unloading) ··· 267 327 u8 *lut, u16 lut_size, 268 328 bool set) 269 329 { 330 330 + struct iavf_aqc_get_set_rss_lut *cmd_resp; 331 331 + struct libie_aq_desc desc; 270 332 enum iavf_status status; 271 271 - struct iavf_aq_desc desc; 272 272 - struct iavf_aqc_get_set_rss_lut *cmd_resp = 273 273 - (struct iavf_aqc_get_set_rss_lut *)&desc.params.raw; 274 333 u16 flags; 334 334 + 335 335 + cmd_resp = libie_aq_raw(&desc); 275 336 276 337 if (set) 277 338 iavf_fill_default_direct_cmd_desc(&desc, ··· 282 341 iavf_aqc_opc_get_rss_lut); 283 342 284 343 /* Indirect command */ 285 285 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF); 286 286 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD); 344 344 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 345 345 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 287 346 288 347 vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 289 348 FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_VALID, 1); ··· 333 392 struct iavf_aqc_get_set_rss_key_data *key, 334 393 bool set) 335 394 { 336 336 - enum iavf_status status; 337 337 - struct iavf_aq_desc desc; 338 338 - struct iavf_aqc_get_set_rss_key *cmd_resp = 339 339 - (struct iavf_aqc_get_set_rss_key *)&desc.params.raw; 340 395 u16 key_size = sizeof(struct iavf_aqc_get_set_rss_key_data); 396 396 + struct iavf_aqc_get_set_rss_key *cmd_resp; 397 397 + struct libie_aq_desc desc; 398 398 + enum iavf_status status; 399 399 + 400 400 + cmd_resp = libie_aq_raw(&desc); 341 401 342 402 if (set) 343 403 iavf_fill_default_direct_cmd_desc(&desc, ··· 348 406 iavf_aqc_opc_get_rss_key); 349 407 350 408 /* Indirect command */ 351 351 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF); 352 352 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD); 409 409 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 410 410 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 353 411 354 412 vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 355 413 FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_VALID, 1); ··· 394 452 struct iavf_asq_cmd_details *cmd_details) 395 453 { 396 454 struct iavf_asq_cmd_details details; 397 397 - struct iavf_aq_desc desc; 455 455 + struct libie_aq_desc desc; 398 456 enum iavf_status status; 399 457 400 458 iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_send_msg_to_pf); 401 401 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_SI); 459 459 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI); 402 460 desc.cookie_high = cpu_to_le32(v_opcode); 403 461 desc.cookie_low = cpu_to_le32(v_retval); 404 462 if (msglen) { 405 405 - desc.flags |= cpu_to_le16((u16)(IAVF_AQ_FLAG_BUF 406 406 - | IAVF_AQ_FLAG_RD)); 463 463 + desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF 464 464 + | LIBIE_AQ_FLAG_RD)); 407 465 if (msglen > IAVF_AQ_LARGE_BUF) 408 408 - desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_LB); 466 466 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 409 467 desc.datalen = cpu_to_le16(msglen); 410 468 } 411 469 if (!cmd_details) {

+3 -2

drivers/net/ethernet/intel/iavf/iavf_main.c

reviewed

··· 50 50 MODULE_DESCRIPTION("Intel(R) Ethernet Adaptive Virtual Function Network Driver"); 51 51 MODULE_IMPORT_NS("LIBETH"); 52 52 MODULE_IMPORT_NS("LIBIE"); 53 53 + MODULE_IMPORT_NS("LIBIE_ADMINQ"); 53 54 MODULE_LICENSE("GPL v2"); 54 55 55 56 static const struct net_device_ops iavf_netdev_ops; ··· 1695 1694 if (status) { 1696 1695 dev_err(&adapter->pdev->dev, "Cannot set RSS key, err %s aq_err %s\n", 1697 1696 iavf_stat_str(hw, status), 1698 1698 - iavf_aq_str(hw, hw->aq.asq_last_status)); 1697 1697 + libie_aq_str(hw->aq.asq_last_status)); 1699 1698 return iavf_status_to_errno(status); 1700 1699 1701 1700 } ··· 1705 1704 if (status) { 1706 1705 dev_err(&adapter->pdev->dev, "Cannot set RSS lut, err %s aq_err %s\n", 1707 1706 iavf_stat_str(hw, status), 1708 1708 - iavf_aq_str(hw, hw->aq.asq_last_status)); 1707 1707 + libie_aq_str(hw->aq.asq_last_status)); 1709 1708 return iavf_status_to_errno(status); 1710 1709 } 1711 1710

+1 -2

drivers/net/ethernet/intel/iavf/iavf_prototype.h

reviewed

··· 22 22 struct iavf_arq_event_info *e, 23 23 u16 *events_pending); 24 24 enum iavf_status iavf_asq_send_command(struct iavf_hw *hw, 25 25 - struct iavf_aq_desc *desc, 25 25 + struct libie_aq_desc *desc, 26 26 void *buff, /* can be NULL */ 27 27 u16 buff_size, 28 28 struct iavf_asq_cmd_details *cmd_details); ··· 34 34 35 35 bool iavf_check_asq_alive(struct iavf_hw *hw); 36 36 enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading); 37 37 - const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err); 38 37 const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err); 39 38 40 39 enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,

+1 -1

drivers/net/ethernet/intel/iavf/iavf_type.h

reviewed

··· 19 19 20 20 /* forward declaration */ 21 21 struct iavf_hw; 22 22 - typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 22 22 + typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct libie_aq_desc *); 23 23 24 24 /* Data type manipulation macros. */ 25 25

+1 -1

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

reviewed

··· 29 29 if (status) 30 30 dev_dbg(&adapter->pdev->dev, "Unable to send opcode %d to PF, status %s, aq_err %s\n", 31 31 op, iavf_stat_str(hw, status), 32 32 - iavf_aq_str(hw, hw->aq.asq_last_status)); 32 32 + libie_aq_str(hw->aq.asq_last_status)); 33 33 return iavf_status_to_errno(status); 34 34 } 35 35

+5 -5

drivers/net/ethernet/intel/ice/devlink/devlink.c

reviewed

··· 293 293 err = ice_discover_dev_caps(hw, &ctx->dev_caps); 294 294 if (err) { 295 295 dev_dbg(dev, "Failed to discover device capabilities, status %d aq_err %s\n", 296 296 - err, ice_aq_str(hw->adminq.sq_last_status)); 296 296 + err, libie_aq_str(hw->adminq.sq_last_status)); 297 297 NL_SET_ERR_MSG_MOD(extack, "Unable to discover device capabilities"); 298 298 goto out_free_ctx; 299 299 } ··· 302 302 err = ice_get_inactive_orom_ver(hw, &ctx->pending_orom); 303 303 if (err) { 304 304 dev_dbg(dev, "Unable to read inactive Option ROM version data, status %d aq_err %s\n", 305 305 - err, ice_aq_str(hw->adminq.sq_last_status)); 305 305 + err, libie_aq_str(hw->adminq.sq_last_status)); 306 306 307 307 /* disable display of pending Option ROM */ 308 308 ctx->dev_caps.common_cap.nvm_update_pending_orom = false; ··· 313 313 err = ice_get_inactive_nvm_ver(hw, &ctx->pending_nvm); 314 314 if (err) { 315 315 dev_dbg(dev, "Unable to read inactive NVM version data, status %d aq_err %s\n", 316 316 - err, ice_aq_str(hw->adminq.sq_last_status)); 316 316 + err, libie_aq_str(hw->adminq.sq_last_status)); 317 317 318 318 /* disable display of pending Option ROM */ 319 319 ctx->dev_caps.common_cap.nvm_update_pending_nvm = false; ··· 324 324 err = ice_get_inactive_netlist_ver(hw, &ctx->pending_netlist); 325 325 if (err) { 326 326 dev_dbg(dev, "Unable to read inactive Netlist version data, status %d aq_err %s\n", 327 327 - err, ice_aq_str(hw->adminq.sq_last_status)); 327 327 + err, libie_aq_str(hw->adminq.sq_last_status)); 328 328 329 329 /* disable display of pending Option ROM */ 330 330 ctx->dev_caps.common_cap.nvm_update_pending_netlist = false; ··· 440 440 err = ice_aq_nvm_update_empr(hw); 441 441 if (err) { 442 442 dev_err(dev, "Failed to trigger EMP device reset to reload firmware, err %d aq_err %s\n", 443 443 - err, ice_aq_str(hw->adminq.sq_last_status)); 443 443 + err, libie_aq_str(hw->adminq.sq_last_status)); 444 444 NL_SET_ERR_MSG_MOD(extack, "Failed to trigger EMP device reset to reload firmware"); 445 445 return err; 446 446 }

+4 -2

drivers/net/ethernet/intel/ice/devlink/health.c

reviewed

··· 204 204 if (ret) 205 205 dev_err(ice_pf_to_dev(pf), "Failed to %s firmware health events, err %d aq_err %s\n", 206 206 str_enable_disable(enable), ret, 207 207 - ice_aq_str(pf->hw.adminq.sq_last_status)); 207 207 + libie_aq_str(pf->hw.adminq.sq_last_status)); 208 208 } 209 209 210 210 /** ··· 217 217 void ice_process_health_status_event(struct ice_pf *pf, struct ice_rq_event_info *event) 218 218 { 219 219 const struct ice_aqc_health_status_elem *health_info; 220 220 + const struct ice_aqc_get_health_status *cmd; 220 221 u16 count; 221 222 222 223 health_info = (struct ice_aqc_health_status_elem *)event->msg_buf; 223 223 - count = le16_to_cpu(event->desc.params.get_health_status.health_status_count); 224 224 + cmd = libie_aq_raw(&event->desc); 225 225 + count = le16_to_cpu(cmd->health_status_count); 224 226 225 227 if (count > (event->buf_len / sizeof(*health_info))) { 226 228 dev_err(ice_pf_to_dev(pf), "Received a health status event with invalid element count\n");

-1

drivers/net/ethernet/intel/ice/ice.h

reviewed

··· 960 960 void ice_unplug_aux_dev(struct ice_pf *pf); 961 961 int ice_init_rdma(struct ice_pf *pf); 962 962 void ice_deinit_rdma(struct ice_pf *pf); 963 963 - const char *ice_aq_str(enum ice_aq_err aq_err); 964 963 bool ice_is_wol_supported(struct ice_hw *hw); 965 964 void ice_fdir_del_all_fltrs(struct ice_vsi *vsi); 966 965 int

+2 -268

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

reviewed

··· 4 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 5 #define _ICE_ADMINQ_CMD_H_ 6 6 7 7 + #include <linux/net/intel/libie/adminq.h> 8 8 + 7 9 /* This header file defines the Admin Queue commands, error codes and 8 10 * descriptor format. It is shared between Firmware and Software. 9 11 */ ··· 33 31 34 32 typedef struct __packed { u8 buf[ICE_TXQ_CTX_FULL_SZ]; } ice_txq_ctx_buf_full_t; 35 33 36 36 - struct ice_aqc_generic { 37 37 - __le32 param0; 38 38 - __le32 param1; 39 39 - __le32 addr_high; 40 40 - __le32 addr_low; 41 41 - }; 42 42 - 43 43 - /* Get version (direct 0x0001) */ 44 44 - struct ice_aqc_get_ver { 45 45 - __le32 rom_ver; 46 46 - __le32 fw_build; 47 47 - u8 fw_branch; 48 48 - u8 fw_major; 49 49 - u8 fw_minor; 50 50 - u8 fw_patch; 51 51 - u8 api_branch; 52 52 - u8 api_major; 53 53 - u8 api_minor; 54 54 - u8 api_patch; 55 55 - }; 56 56 - 57 57 - /* Send driver version (indirect 0x0002) */ 58 58 - struct ice_aqc_driver_ver { 59 59 - u8 major_ver; 60 60 - u8 minor_ver; 61 61 - u8 build_ver; 62 62 - u8 subbuild_ver; 63 63 - u8 reserved[4]; 64 64 - __le32 addr_high; 65 65 - __le32 addr_low; 66 66 - }; 67 67 - 68 34 /* Queue Shutdown (direct 0x0003) */ 69 35 struct ice_aqc_q_shutdown { 70 36 u8 driver_unloading; 71 37 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 72 38 u8 reserved[15]; 73 73 - }; 74 74 - 75 75 - /* Request resource ownership (direct 0x0008) 76 76 - * Release resource ownership (direct 0x0009) 77 77 - */ 78 78 - struct ice_aqc_req_res { 79 79 - __le16 res_id; 80 80 - #define ICE_AQC_RES_ID_NVM 1 81 81 - #define ICE_AQC_RES_ID_SDP 2 82 82 - #define ICE_AQC_RES_ID_CHNG_LOCK 3 83 83 - #define ICE_AQC_RES_ID_GLBL_LOCK 4 84 84 - __le16 access_type; 85 85 - #define ICE_AQC_RES_ACCESS_READ 1 86 86 - #define ICE_AQC_RES_ACCESS_WRITE 2 87 87 - 88 88 - /* Upon successful completion, FW writes this value and driver is 89 89 - * expected to release resource before timeout. This value is provided 90 90 - * in milliseconds. 91 91 - */ 92 92 - __le32 timeout; 93 93 - #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 94 94 - #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 95 95 - #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 96 96 - #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 97 97 - /* For SDP: pin ID of the SDP */ 98 98 - __le32 res_number; 99 99 - /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 100 100 - __le16 status; 101 101 - #define ICE_AQ_RES_GLBL_SUCCESS 0 102 102 - #define ICE_AQ_RES_GLBL_IN_PROG 1 103 103 - #define ICE_AQ_RES_GLBL_DONE 2 104 104 - u8 reserved[2]; 105 105 - }; 106 106 - 107 107 - /* Get function capabilities (indirect 0x000A) 108 108 - * Get device capabilities (indirect 0x000B) 109 109 - */ 110 110 - struct ice_aqc_list_caps { 111 111 - u8 cmd_flags; 112 112 - u8 pf_index; 113 113 - u8 reserved[2]; 114 114 - __le32 count; 115 115 - __le32 addr_high; 116 116 - __le32 addr_low; 117 117 - }; 118 118 - 119 119 - /* Device/Function buffer entry, repeated per reported capability */ 120 120 - struct ice_aqc_list_caps_elem { 121 121 - __le16 cap; 122 122 - #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 123 123 - #define ICE_AQC_CAPS_SRIOV 0x0012 124 124 - #define ICE_AQC_CAPS_VF 0x0013 125 125 - #define ICE_AQC_CAPS_VSI 0x0017 126 126 - #define ICE_AQC_CAPS_DCB 0x0018 127 127 - #define ICE_AQC_CAPS_RSS 0x0040 128 128 - #define ICE_AQC_CAPS_RXQS 0x0041 129 129 - #define ICE_AQC_CAPS_TXQS 0x0042 130 130 - #define ICE_AQC_CAPS_MSIX 0x0043 131 131 - #define ICE_AQC_CAPS_FD 0x0045 132 132 - #define ICE_AQC_CAPS_1588 0x0046 133 133 - #define ICE_AQC_CAPS_MAX_MTU 0x0047 134 134 - #define ICE_AQC_CAPS_NVM_VER 0x0048 135 135 - #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 136 136 - #define ICE_AQC_CAPS_OROM_VER 0x004A 137 137 - #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 138 138 - #define ICE_AQC_CAPS_NET_VER 0x004C 139 139 - #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 140 140 - #define ICE_AQC_CAPS_RDMA 0x0051 141 141 - #define ICE_AQC_CAPS_SENSOR_READING 0x0067 142 142 - #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 143 143 - #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 144 144 - #define ICE_AQC_CAPS_NVM_MGMT 0x0080 145 145 - #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 146 146 - #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 147 147 - #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 148 148 - #define ICE_AQC_BIT_ROCEV2_LAG 0x01 149 149 - #define ICE_AQC_BIT_SRIOV_LAG 0x02 150 150 - 151 151 - u8 major_ver; 152 152 - u8 minor_ver; 153 153 - /* Number of resources described by this capability */ 154 154 - __le32 number; 155 155 - /* Only meaningful for some types of resources */ 156 156 - __le32 logical_id; 157 157 - /* Only meaningful for some types of resources */ 158 158 - __le32 phys_id; 159 159 - __le64 rsvd1; 160 160 - __le64 rsvd2; 161 39 }; 162 40 163 41 /* Manage MAC address, read command - indirect (0x0107) ··· 2552 2670 __le16 module_identifier; 2553 2671 u8 log_level; 2554 2672 u8 rsvd0; 2555 2555 - }; 2556 2556 - 2557 2557 - /** 2558 2558 - * struct ice_aq_desc - Admin Queue (AQ) descriptor 2559 2559 - * @flags: ICE_AQ_FLAG_* flags 2560 2560 - * @opcode: AQ command opcode 2561 2561 - * @datalen: length in bytes of indirect/external data buffer 2562 2562 - * @retval: return value from firmware 2563 2563 - * @cookie_high: opaque data high-half 2564 2564 - * @cookie_low: opaque data low-half 2565 2565 - * @params: command-specific parameters 2566 2566 - * 2567 2567 - * Descriptor format for commands the driver posts on the Admin Transmit Queue 2568 2568 - * (ATQ). The firmware writes back onto the command descriptor and returns 2569 2569 - * the result of the command. Asynchronous events that are not an immediate 2570 2570 - * result of the command are written to the Admin Receive Queue (ARQ) using 2571 2571 - * the same descriptor format. Descriptors are in little-endian notation with 2572 2572 - * 32-bit words. 2573 2573 - */ 2574 2574 - struct ice_aq_desc { 2575 2575 - __le16 flags; 2576 2576 - __le16 opcode; 2577 2577 - __le16 datalen; 2578 2578 - __le16 retval; 2579 2579 - __le32 cookie_high; 2580 2580 - __le32 cookie_low; 2581 2581 - union { 2582 2582 - u8 raw[16]; 2583 2583 - struct ice_aqc_generic generic; 2584 2584 - struct ice_aqc_get_ver get_ver; 2585 2585 - struct ice_aqc_driver_ver driver_ver; 2586 2586 - struct ice_aqc_q_shutdown q_shutdown; 2587 2587 - struct ice_aqc_req_res res_owner; 2588 2588 - struct ice_aqc_manage_mac_read mac_read; 2589 2589 - struct ice_aqc_manage_mac_write mac_write; 2590 2590 - struct ice_aqc_clear_pxe clear_pxe; 2591 2591 - struct ice_aqc_list_caps get_cap; 2592 2592 - struct ice_aqc_get_phy_caps get_phy; 2593 2593 - struct ice_aqc_set_phy_cfg set_phy; 2594 2594 - struct ice_aqc_restart_an restart_an; 2595 2595 - struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out; 2596 2596 - struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out; 2597 2597 - struct ice_aqc_get_sensor_reading get_sensor_reading; 2598 2598 - struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 2599 2599 - struct ice_aqc_gpio read_write_gpio; 2600 2600 - struct ice_aqc_sff_eeprom read_write_sff_param; 2601 2601 - struct ice_aqc_set_port_id_led set_port_id_led; 2602 2602 - struct ice_aqc_get_port_options get_port_options; 2603 2603 - struct ice_aqc_set_port_option set_port_option; 2604 2604 - struct ice_aqc_get_sw_cfg get_sw_conf; 2605 2605 - struct ice_aqc_set_port_params set_port_params; 2606 2606 - struct ice_aqc_sw_rules sw_rules; 2607 2607 - struct ice_aqc_add_get_recipe add_get_recipe; 2608 2608 - struct ice_aqc_recipe_to_profile recipe_to_profile; 2609 2609 - struct ice_aqc_get_topo get_topo; 2610 2610 - struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2611 2611 - struct ice_aqc_query_txsched_res query_sched_res; 2612 2612 - struct ice_aqc_query_port_ets port_ets; 2613 2613 - struct ice_aqc_rl_profile rl_profile; 2614 2614 - struct ice_aqc_nvm nvm; 2615 2615 - struct ice_aqc_nvm_checksum nvm_checksum; 2616 2616 - struct ice_aqc_nvm_pkg_data pkg_data; 2617 2617 - struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2618 2618 - struct ice_aqc_pf_vf_msg virt; 2619 2619 - struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2620 2620 - struct ice_aqc_lldp_get_mib lldp_get_mib; 2621 2621 - struct ice_aqc_lldp_set_mib_change lldp_set_event; 2622 2622 - struct ice_aqc_lldp_stop lldp_stop; 2623 2623 - struct ice_aqc_lldp_start lldp_start; 2624 2624 - struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2625 2625 - struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2626 2626 - struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2627 2627 - struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2628 2628 - struct ice_aqc_get_set_rss_key get_set_rss_key; 2629 2629 - struct ice_aqc_neigh_dev_req neigh_dev; 2630 2630 - struct ice_aqc_add_txqs add_txqs; 2631 2631 - struct ice_aqc_dis_txqs dis_txqs; 2632 2632 - struct ice_aqc_cfg_txqs cfg_txqs; 2633 2633 - struct ice_aqc_add_rdma_qset add_rdma_qset; 2634 2634 - struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2635 2635 - struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2636 2636 - struct ice_aqc_download_pkg download_pkg; 2637 2637 - struct ice_aqc_get_cgu_input_measure get_cgu_input_measure; 2638 2638 - struct ice_aqc_set_cgu_input_config set_cgu_input_config; 2639 2639 - struct ice_aqc_get_cgu_input_config get_cgu_input_config; 2640 2640 - struct ice_aqc_set_cgu_output_config set_cgu_output_config; 2641 2641 - struct ice_aqc_get_cgu_output_config get_cgu_output_config; 2642 2642 - struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status; 2643 2643 - struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config; 2644 2644 - struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio; 2645 2645 - struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio; 2646 2646 - struct ice_aqc_get_cgu_info get_cgu_info; 2647 2647 - struct ice_aqc_driver_shared_params drv_shared_params; 2648 2648 - struct ice_aqc_fw_log fw_log; 2649 2649 - struct ice_aqc_set_mac_lb set_mac_lb; 2650 2650 - struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2651 2651 - struct ice_aqc_set_mac_cfg set_mac_cfg; 2652 2652 - struct ice_aqc_set_event_mask set_event_mask; 2653 2653 - struct ice_aqc_get_link_status get_link_status; 2654 2654 - struct ice_aqc_event_lan_overflow lan_overflow; 2655 2655 - struct ice_aqc_get_link_topo get_link_topo; 2656 2656 - struct ice_aqc_set_health_status_cfg set_health_status_cfg; 2657 2657 - struct ice_aqc_get_health_status get_health_status; 2658 2658 - struct ice_aqc_dnl_call_command dnl_call; 2659 2659 - struct ice_aqc_i2c read_write_i2c; 2660 2660 - struct ice_aqc_read_i2c_resp read_i2c_resp; 2661 2661 - struct ice_aqc_get_set_tx_topo get_set_tx_topo; 2662 2662 - } params; 2663 2663 - }; 2664 2664 - 2665 2665 - /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2666 2666 - #define ICE_AQ_LG_BUF 512 2667 2667 - 2668 2668 - #define ICE_AQ_FLAG_DD_S 0 2669 2669 - #define ICE_AQ_FLAG_CMP_S 1 2670 2670 - #define ICE_AQ_FLAG_ERR_S 2 2671 2671 - #define ICE_AQ_FLAG_LB_S 9 2672 2672 - #define ICE_AQ_FLAG_RD_S 10 2673 2673 - #define ICE_AQ_FLAG_BUF_S 12 2674 2674 - #define ICE_AQ_FLAG_SI_S 13 2675 2675 - 2676 2676 - #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2677 2677 - #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2678 2678 - #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2679 2679 - #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2680 2680 - #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2681 2681 - #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2682 2682 - #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2683 2683 - 2684 2684 - /* error codes */ 2685 2685 - enum ice_aq_err { 2686 2686 - ICE_AQ_RC_OK = 0, /* Success */ 2687 2687 - ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2688 2688 - ICE_AQ_RC_ENOENT = 2, /* No such element */ 2689 2689 - ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2690 2690 - ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2691 2691 - ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2692 2692 - ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2693 2693 - ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2694 2694 - ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2695 2695 - ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2696 2696 - ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2697 2697 - ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2698 2698 - ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2699 2699 - ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2700 2700 - ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2701 2701 - ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2702 2702 - ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2703 2673 }; 2704 2674 2705 2675 /* Admin Queue command opcodes */

+194 -190

drivers/net/ethernet/intel/ice/ice_common.c

reviewed

··· 248 248 */ 249 249 int ice_clear_pf_cfg(struct ice_hw *hw) 250 250 { 251 251 - struct ice_aq_desc desc; 251 251 + struct libie_aq_desc desc; 252 252 253 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 254 ··· 276 276 { 277 277 struct ice_aqc_manage_mac_read_resp *resp; 278 278 struct ice_aqc_manage_mac_read *cmd; 279 279 - struct ice_aq_desc desc; 279 279 + struct libie_aq_desc desc; 280 280 int status; 281 281 u16 flags; 282 282 u8 i; 283 283 284 284 - cmd = &desc.params.mac_read; 284 284 + cmd = libie_aq_raw(&desc); 285 285 286 286 if (buf_size < sizeof(*resp)) 287 287 return -EINVAL; ··· 330 330 { 331 331 struct ice_aqc_get_phy_caps *cmd; 332 332 u16 pcaps_size = sizeof(*pcaps); 333 333 - struct ice_aq_desc desc; 333 333 + struct libie_aq_desc desc; 334 334 const char *prefix; 335 335 struct ice_hw *hw; 336 336 int status; 337 337 338 338 - cmd = &desc.params.get_phy; 338 338 + cmd = libie_aq_raw(&desc); 339 339 340 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 341 return -EINVAL; ··· 424 424 struct ice_sq_cd *cd) 425 425 { 426 426 struct ice_aqc_get_link_topo *cmd; 427 427 - struct ice_aq_desc desc; 427 427 + struct libie_aq_desc desc; 428 428 429 429 - cmd = &desc.params.get_link_topo; 429 429 + cmd = libie_aq_raw(&desc); 430 430 431 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 432 ··· 454 454 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 455 u8 *node_part_number, u16 *node_handle) 456 456 { 457 457 - struct ice_aq_desc desc; 457 457 + struct ice_aqc_get_link_topo *resp; 458 458 + struct libie_aq_desc desc; 458 459 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 460 460 - desc.params.get_link_topo = *cmd; 461 461 + resp = libie_aq_raw(&desc); 462 462 + *resp = *cmd; 461 463 462 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 463 465 return -EINTR; 464 466 465 467 if (node_handle) 466 466 - *node_handle = 467 467 - le16_to_cpu(desc.params.get_link_topo.addr.handle); 468 468 + *node_handle = le16_to_cpu(resp->addr.handle); 468 469 if (node_part_number) 469 469 - *node_part_number = desc.params.get_link_topo.node_part_num; 470 470 + *node_part_number = resp->node_part_num; 470 471 471 472 return 0; 472 473 } ··· 690 689 struct ice_link_status *li_old, *li; 691 690 enum ice_media_type *hw_media_type; 692 691 struct ice_fc_info *hw_fc_info; 692 692 + struct libie_aq_desc desc; 693 693 bool tx_pause, rx_pause; 694 694 - struct ice_aq_desc desc; 695 694 struct ice_hw *hw; 696 695 u16 cmd_flags; 697 696 int status; ··· 706 705 707 706 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 707 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 709 - resp = &desc.params.get_link_status; 708 708 + resp = libie_aq_raw(&desc); 710 709 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 710 resp->lport_num = pi->lport; 712 711 ··· 835 834 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836 835 { 837 836 struct ice_aqc_set_mac_cfg *cmd; 838 838 - struct ice_aq_desc desc; 837 837 + struct libie_aq_desc desc; 839 838 840 840 - cmd = &desc.params.set_mac_cfg; 839 839 + cmd = libie_aq_raw(&desc); 841 840 842 841 if (max_frame_size == 0) 843 842 return -EINVAL; ··· 1708 1707 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1709 1708 { 1710 1709 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1711 1711 - (struct ice_aq_desc *)desc, buf, buf_size, cd); 1710 1710 + (struct libie_aq_desc *)desc, buf, buf_size, cd); 1712 1711 } 1713 1712 1714 1713 /** ··· 1793 1792 */ 1794 1793 static int 1795 1794 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1796 1796 - struct ice_aq_desc *desc, void *buf, u16 buf_size, 1795 1795 + struct libie_aq_desc *desc, void *buf, u16 buf_size, 1797 1796 struct ice_sq_cd *cd) 1798 1797 { 1799 1799 - struct ice_aq_desc desc_cpy; 1798 1798 + struct libie_aq_desc desc_cpy; 1800 1799 bool is_cmd_for_retry; 1801 1800 u8 idx = 0; 1802 1801 u16 opcode; ··· 1817 1816 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1818 1817 1819 1818 if (!is_cmd_for_retry || !status || 1820 1820 - hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1819 1819 + hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1821 1820 break; 1822 1821 1823 1822 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); ··· 1840 1839 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1841 1840 */ 1842 1841 int 1843 1843 - ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1842 1842 + ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1844 1843 u16 buf_size, struct ice_sq_cd *cd) 1845 1844 { 1846 1846 - struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1845 1845 + struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1847 1846 bool lock_acquired = false; 1848 1847 int status; 1849 1848 ··· 1874 1873 case ice_aqc_opc_get_recipe_to_profile: 1875 1874 break; 1876 1875 case ice_aqc_opc_release_res: 1877 1877 - if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1876 1876 + if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1878 1877 break; 1879 1878 fallthrough; 1880 1879 default: ··· 1899 1898 */ 1900 1899 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1901 1900 { 1902 1902 - struct ice_aqc_get_ver *resp; 1903 1903 - struct ice_aq_desc desc; 1901 1901 + struct libie_aqc_get_ver *resp; 1902 1902 + struct libie_aq_desc desc; 1904 1903 int status; 1905 1904 1906 1905 resp = &desc.params.get_ver; ··· 1936 1935 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1937 1936 struct ice_sq_cd *cd) 1938 1937 { 1939 1939 - struct ice_aqc_driver_ver *cmd; 1940 1940 - struct ice_aq_desc desc; 1938 1938 + struct libie_aqc_driver_ver *cmd; 1939 1939 + struct libie_aq_desc desc; 1941 1940 u16 len; 1942 1941 1943 1942 cmd = &desc.params.driver_ver; ··· 1947 1946 1948 1947 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1949 1948 1950 1950 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1949 1949 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1951 1950 cmd->major_ver = dv->major_ver; 1952 1951 cmd->minor_ver = dv->minor_ver; 1953 1952 cmd->build_ver = dv->build_ver; ··· 1972 1971 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1973 1972 { 1974 1973 struct ice_aqc_q_shutdown *cmd; 1975 1975 - struct ice_aq_desc desc; 1974 1974 + struct libie_aq_desc desc; 1976 1975 1977 1977 - cmd = &desc.params.q_shutdown; 1976 1976 + cmd = libie_aq_raw(&desc); 1978 1977 1979 1978 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1980 1979 ··· 2015 2014 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2016 2015 struct ice_sq_cd *cd) 2017 2016 { 2018 2018 - struct ice_aqc_req_res *cmd_resp; 2019 2019 - struct ice_aq_desc desc; 2017 2017 + struct libie_aqc_req_res *cmd_resp; 2018 2018 + struct libie_aq_desc desc; 2020 2019 int status; 2021 2020 2022 2021 cmd_resp = &desc.params.res_owner; ··· 2038 2037 /* Global config lock response utilizes an additional status field. 2039 2038 * 2040 2039 * If the Global config lock resource is held by some other driver, the 2041 2041 - * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 2040 2040 + * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2042 2041 * and the timeout field indicates the maximum time the current owner 2043 2042 * of the resource has to free it. 2044 2043 */ 2045 2044 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2046 2046 - if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 2045 2045 + if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2047 2046 *timeout = le32_to_cpu(cmd_resp->timeout); 2048 2047 return 0; 2049 2048 } else if (le16_to_cpu(cmd_resp->status) == 2050 2050 - ICE_AQ_RES_GLBL_IN_PROG) { 2049 2049 + LIBIE_AQ_RES_GLBL_IN_PROG) { 2051 2050 *timeout = le32_to_cpu(cmd_resp->timeout); 2052 2051 return -EIO; 2053 2052 } else if (le16_to_cpu(cmd_resp->status) == 2054 2054 - ICE_AQ_RES_GLBL_DONE) { 2053 2053 + LIBIE_AQ_RES_GLBL_DONE) { 2055 2054 return -EALREADY; 2056 2055 } 2057 2056 ··· 2064 2063 * with a busy return value and the timeout field indicates the maximum 2065 2064 * time the current owner of the resource has to free it. 2066 2065 */ 2067 2067 - if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 2066 2066 + if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2068 2067 *timeout = le32_to_cpu(cmd_resp->timeout); 2069 2068 2070 2069 return status; ··· 2083 2082 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2084 2083 struct ice_sq_cd *cd) 2085 2084 { 2086 2086 - struct ice_aqc_req_res *cmd; 2087 2087 - struct ice_aq_desc desc; 2085 2085 + struct libie_aqc_req_res *cmd; 2086 2086 + struct libie_aq_desc desc; 2088 2087 2089 2088 cmd = &desc.params.res_owner; 2090 2089 ··· 2193 2192 enum ice_adminq_opc opc) 2194 2193 { 2195 2194 struct ice_aqc_alloc_free_res_cmd *cmd; 2196 2196 - struct ice_aq_desc desc; 2195 2195 + struct libie_aq_desc desc; 2197 2196 2198 2198 - cmd = &desc.params.sw_res_ctrl; 2197 2197 + cmd = libie_aq_raw(&desc); 2199 2198 2200 2199 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2201 2200 return -EINVAL; 2202 2201 2203 2202 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2204 2203 2205 2205 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2204 2204 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2206 2205 2207 2206 cmd->num_entries = cpu_to_le16(1); 2208 2207 ··· 2316 2315 */ 2317 2316 static bool 2318 2317 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2319 2319 - struct ice_aqc_list_caps_elem *elem, const char *prefix) 2318 2318 + struct libie_aqc_list_caps_elem *elem, const char *prefix) 2320 2319 { 2321 2320 u32 logical_id = le32_to_cpu(elem->logical_id); 2322 2321 u32 phys_id = le32_to_cpu(elem->phys_id); ··· 2325 2324 bool found = true; 2326 2325 2327 2326 switch (cap) { 2328 2328 - case ICE_AQC_CAPS_VALID_FUNCTIONS: 2327 2327 + case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2329 2328 caps->valid_functions = number; 2330 2329 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2331 2330 caps->valid_functions); 2332 2331 break; 2333 2333 - case ICE_AQC_CAPS_SRIOV: 2332 2332 + case LIBIE_AQC_CAPS_SRIOV: 2334 2333 caps->sr_iov_1_1 = (number == 1); 2335 2334 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2336 2335 caps->sr_iov_1_1); 2337 2336 break; 2338 2338 - case ICE_AQC_CAPS_DCB: 2337 2337 + case LIBIE_AQC_CAPS_DCB: 2339 2338 caps->dcb = (number == 1); 2340 2339 caps->active_tc_bitmap = logical_id; 2341 2340 caps->maxtc = phys_id; ··· 2344 2343 caps->active_tc_bitmap); 2345 2344 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2346 2345 break; 2347 2347 - case ICE_AQC_CAPS_RSS: 2346 2346 + case LIBIE_AQC_CAPS_RSS: 2348 2347 caps->rss_table_size = number; 2349 2348 caps->rss_table_entry_width = logical_id; 2350 2349 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, ··· 2352 2351 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2353 2352 caps->rss_table_entry_width); 2354 2353 break; 2355 2355 - case ICE_AQC_CAPS_RXQS: 2354 2354 + case LIBIE_AQC_CAPS_RXQS: 2356 2355 caps->num_rxq = number; 2357 2356 caps->rxq_first_id = phys_id; 2358 2357 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, ··· 2360 2359 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2361 2360 caps->rxq_first_id); 2362 2361 break; 2363 2363 - case ICE_AQC_CAPS_TXQS: 2362 2362 + case LIBIE_AQC_CAPS_TXQS: 2364 2363 caps->num_txq = number; 2365 2364 caps->txq_first_id = phys_id; 2366 2365 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, ··· 2368 2367 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2369 2368 caps->txq_first_id); 2370 2369 break; 2371 2371 - case ICE_AQC_CAPS_MSIX: 2370 2370 + case LIBIE_AQC_CAPS_MSIX: 2372 2371 caps->num_msix_vectors = number; 2373 2372 caps->msix_vector_first_id = phys_id; 2374 2373 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, ··· 2376 2375 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2377 2376 caps->msix_vector_first_id); 2378 2377 break; 2379 2379 - case ICE_AQC_CAPS_PENDING_NVM_VER: 2378 2378 + case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2380 2379 caps->nvm_update_pending_nvm = true; 2381 2380 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2382 2381 break; 2383 2383 - case ICE_AQC_CAPS_PENDING_OROM_VER: 2382 2382 + case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2384 2383 caps->nvm_update_pending_orom = true; 2385 2384 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2386 2385 break; 2387 2387 - case ICE_AQC_CAPS_PENDING_NET_VER: 2386 2386 + case LIBIE_AQC_CAPS_PENDING_NET_VER: 2388 2387 caps->nvm_update_pending_netlist = true; 2389 2388 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2390 2389 break; 2391 2391 - case ICE_AQC_CAPS_NVM_MGMT: 2390 2390 + case LIBIE_AQC_CAPS_NVM_MGMT: 2392 2391 caps->nvm_unified_update = 2393 2392 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2394 2393 true : false; 2395 2394 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2396 2395 caps->nvm_unified_update); 2397 2396 break; 2398 2398 - case ICE_AQC_CAPS_RDMA: 2397 2397 + case LIBIE_AQC_CAPS_RDMA: 2399 2398 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2400 2399 caps->rdma = (number == 1); 2401 2400 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2402 2401 break; 2403 2403 - case ICE_AQC_CAPS_MAX_MTU: 2402 2402 + case LIBIE_AQC_CAPS_MAX_MTU: 2404 2403 caps->max_mtu = number; 2405 2404 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2406 2405 prefix, caps->max_mtu); 2407 2406 break; 2408 2408 - case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2407 2407 + case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2409 2408 caps->pcie_reset_avoidance = (number > 0); 2410 2409 ice_debug(hw, ICE_DBG_INIT, 2411 2410 "%s: pcie_reset_avoidance = %d\n", prefix, 2412 2411 caps->pcie_reset_avoidance); 2413 2412 break; 2414 2414 - case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2413 2413 + case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2415 2414 caps->reset_restrict_support = (number == 1); 2416 2415 ice_debug(hw, ICE_DBG_INIT, 2417 2416 "%s: reset_restrict_support = %d\n", prefix, 2418 2417 caps->reset_restrict_support); 2419 2418 break; 2420 2420 - case ICE_AQC_CAPS_FW_LAG_SUPPORT: 2421 2421 - caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); 2419 2419 + case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2420 2420 + caps->roce_lag = !!(number & LIBIE_AQC_BIT_ROCEV2_LAG); 2422 2421 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2423 2422 prefix, caps->roce_lag); 2424 2424 - caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); 2423 2423 + caps->sriov_lag = !!(number & LIBIE_AQC_BIT_SRIOV_LAG); 2425 2424 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2426 2425 prefix, caps->sriov_lag); 2427 2426 break; 2428 2428 - case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2427 2427 + case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2429 2428 caps->tx_sched_topo_comp_mode_en = (number == 1); 2430 2429 break; 2431 2430 default: ··· 2479 2478 */ 2480 2479 static void 2481 2480 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2482 2482 - struct ice_aqc_list_caps_elem *cap) 2481 2481 + struct libie_aqc_list_caps_elem *cap) 2483 2482 { 2484 2483 u32 logical_id = le32_to_cpu(cap->logical_id); 2485 2484 u32 number = le32_to_cpu(cap->number); ··· 2502 2501 */ 2503 2502 static void 2504 2503 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2505 2505 - struct ice_aqc_list_caps_elem *cap) 2504 2504 + struct libie_aqc_list_caps_elem *cap) 2506 2505 { 2507 2506 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2508 2507 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", ··· 2521 2520 */ 2522 2521 static void 2523 2522 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2524 2524 - struct ice_aqc_list_caps_elem *cap) 2523 2523 + struct libie_aqc_list_caps_elem *cap) 2525 2524 { 2526 2525 struct ice_ts_func_info *info = &func_p->ts_func_info; 2527 2526 u32 number = le32_to_cpu(cap->number); ··· 2620 2619 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2621 2620 void *buf, u32 cap_count) 2622 2621 { 2623 2623 - struct ice_aqc_list_caps_elem *cap_resp; 2622 2622 + struct libie_aqc_list_caps_elem *cap_resp; 2624 2623 u32 i; 2625 2624 2626 2625 cap_resp = buf; ··· 2635 2634 &cap_resp[i], "func caps"); 2636 2635 2637 2636 switch (cap) { 2638 2638 - case ICE_AQC_CAPS_VF: 2637 2637 + case LIBIE_AQC_CAPS_VF: 2639 2638 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2640 2639 break; 2641 2641 - case ICE_AQC_CAPS_VSI: 2640 2640 + case LIBIE_AQC_CAPS_VSI: 2642 2641 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2643 2642 break; 2644 2644 - case ICE_AQC_CAPS_1588: 2643 2643 + case LIBIE_AQC_CAPS_1588: 2645 2644 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2646 2645 break; 2647 2647 - case ICE_AQC_CAPS_FD: 2646 2646 + case LIBIE_AQC_CAPS_FD: 2648 2647 ice_parse_fdir_func_caps(hw, func_p); 2649 2648 break; 2650 2649 default: ··· 2688 2687 */ 2689 2688 static void 2690 2689 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2691 2691 - struct ice_aqc_list_caps_elem *cap) 2690 2690 + struct libie_aqc_list_caps_elem *cap) 2692 2691 { 2693 2692 u32 number = le32_to_cpu(cap->number); 2694 2693 ··· 2709 2708 */ 2710 2709 static void 2711 2710 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2712 2712 - struct ice_aqc_list_caps_elem *cap) 2711 2711 + struct libie_aqc_list_caps_elem *cap) 2713 2712 { 2714 2713 u32 number = le32_to_cpu(cap->number); 2715 2714 ··· 2728 2727 */ 2729 2728 static void 2730 2729 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2731 2731 - struct ice_aqc_list_caps_elem *cap) 2730 2730 + struct libie_aqc_list_caps_elem *cap) 2732 2731 { 2733 2732 u32 number = le32_to_cpu(cap->number); 2734 2733 ··· 2747 2746 */ 2748 2747 static void 2749 2748 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2750 2750 - struct ice_aqc_list_caps_elem *cap) 2749 2749 + struct libie_aqc_list_caps_elem *cap) 2751 2750 { 2752 2751 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2753 2752 u32 logical_id = le32_to_cpu(cap->logical_id); ··· 2808 2807 */ 2809 2808 static void 2810 2809 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2811 2811 - struct ice_aqc_list_caps_elem *cap) 2810 2810 + struct libie_aqc_list_caps_elem *cap) 2812 2811 { 2813 2812 u32 number = le32_to_cpu(cap->number); 2814 2813 ··· 2828 2827 */ 2829 2828 static void 2830 2829 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2831 2831 - struct ice_aqc_list_caps_elem *cap) 2830 2830 + struct libie_aqc_list_caps_elem *cap) 2832 2831 { 2833 2832 dev_p->supported_sensors = le32_to_cpu(cap->number); 2834 2833 ··· 2847 2846 */ 2848 2847 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2849 2848 struct ice_hw_dev_caps *dev_p, 2850 2850 - struct ice_aqc_list_caps_elem *cap) 2849 2849 + struct libie_aqc_list_caps_elem *cap) 2851 2850 { 2852 2851 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2853 2852 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; ··· 2883 2882 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2884 2883 void *buf, u32 cap_count) 2885 2884 { 2886 2886 - struct ice_aqc_list_caps_elem *cap_resp; 2885 2885 + struct libie_aqc_list_caps_elem *cap_resp; 2887 2886 u32 i; 2888 2887 2889 2888 cap_resp = buf; ··· 2898 2897 &cap_resp[i], "dev caps"); 2899 2898 2900 2899 switch (cap) { 2901 2901 - case ICE_AQC_CAPS_VALID_FUNCTIONS: 2900 2900 + case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2902 2901 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2903 2902 break; 2904 2904 - case ICE_AQC_CAPS_VF: 2903 2903 + case LIBIE_AQC_CAPS_VF: 2905 2904 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2906 2905 break; 2907 2907 - case ICE_AQC_CAPS_VSI: 2906 2906 + case LIBIE_AQC_CAPS_VSI: 2908 2907 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2909 2908 break; 2910 2910 - case ICE_AQC_CAPS_1588: 2909 2909 + case LIBIE_AQC_CAPS_1588: 2911 2910 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2912 2911 break; 2913 2913 - case ICE_AQC_CAPS_FD: 2912 2912 + case LIBIE_AQC_CAPS_FD: 2914 2913 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2915 2914 break; 2916 2916 - case ICE_AQC_CAPS_SENSOR_READING: 2915 2915 + case LIBIE_AQC_CAPS_SENSOR_READING: 2917 2916 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2918 2917 break; 2919 2919 - case ICE_AQC_CAPS_NAC_TOPOLOGY: 2918 2918 + case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2920 2919 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2921 2920 break; 2922 2921 default: ··· 3036 3035 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3037 3036 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3038 3037 { 3039 3039 - struct ice_aqc_list_caps *cmd; 3040 3040 - struct ice_aq_desc desc; 3038 3038 + struct libie_aqc_list_caps *cmd; 3039 3039 + struct libie_aq_desc desc; 3041 3040 int status; 3042 3041 3043 3042 cmd = &desc.params.get_cap; ··· 3078 3077 * device will return, we can simply send a 4KB buffer, the maximum 3079 3078 * possible size that firmware can return. 3080 3079 */ 3081 3081 - cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3080 3080 + cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3082 3081 3083 3082 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3084 3083 ice_aqc_opc_list_dev_caps, NULL); ··· 3112 3111 * device will return, we can simply send a 4KB buffer, the maximum 3113 3112 * possible size that firmware can return. 3114 3113 */ 3115 3115 - cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 3114 3114 + cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3116 3115 3117 3116 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3118 3117 ice_aqc_opc_list_func_caps, NULL); ··· 3221 3220 struct ice_sq_cd *cd) 3222 3221 { 3223 3222 struct ice_aqc_manage_mac_write *cmd; 3224 3224 - struct ice_aq_desc desc; 3223 3223 + struct libie_aq_desc desc; 3225 3224 3226 3226 - cmd = &desc.params.mac_write; 3225 3225 + cmd = libie_aq_raw(&desc); 3227 3226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3228 3227 3229 3228 cmd->flags = flags; ··· 3240 3239 */ 3241 3240 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3242 3241 { 3243 3243 - struct ice_aq_desc desc; 3242 3242 + struct ice_aqc_clear_pxe *cmd; 3243 3243 + struct libie_aq_desc desc; 3244 3244 3245 3245 + cmd = libie_aq_raw(&desc); 3245 3246 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3246 3246 - desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3247 3247 + cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3247 3248 3248 3249 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3249 3250 } ··· 3278 3275 { 3279 3276 struct ice_aqc_set_port_params *cmd; 3280 3277 struct ice_hw *hw = pi->hw; 3281 3281 - struct ice_aq_desc desc; 3278 3278 + struct libie_aq_desc desc; 3282 3279 u16 cmd_flags = 0; 3283 3280 3284 3284 - cmd = &desc.params.set_port_params; 3281 3281 + cmd = libie_aq_raw(&desc); 3285 3282 3286 3283 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3287 3284 if (double_vlan) ··· 3518 3515 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3519 3516 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3520 3517 { 3521 3521 - struct ice_aq_desc desc; 3518 3518 + struct ice_aqc_set_phy_cfg *cmd; 3519 3519 + struct libie_aq_desc desc; 3522 3520 int status; 3523 3521 3524 3522 if (!cfg) ··· 3534 3530 } 3535 3531 3536 3532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3537 3537 - desc.params.set_phy.lport_num = pi->lport; 3538 3538 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3533 3533 + cmd = libie_aq_raw(&desc); 3534 3534 + cmd->lport_num = pi->lport; 3535 3535 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3539 3536 3540 3537 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3541 3538 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", ··· 3552 3547 cfg->link_fec_opt); 3553 3548 3554 3549 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3555 3555 - if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3550 3550 + if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3556 3551 status = 0; 3557 3552 3558 3553 if (!status) ··· 3609 3604 { 3610 3605 struct ice_aqc_dnl_call_command *cmd; 3611 3606 struct ice_aqc_dnl_call buf = {}; 3612 3612 - struct ice_aq_desc desc; 3607 3607 + struct libie_aq_desc desc; 3613 3608 int err; 3614 3609 3615 3610 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3616 3611 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3617 3612 cpu_to_le16(op_code | (serdes_num & 0xF)); 3618 3618 - cmd = &desc.params.dnl_call; 3613 3613 + cmd = libie_aq_raw(&desc); 3619 3614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3620 3620 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF | 3621 3621 - ICE_AQ_FLAG_RD | 3622 3622 - ICE_AQ_FLAG_SI); 3615 3615 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3616 3616 + LIBIE_AQ_FLAG_RD | 3617 3617 + LIBIE_AQ_FLAG_SI); 3623 3618 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3624 3619 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3625 3620 ··· 3657 3652 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3658 3653 enum ice_fec_stats_types fec_type, u32 *output) 3659 3654 { 3660 3660 - u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI); 3655 3655 + u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3661 3656 struct ice_sbq_msg_input msg = {}; 3662 3657 u32 receiver_id, reg_offset; 3663 3658 int err; ··· 4080 4075 struct ice_sq_cd *cd) 4081 4076 { 4082 4077 struct ice_aqc_restart_an *cmd; 4083 4083 - struct ice_aq_desc desc; 4078 4078 + struct libie_aq_desc desc; 4084 4079 4085 4085 - cmd = &desc.params.restart_an; 4080 4080 + cmd = libie_aq_raw(&desc); 4086 4081 4087 4082 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4088 4083 ··· 4110 4105 struct ice_sq_cd *cd) 4111 4106 { 4112 4107 struct ice_aqc_set_event_mask *cmd; 4113 4113 - struct ice_aq_desc desc; 4108 4108 + struct libie_aq_desc desc; 4114 4109 4115 4115 - cmd = &desc.params.set_event_mask; 4110 4110 + cmd = libie_aq_raw(&desc); 4116 4111 4117 4112 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4118 4113 ··· 4134 4129 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4135 4130 { 4136 4131 struct ice_aqc_set_mac_lb *cmd; 4137 4137 - struct ice_aq_desc desc; 4132 4132 + struct libie_aq_desc desc; 4138 4133 4139 4139 - cmd = &desc.params.set_mac_lb; 4134 4134 + cmd = libie_aq_raw(&desc); 4140 4135 4141 4136 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4142 4137 if (ena_lpbk) ··· 4159 4154 { 4160 4155 struct ice_aqc_set_port_id_led *cmd; 4161 4156 struct ice_hw *hw = pi->hw; 4162 4162 - struct ice_aq_desc desc; 4157 4157 + struct libie_aq_desc desc; 4163 4158 4164 4164 - cmd = &desc.params.set_port_id_led; 4159 4159 + cmd = libie_aq_raw(&desc); 4165 4160 4166 4161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4167 4162 ··· 4197 4192 u8 *pending_option_idx, bool *pending_option_valid) 4198 4193 { 4199 4194 struct ice_aqc_get_port_options *cmd; 4200 4200 - struct ice_aq_desc desc; 4195 4195 + struct libie_aq_desc desc; 4201 4196 int status; 4202 4197 u8 i; 4203 4198 ··· 4205 4200 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4206 4201 return -EINVAL; 4207 4202 4208 4208 - cmd = &desc.params.get_port_options; 4203 4203 + cmd = libie_aq_raw(&desc); 4209 4204 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4210 4205 4211 4206 if (lport_valid) ··· 4271 4266 u8 new_option) 4272 4267 { 4273 4268 struct ice_aqc_set_port_option *cmd; 4274 4274 - struct ice_aq_desc desc; 4269 4269 + struct libie_aq_desc desc; 4275 4270 4276 4271 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4277 4272 return -EINVAL; 4278 4273 4279 4279 - cmd = &desc.params.set_port_option; 4274 4274 + cmd = libie_aq_raw(&desc); 4280 4275 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4281 4276 4282 4277 if (lport_valid) ··· 4362 4357 bool write, struct ice_sq_cd *cd) 4363 4358 { 4364 4359 struct ice_aqc_sff_eeprom *cmd; 4365 4365 - struct ice_aq_desc desc; 4360 4360 + struct libie_aq_desc desc; 4366 4361 u16 i2c_bus_addr; 4367 4362 int status; 4368 4363 ··· 4370 4365 return -EINVAL; 4371 4366 4372 4367 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4373 4373 - cmd = &desc.params.read_write_sff_param; 4374 4374 - desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 4368 4368 + cmd = libie_aq_raw(&desc); 4369 4369 + desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4375 4370 cmd->lport_num = (u8)(lport & 0xff); 4376 4371 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4377 4372 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | ··· 4431 4426 struct ice_aqc_get_set_rss_lut *desc_params; 4432 4427 enum ice_aqc_lut_flags flags; 4433 4428 enum ice_lut_size lut_size; 4434 4434 - struct ice_aq_desc desc; 4429 4429 + struct libie_aq_desc desc; 4435 4430 u8 *lut = params->lut; 4436 4431 4437 4432 ··· 4447 4442 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4448 4443 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4449 4444 if (set) 4450 4450 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4445 4445 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4451 4446 4452 4452 - desc_params = &desc.params.get_set_rss_lut; 4447 4447 + desc_params = libie_aq_raw(&desc); 4453 4448 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4454 4449 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4455 4450 ··· 4504 4499 { 4505 4500 struct ice_aqc_get_set_rss_key *desc_params; 4506 4501 u16 key_size = sizeof(*key); 4507 4507 - struct ice_aq_desc desc; 4502 4502 + struct libie_aq_desc desc; 4508 4503 4509 4504 if (set) { 4510 4505 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4511 4511 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4506 4506 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4512 4507 } else { 4513 4508 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4514 4509 } 4515 4510 4516 4516 - desc_params = &desc.params.get_set_rss_key; 4511 4511 + desc_params = libie_aq_raw(&desc); 4517 4512 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4518 4513 4519 4514 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); ··· 4585 4580 { 4586 4581 struct ice_aqc_add_tx_qgrp *list; 4587 4582 struct ice_aqc_add_txqs *cmd; 4588 4588 - struct ice_aq_desc desc; 4583 4583 + struct libie_aq_desc desc; 4589 4584 u16 i, sum_size = 0; 4590 4585 4591 4591 - cmd = &desc.params.add_txqs; 4586 4586 + cmd = libie_aq_raw(&desc); 4592 4587 4593 4588 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4594 4589 ··· 4607 4602 if (buf_size != sum_size) 4608 4603 return -EINVAL; 4609 4604 4610 4610 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4605 4605 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4611 4606 4612 4607 cmd->num_qgrps = num_qgrps; 4613 4608 ··· 4634 4629 { 4635 4630 struct ice_aqc_dis_txq_item *item; 4636 4631 struct ice_aqc_dis_txqs *cmd; 4637 4637 - struct ice_aq_desc desc; 4632 4632 + struct libie_aq_desc desc; 4638 4633 u16 vmvf_and_timeout; 4639 4634 u16 i, sz = 0; 4640 4635 int status; 4641 4636 4642 4642 - cmd = &desc.params.dis_txqs; 4637 4637 + cmd = libie_aq_raw(&desc); 4643 4638 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4644 4639 4645 4640 /* qg_list can be NULL only in VM/VF reset flow */ ··· 4680 4675 /* set RD bit to indicate that command buffer is provided by the driver 4681 4676 * and it needs to be read by the firmware 4682 4677 */ 4683 4683 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4678 4678 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4684 4679 4685 4680 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4686 4681 u16 item_size = struct_size(item, q_id, item->num_qs); ··· 4732 4727 struct ice_sq_cd *cd) 4733 4728 { 4734 4729 struct ice_aqc_cfg_txqs *cmd; 4735 4735 - struct ice_aq_desc desc; 4730 4730 + struct libie_aq_desc desc; 4736 4731 int status; 4737 4732 4738 4738 - cmd = &desc.params.cfg_txqs; 4733 4733 + cmd = libie_aq_raw(&desc); 4739 4734 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4740 4740 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4735 4735 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4741 4736 4742 4737 if (!buf) 4743 4738 return -EINVAL; ··· 4773 4768 { 4774 4769 struct ice_aqc_add_rdma_qset_data *list; 4775 4770 struct ice_aqc_add_rdma_qset *cmd; 4776 4776 - struct ice_aq_desc desc; 4771 4771 + struct libie_aq_desc desc; 4777 4772 u16 i, sum_size = 0; 4778 4773 4779 4779 - cmd = &desc.params.add_rdma_qset; 4774 4774 + cmd = libie_aq_raw(&desc); 4780 4775 4781 4776 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4782 4777 ··· 4794 4789 if (buf_size != sum_size) 4795 4790 return -EINVAL; 4796 4791 4797 4797 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4792 4792 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4798 4793 4799 4794 cmd->num_qset_grps = num_qset_grps; 4800 4795 ··· 5228 5223 u16 meas_num) 5229 5224 { 5230 5225 struct ice_aqc_get_cgu_input_measure *cmd; 5231 5231 - struct ice_aq_desc desc; 5226 5226 + struct libie_aq_desc desc; 5232 5227 5233 5228 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5234 5234 - cmd = &desc.params.get_cgu_input_measure; 5229 5229 + cmd = libie_aq_raw(&desc); 5235 5230 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5236 5231 5237 5232 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); ··· 5249 5244 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5250 5245 struct ice_aqc_get_cgu_abilities *abilities) 5251 5246 { 5252 5252 - struct ice_aq_desc desc; 5247 5247 + struct libie_aq_desc desc; 5253 5248 5254 5249 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5255 5250 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); ··· 5272 5267 u32 freq, s32 phase_delay) 5273 5268 { 5274 5269 struct ice_aqc_set_cgu_input_config *cmd; 5275 5275 - struct ice_aq_desc desc; 5270 5270 + struct libie_aq_desc desc; 5276 5271 5277 5272 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5278 5278 - cmd = &desc.params.set_cgu_input_config; 5273 5273 + cmd = libie_aq_raw(&desc); 5279 5274 cmd->input_idx = input_idx; 5280 5275 cmd->flags1 = flags1; 5281 5276 cmd->flags2 = flags2; ··· 5304 5299 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5305 5300 { 5306 5301 struct ice_aqc_get_cgu_input_config *cmd; 5307 5307 - struct ice_aq_desc desc; 5302 5302 + struct libie_aq_desc desc; 5308 5303 int ret; 5309 5304 5310 5305 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5311 5311 - cmd = &desc.params.get_cgu_input_config; 5306 5306 + cmd = libie_aq_raw(&desc); 5312 5307 cmd->input_idx = input_idx; 5313 5308 5314 5309 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); ··· 5347 5342 u8 src_sel, u32 freq, s32 phase_delay) 5348 5343 { 5349 5344 struct ice_aqc_set_cgu_output_config *cmd; 5350 5350 - struct ice_aq_desc desc; 5345 5345 + struct libie_aq_desc desc; 5351 5346 5352 5347 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5353 5353 - cmd = &desc.params.set_cgu_output_config; 5348 5348 + cmd = libie_aq_raw(&desc); 5354 5349 cmd->output_idx = output_idx; 5355 5350 cmd->flags = flags; 5356 5351 cmd->src_sel = src_sel; ··· 5377 5372 u8 *src_sel, u32 *freq, u32 *src_freq) 5378 5373 { 5379 5374 struct ice_aqc_get_cgu_output_config *cmd; 5380 5380 - struct ice_aq_desc desc; 5375 5375 + struct libie_aq_desc desc; 5381 5376 int ret; 5382 5377 5383 5378 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5384 5384 - cmd = &desc.params.get_cgu_output_config; 5379 5379 + cmd = libie_aq_raw(&desc); 5385 5380 cmd->output_idx = output_idx; 5386 5381 5387 5382 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); ··· 5418 5413 u8 *eec_mode) 5419 5414 { 5420 5415 struct ice_aqc_get_cgu_dpll_status *cmd; 5421 5421 - struct ice_aq_desc desc; 5416 5416 + struct libie_aq_desc desc; 5422 5417 int status; 5423 5418 5424 5419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5425 5425 - cmd = &desc.params.get_cgu_dpll_status; 5420 5420 + cmd = libie_aq_raw(&desc); 5426 5421 cmd->dpll_num = dpll_num; 5427 5422 5428 5423 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); ··· 5456 5451 u8 config, u8 eec_mode) 5457 5452 { 5458 5453 struct ice_aqc_set_cgu_dpll_config *cmd; 5459 5459 - struct ice_aq_desc desc; 5454 5454 + struct libie_aq_desc desc; 5460 5455 5461 5456 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5462 5462 - cmd = &desc.params.set_cgu_dpll_config; 5457 5457 + cmd = libie_aq_raw(&desc); 5463 5458 cmd->dpll_num = dpll_num; 5464 5459 cmd->ref_state = ref_state; 5465 5460 cmd->config = config; ··· 5483 5478 u8 ref_priority) 5484 5479 { 5485 5480 struct ice_aqc_set_cgu_ref_prio *cmd; 5486 5486 - struct ice_aq_desc desc; 5481 5481 + struct libie_aq_desc desc; 5487 5482 5488 5483 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5489 5489 - cmd = &desc.params.set_cgu_ref_prio; 5484 5484 + cmd = libie_aq_raw(&desc); 5490 5485 cmd->dpll_num = dpll_num; 5491 5486 cmd->ref_idx = ref_idx; 5492 5487 cmd->ref_priority = ref_priority; ··· 5509 5504 u8 *ref_prio) 5510 5505 { 5511 5506 struct ice_aqc_get_cgu_ref_prio *cmd; 5512 5512 - struct ice_aq_desc desc; 5507 5507 + struct libie_aq_desc desc; 5513 5508 int status; 5514 5509 5515 5510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5516 5516 - cmd = &desc.params.get_cgu_ref_prio; 5511 5511 + cmd = libie_aq_raw(&desc); 5517 5512 cmd->dpll_num = dpll_num; 5518 5513 cmd->ref_idx = ref_idx; 5519 5514 ··· 5539 5534 u32 *cgu_fw_ver) 5540 5535 { 5541 5536 struct ice_aqc_get_cgu_info *cmd; 5542 5542 - struct ice_aq_desc desc; 5537 5537 + struct libie_aq_desc desc; 5543 5538 int status; 5544 5539 5545 5540 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5546 5546 - cmd = &desc.params.get_cgu_info; 5541 5541 + cmd = libie_aq_raw(&desc); 5547 5542 5548 5543 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5549 5544 if (!status) { ··· 5570 5565 u32 *freq) 5571 5566 { 5572 5567 struct ice_aqc_set_phy_rec_clk_out *cmd; 5573 5573 - struct ice_aq_desc desc; 5568 5568 + struct libie_aq_desc desc; 5574 5569 int status; 5575 5570 5576 5571 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5577 5577 - cmd = &desc.params.set_phy_rec_clk_out; 5572 5572 + cmd = libie_aq_raw(&desc); 5578 5573 cmd->phy_output = phy_output; 5579 5574 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5580 5575 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; ··· 5603 5598 u8 *flags, u16 *node_handle) 5604 5599 { 5605 5600 struct ice_aqc_get_phy_rec_clk_out *cmd; 5606 5606 - struct ice_aq_desc desc; 5601 5601 + struct libie_aq_desc desc; 5607 5602 int status; 5608 5603 5609 5604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5610 5610 - cmd = &desc.params.get_phy_rec_clk_out; 5605 5605 + cmd = libie_aq_raw(&desc); 5611 5606 cmd->phy_output = *phy_output; 5612 5607 5613 5608 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); ··· 5635 5630 struct ice_aqc_get_sensor_reading_resp *data) 5636 5631 { 5637 5632 struct ice_aqc_get_sensor_reading *cmd; 5638 5638 - struct ice_aq_desc desc; 5633 5633 + struct libie_aq_desc desc; 5639 5634 int status; 5640 5635 5641 5636 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5642 5642 - cmd = &desc.params.get_sensor_reading; 5637 5637 + cmd = libie_aq_raw(&desc); 5643 5638 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5644 5639 #define ICE_INTERNAL_TEMP_SENSOR 0 5645 5640 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; ··· 5647 5642 5648 5643 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5649 5644 if (!status) 5650 5650 - memcpy(data, &desc.params.get_sensor_reading_resp, 5645 5645 + memcpy(data, &desc.params.raw, 5651 5646 sizeof(*data)); 5652 5647 5653 5648 return status; ··· 5844 5839 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5845 5840 struct ice_sq_cd *cd) 5846 5841 { 5847 5847 - struct ice_aq_desc desc = { 0 }; 5842 5842 + struct libie_aq_desc desc = { 0 }; 5848 5843 struct ice_aqc_i2c *cmd; 5849 5844 u8 data_size; 5850 5845 int status; 5851 5846 5852 5847 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5853 5853 - cmd = &desc.params.read_write_i2c; 5848 5848 + cmd = libie_aq_raw(&desc); 5854 5849 5855 5850 if (!data) 5856 5851 return -EINVAL; ··· 5867 5862 struct ice_aqc_read_i2c_resp *resp; 5868 5863 u8 i; 5869 5864 5870 5870 - resp = &desc.params.read_i2c_resp; 5865 5865 + resp = libie_aq_raw(&desc); 5871 5866 for (i = 0; i < data_size; i++) { 5872 5867 *data = resp->i2c_data[i]; 5873 5868 data++; ··· 5899 5894 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 5900 5895 struct ice_sq_cd *cd) 5901 5896 { 5902 5902 - struct ice_aq_desc desc = { 0 }; 5897 5897 + struct libie_aq_desc desc = { 0 }; 5903 5898 struct ice_aqc_i2c *cmd; 5904 5899 u8 data_size; 5905 5900 5906 5901 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5907 5907 - cmd = &desc.params.read_write_i2c; 5902 5902 + cmd = libie_aq_raw(&desc); 5908 5903 5909 5904 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5910 5905 ··· 5936 5931 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5937 5932 { 5938 5933 struct ice_aqc_get_link_topo *cmd; 5939 5939 - struct ice_aq_desc desc; 5934 5934 + struct libie_aq_desc desc; 5940 5935 int err; 5941 5936 u8 idx; 5942 5937 ··· 5959 5954 5960 5955 /* If handle was not detected read it from the netlist */ 5961 5956 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5962 5962 - cmd = &desc.params.get_link_topo; 5957 5957 + cmd = libie_aq_raw(&desc); 5963 5958 cmd->addr.topo_params.node_type_ctx = 5964 5959 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 5965 5960 cmd->addr.topo_params.index = idx; ··· 5969 5964 return -ENXIO; 5970 5965 5971 5966 /* Verify if we found the right IO expander type */ 5972 5972 - if (desc.params.get_link_topo.node_part_num != 5973 5973 - ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5967 5967 + if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5974 5968 return -ENXIO; 5975 5969 5976 5970 /* If present save the handle and return it */ 5977 5971 hw->io_expander_handle = 5978 5978 - le16_to_cpu(desc.params.get_link_topo.addr.handle); 5972 5972 + le16_to_cpu(cmd->addr.handle); 5979 5973 *pca9575_handle = hw->io_expander_handle; 5980 5974 5981 5975 return 0; ··· 6025 6021 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6026 6022 struct ice_sq_cd *cd) 6027 6023 { 6024 6024 + struct libie_aq_desc desc; 6028 6025 struct ice_aqc_gpio *cmd; 6029 6029 - struct ice_aq_desc desc; 6030 6026 6031 6027 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6032 6032 - cmd = &desc.params.read_write_gpio; 6028 6028 + cmd = libie_aq_raw(&desc); 6033 6029 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6034 6030 cmd->gpio_num = pin_idx; 6035 6031 cmd->gpio_val = value ? 1 : 0; ··· 6052 6048 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6053 6049 bool *value, struct ice_sq_cd *cd) 6054 6050 { 6051 6051 + struct libie_aq_desc desc; 6055 6052 struct ice_aqc_gpio *cmd; 6056 6056 - struct ice_aq_desc desc; 6057 6053 int status; 6058 6054 6059 6055 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6060 6060 - cmd = &desc.params.read_write_gpio; 6056 6056 + cmd = libie_aq_raw(&desc); 6061 6057 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6062 6058 cmd->gpio_num = pin_idx; 6063 6059 ··· 6220 6216 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6221 6217 { 6222 6218 struct ice_aqc_set_health_status_cfg *cmd; 6223 6223 - struct ice_aq_desc desc; 6219 6219 + struct libie_aq_desc desc; 6224 6220 6225 6225 - cmd = &desc.params.set_health_status_cfg; 6221 6221 + cmd = libie_aq_raw(&desc); 6226 6222 6227 6223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6228 6224 ··· 6246 6242 struct ice_sq_cd *cd) 6247 6243 { 6248 6244 struct ice_aqc_lldp_set_local_mib *cmd; 6249 6249 - struct ice_aq_desc desc; 6245 6245 + struct libie_aq_desc desc; 6250 6246 6251 6251 - cmd = &desc.params.lldp_set_mib; 6247 6247 + cmd = libie_aq_raw(&desc); 6252 6248 6253 6249 if (buf_size == 0 || !buf) 6254 6250 return -EINVAL; 6255 6251 6256 6252 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6257 6253 6258 6258 - desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 6254 6254 + desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6259 6255 desc.datalen = cpu_to_le16(buf_size); 6260 6256 6261 6257 cmd->type = mib_type; ··· 6291 6287 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6292 6288 { 6293 6289 struct ice_aqc_lldp_filter_ctrl *cmd; 6294 6294 - struct ice_aq_desc desc; 6290 6290 + struct libie_aq_desc desc; 6295 6291 6296 6292 if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) 6297 6293 return -EOPNOTSUPP; 6298 6294 6299 6299 - cmd = &desc.params.lldp_filter_ctrl; 6295 6295 + cmd = libie_aq_raw(&desc); 6300 6296 6301 6297 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6302 6298 ··· 6316 6312 */ 6317 6313 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6318 6314 { 6319 6319 - struct ice_aq_desc desc; 6315 6315 + struct libie_aq_desc desc; 6320 6316 6321 6317 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6322 6318 ··· 6393 6389 }; 6394 6390 int err; 6395 6391 6396 6396 - err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6392 6392 + err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6397 6393 if (err) { 6398 6394 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6399 6395 addr, err); ··· 6426 6422 }; 6427 6423 int err; 6428 6424 6429 6429 - err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 6425 6425 + err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6430 6426 if (err) 6431 6427 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6432 6428 addr, err);

+3 -3

drivers/net/ethernet/intel/ice/ice_common.h

reviewed

··· 109 109 struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw); 110 110 int 111 111 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 112 112 - struct ice_aq_desc *desc, void *buf, u16 buf_size, 112 112 + struct libie_aq_desc *desc, void *buf, u16 buf_size, 113 113 struct ice_sq_cd *cd); 114 114 void ice_clear_pxe_mode(struct ice_hw *hw); 115 115 int ice_get_caps(struct ice_hw *hw); ··· 138 138 139 139 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 140 140 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 141 141 - void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 141 141 + void ice_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode); 142 142 143 143 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf); 144 144 145 145 extern struct mutex ice_global_cfg_lock_sw; 146 146 147 147 int 148 148 - ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 148 148 + ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, 149 149 void *buf, u16 buf_size, struct ice_sq_cd *cd); 150 150 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 151 151

+27 -26

drivers/net/ethernet/intel/ice/ice_controlq.c

reviewed

··· 90 90 static int 91 91 ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq) 92 92 { 93 93 - size_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc); 93 93 + size_t size = cq->num_sq_entries * sizeof(struct libie_aq_desc); 94 94 95 95 cq->sq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size, 96 96 &cq->sq.desc_buf.pa, ··· 110 110 static int 111 111 ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq) 112 112 { 113 113 - size_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc); 113 113 + size_t size = cq->num_rq_entries * sizeof(struct libie_aq_desc); 114 114 115 115 cq->rq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size, 116 116 &cq->rq.desc_buf.pa, ··· 159 159 160 160 /* allocate the mapped buffers */ 161 161 for (i = 0; i < cq->num_rq_entries; i++) { 162 162 - struct ice_aq_desc *desc; 162 162 + struct libie_aq_desc *desc; 163 163 struct ice_dma_mem *bi; 164 164 165 165 bi = &cq->rq.r.rq_bi[i]; ··· 173 173 /* now configure the descriptors for use */ 174 174 desc = ICE_CTL_Q_DESC(cq->rq, i); 175 175 176 176 - desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF); 177 177 - if (cq->rq_buf_size > ICE_AQ_LG_BUF) 178 178 - desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB); 176 176 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 177 177 + if (cq->rq_buf_size > LIBIE_AQ_LG_BUF) 178 178 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 179 179 desc->opcode = 0; 180 180 /* This is in accordance with control queue design, there is no 181 181 * register for buffer size configuration ··· 858 858 { 859 859 struct ice_ctl_q_ring *sq = &cq->sq; 860 860 u16 ntc = sq->next_to_clean; 861 861 - struct ice_aq_desc *desc; 861 861 + struct libie_aq_desc *desc; 862 862 863 863 desc = ICE_CTL_Q_DESC(*sq, ntc); 864 864 ··· 912 912 static void ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq, 913 913 void *desc, void *buf, u16 buf_len, bool response) 914 914 { 915 915 - struct ice_aq_desc *cq_desc = desc; 915 915 + struct libie_aq_desc *cq_desc = desc; 916 916 u16 datalen, flags; 917 917 918 918 if (!IS_ENABLED(CONFIG_DYNAMIC_DEBUG) && ··· 939 939 * by the DD and/or CMP flag set or a command with the RD flag set. 940 940 */ 941 941 if (buf && cq_desc->datalen && 942 942 - (flags & (ICE_AQ_FLAG_DD | ICE_AQ_FLAG_CMP | ICE_AQ_FLAG_RD))) { 942 942 + (flags & (LIBIE_AQ_FLAG_DD | LIBIE_AQ_FLAG_CMP | 943 943 + LIBIE_AQ_FLAG_RD))) { 943 944 char prefix[] = KBUILD_MODNAME " 0x12341234 0x12341234 "; 944 945 945 946 sprintf(prefix, KBUILD_MODNAME " 0x%08X 0x%08X ", ··· 993 992 */ 994 993 int 995 994 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 996 996 - struct ice_aq_desc *desc, void *buf, u16 buf_size, 995 995 + struct libie_aq_desc *desc, void *buf, u16 buf_size, 997 996 struct ice_sq_cd *cd) 998 997 { 999 998 struct ice_dma_mem *dma_buf = NULL; 1000 1000 - struct ice_aq_desc *desc_on_ring; 999 999 + struct libie_aq_desc *desc_on_ring; 1001 1000 bool cmd_completed = false; 1002 1001 int status = 0; 1003 1002 u16 retval = 0; ··· 1008 1007 return -EBUSY; 1009 1008 mutex_lock(&cq->sq_lock); 1010 1009 1011 1011 - cq->sq_last_status = ICE_AQ_RC_OK; 1010 1010 + cq->sq_last_status = LIBIE_AQ_RC_OK; 1012 1011 1013 1012 if (!cq->sq.count) { 1014 1013 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send queue not initialized.\n"); ··· 1029 1028 goto sq_send_command_error; 1030 1029 } 1031 1030 1032 1032 - desc->flags |= cpu_to_le16(ICE_AQ_FLAG_BUF); 1033 1033 - if (buf_size > ICE_AQ_LG_BUF) 1034 1034 - desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB); 1031 1031 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 1032 1032 + if (buf_size > LIBIE_AQ_LG_BUF) 1033 1033 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 1035 1034 } 1036 1035 1037 1036 val = rd32(hw, cq->sq.head); ··· 1113 1112 retval &= 0xff; 1114 1113 } 1115 1114 cmd_completed = true; 1116 1116 - if (!status && retval != ICE_AQ_RC_OK) 1115 1115 + if (!status && retval != LIBIE_AQ_RC_OK) 1117 1116 status = -EIO; 1118 1118 - cq->sq_last_status = (enum ice_aq_err)retval; 1117 1117 + cq->sq_last_status = (enum libie_aq_err)retval; 1119 1118 } 1120 1119 1121 1120 ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n"); ··· 1150 1149 * 1151 1150 * Fill the desc with default values 1152 1151 */ 1153 1153 - void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode) 1152 1152 + void ice_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode) 1154 1153 { 1155 1154 /* zero out the desc */ 1156 1155 memset(desc, 0, sizeof(*desc)); 1157 1156 desc->opcode = cpu_to_le16(opcode); 1158 1158 - desc->flags = cpu_to_le16(ICE_AQ_FLAG_SI); 1157 1157 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 1159 1158 } 1160 1159 1161 1160 /** ··· 1173 1172 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1174 1173 struct ice_rq_event_info *e, u16 *pending) 1175 1174 { 1175 1175 + enum libie_aq_err rq_last_status; 1176 1176 u16 ntc = cq->rq.next_to_clean; 1177 1177 - enum ice_aq_err rq_last_status; 1178 1178 - struct ice_aq_desc *desc; 1177 1177 + struct libie_aq_desc *desc; 1179 1178 struct ice_dma_mem *bi; 1180 1179 int ret_code = 0; 1181 1180 u16 desc_idx; ··· 1208 1207 desc = ICE_CTL_Q_DESC(cq->rq, ntc); 1209 1208 desc_idx = ntc; 1210 1209 1211 1211 - rq_last_status = (enum ice_aq_err)le16_to_cpu(desc->retval); 1210 1210 + rq_last_status = (enum libie_aq_err)le16_to_cpu(desc->retval); 1212 1211 flags = le16_to_cpu(desc->flags); 1213 1213 - if (flags & ICE_AQ_FLAG_ERR) { 1212 1212 + if (flags & LIBIE_AQ_FLAG_ERR) { 1214 1213 ret_code = -EIO; 1215 1214 ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n", 1216 1215 le16_to_cpu(desc->opcode), rq_last_status); ··· 1231 1230 bi = &cq->rq.r.rq_bi[ntc]; 1232 1231 memset(desc, 0, sizeof(*desc)); 1233 1232 1234 1234 - desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF); 1235 1235 - if (cq->rq_buf_size > ICE_AQ_LG_BUF) 1236 1236 - desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB); 1233 1233 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF); 1234 1234 + if (cq->rq_buf_size > LIBIE_AQ_LG_BUF) 1235 1235 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 1237 1236 desc->datalen = cpu_to_le16(bi->size); 1238 1237 desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1239 1238 desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));

+4 -4

drivers/net/ethernet/intel/ice/ice_controlq.h

reviewed

··· 12 12 #define ICE_SBQ_MAX_BUF_LEN 512 13 13 14 14 #define ICE_CTL_Q_DESC(R, i) \ 15 15 - (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 15 15 + (&(((struct libie_aq_desc *)((R).desc_buf.va))[i])) 16 16 17 17 #define ICE_CTL_Q_DESC_UNUSED(R) \ 18 18 ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ ··· 76 76 77 77 /* sq transaction details */ 78 78 struct ice_sq_cd { 79 79 - struct ice_aq_desc *wb_desc; 79 79 + struct libie_aq_desc *wb_desc; 80 80 }; 81 81 82 82 /* rq event information */ 83 83 struct ice_rq_event_info { 84 84 - struct ice_aq_desc desc; 84 84 + struct libie_aq_desc desc; 85 85 u16 msg_len; 86 86 u16 buf_len; 87 87 u8 *msg_buf; ··· 96 96 u16 num_sq_entries; /* send queue depth */ 97 97 u16 rq_buf_size; /* receive queue buffer size */ 98 98 u16 sq_buf_size; /* send queue buffer size */ 99 99 - enum ice_aq_err sq_last_status; /* last status on send queue */ 99 99 + enum libie_aq_err sq_last_status; /* last status on send queue */ 100 100 struct mutex sq_lock; /* Send queue lock */ 101 101 struct mutex rq_lock; /* Receive queue lock */ 102 102 };

+18 -18

drivers/net/ethernet/intel/ice/ice_dcb.c

reviewed

··· 24 24 struct ice_sq_cd *cd) 25 25 { 26 26 struct ice_aqc_lldp_get_mib *cmd; 27 27 - struct ice_aq_desc desc; 27 27 + struct libie_aq_desc desc; 28 28 int status; 29 29 30 30 - cmd = &desc.params.lldp_get_mib; 30 30 + cmd = libie_aq_raw(&desc); 31 31 32 32 if (buf_size == 0 || !buf) 33 33 return -EINVAL; ··· 64 64 struct ice_sq_cd *cd) 65 65 { 66 66 struct ice_aqc_lldp_set_mib_change *cmd; 67 67 - struct ice_aq_desc desc; 67 67 + struct libie_aq_desc desc; 68 68 69 69 - cmd = &desc.params.lldp_set_event; 69 69 + cmd = libie_aq_raw(&desc); 70 70 71 71 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_mib_change); 72 72 ··· 95 95 struct ice_sq_cd *cd) 96 96 { 97 97 struct ice_aqc_lldp_stop *cmd; 98 98 - struct ice_aq_desc desc; 98 98 + struct libie_aq_desc desc; 99 99 100 100 - cmd = &desc.params.lldp_stop; 100 100 + cmd = libie_aq_raw(&desc); 101 101 102 102 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_stop); 103 103 ··· 121 121 int ice_aq_start_lldp(struct ice_hw *hw, bool persist, struct ice_sq_cd *cd) 122 122 { 123 123 struct ice_aqc_lldp_start *cmd; 124 124 - struct ice_aq_desc desc; 124 124 + struct libie_aq_desc desc; 125 125 126 126 - cmd = &desc.params.lldp_start; 126 126 + cmd = libie_aq_raw(&desc); 127 127 128 128 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_start); 129 129 ··· 677 677 bool *dcbx_agent_status, struct ice_sq_cd *cd) 678 678 { 679 679 struct ice_aqc_lldp_stop_start_specific_agent *cmd; 680 680 - struct ice_aq_desc desc; 680 680 + struct libie_aq_desc desc; 681 681 u16 opcode; 682 682 int status; 683 683 684 684 - cmd = &desc.params.lldp_agent_ctrl; 684 684 + cmd = libie_aq_raw(&desc); 685 685 686 686 opcode = ice_aqc_opc_lldp_stop_start_specific_agent; 687 687 ··· 714 714 struct ice_aqc_get_cee_dcb_cfg_resp *buff, 715 715 struct ice_sq_cd *cd) 716 716 { 717 717 - struct ice_aq_desc desc; 717 717 + struct libie_aq_desc desc; 718 718 719 719 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cee_dcb_cfg); 720 720 ··· 733 733 int ice_aq_set_pfc_mode(struct ice_hw *hw, u8 pfc_mode, struct ice_sq_cd *cd) 734 734 { 735 735 struct ice_aqc_set_query_pfc_mode *cmd; 736 736 - struct ice_aq_desc desc; 736 736 + struct libie_aq_desc desc; 737 737 int status; 738 738 739 739 if (pfc_mode > ICE_AQC_PFC_DSCP_BASED_PFC) 740 740 return -EINVAL; 741 741 742 742 - cmd = &desc.params.set_query_pfc_mode; 742 742 + cmd = libie_aq_raw(&desc); 743 743 744 744 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_pfc_mode); 745 745 ··· 914 914 ret = ice_aq_get_dcb_cfg(pi->hw, ICE_AQ_LLDP_MIB_REMOTE, 915 915 ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID, dcbx_cfg); 916 916 /* Don't treat ENOENT as an error for Remote MIBs */ 917 917 - if (pi->hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT) 917 917 + if (pi->hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT) 918 918 ret = 0; 919 919 920 920 out: ··· 941 941 /* CEE mode */ 942 942 ret = ice_get_ieee_or_cee_dcb_cfg(pi, ICE_DCBX_MODE_CEE); 943 943 ice_cee_to_dcb_cfg(&cee_cfg, pi); 944 944 - } else if (pi->hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT) { 944 944 + } else if (pi->hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT) { 945 945 /* CEE mode not enabled try querying IEEE data */ 946 946 dcbx_cfg = &pi->qos_cfg.local_dcbx_cfg; 947 947 dcbx_cfg->dcbx_mode = ICE_DCBX_MODE_IEEE; ··· 965 965 struct ice_aqc_lldp_get_mib *mib; 966 966 u8 change_type, dcbx_mode; 967 967 968 968 - mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw; 968 968 + mib = libie_aq_raw(&event->desc); 969 969 970 970 change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M, mib->type); 971 971 if (change_type == ICE_AQ_LLDP_MIB_REMOTE) ··· 1537 1537 struct ice_sq_cd *cd) 1538 1538 { 1539 1539 struct ice_aqc_query_port_ets *cmd; 1540 1540 - struct ice_aq_desc desc; 1540 1540 + struct libie_aq_desc desc; 1541 1541 int status; 1542 1542 1543 1543 if (!pi) 1544 1544 return -EINVAL; 1545 1545 - cmd = &desc.params.port_ets; 1545 1545 + cmd = libie_aq_raw(&desc); 1546 1546 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_port_ets); 1547 1547 cmd->port_teid = pi->root->info.node_teid; 1548 1548

+1 -1

drivers/net/ethernet/intel/ice/ice_dcb_lib.c

reviewed

··· 1020 1020 } 1021 1021 1022 1022 pi = pf->hw.port_info; 1023 1023 - mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw; 1023 1023 + mib = libie_aq_raw(&event->desc); 1024 1024 1025 1025 /* Ignore if event is not for Nearest Bridge */ 1026 1026 mib_type = FIELD_GET(ICE_AQ_LLDP_BRID_TYPE_M, mib->type);

+24 -23

drivers/net/ethernet/intel/ice/ice_ddp.c

reviewed

··· 1101 1101 return &bld->buf; 1102 1102 } 1103 1103 1104 1104 - static enum ice_ddp_state ice_map_aq_err_to_ddp_state(enum ice_aq_err aq_err) 1104 1104 + static enum ice_ddp_state ice_map_aq_err_to_ddp_state(enum libie_aq_err aq_err) 1105 1105 { 1106 1106 switch (aq_err) { 1107 1107 - case ICE_AQ_RC_ENOSEC: 1108 1108 - case ICE_AQ_RC_EBADSIG: 1107 1107 + case LIBIE_AQ_RC_ENOSEC: 1108 1108 + case LIBIE_AQ_RC_EBADSIG: 1109 1109 return ICE_DDP_PKG_FILE_SIGNATURE_INVALID; 1110 1110 - case ICE_AQ_RC_ESVN: 1110 1110 + case LIBIE_AQ_RC_ESVN: 1111 1111 return ICE_DDP_PKG_FILE_REVISION_TOO_LOW; 1112 1112 - case ICE_AQ_RC_EBADMAN: 1113 1113 - case ICE_AQ_RC_EBADBUF: 1112 1112 + case LIBIE_AQ_RC_EBADMAN: 1113 1113 + case LIBIE_AQ_RC_EBADBUF: 1114 1114 return ICE_DDP_PKG_LOAD_ERROR; 1115 1115 default: 1116 1116 return ICE_DDP_PKG_ERR; ··· 1180 1180 u32 *error_info, struct ice_sq_cd *cd) 1181 1181 { 1182 1182 struct ice_aqc_download_pkg *cmd; 1183 1183 - struct ice_aq_desc desc; 1183 1183 + struct libie_aq_desc desc; 1184 1184 int status; 1185 1185 1186 1186 if (error_offset) ··· 1188 1188 if (error_info) 1189 1189 *error_info = 0; 1190 1190 1191 1191 - cmd = &desc.params.download_pkg; 1191 1191 + cmd = libie_aq_raw(&desc); 1192 1192 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_download_pkg); 1193 1193 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1193 1193 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1194 1194 1195 1195 if (last_buf) 1196 1196 cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF; ··· 1259 1259 struct ice_buf_hdr *prev_hunk = ctx->hdr; 1260 1260 struct ice_hw *hw = ctx->hw; 1261 1261 bool prev_was_last = !hunk; 1262 1262 - enum ice_aq_err aq_err; 1262 1262 + enum libie_aq_err aq_err; 1263 1263 u32 offset, info; 1264 1264 int attempt, err; 1265 1265 ··· 1278 1278 prev_was_last, &offset, &info, NULL); 1279 1279 1280 1280 aq_err = hw->adminq.sq_last_status; 1281 1281 - if (aq_err != ICE_AQ_RC_ENOSEC && aq_err != ICE_AQ_RC_EBADSIG) 1281 1281 + if (aq_err != LIBIE_AQ_RC_ENOSEC && 1282 1282 + aq_err != LIBIE_AQ_RC_EBADSIG) 1282 1283 break; 1283 1284 } 1284 1285 ··· 1538 1537 static enum ice_ddp_state 1539 1538 ice_download_pkg_with_sig_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr) 1540 1539 { 1541 1541 - enum ice_aq_err aq_err = hw->adminq.sq_last_status; 1540 1540 + enum libie_aq_err aq_err = hw->adminq.sq_last_status; 1542 1541 enum ice_ddp_state state = ICE_DDP_PKG_ERR; 1543 1542 struct ice_ddp_send_ctx ctx = { .hw = hw }; 1544 1543 int status; ··· 1688 1687 struct ice_aqc_get_pkg_info_resp *pkg_info, 1689 1688 u16 buf_size, struct ice_sq_cd *cd) 1690 1689 { 1691 1691 - struct ice_aq_desc desc; 1690 1690 + struct libie_aq_desc desc; 1692 1691 1693 1692 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_pkg_info_list); 1694 1693 ··· 1712 1711 u32 *error_info, struct ice_sq_cd *cd) 1713 1712 { 1714 1713 struct ice_aqc_download_pkg *cmd; 1715 1715 - struct ice_aq_desc desc; 1714 1714 + struct libie_aq_desc desc; 1716 1715 int status; 1717 1716 1718 1717 if (error_offset) ··· 1720 1719 if (error_info) 1721 1720 *error_info = 0; 1722 1721 1723 1723 - cmd = &desc.params.download_pkg; 1722 1722 + cmd = libie_aq_raw(&desc); 1724 1723 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_pkg); 1725 1725 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1724 1724 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1726 1725 1727 1726 if (last_buf) 1728 1727 cmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF; ··· 1754 1753 int ice_aq_upload_section(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, 1755 1754 u16 buf_size, struct ice_sq_cd *cd) 1756 1755 { 1757 1757 - struct ice_aq_desc desc; 1756 1756 + struct libie_aq_desc desc; 1758 1757 1759 1758 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_upload_section); 1760 1760 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1759 1759 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1761 1760 1762 1761 return ice_aq_send_cmd(hw, &desc, pkg_buf, buf_size, cd); 1763 1762 } ··· 2336 2335 struct ice_sq_cd *cd, u8 *flags, bool set) 2337 2336 { 2338 2337 struct ice_aqc_get_set_tx_topo *cmd; 2339 2339 - struct ice_aq_desc desc; 2338 2338 + struct libie_aq_desc desc; 2340 2339 int status; 2341 2340 2342 2342 - cmd = &desc.params.get_set_tx_topo; 2341 2341 + cmd = libie_aq_raw(&desc); 2343 2342 if (set) { 2344 2343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_tx_topo); 2345 2344 cmd->set_flags = ICE_AQC_TX_TOPO_FLAGS_ISSUED; ··· 2348 2347 cmd->set_flags |= ICE_AQC_TX_TOPO_FLAGS_SRC_RAM | 2349 2348 ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW; 2350 2349 2351 2351 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2350 2350 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2352 2351 } else { 2353 2352 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo); 2354 2353 cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM; 2355 2354 2356 2355 if (hw->mac_type == ICE_MAC_E810 || 2357 2356 hw->mac_type == ICE_MAC_GENERIC) 2358 2358 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2357 2357 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2359 2358 } 2360 2359 2361 2360 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); ··· 2363 2362 return status; 2364 2363 /* read the return flag values (first byte) for get operation */ 2365 2364 if (!set && flags) 2366 2366 - *flags = desc.params.get_set_tx_topo.set_flags; 2365 2365 + *flags = cmd->set_flags; 2367 2366 2368 2367 return 0; 2369 2368 }

+13 -13

drivers/net/ethernet/intel/ice/ice_dpll.c

reviewed

··· 170 170 NL_SET_ERR_MSG_FMT(extack, 171 171 "err:%d %s failed to set pin freq:%u on pin:%u", 172 172 ret, 173 173 - ice_aq_str(pf->hw.adminq.sq_last_status), 173 173 + libie_aq_str(pf->hw.adminq.sq_last_status), 174 174 freq, pin->idx); 175 175 return ret; 176 176 } ··· 477 477 if (ret) 478 478 NL_SET_ERR_MSG_FMT(extack, 479 479 "err:%d %s failed to enable %s pin:%u", 480 480 - ret, ice_aq_str(hw->adminq.sq_last_status), 480 480 + ret, libie_aq_str(hw->adminq.sq_last_status), 481 481 pin_type_name[pin_type], pin->idx); 482 482 483 483 return ret; ··· 522 522 if (ret) 523 523 NL_SET_ERR_MSG_FMT(extack, 524 524 "err:%d %s failed to disable %s pin:%u", 525 525 - ret, ice_aq_str(hw->adminq.sq_last_status), 525 525 + ret, libie_aq_str(hw->adminq.sq_last_status), 526 526 pin_type_name[pin_type], pin->idx); 527 527 528 528 return ret; ··· 701 701 NL_SET_ERR_MSG_FMT(extack, 702 702 "err:%d %s failed to update %s pin:%u", 703 703 ret, 704 704 - ice_aq_str(pf->hw.adminq.sq_last_status), 704 704 + libie_aq_str(pf->hw.adminq.sq_last_status), 705 705 pin_type_name[pin_type], pin->idx); 706 706 else 707 707 dev_err_ratelimited(ice_pf_to_dev(pf), 708 708 "err:%d %s failed to update %s pin:%u\n", 709 709 ret, 710 710 - ice_aq_str(pf->hw.adminq.sq_last_status), 710 710 + libie_aq_str(pf->hw.adminq.sq_last_status), 711 711 pin_type_name[pin_type], pin->idx); 712 712 return ret; 713 713 } ··· 740 740 NL_SET_ERR_MSG_FMT(extack, 741 741 "err:%d %s failed to set pin prio:%u on pin:%u", 742 742 ret, 743 743 - ice_aq_str(pf->hw.adminq.sq_last_status), 743 743 + libie_aq_str(pf->hw.adminq.sq_last_status), 744 744 prio, pin->idx); 745 745 else 746 746 dpll->input_prio[pin->idx] = prio; ··· 1662 1662 NL_SET_ERR_MSG_FMT(extack, 1663 1663 "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u", 1664 1664 ret, 1665 1665 - ice_aq_str(pf->hw.adminq.sq_last_status), 1665 1665 + libie_aq_str(pf->hw.adminq.sq_last_status), 1666 1666 phase_adjust, p->idx, d->dpll_idx); 1667 1667 1668 1668 return ret; ··· 2313 2313 NL_SET_ERR_MSG_FMT(extack, 2314 2314 "err:%d %s failed to set pin state:%u for pin:%u on parent:%u", 2315 2315 ret, 2316 2316 - ice_aq_str(pf->hw.adminq.sq_last_status), 2316 2316 + libie_aq_str(pf->hw.adminq.sq_last_status), 2317 2317 state, p->idx, parent->idx); 2318 2318 unlock: 2319 2319 mutex_unlock(&pf->dplls.lock); ··· 2509 2509 int ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, 2510 2510 ARRAY_SIZE(meas)); 2511 2511 2512 2512 - if (ret && pf->hw.adminq.sq_last_status == ICE_AQ_RC_ESRCH) 2512 2512 + if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_ESRCH) 2513 2513 return false; 2514 2514 2515 2515 return true; ··· 2562 2562 *phase_offset_pins_updated = 0; 2563 2563 ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, 2564 2564 ARRAY_SIZE(meas)); 2565 2565 - if (ret && pf->hw.adminq.sq_last_status == ICE_AQ_RC_EAGAIN) { 2565 2565 + if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_EAGAIN) { 2566 2566 return 0; 2567 2567 } else if (ret) { 2568 2568 dev_err(ice_pf_to_dev(pf), 2569 2569 "failed to get input pin measurements dpll=%d, ret=%d %s\n", 2570 2570 DPLL_TYPE_PPS, ret, 2571 2571 - ice_aq_str(pf->hw.adminq.sq_last_status)); 2571 2571 + libie_aq_str(pf->hw.adminq.sq_last_status)); 2572 2572 return ret; 2573 2573 } 2574 2574 for (i = 0; i < pf->dplls.num_inputs; i++) { ··· 2627 2627 dev_err(ice_pf_to_dev(pf), 2628 2628 "update dpll=%d state failed, ret=%d %s\n", 2629 2629 d->dpll_idx, ret, 2630 2630 - ice_aq_str(pf->hw.adminq.sq_last_status)); 2630 2630 + libie_aq_str(pf->hw.adminq.sq_last_status)); 2631 2631 return ret; 2632 2632 } 2633 2633 if (init) { ··· 3678 3678 if (ret) { 3679 3679 dev_err(ice_pf_to_dev(pf), 3680 3680 "err:%d %s failed to read cgu abilities\n", 3681 3681 - ret, ice_aq_str(hw->adminq.sq_last_status)); 3681 3681 + ret, libie_aq_str(hw->adminq.sq_last_status)); 3682 3682 return ret; 3683 3683 } 3684 3684

+6 -6

drivers/net/ethernet/intel/ice/ice_ethtool.c

reviewed

··· 879 879 ret = ice_acquire_nvm(hw, ICE_RES_READ); 880 880 if (ret) { 881 881 dev_err(dev, "ice_acquire_nvm failed, err %d aq_err %s\n", 882 882 - ret, ice_aq_str(hw->adminq.sq_last_status)); 882 882 + ret, libie_aq_str(hw->adminq.sq_last_status)); 883 883 goto out; 884 884 } 885 885 ··· 887 887 false); 888 888 if (ret) { 889 889 dev_err(dev, "ice_read_flat_nvm failed, err %d aq_err %s\n", 890 890 - ret, ice_aq_str(hw->adminq.sq_last_status)); 890 890 + ret, libie_aq_str(hw->adminq.sq_last_status)); 891 891 goto release; 892 892 } 893 893 ··· 3542 3542 3543 3543 if (aq_failures & ICE_SET_FC_AQ_FAIL_GET) { 3544 3544 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %d aq_err %s\n", 3545 3545 - err, ice_aq_str(hw->adminq.sq_last_status)); 3545 3545 + err, libie_aq_str(hw->adminq.sq_last_status)); 3546 3546 err = -EAGAIN; 3547 3547 } else if (aq_failures & ICE_SET_FC_AQ_FAIL_SET) { 3548 3548 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %d aq_err %s\n", 3549 3549 - err, ice_aq_str(hw->adminq.sq_last_status)); 3549 3549 + err, libie_aq_str(hw->adminq.sq_last_status)); 3550 3550 err = -EAGAIN; 3551 3551 } else if (aq_failures & ICE_SET_FC_AQ_FAIL_UPDATE) { 3552 3552 netdev_info(netdev, "Set fc failed on the get_link_info call with err %d aq_err %s\n", 3553 3553 - err, ice_aq_str(hw->adminq.sq_last_status)); 3553 3553 + err, libie_aq_str(hw->adminq.sq_last_status)); 3554 3554 err = -EAGAIN; 3555 3555 } 3556 3556 ··· 3861 3861 err = ice_set_rss_lut(vsi, lut, vsi->rss_table_size); 3862 3862 if (err) 3863 3863 dev_err(dev, "Cannot set RSS lut, err %d aq_err %s\n", err, 3864 3864 - ice_aq_str(hw->adminq.sq_last_status)); 3864 3864 + libie_aq_str(hw->adminq.sq_last_status)); 3865 3865 3866 3866 kfree(lut); 3867 3867 return err;

+21 -17

drivers/net/ethernet/intel/ice/ice_fw_update.c

reviewed

··· 68 68 69 69 if (status) { 70 70 dev_err(dev, "Failed to send record package data to firmware, err %d aq_err %s\n", 71 71 - status, ice_aq_str(hw->adminq.sq_last_status)); 71 71 + status, libie_aq_str(hw->adminq.sq_last_status)); 72 72 NL_SET_ERR_MSG_MOD(extack, "Failed to record package data to firmware"); 73 73 return -EIO; 74 74 } ··· 257 257 258 258 if (status) { 259 259 dev_err(dev, "Failed to transfer component table to firmware, err %d aq_err %s\n", 260 260 - status, ice_aq_str(hw->adminq.sq_last_status)); 260 260 + status, libie_aq_str(hw->adminq.sq_last_status)); 261 261 NL_SET_ERR_MSG_MOD(extack, "Failed to transfer component table to firmware"); 262 262 return -EIO; 263 263 } ··· 299 299 struct device *dev = ice_pf_to_dev(pf); 300 300 struct ice_aq_task task = {}; 301 301 struct ice_hw *hw = &pf->hw; 302 302 - struct ice_aq_desc *desc; 302 302 + struct libie_aq_desc *desc; 303 303 + struct ice_aqc_nvm *cmd; 303 304 u32 completion_offset; 304 305 int err; 305 306 ··· 314 313 if (err) { 315 314 dev_err(dev, "Failed to flash module 0x%02x with block of size %u at offset %u, err %d aq_err %s\n", 316 315 module, block_size, offset, err, 317 317 - ice_aq_str(hw->adminq.sq_last_status)); 316 316 + libie_aq_str(hw->adminq.sq_last_status)); 318 317 NL_SET_ERR_MSG_MOD(extack, "Failed to program flash module"); 319 318 return -EIO; 320 319 } ··· 334 333 } 335 334 336 335 desc = &task.event.desc; 337 337 - completion_module = le16_to_cpu(desc->params.nvm.module_typeid); 336 336 + cmd = libie_aq_raw(desc); 337 337 + completion_module = le16_to_cpu(cmd->module_typeid); 338 338 completion_retval = le16_to_cpu(desc->retval); 339 339 340 340 - completion_offset = le16_to_cpu(desc->params.nvm.offset_low); 341 341 - completion_offset |= desc->params.nvm.offset_high << 16; 340 340 + completion_offset = le16_to_cpu(cmd->offset_low); 341 341 + completion_offset |= cmd->offset_high << 16; 342 342 343 343 if (completion_module != module) { 344 344 dev_err(dev, "Unexpected module_typeid in write completion: got 0x%x, expected 0x%x\n", ··· 358 356 if (completion_retval) { 359 357 dev_err(dev, "Firmware failed to flash module 0x%02x with block of size %u at offset %u, err %s\n", 360 358 module, block_size, offset, 361 361 - ice_aq_str((enum ice_aq_err)completion_retval)); 359 359 + libie_aq_str((enum libie_aq_err)completion_retval)); 362 360 NL_SET_ERR_MSG_MOD(extack, "Firmware failed to program flash module"); 363 361 return -EIO; 364 362 } ··· 371 369 */ 372 370 if (reset_level && last_cmd && module == ICE_SR_1ST_NVM_BANK_PTR) { 373 371 if (hw->dev_caps.common_cap.pcie_reset_avoidance) { 374 374 - *reset_level = desc->params.nvm.cmd_flags & 372 372 + *reset_level = cmd->cmd_flags & 375 373 ICE_AQC_NVM_RESET_LVL_M; 376 374 dev_dbg(dev, "Firmware reported required reset level as %u\n", 377 375 *reset_level); ··· 489 487 struct device *dev = ice_pf_to_dev(pf); 490 488 struct ice_aq_task task = {}; 491 489 struct ice_hw *hw = &pf->hw; 492 492 - struct ice_aq_desc *desc; 490 490 + struct libie_aq_desc *desc; 491 491 + struct ice_aqc_nvm *cmd; 493 492 struct devlink *devlink; 494 493 int err; 495 494 ··· 506 503 if (err) { 507 504 dev_err(dev, "Failed to erase %s (module 0x%02x), err %d aq_err %s\n", 508 505 component, module, err, 509 509 - ice_aq_str(hw->adminq.sq_last_status)); 506 506 + libie_aq_str(hw->adminq.sq_last_status)); 510 507 NL_SET_ERR_MSG_MOD(extack, "Failed to erase flash module"); 511 508 err = -EIO; 512 509 goto out_notify_devlink; ··· 521 518 } 522 519 523 520 desc = &task.event.desc; 524 524 - completion_module = le16_to_cpu(desc->params.nvm.module_typeid); 521 521 + cmd = libie_aq_raw(desc); 522 522 + completion_module = le16_to_cpu(cmd->module_typeid); 525 523 completion_retval = le16_to_cpu(desc->retval); 526 524 527 525 if (completion_module != module) { ··· 536 532 if (completion_retval) { 537 533 dev_err(dev, "Firmware failed to erase %s (module 0x02%x), aq_err %s\n", 538 534 component, module, 539 539 - ice_aq_str((enum ice_aq_err)completion_retval)); 535 535 + libie_aq_str((enum libie_aq_err)completion_retval)); 540 536 NL_SET_ERR_MSG_MOD(extack, "Firmware failed to erase flash"); 541 537 err = -EIO; 542 538 goto out_notify_devlink; ··· 583 579 err = ice_nvm_write_activate(hw, activate_flags, &response_flags); 584 580 if (err) { 585 581 dev_err(dev, "Failed to switch active flash banks, err %d aq_err %s\n", 586 586 - err, ice_aq_str(hw->adminq.sq_last_status)); 582 582 + err, libie_aq_str(hw->adminq.sq_last_status)); 587 583 NL_SET_ERR_MSG_MOD(extack, "Failed to switch active flash banks"); 588 584 return -EIO; 589 585 } ··· 615 611 completion_retval = le16_to_cpu(task.event.desc.retval); 616 612 if (completion_retval) { 617 613 dev_err(dev, "Firmware failed to switch active flash banks aq_err %s\n", 618 618 - ice_aq_str((enum ice_aq_err)completion_retval)); 614 614 + libie_aq_str((enum libie_aq_err)completion_retval)); 619 615 NL_SET_ERR_MSG_MOD(extack, "Firmware failed to switch active flash banks"); 620 616 return -EIO; 621 617 } ··· 953 949 err = ice_acquire_nvm(hw, ICE_RES_WRITE); 954 950 if (err) { 955 951 dev_err(dev, "Failed to acquire device flash lock, err %d aq_err %s\n", 956 956 - err, ice_aq_str(hw->adminq.sq_last_status)); 952 952 + err, libie_aq_str(hw->adminq.sq_last_status)); 957 953 NL_SET_ERR_MSG_MOD(extack, "Failed to acquire device flash lock"); 958 954 return err; 959 955 } ··· 1046 1042 err = ice_acquire_nvm(hw, ICE_RES_WRITE); 1047 1043 if (err) { 1048 1044 dev_err(dev, "Failed to acquire device flash lock, err %d aq_err %s\n", 1049 1049 - err, ice_aq_str(hw->adminq.sq_last_status)); 1045 1045 + err, libie_aq_str(hw->adminq.sq_last_status)); 1050 1046 NL_SET_ERR_MSG_MOD(extack, "Failed to acquire device flash lock"); 1051 1047 return err; 1052 1048 }

+9 -7

drivers/net/ethernet/intel/ice/ice_fwlog.c

reviewed

··· 240 240 { 241 241 struct ice_aqc_fw_log_cfg_resp *fw_modules; 242 242 struct ice_aqc_fw_log *cmd; 243 243 - struct ice_aq_desc desc; 243 243 + struct libie_aq_desc desc; 244 244 int status; 245 245 int i; 246 246 ··· 255 255 } 256 256 257 257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_config); 258 258 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 258 258 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 259 259 260 260 - cmd = &desc.params.fw_log; 260 260 + cmd = libie_aq_raw(&desc); 261 261 262 262 cmd->cmd_flags = ICE_AQC_FW_LOG_CONF_SET_VALID; 263 263 cmd->ops.cfg.log_resolution = cpu_to_le16(log_resolution); ··· 309 309 { 310 310 struct ice_aqc_fw_log_cfg_resp *fw_modules; 311 311 struct ice_aqc_fw_log *cmd; 312 312 - struct ice_aq_desc desc; 312 312 + struct libie_aq_desc desc; 313 313 u16 module_id_cnt; 314 314 int status; 315 315 void *buf; ··· 322 322 return -ENOMEM; 323 323 324 324 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_query); 325 325 - cmd = &desc.params.fw_log; 325 325 + cmd = libie_aq_raw(&desc); 326 326 327 327 cmd->cmd_flags = ICE_AQC_FW_LOG_AQ_QUERY; 328 328 ··· 384 384 */ 385 385 static int ice_aq_fwlog_register(struct ice_hw *hw, bool reg) 386 386 { 387 387 - struct ice_aq_desc desc; 387 387 + struct ice_aqc_fw_log *cmd; 388 388 + struct libie_aq_desc desc; 388 389 389 390 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logs_register); 391 391 + cmd = libie_aq_raw(&desc); 390 392 391 393 if (reg) 392 392 - desc.params.fw_log.cmd_flags = ICE_AQC_FW_LOG_AQ_REGISTER; 394 394 + cmd->cmd_flags = ICE_AQC_FW_LOG_AQ_REGISTER; 393 395 394 396 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 395 397 }

+2 -2

drivers/net/ethernet/intel/ice/ice_lag.c

reviewed

··· 1144 1144 { 1145 1145 struct ice_aqc_alloc_free_res_elem *buf; 1146 1146 struct ice_aqc_set_port_params *cmd; 1147 1147 - struct ice_aq_desc desc; 1147 1147 + struct libie_aq_desc desc; 1148 1148 u16 buf_len, swid; 1149 1149 int status, i; 1150 1150 ··· 1192 1192 else 1193 1193 swid = local_lag->pf->hw.port_info->sw_id; 1194 1194 1195 1195 - cmd = &desc.params.set_port_params; 1195 1195 + cmd = libie_aq_raw(&desc); 1196 1196 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 1197 1197 1198 1198 cmd->swid = cpu_to_le16(ICE_AQC_PORT_SWID_VALID | swid);

+5 -5

drivers/net/ethernet/intel/ice/ice_lib.c

reviewed

··· 3736 3736 3737 3737 status = ice_aq_set_link_restart_an(pi, ena, NULL); 3738 3738 3739 3739 - /* if link is owned by manageability, FW will return ICE_AQ_RC_EMODE. 3739 3739 + /* if link is owned by manageability, FW will return LIBIE_AQ_RC_EMODE. 3740 3740 * this is not a fatal error, so print a warning message and return 3741 3741 * a success code. Return an error if FW returns an error code other 3742 3742 - * than ICE_AQ_RC_EMODE 3742 3742 + * than LIBIE_AQ_RC_EMODE 3743 3743 */ 3744 3744 if (status == -EIO) { 3745 3745 - if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3745 3745 + if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3746 3746 dev_dbg(dev, "can't set link to %s, err %d aq_err %s. not fatal, continuing\n", 3747 3747 (ena ? "ON" : "OFF"), status, 3748 3748 - ice_aq_str(hw->adminq.sq_last_status)); 3748 3748 + libie_aq_str(hw->adminq.sq_last_status)); 3749 3749 } else if (status) { 3750 3750 dev_err(dev, "can't set link to %s, err %d aq_err %s\n", 3751 3751 (ena ? "ON" : "OFF"), status, 3752 3752 - ice_aq_str(hw->adminq.sq_last_status)); 3752 3752 + libie_aq_str(hw->adminq.sq_last_status)); 3753 3753 return status; 3754 3754 } 3755 3755

+11 -56

drivers/net/ethernet/intel/ice/ice_main.c

reviewed

··· 38 38 39 39 MODULE_DESCRIPTION(DRV_SUMMARY); 40 40 MODULE_IMPORT_NS("LIBIE"); 41 41 + MODULE_IMPORT_NS("LIBIE_ADMINQ"); 41 42 MODULE_LICENSE("GPL v2"); 42 43 MODULE_FIRMWARE(ICE_DDP_PKG_FILE); 43 44 ··· 380 379 * should go into promiscuous mode. There should be some 381 380 * space reserved for promiscuous filters. 382 381 */ 383 383 - if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOSPC && 382 382 + if (hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOSPC && 384 383 !test_and_set_bit(ICE_FLTR_OVERFLOW_PROMISC, 385 384 vsi->state)) { 386 385 promisc_forced_on = true; ··· 1120 1119 if (status) 1121 1120 dev_dbg(dev, "Failed to update link status on port %d, err %d aq_err %s\n", 1122 1121 pi->lport, status, 1123 1123 - ice_aq_str(pi->hw->adminq.sq_last_status)); 1122 1122 + libie_aq_str(pi->hw->adminq.sq_last_status)); 1124 1123 1125 1124 ice_check_link_cfg_err(pf, pi->phy.link_info.link_cfg_err); 1126 1125 ··· 4225 4224 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 4226 4225 if (status) { 4227 4226 dev_err(ice_pf_to_dev(vsi->back), "Failed to update VSI for safe mode VLANs, err %d aq_err %s\n", 4228 4228 - status, ice_aq_str(hw->adminq.sq_last_status)); 4227 4227 + status, libie_aq_str(hw->adminq.sq_last_status)); 4229 4228 } else { 4230 4229 vsi->info.sec_flags = ctxt->info.sec_flags; 4231 4230 vsi->info.sw_flags2 = ctxt->info.sw_flags2; ··· 5432 5431 status = ice_aq_manage_mac_write(hw, mac_addr, flags, NULL); 5433 5432 if (status) 5434 5433 dev_err(dev, "Failed to enable Multicast Magic Packet wake, err %d aq_err %s\n", 5435 5435 - status, ice_aq_str(hw->adminq.sq_last_status)); 5434 5434 + status, libie_aq_str(hw->adminq.sq_last_status)); 5436 5435 } 5437 5436 5438 5437 /** ··· 7912 7911 } 7913 7912 7914 7913 /** 7915 7915 - * ice_aq_str - convert AQ err code to a string 7916 7916 - * @aq_err: the AQ error code to convert 7917 7917 - */ 7918 7918 - const char *ice_aq_str(enum ice_aq_err aq_err) 7919 7919 - { 7920 7920 - switch (aq_err) { 7921 7921 - case ICE_AQ_RC_OK: 7922 7922 - return "OK"; 7923 7923 - case ICE_AQ_RC_EPERM: 7924 7924 - return "ICE_AQ_RC_EPERM"; 7925 7925 - case ICE_AQ_RC_ENOENT: 7926 7926 - return "ICE_AQ_RC_ENOENT"; 7927 7927 - case ICE_AQ_RC_ESRCH: 7928 7928 - return "ICE_AQ_RC_ESRCH"; 7929 7929 - case ICE_AQ_RC_EAGAIN: 7930 7930 - return "ICE_AQ_RC_EAGAIN"; 7931 7931 - case ICE_AQ_RC_ENOMEM: 7932 7932 - return "ICE_AQ_RC_ENOMEM"; 7933 7933 - case ICE_AQ_RC_EBUSY: 7934 7934 - return "ICE_AQ_RC_EBUSY"; 7935 7935 - case ICE_AQ_RC_EEXIST: 7936 7936 - return "ICE_AQ_RC_EEXIST"; 7937 7937 - case ICE_AQ_RC_EINVAL: 7938 7938 - return "ICE_AQ_RC_EINVAL"; 7939 7939 - case ICE_AQ_RC_ENOSPC: 7940 7940 - return "ICE_AQ_RC_ENOSPC"; 7941 7941 - case ICE_AQ_RC_ENOSYS: 7942 7942 - return "ICE_AQ_RC_ENOSYS"; 7943 7943 - case ICE_AQ_RC_EMODE: 7944 7944 - return "ICE_AQ_RC_EMODE"; 7945 7945 - case ICE_AQ_RC_ENOSEC: 7946 7946 - return "ICE_AQ_RC_ENOSEC"; 7947 7947 - case ICE_AQ_RC_EBADSIG: 7948 7948 - return "ICE_AQ_RC_EBADSIG"; 7949 7949 - case ICE_AQ_RC_ESVN: 7950 7950 - return "ICE_AQ_RC_ESVN"; 7951 7951 - case ICE_AQ_RC_EBADMAN: 7952 7952 - return "ICE_AQ_RC_EBADMAN"; 7953 7953 - case ICE_AQ_RC_EBADBUF: 7954 7954 - return "ICE_AQ_RC_EBADBUF"; 7955 7955 - } 7956 7956 - 7957 7957 - return "ICE_AQ_RC_UNKNOWN"; 7958 7958 - } 7959 7959 - 7960 7960 - /** 7961 7914 * ice_set_rss_lut - Set RSS LUT 7962 7915 * @vsi: Pointer to VSI structure 7963 7916 * @lut: Lookup table ··· 7936 7981 status = ice_aq_set_rss_lut(hw, &params); 7937 7982 if (status) 7938 7983 dev_err(ice_pf_to_dev(vsi->back), "Cannot set RSS lut, err %d aq_err %s\n", 7939 7939 - status, ice_aq_str(hw->adminq.sq_last_status)); 7984 7984 + status, libie_aq_str(hw->adminq.sq_last_status)); 7940 7985 7941 7986 return status; 7942 7987 } ··· 7959 8004 status = ice_aq_set_rss_key(hw, vsi->idx, (struct ice_aqc_get_set_rss_keys *)seed); 7960 8005 if (status) 7961 8006 dev_err(ice_pf_to_dev(vsi->back), "Cannot set RSS key, err %d aq_err %s\n", 7962 7962 - status, ice_aq_str(hw->adminq.sq_last_status)); 8007 8007 + status, libie_aq_str(hw->adminq.sq_last_status)); 7963 8008 7964 8009 return status; 7965 8010 } ··· 7989 8034 status = ice_aq_get_rss_lut(hw, &params); 7990 8035 if (status) 7991 8036 dev_err(ice_pf_to_dev(vsi->back), "Cannot get RSS lut, err %d aq_err %s\n", 7992 7992 - status, ice_aq_str(hw->adminq.sq_last_status)); 8037 8037 + status, libie_aq_str(hw->adminq.sq_last_status)); 7993 8038 7994 8039 return status; 7995 8040 } ··· 8012 8057 status = ice_aq_get_rss_key(hw, vsi->idx, (struct ice_aqc_get_set_rss_keys *)seed); 8013 8058 if (status) 8014 8059 dev_err(ice_pf_to_dev(vsi->back), "Cannot get RSS key, err %d aq_err %s\n", 8015 8015 - status, ice_aq_str(hw->adminq.sq_last_status)); 8060 8060 + status, libie_aq_str(hw->adminq.sq_last_status)); 8016 8061 8017 8062 return status; 8018 8063 } ··· 8129 8174 ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 8130 8175 if (ret) { 8131 8176 dev_err(ice_pf_to_dev(vsi->back), "update VSI for bridge mode failed, bmode = %d err %d aq_err %s\n", 8132 8132 - bmode, ret, ice_aq_str(hw->adminq.sq_last_status)); 8177 8177 + bmode, ret, libie_aq_str(hw->adminq.sq_last_status)); 8133 8178 goto out; 8134 8179 } 8135 8180 /* Update sw flags for book keeping */ ··· 8197 8242 if (err) { 8198 8243 netdev_err(dev, "switch rule update failed, mode = %d err %d aq_err %s\n", 8199 8244 mode, err, 8200 8200 - ice_aq_str(hw->adminq.sq_last_status)); 8245 8245 + libie_aq_str(hw->adminq.sq_last_status)); 8201 8246 /* revert hw->evb_veb */ 8202 8247 hw->evb_veb = (pf_sw->bridge_mode == BRIDGE_MODE_VEB); 8203 8248 return err;

+19 -19

drivers/net/ethernet/intel/ice/ice_nvm.c

reviewed

··· 22 22 u16 length, void *data, bool last_command, 23 23 bool read_shadow_ram, struct ice_sq_cd *cd) 24 24 { 25 25 - struct ice_aq_desc desc; 25 25 + struct libie_aq_desc desc; 26 26 struct ice_aqc_nvm *cmd; 27 27 28 28 - cmd = &desc.params.nvm; 28 28 + cmd = libie_aq_raw(&desc); 29 29 30 30 if (offset > ICE_AQC_NVM_MAX_OFFSET) 31 31 return -EINVAL; ··· 125 125 u16 length, void *data, bool last_command, u8 command_flags, 126 126 struct ice_sq_cd *cd) 127 127 { 128 128 - struct ice_aq_desc desc; 128 128 + struct libie_aq_desc desc; 129 129 struct ice_aqc_nvm *cmd; 130 130 131 131 - cmd = &desc.params.nvm; 131 131 + cmd = libie_aq_raw(&desc); 132 132 133 133 /* In offset the highest byte must be zeroed. */ 134 134 if (offset & 0xFF000000) ··· 146 146 cmd->offset_high = (offset >> 16) & 0xFF; 147 147 cmd->length = cpu_to_le16(length); 148 148 149 149 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 149 149 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 150 150 151 151 return ice_aq_send_cmd(hw, &desc, data, length, cd); 152 152 } ··· 161 161 */ 162 162 int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd) 163 163 { 164 164 - struct ice_aq_desc desc; 164 164 + struct libie_aq_desc desc; 165 165 struct ice_aqc_nvm *cmd; 166 166 167 167 - cmd = &desc.params.nvm; 167 167 + cmd = libie_aq_raw(&desc); 168 168 169 169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase); 170 170 ··· 869 869 870 870 status = ice_read_flat_nvm(hw, offset, &len, &data, false); 871 871 if (status == -EIO && 872 872 - hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) { 872 872 + hw->adminq.sq_last_status == LIBIE_AQ_RC_EINVAL) { 873 873 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n", 874 874 __func__, offset); 875 875 status = 0; ··· 1182 1182 int ice_nvm_validate_checksum(struct ice_hw *hw) 1183 1183 { 1184 1184 struct ice_aqc_nvm_checksum *cmd; 1185 1185 - struct ice_aq_desc desc; 1185 1185 + struct libie_aq_desc desc; 1186 1186 int status; 1187 1187 1188 1188 status = ice_acquire_nvm(hw, ICE_RES_READ); 1189 1189 if (status) 1190 1190 return status; 1191 1191 1192 1192 - cmd = &desc.params.nvm_checksum; 1192 1192 + cmd = libie_aq_raw(&desc); 1193 1193 1194 1194 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum); 1195 1195 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY; ··· 1226 1226 */ 1227 1227 int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags) 1228 1228 { 1229 1229 + struct libie_aq_desc desc; 1229 1230 struct ice_aqc_nvm *cmd; 1230 1230 - struct ice_aq_desc desc; 1231 1231 int err; 1232 1232 1233 1233 - cmd = &desc.params.nvm; 1233 1233 + cmd = libie_aq_raw(&desc); 1234 1234 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate); 1235 1235 1236 1236 cmd->cmd_flags = (u8)(cmd_flags & 0xFF); ··· 1252 1252 */ 1253 1253 int ice_aq_nvm_update_empr(struct ice_hw *hw) 1254 1254 { 1255 1255 - struct ice_aq_desc desc; 1255 1255 + struct libie_aq_desc desc; 1256 1256 1257 1257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr); 1258 1258 ··· 1278 1278 u16 length, struct ice_sq_cd *cd) 1279 1279 { 1280 1280 struct ice_aqc_nvm_pkg_data *cmd; 1281 1281 - struct ice_aq_desc desc; 1281 1281 + struct libie_aq_desc desc; 1282 1282 1283 1283 if (length != 0 && !data) 1284 1284 return -EINVAL; 1285 1285 1286 1286 - cmd = &desc.params.pkg_data; 1286 1286 + cmd = libie_aq_raw(&desc); 1287 1287 1288 1288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data); 1289 1289 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1289 1289 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1290 1290 1291 1291 if (del_pkg_data_flag) 1292 1292 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE; ··· 1316 1316 u8 *comp_response_code, struct ice_sq_cd *cd) 1317 1317 { 1318 1318 struct ice_aqc_nvm_pass_comp_tbl *cmd; 1319 1319 - struct ice_aq_desc desc; 1319 1319 + struct libie_aq_desc desc; 1320 1320 int status; 1321 1321 1322 1322 if (!data || !comp_response || !comp_response_code) 1323 1323 return -EINVAL; 1324 1324 1325 1325 - cmd = &desc.params.pass_comp_tbl; 1325 1325 + cmd = libie_aq_raw(&desc); 1326 1326 1327 1327 ice_fill_dflt_direct_cmd_desc(&desc, 1328 1328 ice_aqc_opc_nvm_pass_component_tbl); 1329 1329 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1329 1329 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1330 1330 1331 1331 cmd->transfer_flag = transfer_flag; 1332 1332 status = ice_aq_send_cmd(hw, &desc, data, length, cd);

+8 -8

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

reviewed

··· 424 424 }; 425 425 int err; 426 426 427 427 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 427 427 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 428 428 if (err) 429 429 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 430 430 err); ··· 451 451 }; 452 452 int err; 453 453 454 454 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 454 454 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 455 455 if (err) 456 456 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 457 457 err); ··· 2348 2348 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2349 2349 msg.opcode = ice_sbq_msg_rd; 2350 2350 2351 2351 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2351 2351 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2352 2352 if (err) { 2353 2353 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2354 2354 err); ··· 2426 2426 msg.opcode = ice_sbq_msg_wr; 2427 2427 msg.data = val; 2428 2428 2429 2429 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2429 2429 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2430 2430 if (err) { 2431 2431 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2432 2432 err); ··· 2587 2587 2588 2588 msg.opcode = ice_sbq_msg_rd; 2589 2589 2590 2590 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2590 2590 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2591 2591 if (err) { 2592 2592 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2593 2593 err); ··· 2622 2622 msg.opcode = ice_sbq_msg_wr; 2623 2623 msg.data = val; 2624 2624 2625 2625 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2625 2625 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2626 2626 if (err) { 2627 2627 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2628 2628 err); ··· 4267 4267 msg.opcode = ice_sbq_msg_rd; 4268 4268 msg.dest_dev = ice_sbq_dev_phy_0; 4269 4269 4270 4270 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4270 4270 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4271 4271 if (err) { 4272 4272 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4273 4273 err); ··· 4298 4298 msg.dest_dev = ice_sbq_dev_phy_0; 4299 4299 msg.data = val; 4300 4300 4301 4301 - err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4301 4301 + err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4302 4302 if (err) { 4303 4303 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4304 4304 err);

+9 -9

drivers/net/ethernet/intel/ice/ice_sched.c

reviewed

··· 123 123 u16 *elems_resp, struct ice_sq_cd *cd) 124 124 { 125 125 struct ice_aqc_sched_elem_cmd *cmd; 126 126 - struct ice_aq_desc desc; 126 126 + struct libie_aq_desc desc; 127 127 int status; 128 128 129 129 - cmd = &desc.params.sched_elem_cmd; 129 129 + cmd = libie_aq_raw(&desc); 130 130 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc); 131 131 cmd->num_elem_req = cpu_to_le16(elems_req); 132 132 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 132 132 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 133 133 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 134 134 if (!status && elems_resp) 135 135 *elems_resp = le16_to_cpu(cmd->num_elem_resp); ··· 392 392 u8 *num_branches, struct ice_sq_cd *cd) 393 393 { 394 394 struct ice_aqc_get_topo *cmd; 395 395 - struct ice_aq_desc desc; 395 395 + struct libie_aq_desc desc; 396 396 int status; 397 397 398 398 - cmd = &desc.params.get_topo; 398 398 + cmd = libie_aq_raw(&desc); 399 399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo); 400 400 cmd->port_num = lport; 401 401 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); ··· 518 518 struct ice_aqc_query_txsched_res_resp *buf, 519 519 struct ice_sq_cd *cd) 520 520 { 521 521 - struct ice_aq_desc desc; 521 521 + struct libie_aq_desc desc; 522 522 523 523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res); 524 524 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); ··· 683 683 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd) 684 684 { 685 685 struct ice_aqc_rl_profile *cmd; 686 686 - struct ice_aq_desc desc; 686 686 + struct libie_aq_desc desc; 687 687 int status; 688 688 689 689 - cmd = &desc.params.rl_profile; 689 689 + cmd = libie_aq_raw(&desc); 690 690 691 691 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 692 692 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 692 692 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 693 693 cmd->num_profiles = cpu_to_le16(num_profiles); 694 694 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 695 695 if (!status && num_processed)

+3 -1

drivers/net/ethernet/intel/ice/ice_sriov.c

reviewed

··· 1161 1161 void 1162 1162 ice_vf_lan_overflow_event(struct ice_pf *pf, struct ice_rq_event_info *event) 1163 1163 { 1164 1164 + struct ice_aqc_event_lan_overflow *cmd; 1164 1165 u32 gldcb_rtctq, queue; 1165 1166 struct ice_vf *vf; 1166 1167 1167 1167 - gldcb_rtctq = le32_to_cpu(event->desc.params.lan_overflow.prtdcb_ruptq); 1168 1168 + cmd = libie_aq_raw(&event->desc); 1169 1169 + gldcb_rtctq = le32_to_cpu(cmd->prtdcb_ruptq); 1168 1170 dev_dbg(ice_pf_to_dev(pf), "GLDCB_RTCTQ: 0x%08x\n", gldcb_rtctq); 1169 1171 1170 1172 /* event returns device global Rx queue number */

+28 -27

drivers/net/ethernet/intel/ice/ice_switch.c

reviewed

··· 1511 1511 struct ice_sq_cd *cd) 1512 1512 { 1513 1513 struct ice_aqc_get_sw_cfg *cmd; 1514 1514 - struct ice_aq_desc desc; 1514 1514 + struct libie_aq_desc desc; 1515 1515 int status; 1516 1516 1517 1517 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sw_cfg); 1518 1518 - cmd = &desc.params.get_sw_conf; 1518 1518 + cmd = libie_aq_raw(&desc); 1519 1519 cmd->element = cpu_to_le16(*req_desc); 1520 1520 1521 1521 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); ··· 1541 1541 { 1542 1542 struct ice_aqc_add_update_free_vsi_resp *res; 1543 1543 struct ice_aqc_add_get_update_free_vsi *cmd; 1544 1544 - struct ice_aq_desc desc; 1544 1544 + struct libie_aq_desc desc; 1545 1545 int status; 1546 1546 1547 1547 - cmd = &desc.params.vsi_cmd; 1548 1548 - res = &desc.params.add_update_free_vsi_res; 1547 1547 + cmd = libie_aq_raw(&desc); 1548 1548 + res = libie_aq_raw(&desc); 1549 1549 1550 1550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_vsi); 1551 1551 ··· 1556 1556 1557 1557 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1558 1558 1559 1559 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1559 1559 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1560 1560 1561 1561 status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info, 1562 1562 sizeof(vsi_ctx->info), cd); ··· 1585 1585 { 1586 1586 struct ice_aqc_add_update_free_vsi_resp *resp; 1587 1587 struct ice_aqc_add_get_update_free_vsi *cmd; 1588 1588 - struct ice_aq_desc desc; 1588 1588 + struct libie_aq_desc desc; 1589 1589 int status; 1590 1590 1591 1591 - cmd = &desc.params.vsi_cmd; 1592 1592 - resp = &desc.params.add_update_free_vsi_res; 1591 1591 + cmd = libie_aq_raw(&desc); 1592 1592 + resp = libie_aq_raw(&desc); 1593 1593 1594 1594 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_free_vsi); 1595 1595 ··· 1620 1620 { 1621 1621 struct ice_aqc_add_update_free_vsi_resp *resp; 1622 1622 struct ice_aqc_add_get_update_free_vsi *cmd; 1623 1623 - struct ice_aq_desc desc; 1623 1623 + struct libie_aq_desc desc; 1624 1624 int status; 1625 1625 1626 1626 - cmd = &desc.params.vsi_cmd; 1627 1627 - resp = &desc.params.add_update_free_vsi_res; 1626 1626 + cmd = libie_aq_raw(&desc); 1627 1627 + resp = libie_aq_raw(&desc); 1628 1628 1629 1629 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_vsi); 1630 1630 1631 1631 cmd->vsi_num = cpu_to_le16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID); 1632 1632 1633 1633 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1633 1633 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1634 1634 1635 1635 status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info, 1636 1636 sizeof(vsi_ctx->info), cd); ··· 1944 1944 ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz, 1945 1945 u8 num_rules, enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1946 1946 { 1947 1947 - struct ice_aq_desc desc; 1947 1947 + struct ice_aqc_sw_rules *cmd; 1948 1948 + struct libie_aq_desc desc; 1948 1949 int status; 1949 1950 1950 1951 if (opc != ice_aqc_opc_add_sw_rules && ··· 1954 1953 return -EINVAL; 1955 1954 1956 1955 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1956 1956 + cmd = libie_aq_raw(&desc); 1957 1957 1958 1958 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1959 1959 - desc.params.sw_rules.num_rules_fltr_entry_index = 1960 1960 - cpu_to_le16(num_rules); 1958 1958 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1959 1959 + cmd->num_rules_fltr_entry_index = cpu_to_le16(num_rules); 1961 1960 status = ice_aq_send_cmd(hw, &desc, rule_list, rule_list_sz, cd); 1962 1961 if (opc != ice_aqc_opc_add_sw_rules && 1963 1963 - hw->adminq.sq_last_status == ICE_AQ_RC_ENOENT) 1962 1962 + hw->adminq.sq_last_status == LIBIE_AQ_RC_ENOENT) 1964 1963 status = -ENOENT; 1965 1964 1966 1965 if (!status) { ··· 1990 1989 u16 num_recipes, struct ice_sq_cd *cd) 1991 1990 { 1992 1991 struct ice_aqc_add_get_recipe *cmd; 1993 1993 - struct ice_aq_desc desc; 1992 1992 + struct libie_aq_desc desc; 1994 1993 u16 buf_size; 1995 1994 1996 1996 - cmd = &desc.params.add_get_recipe; 1995 1995 + cmd = libie_aq_raw(&desc); 1997 1996 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_recipe); 1998 1997 1999 1998 cmd->num_sub_recipes = cpu_to_le16(num_recipes); 2000 2000 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1999 1999 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2001 2000 2002 2001 buf_size = num_recipes * sizeof(*s_recipe_list); 2003 2002 ··· 2027 2026 u16 *num_recipes, u16 recipe_root, struct ice_sq_cd *cd) 2028 2027 { 2029 2028 struct ice_aqc_add_get_recipe *cmd; 2030 2030 - struct ice_aq_desc desc; 2029 2029 + struct libie_aq_desc desc; 2031 2030 u16 buf_size; 2032 2031 int status; 2033 2032 2034 2033 if (*num_recipes != ICE_MAX_NUM_RECIPES) 2035 2034 return -EINVAL; 2036 2035 2037 2037 - cmd = &desc.params.add_get_recipe; 2036 2036 + cmd = libie_aq_raw(&desc); 2038 2037 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe); 2039 2038 2040 2039 cmd->return_index = cpu_to_le16(recipe_root); ··· 2119 2118 struct ice_sq_cd *cd) 2120 2119 { 2121 2120 struct ice_aqc_recipe_to_profile *cmd; 2122 2122 - struct ice_aq_desc desc; 2121 2121 + struct libie_aq_desc desc; 2123 2122 2124 2124 - cmd = &desc.params.recipe_to_profile; 2123 2123 + cmd = libie_aq_raw(&desc); 2125 2124 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_recipe_to_profile); 2126 2125 cmd->profile_id = cpu_to_le16(profile_id); 2127 2126 /* Set the recipe ID bit in the bitmask to let the device know which ··· 2145 2144 struct ice_sq_cd *cd) 2146 2145 { 2147 2146 struct ice_aqc_recipe_to_profile *cmd; 2148 2148 - struct ice_aq_desc desc; 2147 2147 + struct libie_aq_desc desc; 2149 2148 int status; 2150 2149 2151 2151 - cmd = &desc.params.recipe_to_profile; 2150 2150 + cmd = libie_aq_raw(&desc); 2152 2151 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe_to_profile); 2153 2152 cmd->profile_id = cpu_to_le16(profile_id); 2154 2153

+3 -3

drivers/net/ethernet/intel/ice/ice_vf_mbx.c

reviewed

··· 23 23 u8 *msg, u16 msglen, struct ice_sq_cd *cd) 24 24 { 25 25 struct ice_aqc_pf_vf_msg *cmd; 26 26 - struct ice_aq_desc desc; 26 26 + struct libie_aq_desc desc; 27 27 28 28 ice_fill_dflt_direct_cmd_desc(&desc, ice_mbx_opc_send_msg_to_vf); 29 29 30 30 - cmd = &desc.params.virt; 30 30 + cmd = libie_aq_raw(&desc); 31 31 cmd->id = cpu_to_le32(vfid); 32 32 33 33 desc.cookie_high = cpu_to_le32(v_opcode); 34 34 desc.cookie_low = cpu_to_le32(v_retval); 35 35 36 36 if (msglen) 37 37 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 37 37 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 38 38 39 39 return ice_sq_send_cmd(hw, &hw->mailboxq, &desc, msg, msglen, cd); 40 40 }

+3 -3

drivers/net/ethernet/intel/ice/ice_virtchnl.c

reviewed

··· 304 304 305 305 aq_ret = ice_aq_send_msg_to_vf(&pf->hw, vf->vf_id, v_opcode, v_retval, 306 306 msg, msglen, NULL); 307 307 - if (aq_ret && pf->hw.mailboxq.sq_last_status != ICE_AQ_RC_ENOSYS) { 307 307 + if (aq_ret && pf->hw.mailboxq.sq_last_status != LIBIE_AQ_RC_ENOSYS) { 308 308 dev_info(dev, "Unable to send the message to VF %d ret %d aq_err %s\n", 309 309 vf->vf_id, aq_ret, 310 310 - ice_aq_str(pf->hw.mailboxq.sq_last_status)); 310 310 + libie_aq_str(pf->hw.mailboxq.sq_last_status)); 311 311 return -EIO; 312 312 } 313 313 ··· 852 852 status = ice_update_vsi(hw, vsi->idx, ctx, NULL); 853 853 if (status) { 854 854 dev_err(dev, "update VSI for RSS failed, err %d aq_err %s\n", 855 855 - status, ice_aq_str(hw->adminq.sq_last_status)); 855 855 + status, libie_aq_str(hw->adminq.sq_last_status)); 856 856 v_ret = VIRTCHNL_STATUS_ERR_PARAM; 857 857 } else { 858 858 vsi->info.q_opt_rss = ctx->info.q_opt_rss;

+3 -3

drivers/net/ethernet/intel/ice/ice_vlan_mode.c

reviewed

··· 63 63 ice_aq_get_vlan_mode(struct ice_hw *hw, 64 64 struct ice_aqc_get_vlan_mode *get_params) 65 65 { 66 66 - struct ice_aq_desc desc; 66 66 + struct libie_aq_desc desc; 67 67 68 68 if (!get_params) 69 69 return -EINVAL; ··· 275 275 struct ice_aqc_set_vlan_mode *set_params) 276 276 { 277 277 u8 rdma_packet, mng_vlan_prot_id; 278 278 - struct ice_aq_desc desc; 278 278 + struct libie_aq_desc desc; 279 279 280 280 if (!set_params) 281 281 return -EINVAL; ··· 295 295 296 296 ice_fill_dflt_direct_cmd_desc(&desc, 297 297 ice_aqc_opc_set_vlan_mode_parameters); 298 298 - desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 298 298 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 299 299 300 300 return ice_aq_send_cmd(hw, &desc, set_params, sizeof(*set_params), 301 301 NULL);

+12 -12

drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c

reviewed

··· 113 113 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 114 114 if (err) { 115 115 dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN insert failed, err %d aq_err %s\n", 116 116 - err, ice_aq_str(hw->adminq.sq_last_status)); 116 116 + err, libie_aq_str(hw->adminq.sq_last_status)); 117 117 goto out; 118 118 } 119 119 ··· 169 169 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 170 170 if (err) { 171 171 dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN strip failed, ena = %d err %d aq_err %s\n", 172 172 - ena, err, ice_aq_str(hw->adminq.sq_last_status)); 172 172 + ena, err, libie_aq_str(hw->adminq.sq_last_status)); 173 173 goto out; 174 174 } 175 175 ··· 258 258 ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 259 259 if (ret) { 260 260 dev_info(ice_hw_to_dev(hw), "update VSI for port VLAN failed, err %d aq_err %s\n", 261 261 - ret, ice_aq_str(hw->adminq.sq_last_status)); 261 261 + ret, libie_aq_str(hw->adminq.sq_last_status)); 262 262 goto out; 263 263 } 264 264 ··· 306 306 ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 307 307 if (ret) 308 308 dev_err(ice_hw_to_dev(hw), "update VSI for port VLAN failed, err %d aq_err %s\n", 309 309 - ret, ice_aq_str(hw->adminq.sq_last_status)); 309 309 + ret, libie_aq_str(hw->adminq.sq_last_status)); 310 310 311 311 kfree(ctxt); 312 312 return ret; ··· 353 353 if (status) { 354 354 netdev_err(vsi->netdev, "%sabling VLAN pruning on VSI handle: %d, VSI HW ID: %d failed, err = %d, aq_err = %s\n", 355 355 ena ? "En" : "Dis", vsi->idx, vsi->vsi_num, status, 356 356 - ice_aq_str(pf->hw.adminq.sq_last_status)); 356 356 + libie_aq_str(pf->hw.adminq.sq_last_status)); 357 357 goto err_out; 358 358 } 359 359 ··· 497 497 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 498 498 if (err) 499 499 dev_err(ice_pf_to_dev(vsi->back), "update VSI for enabling outer VLAN stripping failed, err %d aq_err %s\n", 500 500 - err, ice_aq_str(hw->adminq.sq_last_status)); 500 500 + err, libie_aq_str(hw->adminq.sq_last_status)); 501 501 else 502 502 vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags; 503 503 ··· 544 544 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 545 545 if (err) 546 546 dev_err(ice_pf_to_dev(vsi->back), "update VSI for disabling outer VLAN stripping failed, err %d aq_err %s\n", 547 547 - err, ice_aq_str(hw->adminq.sq_last_status)); 547 547 + err, libie_aq_str(hw->adminq.sq_last_status)); 548 548 else 549 549 vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags; 550 550 ··· 604 604 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 605 605 if (err) 606 606 dev_err(ice_pf_to_dev(vsi->back), "update VSI for enabling outer VLAN insertion failed, err %d aq_err %s\n", 607 607 - err, ice_aq_str(hw->adminq.sq_last_status)); 607 607 + err, libie_aq_str(hw->adminq.sq_last_status)); 608 608 else 609 609 vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags; 610 610 ··· 654 654 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 655 655 if (err) 656 656 dev_err(ice_pf_to_dev(vsi->back), "update VSI for disabling outer VLAN insertion failed, err %d aq_err %s\n", 657 657 - err, ice_aq_str(hw->adminq.sq_last_status)); 657 657 + err, libie_aq_str(hw->adminq.sq_last_status)); 658 658 else 659 659 vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags; 660 660 ··· 720 720 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 721 721 if (err) { 722 722 dev_err(ice_pf_to_dev(vsi->back), "update VSI for setting outer port based VLAN failed, err %d aq_err %s\n", 723 723 - err, ice_aq_str(hw->adminq.sq_last_status)); 723 723 + err, libie_aq_str(hw->adminq.sq_last_status)); 724 724 } else { 725 725 vsi->info.port_based_outer_vlan = ctxt->info.port_based_outer_vlan; 726 726 vsi->info.outer_vlan_flags = ctxt->info.outer_vlan_flags; ··· 782 782 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 783 783 if (err) 784 784 dev_err(ice_pf_to_dev(vsi->back), "update VSI for clearing outer port based VLAN failed, err %d aq_err %s\n", 785 785 - err, ice_aq_str(hw->adminq.sq_last_status)); 785 785 + err, libie_aq_str(hw->adminq.sq_last_status)); 786 786 787 787 kfree(ctxt); 788 788 return err; ··· 830 830 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 831 831 if (err) { 832 832 dev_err(ice_pf_to_dev(vsi->back), "update VSI for clearing port based VLAN failed, err %d aq_err %s\n", 833 833 - err, ice_aq_str(hw->adminq.sq_last_status)); 833 833 + err, libie_aq_str(hw->adminq.sq_last_status)); 834 834 } else { 835 835 vsi->info.port_based_outer_vlan = 836 836 ctxt->info.port_based_outer_vlan;

+2 -2

drivers/net/ethernet/intel/ixgbe/devlink/region.c

reviewed

··· 74 74 * total period of reading whole NVM is longer than the maximum 75 75 * period the lock can be taken defined by the IXGBE_NVM_TIMEOUT. 76 76 */ 77 77 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 77 77 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 78 78 if (err) { 79 79 NL_SET_ERR_MSG_MOD(extack, 80 80 "Failed to acquire NVM semaphore"); ··· 184 184 return -ERANGE; 185 185 } 186 186 187 187 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 187 187 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 188 188 if (err) { 189 189 NL_SET_ERR_MSG_MOD(extack, "Failed to acquire NVM semaphore"); 190 190 return -EBUSY;

+137 -135

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

reviewed

··· 56 56 * Admin Command failed with error Y. 57 57 */ 58 58 static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, 59 59 - struct ixgbe_aci_desc *desc, 59 59 + struct libie_aq_desc *desc, 60 60 void *buf, u16 buf_size) 61 61 { 62 62 u16 opcode, buf_tail_size = buf_size % 4; ··· 64 64 u32 hicr, i, buf_tail = 0; 65 65 bool valid_buf = false; 66 66 67 67 - hw->aci.last_status = IXGBE_ACI_RC_OK; 67 67 + hw->aci.last_status = LIBIE_AQ_RC_OK; 68 68 69 69 /* It's necessary to check if mechanism is enabled */ 70 70 hicr = IXGBE_READ_REG(hw, IXGBE_PF_HICR); ··· 73 73 return -EIO; 74 74 75 75 if (hicr & IXGBE_PF_HICR_C) { 76 76 - hw->aci.last_status = IXGBE_ACI_RC_EBUSY; 76 76 + hw->aci.last_status = LIBIE_AQ_RC_EBUSY; 77 77 return -EBUSY; 78 78 } 79 79 ··· 83 83 return -EINVAL; 84 84 85 85 if (buf) 86 86 - desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_BUF); 86 86 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 87 87 88 88 - if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_BUF)) { 88 88 + if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_BUF)) { 89 89 if ((buf && !buf_size) || 90 90 (!buf && buf_size)) 91 91 return -EINVAL; ··· 98 98 memcpy(&buf_tail, buf + buf_size - buf_tail_size, 99 99 buf_tail_size); 100 100 101 101 - if (((buf_size + 3) & ~0x3) > IXGBE_ACI_LG_BUF) 102 102 - desc->flags |= cpu_to_le16(IXGBE_ACI_FLAG_LB); 101 101 + if (((buf_size + 3) & ~0x3) > LIBIE_AQ_LG_BUF) 102 102 + desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 103 103 104 104 desc->datalen = cpu_to_le16(buf_size); 105 105 106 106 - if (desc->flags & cpu_to_le16(IXGBE_ACI_FLAG_RD)) { 106 106 + if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_RD)) { 107 107 for (i = 0; i < buf_size / 4; i++) 108 108 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]); 109 109 if (buf_tail_size) ··· 174 174 return -EIO; 175 175 176 176 if (desc->retval) { 177 177 - hw->aci.last_status = (enum ixgbe_aci_err) 177 177 + hw->aci.last_status = (enum libie_aq_err) 178 178 le16_to_cpu(desc->retval); 179 179 return -EIO; 180 180 } ··· 207 207 * 208 208 * Return: the exit code of the operation. 209 209 */ 210 210 - int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc, 210 210 + int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc, 211 211 void *buf, u16 buf_size) 212 212 { 213 213 u16 opcode = le16_to_cpu(desc->opcode); 214 214 - struct ixgbe_aci_desc desc_cpy; 215 215 - enum ixgbe_aci_err last_status; 214 214 + struct libie_aq_desc desc_cpy; 215 215 + enum libie_aq_err last_status; 216 216 u8 idx = 0, *buf_cpy = NULL; 217 217 bool is_cmd_for_retry; 218 218 unsigned long timeout; ··· 237 237 mutex_unlock(&hw->aci.lock); 238 238 239 239 if (!is_cmd_for_retry || !err || 240 240 - last_status != IXGBE_ACI_RC_EBUSY) 240 240 + last_status != LIBIE_AQ_RC_EBUSY) 241 241 break; 242 242 243 243 if (buf) ··· 286 286 int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e, 287 287 bool *pending) 288 288 { 289 289 - struct ixgbe_aci_desc desc; 289 289 + struct libie_aq_desc desc; 290 290 int err; 291 291 292 292 if (!e || (!e->msg_buf && e->buf_len)) ··· 335 335 * Helper function to fill the descriptor desc with default values 336 336 * and the provided opcode. 337 337 */ 338 338 - void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode) 338 338 + void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode) 339 339 { 340 340 /* Zero out the desc. */ 341 341 memset(desc, 0, sizeof(*desc)); 342 342 desc->opcode = cpu_to_le16(opcode); 343 343 - desc->flags = cpu_to_le16(IXGBE_ACI_FLAG_SI); 343 343 + desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 344 344 } 345 345 346 346 /** ··· 353 353 */ 354 354 static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw) 355 355 { 356 356 - struct ixgbe_aci_cmd_get_ver *resp; 357 357 - struct ixgbe_aci_desc desc; 356 356 + struct libie_aqc_get_ver *resp; 357 357 + struct libie_aq_desc desc; 358 358 int err; 359 359 360 360 resp = &desc.params.get_ver; ··· 393 393 * 394 394 * Return: the exit code of the operation. 395 395 */ 396 396 - static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res, 397 397 - enum ixgbe_aci_res_access_type access, 396 396 + static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 397 397 + enum libie_aq_res_access_type access, 398 398 u8 sdp_number, u32 *timeout) 399 399 { 400 400 - struct ixgbe_aci_cmd_req_res *cmd_resp; 401 401 - struct ixgbe_aci_desc desc; 400 400 + struct libie_aqc_req_res *cmd_resp; 401 401 + struct libie_aq_desc desc; 402 402 int err; 403 403 404 404 cmd_resp = &desc.params.res_owner; ··· 417 417 * with a busy return value and the timeout field indicates the maximum 418 418 * time the current owner of the resource has to free it. 419 419 */ 420 420 - if (!err || hw->aci.last_status == IXGBE_ACI_RC_EBUSY) 420 420 + if (!err || hw->aci.last_status == LIBIE_AQ_RC_EBUSY) 421 421 *timeout = le32_to_cpu(cmd_resp->timeout); 422 422 423 423 return err; ··· 433 433 * 434 434 * Return: the exit code of the operation. 435 435 */ 436 436 - static int ixgbe_aci_release_res(struct ixgbe_hw *hw, 437 437 - enum ixgbe_aci_res_ids res, u8 sdp_number) 436 436 + static int ixgbe_aci_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 437 437 + u8 sdp_number) 438 438 { 439 439 - struct ixgbe_aci_cmd_req_res *cmd; 440 440 - struct ixgbe_aci_desc desc; 439 439 + struct libie_aqc_req_res *cmd; 440 440 + struct libie_aq_desc desc; 441 441 442 442 cmd = &desc.params.res_owner; 443 443 ··· 465 465 * 466 466 * Return: the exit code of the operation. 467 467 */ 468 468 - int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res, 469 469 - enum ixgbe_aci_res_access_type access, u32 timeout) 468 468 + int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 469 469 + enum libie_aq_res_access_type access, u32 timeout) 470 470 { 471 471 #define IXGBE_RES_POLLING_DELAY_MS 10 472 472 u32 delay = IXGBE_RES_POLLING_DELAY_MS; ··· 514 514 * 515 515 * Release a common resource using ixgbe_aci_release_res. 516 516 */ 517 517 - void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res) 517 517 + void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res) 518 518 { 519 519 u32 total_delay = 0; 520 520 int err; ··· 547 547 */ 548 548 static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw, 549 549 struct ixgbe_hw_caps *caps, 550 550 - struct ixgbe_aci_cmd_list_caps_elem *elem, 550 550 + struct libie_aqc_list_caps_elem *elem, 551 551 const char *prefix) 552 552 { 553 553 u32 logical_id = le32_to_cpu(elem->logical_id); ··· 556 556 u16 cap = le16_to_cpu(elem->cap); 557 557 558 558 switch (cap) { 559 559 - case IXGBE_ACI_CAPS_VALID_FUNCTIONS: 559 559 + case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 560 560 caps->valid_functions = number; 561 561 break; 562 562 - case IXGBE_ACI_CAPS_SRIOV: 562 562 + case LIBIE_AQC_CAPS_SRIOV: 563 563 caps->sr_iov_1_1 = (number == 1); 564 564 break; 565 565 - case IXGBE_ACI_CAPS_VMDQ: 565 565 + case LIBIE_AQC_CAPS_VMDQ: 566 566 caps->vmdq = (number == 1); 567 567 break; 568 568 - case IXGBE_ACI_CAPS_DCB: 568 568 + case LIBIE_AQC_CAPS_DCB: 569 569 caps->dcb = (number == 1); 570 570 caps->active_tc_bitmap = logical_id; 571 571 caps->maxtc = phys_id; 572 572 break; 573 573 - case IXGBE_ACI_CAPS_RSS: 573 573 + case LIBIE_AQC_CAPS_RSS: 574 574 caps->rss_table_size = number; 575 575 caps->rss_table_entry_width = logical_id; 576 576 break; 577 577 - case IXGBE_ACI_CAPS_RXQS: 577 577 + case LIBIE_AQC_CAPS_RXQS: 578 578 caps->num_rxq = number; 579 579 caps->rxq_first_id = phys_id; 580 580 break; 581 581 - case IXGBE_ACI_CAPS_TXQS: 581 581 + case LIBIE_AQC_CAPS_TXQS: 582 582 caps->num_txq = number; 583 583 caps->txq_first_id = phys_id; 584 584 break; 585 585 - case IXGBE_ACI_CAPS_MSIX: 585 585 + case LIBIE_AQC_CAPS_MSIX: 586 586 caps->num_msix_vectors = number; 587 587 caps->msix_vector_first_id = phys_id; 588 588 break; 589 589 - case IXGBE_ACI_CAPS_NVM_VER: 589 589 + case LIBIE_AQC_CAPS_NVM_VER: 590 590 break; 591 591 - case IXGBE_ACI_CAPS_PENDING_NVM_VER: 591 591 + case LIBIE_AQC_CAPS_PENDING_NVM_VER: 592 592 caps->nvm_update_pending_nvm = true; 593 593 break; 594 594 - case IXGBE_ACI_CAPS_PENDING_OROM_VER: 594 594 + case LIBIE_AQC_CAPS_PENDING_OROM_VER: 595 595 caps->nvm_update_pending_orom = true; 596 596 break; 597 597 - case IXGBE_ACI_CAPS_PENDING_NET_VER: 597 597 + case LIBIE_AQC_CAPS_PENDING_NET_VER: 598 598 caps->nvm_update_pending_netlist = true; 599 599 break; 600 600 - case IXGBE_ACI_CAPS_NVM_MGMT: 600 600 + case LIBIE_AQC_CAPS_NVM_MGMT: 601 601 caps->nvm_unified_update = 602 602 (number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 603 603 true : false; 604 604 break; 605 605 - case IXGBE_ACI_CAPS_MAX_MTU: 605 605 + case LIBIE_AQC_CAPS_MAX_MTU: 606 606 caps->max_mtu = number; 607 607 break; 608 608 - case IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE: 608 608 + case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 609 609 caps->pcie_reset_avoidance = (number > 0); 610 610 break; 611 611 - case IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT: 611 611 + case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 612 612 caps->reset_restrict_support = (number == 1); 613 613 break; 614 614 - case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0: 615 615 - case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1: 616 616 - case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2: 617 617 - case IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3: 614 614 + case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 615 615 + case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 616 616 + case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 617 617 + case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 618 618 { 619 619 - u8 index = cap - IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0; 619 619 + u8 index = cap - LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 620 620 621 621 caps->ext_topo_dev_img_ver_high[index] = number; 622 622 caps->ext_topo_dev_img_ver_low[index] = logical_id; ··· 637 637 } 638 638 639 639 /** 640 640 - * ixgbe_parse_valid_functions_cap - Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS caps 640 640 + * ixgbe_parse_valid_functions_cap - Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS caps 641 641 * @hw: pointer to the HW struct 642 642 * @dev_p: pointer to device capabilities structure 643 643 * @cap: capability element to parse 644 644 * 645 645 - * Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS for device capabilities. 645 645 + * Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 646 646 */ 647 647 static void 648 648 ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw, 649 649 struct ixgbe_hw_dev_caps *dev_p, 650 650 - struct ixgbe_aci_cmd_list_caps_elem *cap) 650 650 + struct libie_aqc_list_caps_elem *cap) 651 651 { 652 652 dev_p->num_funcs = hweight32(le32_to_cpu(cap->number)); 653 653 } 654 654 655 655 /** 656 656 - * ixgbe_parse_vf_dev_caps - Parse IXGBE_ACI_CAPS_VF device caps 656 656 + * ixgbe_parse_vf_dev_caps - Parse LIBIE_AQC_CAPS_VF device caps 657 657 * @hw: pointer to the HW struct 658 658 * @dev_p: pointer to device capabilities structure 659 659 * @cap: capability element to parse 660 660 * 661 661 - * Parse IXGBE_ACI_CAPS_VF for device capabilities. 661 661 + * Parse LIBIE_AQC_CAPS_VF for device capabilities. 662 662 */ 663 663 static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw, 664 664 struct ixgbe_hw_dev_caps *dev_p, 665 665 - struct ixgbe_aci_cmd_list_caps_elem *cap) 665 665 + struct libie_aqc_list_caps_elem *cap) 666 666 { 667 667 dev_p->num_vfs_exposed = le32_to_cpu(cap->number); 668 668 } 669 669 670 670 /** 671 671 - * ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps 671 671 + * ixgbe_parse_vsi_dev_caps - Parse LIBIE_AQC_CAPS_VSI device caps 672 672 * @hw: pointer to the HW struct 673 673 * @dev_p: pointer to device capabilities structure 674 674 * @cap: capability element to parse 675 675 * 676 676 - * Parse IXGBE_ACI_CAPS_VSI for device capabilities. 676 676 + * Parse LIBIE_AQC_CAPS_VSI for device capabilities. 677 677 */ 678 678 static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw, 679 679 struct ixgbe_hw_dev_caps *dev_p, 680 680 - struct ixgbe_aci_cmd_list_caps_elem *cap) 680 680 + struct libie_aqc_list_caps_elem *cap) 681 681 { 682 682 dev_p->num_vsi_allocd_to_host = le32_to_cpu(cap->number); 683 683 } 684 684 685 685 /** 686 686 - * ixgbe_parse_fdir_dev_caps - Parse IXGBE_ACI_CAPS_FD device caps 686 686 + * ixgbe_parse_fdir_dev_caps - Parse LIBIE_AQC_CAPS_FD device caps 687 687 * @hw: pointer to the HW struct 688 688 * @dev_p: pointer to device capabilities structure 689 689 * @cap: capability element to parse 690 690 * 691 691 - * Parse IXGBE_ACI_CAPS_FD for device capabilities. 691 691 + * Parse LIBIE_AQC_CAPS_FD for device capabilities. 692 692 */ 693 693 static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw, 694 694 struct ixgbe_hw_dev_caps *dev_p, 695 695 - struct ixgbe_aci_cmd_list_caps_elem *cap) 695 695 + struct libie_aqc_list_caps_elem *cap) 696 696 { 697 697 dev_p->num_flow_director_fltr = le32_to_cpu(cap->number); 698 698 } ··· 715 715 struct ixgbe_hw_dev_caps *dev_p, 716 716 void *buf, u32 cap_count) 717 717 { 718 718 - struct ixgbe_aci_cmd_list_caps_elem *cap_resp; 718 718 + struct libie_aqc_list_caps_elem *cap_resp; 719 719 u32 i; 720 720 721 721 - cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf; 721 721 + cap_resp = (struct libie_aqc_list_caps_elem *)buf; 722 722 723 723 memset(dev_p, 0, sizeof(*dev_p)); 724 724 ··· 729 729 "dev caps"); 730 730 731 731 switch (cap) { 732 732 - case IXGBE_ACI_CAPS_VALID_FUNCTIONS: 732 732 + case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 733 733 ixgbe_parse_valid_functions_cap(hw, dev_p, 734 734 &cap_resp[i]); 735 735 break; 736 736 - case IXGBE_ACI_CAPS_VF: 736 736 + case LIBIE_AQC_CAPS_VF: 737 737 ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 738 738 break; 739 739 - case IXGBE_ACI_CAPS_VSI: 739 739 + case LIBIE_AQC_CAPS_VSI: 740 740 ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 741 741 break; 742 742 - case IXGBE_ACI_CAPS_FD: 742 742 + case LIBIE_AQC_CAPS_FD: 743 743 ixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 744 744 break; 745 745 default: ··· 750 750 } 751 751 752 752 /** 753 753 - * ixgbe_parse_vf_func_caps - Parse IXGBE_ACI_CAPS_VF function caps 753 753 + * ixgbe_parse_vf_func_caps - Parse LIBIE_AQC_CAPS_VF function caps 754 754 * @hw: pointer to the HW struct 755 755 * @func_p: pointer to function capabilities structure 756 756 * @cap: pointer to the capability element to parse 757 757 * 758 758 - * Extract function capabilities for IXGBE_ACI_CAPS_VF. 758 758 + * Extract function capabilities for LIBIE_AQC_CAPS_VF. 759 759 */ 760 760 static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw, 761 761 struct ixgbe_hw_func_caps *func_p, 762 762 - struct ixgbe_aci_cmd_list_caps_elem *cap) 762 762 + struct libie_aqc_list_caps_elem *cap) 763 763 { 764 764 func_p->num_allocd_vfs = le32_to_cpu(cap->number); 765 765 func_p->vf_base_id = le32_to_cpu(cap->logical_id); ··· 786 786 } 787 787 788 788 /** 789 789 - * ixgbe_parse_vsi_func_caps - Parse IXGBE_ACI_CAPS_VSI function caps 789 789 + * ixgbe_parse_vsi_func_caps - Parse LIBIE_AQC_CAPS_VSI function caps 790 790 * @hw: pointer to the HW struct 791 791 * @func_p: pointer to function capabilities structure 792 792 * @cap: pointer to the capability element to parse 793 793 * 794 794 - * Extract function capabilities for IXGBE_ACI_CAPS_VSI. 794 794 + * Extract function capabilities for LIBIE_AQC_CAPS_VSI. 795 795 */ 796 796 static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw, 797 797 struct ixgbe_hw_func_caps *func_p, 798 798 - struct ixgbe_aci_cmd_list_caps_elem *cap) 798 798 + struct libie_aqc_list_caps_elem *cap) 799 799 { 800 800 func_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI); 801 801 } ··· 818 818 struct ixgbe_hw_func_caps *func_p, 819 819 void *buf, u32 cap_count) 820 820 { 821 821 - struct ixgbe_aci_cmd_list_caps_elem *cap_resp; 821 821 + struct libie_aqc_list_caps_elem *cap_resp; 822 822 u32 i; 823 823 824 824 - cap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf; 824 824 + cap_resp = (struct libie_aqc_list_caps_elem *)buf; 825 825 826 826 memset(func_p, 0, sizeof(*func_p)); 827 827 ··· 832 832 &cap_resp[i], "func caps"); 833 833 834 834 switch (cap) { 835 835 - case IXGBE_ACI_CAPS_VF: 835 835 + case LIBIE_AQC_CAPS_VF: 836 836 ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 837 837 break; 838 838 - case IXGBE_ACI_CAPS_VSI: 838 838 + case LIBIE_AQC_CAPS_VSI: 839 839 ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 840 840 break; 841 841 default: ··· 869 869 int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size, 870 870 u32 *cap_count, enum ixgbe_aci_opc opc) 871 871 { 872 872 - struct ixgbe_aci_cmd_list_caps *cmd; 873 873 - struct ixgbe_aci_desc desc; 872 872 + struct libie_aqc_list_caps *cmd; 873 873 + struct libie_aq_desc desc; 874 874 int err; 875 875 876 876 cmd = &desc.params.get_cap; ··· 914 914 * possible size that firmware can return. 915 915 */ 916 916 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 917 917 - sizeof(struct ixgbe_aci_cmd_list_caps_elem); 917 917 + sizeof(struct libie_aqc_list_caps_elem); 918 918 919 919 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 920 920 &cap_count, ··· 953 953 * possible size that firmware can return. 954 954 */ 955 955 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 956 956 - sizeof(struct ixgbe_aci_cmd_list_caps_elem); 956 956 + sizeof(struct libie_aqc_list_caps_elem); 957 957 958 958 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 959 959 &cap_count, ··· 996 996 int ixgbe_aci_disable_rxen(struct ixgbe_hw *hw) 997 997 { 998 998 struct ixgbe_aci_cmd_disable_rxen *cmd; 999 999 - struct ixgbe_aci_desc desc; 999 999 + struct libie_aq_desc desc; 1000 1000 1001 1001 - cmd = &desc.params.disable_rxen; 1001 1001 + cmd = libie_aq_raw(&desc); 1002 1002 1003 1003 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen); 1004 1004 ··· 1024 1024 { 1025 1025 struct ixgbe_aci_cmd_get_phy_caps *cmd; 1026 1026 u16 pcaps_size = sizeof(*pcaps); 1027 1027 - struct ixgbe_aci_desc desc; 1027 1027 + struct libie_aq_desc desc; 1028 1028 int err; 1029 1029 1030 1030 - cmd = &desc.params.get_phy; 1030 1030 + cmd = libie_aq_raw(&desc); 1031 1031 1032 1032 if (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M)) 1033 1033 return -EINVAL; ··· 1091 1091 int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, 1092 1092 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1093 1093 { 1094 1094 - struct ixgbe_aci_desc desc; 1094 1094 + struct ixgbe_aci_cmd_set_phy_cfg *cmd; 1095 1095 + struct libie_aq_desc desc; 1095 1096 int err; 1096 1097 1097 1098 if (!cfg) 1098 1099 return -EINVAL; 1099 1100 1101 1101 + cmd = libie_aq_raw(&desc); 1100 1102 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1101 1103 cfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK; 1102 1104 1103 1105 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg); 1104 1104 - desc.params.set_phy.lport_num = hw->bus.func; 1105 1105 - desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 1106 1106 + cmd->lport_num = hw->bus.func; 1107 1107 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1106 1108 1107 1109 err = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg)); 1108 1110 if (!err) ··· 1125 1123 int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link) 1126 1124 { 1127 1125 struct ixgbe_aci_cmd_restart_an *cmd; 1128 1128 - struct ixgbe_aci_desc desc; 1126 1126 + struct libie_aq_desc desc; 1129 1127 1130 1130 - cmd = &desc.params.restart_an; 1128 1128 + cmd = libie_aq_raw(&desc); 1131 1129 1132 1130 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an); 1133 1131 ··· 1153 1151 static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw) 1154 1152 { 1155 1153 struct ixgbe_aci_cmd_get_link_topo *cmd; 1156 1156 - struct ixgbe_aci_desc desc; 1154 1154 + struct libie_aq_desc desc; 1157 1155 1158 1158 - cmd = &desc.params.get_link_topo; 1156 1156 + cmd = libie_aq_raw(&desc); 1159 1157 1160 1158 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 1161 1159 ··· 1348 1346 struct ixgbe_aci_cmd_get_link_status *resp; 1349 1347 struct ixgbe_link_status *li_old, *li; 1350 1348 struct ixgbe_fc_info *hw_fc_info; 1351 1351 - struct ixgbe_aci_desc desc; 1349 1349 + struct libie_aq_desc desc; 1352 1350 bool tx_pause, rx_pause; 1353 1351 u8 cmd_flags; 1354 1352 int err; ··· 1362 1360 1363 1361 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status); 1364 1362 cmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS; 1365 1365 - resp = &desc.params.get_link_status; 1363 1363 + resp = libie_aq_raw(&desc); 1366 1364 resp->cmd_flags = cpu_to_le16(cmd_flags); 1367 1365 resp->lport_num = hw->bus.func; 1368 1366 ··· 1425 1423 int ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask) 1426 1424 { 1427 1425 struct ixgbe_aci_cmd_set_event_mask *cmd; 1428 1428 - struct ixgbe_aci_desc desc; 1426 1426 + struct libie_aq_desc desc; 1429 1427 1430 1430 - cmd = &desc.params.set_event_mask; 1428 1428 + cmd = libie_aq_raw(&desc); 1431 1429 1432 1430 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask); 1433 1431 ··· 1498 1496 int ixgbe_aci_set_port_id_led(struct ixgbe_hw *hw, bool orig_mode) 1499 1497 { 1500 1498 struct ixgbe_aci_cmd_set_port_id_led *cmd; 1501 1501 - struct ixgbe_aci_desc desc; 1499 1499 + struct libie_aq_desc desc; 1502 1500 1503 1503 - cmd = &desc.params.set_port_id_led; 1501 1501 + cmd = libie_aq_raw(&desc); 1504 1502 1505 1503 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_port_id_led); 1506 1504 ··· 2262 2260 struct ixgbe_aci_cmd_get_link_topo *cmd, 2263 2261 u8 *node_part_number, u16 *node_handle) 2264 2262 { 2265 2265 - struct ixgbe_aci_desc desc; 2263 2263 + struct ixgbe_aci_cmd_get_link_topo *resp; 2264 2264 + struct libie_aq_desc desc; 2266 2265 2267 2266 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 2268 2268 - desc.params.get_link_topo = *cmd; 2267 2267 + resp = libie_aq_raw(&desc); 2268 2268 + *resp = *cmd; 2269 2269 2270 2270 if (ixgbe_aci_send_cmd(hw, &desc, NULL, 0)) 2271 2271 return -EOPNOTSUPP; 2272 2272 2273 2273 if (node_handle) 2274 2274 - *node_handle = 2275 2275 - le16_to_cpu(desc.params.get_link_topo.addr.handle); 2274 2274 + *node_handle = le16_to_cpu(resp->addr.handle); 2276 2275 if (node_part_number) 2277 2277 - *node_part_number = desc.params.get_link_topo.node_part_num; 2276 2276 + *node_part_number = resp->node_part_num; 2278 2277 2279 2278 return 0; 2280 2279 } ··· 2289 2286 * 2290 2287 * Return: the exit code of the operation. 2291 2288 */ 2292 2292 - int ixgbe_acquire_nvm(struct ixgbe_hw *hw, 2293 2293 - enum ixgbe_aci_res_access_type access) 2289 2289 + int ixgbe_acquire_nvm(struct ixgbe_hw *hw, enum libie_aq_res_access_type access) 2294 2290 { 2295 2291 u32 fla; 2296 2292 ··· 2298 2296 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2299 2297 return 0; 2300 2298 2301 2301 - return ixgbe_acquire_res(hw, IXGBE_NVM_RES_ID, access, 2299 2299 + return ixgbe_acquire_res(hw, LIBIE_AQC_RES_ID_NVM, access, 2302 2300 IXGBE_NVM_TIMEOUT); 2303 2301 } 2304 2302 ··· 2317 2315 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2318 2316 return; 2319 2317 2320 2320 - ixgbe_release_res(hw, IXGBE_NVM_RES_ID); 2318 2318 + ixgbe_release_res(hw, LIBIE_AQC_RES_ID_NVM); 2321 2319 } 2322 2320 2323 2321 /** ··· 2339 2337 bool read_shadow_ram) 2340 2338 { 2341 2339 struct ixgbe_aci_cmd_nvm *cmd; 2342 2342 - struct ixgbe_aci_desc desc; 2340 2340 + struct libie_aq_desc desc; 2343 2341 2344 2342 if (offset > IXGBE_ACI_NVM_MAX_OFFSET) 2345 2343 return -EINVAL; 2346 2344 2347 2347 - cmd = &desc.params.nvm; 2345 2345 + cmd = libie_aq_raw(&desc); 2348 2346 2349 2347 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read); 2350 2348 ··· 2374 2372 int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid) 2375 2373 { 2376 2374 struct ixgbe_aci_cmd_nvm *cmd; 2377 2377 - struct ixgbe_aci_desc desc; 2375 2375 + struct libie_aq_desc desc; 2378 2376 __le16 len; 2379 2377 int err; 2380 2378 ··· 2387 2385 if (err) 2388 2386 return err; 2389 2387 2390 2390 - cmd = &desc.params.nvm; 2388 2388 + cmd = libie_aq_raw(&desc); 2391 2389 2392 2390 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_erase); 2393 2391 ··· 2418 2416 bool last_command, u8 command_flags) 2419 2417 { 2420 2418 struct ixgbe_aci_cmd_nvm *cmd; 2421 2421 - struct ixgbe_aci_desc desc; 2419 2419 + struct libie_aq_desc desc; 2422 2420 2423 2423 - cmd = &desc.params.nvm; 2421 2421 + cmd = libie_aq_raw(&desc); 2424 2422 2425 2423 /* In offset the highest byte must be zeroed. */ 2426 2424 if (offset & 0xFF000000) ··· 2438 2436 cmd->offset_high = FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_U_MASK, offset); 2439 2437 cmd->length = cpu_to_le16(length); 2440 2438 2441 2441 - desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 2439 2439 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2442 2440 2443 2441 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2444 2442 } ··· 2469 2467 u8 *response_flags) 2470 2468 { 2471 2469 struct ixgbe_aci_cmd_nvm *cmd; 2472 2472 - struct ixgbe_aci_desc desc; 2470 2470 + struct libie_aq_desc desc; 2473 2471 s32 err; 2474 2472 2475 2475 - cmd = &desc.params.nvm; 2473 2473 + cmd = libie_aq_raw(&desc); 2476 2474 ixgbe_fill_dflt_direct_cmd_desc(&desc, 2477 2475 ixgbe_aci_opc_nvm_write_activate); 2478 2476 ··· 2500 2498 int ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw) 2501 2499 { 2502 2500 struct ixgbe_aci_cmd_nvm_checksum *cmd; 2503 2503 - struct ixgbe_aci_desc desc; 2501 2501 + struct libie_aq_desc desc; 2504 2502 int err; 2505 2503 2506 2506 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2504 2504 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2507 2505 if (err) 2508 2506 return err; 2509 2507 2510 2510 - cmd = &desc.params.nvm_checksum; 2508 2508 + cmd = libie_aq_raw(&desc); 2511 2509 2512 2510 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum); 2513 2511 cmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY; ··· 2543 2541 u32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1; 2544 2542 int err; 2545 2543 2546 2546 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2544 2544 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2547 2545 if (err) 2548 2546 return err; 2549 2547 ··· 2554 2552 2555 2553 err = ixgbe_read_flat_nvm(hw, offset, &len, &data, false); 2556 2554 if (err == -EIO && 2557 2557 - hw->aci.last_status == IXGBE_ACI_RC_EINVAL) { 2555 2555 + hw->aci.last_status == LIBIE_AQ_RC_EINVAL) { 2558 2556 err = 0; 2559 2557 max_size = offset; 2560 2558 } else if (!err) { ··· 2807 2805 if (!start) 2808 2806 return -EINVAL; 2809 2807 2810 2810 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 2808 2808 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2811 2809 if (err) 2812 2810 return err; 2813 2811 ··· 3391 3389 */ 3392 3390 int ixgbe_aci_nvm_update_empr(struct ixgbe_hw *hw) 3393 3391 { 3394 3394 - struct ixgbe_aci_desc desc; 3392 3392 + struct libie_aq_desc desc; 3395 3393 3396 3394 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_update_empr); 3397 3395 ··· 3417 3415 u8 *data, u16 length) 3418 3416 { 3419 3417 struct ixgbe_aci_cmd_nvm_pkg_data *cmd; 3420 3420 - struct ixgbe_aci_desc desc; 3418 3418 + struct libie_aq_desc desc; 3421 3419 3422 3420 if (length != 0 && !data) 3423 3421 return -EINVAL; 3424 3422 3425 3425 - cmd = &desc.params.pkg_data; 3423 3423 + cmd = libie_aq_raw(&desc); 3426 3424 3427 3425 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_pkg_data); 3428 3428 - desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 3426 3426 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3429 3427 3430 3428 if (del_pkg_data_flag) 3431 3429 cmd->cmd_flags |= IXGBE_ACI_NVM_PKG_DELETE; ··· 3455 3453 u8 *comp_response_code) 3456 3454 { 3457 3455 struct ixgbe_aci_cmd_nvm_pass_comp_tbl *cmd; 3458 3458 - struct ixgbe_aci_desc desc; 3456 3456 + struct libie_aq_desc desc; 3459 3457 int err; 3460 3458 3461 3459 if (!data || !comp_response || !comp_response_code) 3462 3460 return -EINVAL; 3463 3461 3464 3464 - cmd = &desc.params.pass_comp_tbl; 3462 3462 + cmd = libie_aq_raw(&desc); 3465 3463 3466 3464 ixgbe_fill_dflt_direct_cmd_desc(&desc, 3467 3465 ixgbe_aci_opc_nvm_pass_component_tbl); 3468 3468 - desc.flags |= cpu_to_le16(IXGBE_ACI_FLAG_RD); 3466 3466 + desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3469 3467 3470 3468 cmd->transfer_flag = transfer_flag; 3471 3469 err = ixgbe_aci_send_cmd(hw, &desc, data, length); ··· 3619 3617 return err; 3620 3618 } 3621 3619 3622 3622 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3620 3620 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3623 3621 if (err) 3624 3622 return err; 3625 3623 ··· 3652 3650 return err; 3653 3651 } 3654 3652 3655 3655 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3653 3653 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3656 3654 if (err) 3657 3655 return err; 3658 3656 ··· 3692 3690 if (checksum_val) { 3693 3691 u16 tmp_checksum; 3694 3692 3695 3695 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_READ); 3693 3693 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3696 3694 if (err) 3697 3695 return err; 3698 3696

+6 -6

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h

reviewed

··· 6 6 7 7 #include "ixgbe_type.h" 8 8 9 9 - int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc, 9 9 + int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc, 10 10 void *buf, u16 buf_size); 11 11 bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw); 12 12 int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e, 13 13 bool *pending); 14 14 - void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode); 15 15 - int ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res, 16 16 - enum ixgbe_aci_res_access_type access, u32 timeout); 17 17 - void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res); 14 14 + void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode); 15 15 + int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 16 16 + enum libie_aq_res_access_type access, u32 timeout); 17 17 + void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res); 18 18 int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size, 19 19 u32 *cap_count, enum ixgbe_aci_opc opc); 20 20 int ixgbe_discover_dev_caps(struct ixgbe_hw *hw, ··· 62 62 struct ixgbe_aci_cmd_get_link_topo *cmd, 63 63 u8 *node_part_number, u16 *node_handle); 64 64 int ixgbe_acquire_nvm(struct ixgbe_hw *hw, 65 65 - enum ixgbe_aci_res_access_type access); 65 65 + enum libie_aq_res_access_type access); 66 66 void ixgbe_release_nvm(struct ixgbe_hw *hw); 67 67 int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset, 68 68 u16 length, void *data, bool last_command,

+2 -2

drivers/net/ethernet/intel/ixgbe/ixgbe_fw_update.c

reviewed

··· 593 593 "Canceling previous pending update", 594 594 component, 0, 0); 595 595 596 596 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_WRITE); 596 596 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_WRITE); 597 597 if (err) { 598 598 NL_SET_ERR_MSG_MOD(extack, 599 599 "Failed to acquire device flash lock"); ··· 686 686 if (err) 687 687 return err; 688 688 689 689 - err = ixgbe_acquire_nvm(hw, IXGBE_RES_WRITE); 689 689 + err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_WRITE); 690 690 if (err) { 691 691 NL_SET_ERR_MSG_MOD(extack, 692 692 "Failed to acquire device flash lock");

+4 -222

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

reviewed

··· 4 4 #ifndef _IXGBE_TYPE_E610_H_ 5 5 #define _IXGBE_TYPE_E610_H_ 6 6 7 7 + #include <linux/net/intel/libie/adminq.h> 8 8 + 7 9 #define BYTES_PER_DWORD 4 8 10 9 11 /* General E610 defines */ ··· 137 135 /* [ms] timeout of waiting for resource release */ 138 136 #define IXGBE_ACI_RELEASE_RES_TIMEOUT 10000 139 137 140 140 - /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 141 141 - #define IXGBE_ACI_LG_BUF 512 142 142 - 143 143 - /* Flags sub-structure 144 144 - * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 145 145 - * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 146 146 - */ 147 147 - 148 148 - #define IXGBE_ACI_FLAG_DD BIT(0) /* 0x1 */ 149 149 - #define IXGBE_ACI_FLAG_CMP BIT(1) /* 0x2 */ 150 150 - #define IXGBE_ACI_FLAG_ERR BIT(2) /* 0x4 */ 151 151 - #define IXGBE_ACI_FLAG_VFE BIT(3) /* 0x8 */ 152 152 - #define IXGBE_ACI_FLAG_LB BIT(9) /* 0x200 */ 153 153 - #define IXGBE_ACI_FLAG_RD BIT(10) /* 0x400 */ 154 154 - #define IXGBE_ACI_FLAG_VFC BIT(11) /* 0x800 */ 155 155 - #define IXGBE_ACI_FLAG_BUF BIT(12) /* 0x1000 */ 156 156 - #define IXGBE_ACI_FLAG_SI BIT(13) /* 0x2000 */ 157 157 - #define IXGBE_ACI_FLAG_EI BIT(14) /* 0x4000 */ 158 158 - #define IXGBE_ACI_FLAG_FE BIT(15) /* 0x8000 */ 159 159 - 160 160 - /* Admin Command Interface (ACI) error codes */ 161 161 - enum ixgbe_aci_err { 162 162 - IXGBE_ACI_RC_OK = 0, /* Success */ 163 163 - IXGBE_ACI_RC_EPERM = 1, /* Operation not permitted */ 164 164 - IXGBE_ACI_RC_ENOENT = 2, /* No such element */ 165 165 - IXGBE_ACI_RC_ESRCH = 3, /* Bad opcode */ 166 166 - IXGBE_ACI_RC_EINTR = 4, /* Operation interrupted */ 167 167 - IXGBE_ACI_RC_EIO = 5, /* I/O error */ 168 168 - IXGBE_ACI_RC_ENXIO = 6, /* No such resource */ 169 169 - IXGBE_ACI_RC_E2BIG = 7, /* Arg too long */ 170 170 - IXGBE_ACI_RC_EAGAIN = 8, /* Try again */ 171 171 - IXGBE_ACI_RC_ENOMEM = 9, /* Out of memory */ 172 172 - IXGBE_ACI_RC_EACCES = 10, /* Permission denied */ 173 173 - IXGBE_ACI_RC_EFAULT = 11, /* Bad address */ 174 174 - IXGBE_ACI_RC_EBUSY = 12, /* Device or resource busy */ 175 175 - IXGBE_ACI_RC_EEXIST = 13, /* Object already exists */ 176 176 - IXGBE_ACI_RC_EINVAL = 14, /* Invalid argument */ 177 177 - IXGBE_ACI_RC_ENOTTY = 15, /* Not a typewriter */ 178 178 - IXGBE_ACI_RC_ENOSPC = 16, /* No space left or alloc failure */ 179 179 - IXGBE_ACI_RC_ENOSYS = 17, /* Function not implemented */ 180 180 - IXGBE_ACI_RC_ERANGE = 18, /* Parameter out of range */ 181 181 - IXGBE_ACI_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 182 182 - IXGBE_ACI_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 183 183 - IXGBE_ACI_RC_EMODE = 21, /* Op not allowed in current dev mode */ 184 184 - IXGBE_ACI_RC_EFBIG = 22, /* File too big */ 185 185 - IXGBE_ACI_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 186 186 - IXGBE_ACI_RC_ENOSEC = 24, /* Missing security manifest */ 187 187 - IXGBE_ACI_RC_EBADSIG = 25, /* Bad RSA signature */ 188 188 - IXGBE_ACI_RC_ESVN = 26, /* SVN number prohibits this package */ 189 189 - IXGBE_ACI_RC_EBADMAN = 27, /* Manifest hash mismatch */ 190 190 - IXGBE_ACI_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 191 191 - IXGBE_ACI_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 192 192 - }; 193 193 - 194 138 /* Admin Command Interface (ACI) opcodes */ 195 139 enum ixgbe_aci_opc { 196 140 ixgbe_aci_opc_get_ver = 0x0001, ··· 213 265 ixgbe_aci_opc_clear_health_status = 0xFF23, 214 266 }; 215 267 216 216 - /* Get version (direct 0x0001) */ 217 217 - struct ixgbe_aci_cmd_get_ver { 218 218 - __le32 rom_ver; 219 219 - __le32 fw_build; 220 220 - u8 fw_branch; 221 221 - u8 fw_major; 222 222 - u8 fw_minor; 223 223 - u8 fw_patch; 224 224 - u8 api_branch; 225 225 - u8 api_major; 226 226 - u8 api_minor; 227 227 - u8 api_patch; 228 228 - }; 229 229 - 230 268 #define IXGBE_DRV_VER_STR_LEN_E610 32 231 231 - 232 232 - /* Send driver version (indirect 0x0002) */ 233 233 - struct ixgbe_aci_cmd_driver_ver { 234 234 - u8 major_ver; 235 235 - u8 minor_ver; 236 236 - u8 build_ver; 237 237 - u8 subbuild_ver; 238 238 - u8 reserved[4]; 239 239 - __le32 addr_high; 240 240 - __le32 addr_low; 241 241 - }; 242 269 243 270 /* Get Expanded Error Code (0x0005, direct) */ 244 271 struct ixgbe_aci_cmd_get_exp_err { ··· 225 302 226 303 /* FW update timeout definitions are in milliseconds */ 227 304 #define IXGBE_NVM_TIMEOUT 180000 228 228 - 229 229 - enum ixgbe_aci_res_access_type { 230 230 - IXGBE_RES_READ = 1, 231 231 - IXGBE_RES_WRITE 232 232 - }; 233 233 - 234 234 - enum ixgbe_aci_res_ids { 235 235 - IXGBE_NVM_RES_ID = 1, 236 236 - IXGBE_SPD_RES_ID, 237 237 - IXGBE_CHANGE_LOCK_RES_ID, 238 238 - IXGBE_GLOBAL_CFG_LOCK_RES_ID 239 239 - }; 240 240 - 241 241 - /* Request resource ownership (direct 0x0008) 242 242 - * Release resource ownership (direct 0x0009) 243 243 - */ 244 244 - struct ixgbe_aci_cmd_req_res { 245 245 - __le16 res_id; 246 246 - __le16 access_type; 247 247 - 248 248 - /* Upon successful completion, FW writes this value and driver is 249 249 - * expected to release resource before timeout. This value is provided 250 250 - * in milliseconds. 251 251 - */ 252 252 - __le32 timeout; 253 253 - #define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 254 254 - #define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 255 255 - #define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 256 256 - #define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 257 257 - /* For SDP: pin ID of the SDP */ 258 258 - __le32 res_number; 259 259 - __le16 status; 260 260 - #define IXGBE_ACI_RES_GLBL_SUCCESS 0 261 261 - #define IXGBE_ACI_RES_GLBL_IN_PROG 1 262 262 - #define IXGBE_ACI_RES_GLBL_DONE 2 263 263 - u8 reserved[2]; 264 264 - }; 265 265 - 266 266 - /* Get function capabilities (indirect 0x000A) 267 267 - * Get device capabilities (indirect 0x000B) 268 268 - */ 269 269 - struct ixgbe_aci_cmd_list_caps { 270 270 - u8 cmd_flags; 271 271 - u8 pf_index; 272 272 - u8 reserved[2]; 273 273 - __le32 count; 274 274 - __le32 addr_high; 275 275 - __le32 addr_low; 276 276 - }; 277 277 - 278 278 - /* Device/Function buffer entry, repeated per reported capability */ 279 279 - struct ixgbe_aci_cmd_list_caps_elem { 280 280 - __le16 cap; 281 281 - #define IXGBE_ACI_CAPS_VALID_FUNCTIONS 0x0005 282 282 - #define IXGBE_ACI_MAX_VALID_FUNCTIONS 0x8 283 283 - #define IXGBE_ACI_CAPS_SRIOV 0x0012 284 284 - #define IXGBE_ACI_CAPS_VF 0x0013 285 285 - #define IXGBE_ACI_CAPS_VMDQ 0x0014 286 286 - #define IXGBE_ACI_CAPS_VSI 0x0017 287 287 - #define IXGBE_ACI_CAPS_DCB 0x0018 288 288 - #define IXGBE_ACI_CAPS_RSS 0x0040 289 289 - #define IXGBE_ACI_CAPS_RXQS 0x0041 290 290 - #define IXGBE_ACI_CAPS_TXQS 0x0042 291 291 - #define IXGBE_ACI_CAPS_MSIX 0x0043 292 292 - #define IXGBE_ACI_CAPS_FD 0x0045 293 293 - #define IXGBE_ACI_CAPS_1588 0x0046 294 294 - #define IXGBE_ACI_CAPS_MAX_MTU 0x0047 295 295 - #define IXGBE_ACI_CAPS_NVM_VER 0x0048 296 296 - #define IXGBE_ACI_CAPS_PENDING_NVM_VER 0x0049 297 297 - #define IXGBE_ACI_CAPS_OROM_VER 0x004A 298 298 - #define IXGBE_ACI_CAPS_PENDING_OROM_VER 0x004B 299 299 - #define IXGBE_ACI_CAPS_PENDING_NET_VER 0x004D 300 300 - #define IXGBE_ACI_CAPS_INLINE_IPSEC 0x0070 301 301 - #define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS 0x0072 302 302 - #define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE 0x0076 303 303 - #define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 304 304 - #define IXGBE_ACI_CAPS_NVM_MGMT 0x0080 305 305 - #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0 0x0081 306 306 - #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1 0x0082 307 307 - #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2 0x0083 308 308 - #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3 0x0084 309 309 - u8 major_ver; 310 310 - u8 minor_ver; 311 311 - /* Number of resources described by this capability */ 312 312 - __le32 number; 313 313 - /* Only meaningful for some types of resources */ 314 314 - __le32 logical_id; 315 315 - /* Only meaningful for some types of resources */ 316 316 - __le32 phys_id; 317 317 - __le64 rsvd1; 318 318 - __le64 rsvd2; 319 319 - }; 320 305 321 306 /* Disable RXEN (direct 0x000C) */ 322 307 struct ixgbe_aci_cmd_disable_rxen { ··· 791 960 u8 cvs[]; /* Component Version String */ 792 961 } __packed; 793 962 794 794 - /** 795 795 - * struct ixgbe_aci_desc - Admin Command (AC) descriptor 796 796 - * @flags: IXGBE_ACI_FLAG_* flags 797 797 - * @opcode: Admin command opcode 798 798 - * @datalen: length in bytes of indirect/external data buffer 799 799 - * @retval: return value from firmware 800 800 - * @cookie_high: opaque data high-half 801 801 - * @cookie_low: opaque data low-half 802 802 - * @params: command-specific parameters 803 803 - * 804 804 - * Descriptor format for commands the driver posts via the 805 805 - * Admin Command Interface (ACI). 806 806 - * The firmware writes back onto the command descriptor and returns 807 807 - * the result of the command. Asynchronous events that are not an immediate 808 808 - * result of the command are written to the Admin Command Interface (ACI) using 809 809 - * the same descriptor format. Descriptors are in little-endian notation with 810 810 - * 32-bit words. 811 811 - */ 812 812 - struct ixgbe_aci_desc { 813 813 - __le16 flags; 814 814 - __le16 opcode; 815 815 - __le16 datalen; 816 816 - __le16 retval; 817 817 - __le32 cookie_high; 818 818 - __le32 cookie_low; 819 819 - union { 820 820 - u8 raw[16]; 821 821 - struct ixgbe_aci_cmd_get_ver get_ver; 822 822 - struct ixgbe_aci_cmd_driver_ver driver_ver; 823 823 - struct ixgbe_aci_cmd_get_exp_err exp_err; 824 824 - struct ixgbe_aci_cmd_req_res res_owner; 825 825 - struct ixgbe_aci_cmd_list_caps get_cap; 826 826 - struct ixgbe_aci_cmd_disable_rxen disable_rxen; 827 827 - struct ixgbe_aci_cmd_get_phy_caps get_phy; 828 828 - struct ixgbe_aci_cmd_set_phy_cfg set_phy; 829 829 - struct ixgbe_aci_cmd_restart_an restart_an; 830 830 - struct ixgbe_aci_cmd_get_link_status get_link_status; 831 831 - struct ixgbe_aci_cmd_set_event_mask set_event_mask; 832 832 - struct ixgbe_aci_cmd_set_port_id_led set_port_id_led; 833 833 - struct ixgbe_aci_cmd_get_link_topo get_link_topo; 834 834 - struct ixgbe_aci_cmd_get_link_topo_pin get_link_topo_pin; 835 835 - struct ixgbe_aci_cmd_sff_eeprom read_write_sff_param; 836 836 - struct ixgbe_aci_cmd_nvm nvm; 837 837 - struct ixgbe_aci_cmd_nvm_checksum nvm_checksum; 838 838 - struct ixgbe_aci_cmd_nvm_pkg_data pkg_data; 839 839 - struct ixgbe_aci_cmd_nvm_pass_comp_tbl pass_comp_tbl; 840 840 - } params; 841 841 - }; 842 842 - 843 963 /* E610-specific adapter context structures */ 844 964 845 965 struct ixgbe_link_status { ··· 954 1172 955 1173 /* ACI event information */ 956 1174 struct ixgbe_aci_event { 957 957 - struct ixgbe_aci_desc desc; 1175 1175 + struct libie_aq_desc desc; 958 1176 u8 *msg_buf; 959 1177 u16 msg_len; 960 1178 u16 buf_len; ··· 962 1180 963 1181 struct ixgbe_aci_info { 964 1182 struct mutex lock; /* admin command interface lock */ 965 965 - enum ixgbe_aci_err last_status; /* last status of sent admin command */ 1183 1183 + enum libie_aq_err last_status; /* last status of sent admin command */ 966 1184 }; 967 1185 968 1186 enum ixgbe_bank_select {

+6

drivers/net/ethernet/intel/libie/Kconfig

reviewed

··· 8 8 libie (Intel Ethernet library) is a common library built on top of 9 9 libeth and containing vendor-specific routines shared between several 10 10 Intel Ethernet drivers. 11 11 + 12 12 + config LIBIE_ADMINQ 13 13 + tristate 14 14 + help 15 15 + Helper functions used by Intel Ethernet drivers for administration 16 16 + queue command interface (aka adminq).

+4

drivers/net/ethernet/intel/libie/Makefile

reviewed

··· 4 4 obj-$(CONFIG_LIBIE) += libie.o 5 5 6 6 libie-y := rx.o 7 7 + 8 8 + obj-$(CONFIG_LIBIE_ADMINQ) += libie_adminq.o 9 9 + 10 10 + libie_adminq-y := adminq.o

+52

drivers/net/ethernet/intel/libie/adminq.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* Copyright (C) 2025 Intel Corporation */ 3 3 + 4 4 + #include <linux/module.h> 5 5 + #include <linux/net/intel/libie/adminq.h> 6 6 + 7 7 + static const char * const libie_aq_str_arr[] = { 8 8 + #define LIBIE_AQ_STR(x) \ 9 9 + [LIBIE_AQ_RC_##x] = "LIBIE_AQ_RC" #x 10 10 + LIBIE_AQ_STR(OK), 11 11 + LIBIE_AQ_STR(EPERM), 12 12 + LIBIE_AQ_STR(ENOENT), 13 13 + LIBIE_AQ_STR(ESRCH), 14 14 + LIBIE_AQ_STR(EIO), 15 15 + LIBIE_AQ_STR(EAGAIN), 16 16 + LIBIE_AQ_STR(ENOMEM), 17 17 + LIBIE_AQ_STR(EACCES), 18 18 + LIBIE_AQ_STR(EBUSY), 19 19 + LIBIE_AQ_STR(EEXIST), 20 20 + LIBIE_AQ_STR(EINVAL), 21 21 + LIBIE_AQ_STR(ENOSPC), 22 22 + LIBIE_AQ_STR(ENOSYS), 23 23 + LIBIE_AQ_STR(EMODE), 24 24 + LIBIE_AQ_STR(ENOSEC), 25 25 + LIBIE_AQ_STR(EBADSIG), 26 26 + LIBIE_AQ_STR(ESVN), 27 27 + LIBIE_AQ_STR(EBADMAN), 28 28 + LIBIE_AQ_STR(EBADBUF), 29 29 + #undef LIBIE_AQ_STR 30 30 + "LIBIE_AQ_RC_UNKNOWN", 31 31 + }; 32 32 + 33 33 + #define __LIBIE_AQ_STR_NUM (ARRAY_SIZE(libie_aq_str_arr) - 1) 34 34 + 35 35 + /** 36 36 + * libie_aq_str - get error string based on aq error 37 37 + * @err: admin queue error type 38 38 + * 39 39 + * Return: error string for passed error code 40 40 + */ 41 41 + const char *libie_aq_str(enum libie_aq_err err) 42 42 + { 43 43 + if (err >= ARRAY_SIZE(libie_aq_str_arr) || 44 44 + !libie_aq_str_arr[err]) 45 45 + err = __LIBIE_AQ_STR_NUM; 46 46 + 47 47 + return libie_aq_str_arr[err]; 48 48 + } 49 49 + EXPORT_SYMBOL_NS_GPL(libie_aq_str, "LIBIE_ADMINQ"); 50 50 + 51 51 + MODULE_DESCRIPTION("Intel(R) Ethernet common library - adminq helpers"); 52 52 + MODULE_LICENSE("GPL");

+308

include/linux/net/intel/libie/adminq.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 + /* Copyright (C) 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __LIBIE_ADMINQ_H 5 5 + #define __LIBIE_ADMINQ_H 6 6 + 7 7 + #include <linux/build_bug.h> 8 8 + #include <linux/types.h> 9 9 + 10 10 + #define LIBIE_CHECK_STRUCT_LEN(n, X) \ 11 11 + static_assert((n) == sizeof(struct X)) 12 12 + 13 13 + /** 14 14 + * struct libie_aqc_generic - Generic structure used in adminq communication 15 15 + * @param0: generic parameter high 32bit 16 16 + * @param1: generic parameter lower 32bit 17 17 + * @addr_high: generic address high 32bit 18 18 + * @addr_low: generic address lower 32bit 19 19 + */ 20 20 + struct libie_aqc_generic { 21 21 + __le32 param0; 22 22 + __le32 param1; 23 23 + __le32 addr_high; 24 24 + __le32 addr_low; 25 25 + }; 26 26 + LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_generic); 27 27 + 28 28 + /** 29 29 + * struct libie_aqc_get_ver - Used in command get version (direct 0x0001) 30 30 + * @rom_ver: rom version 31 31 + * @fw_build: number coressponding to firmware build 32 32 + * @fw_branch: branch identifier of firmware version 33 33 + * @fw_major: major number of firmware version 34 34 + * @fw_minor: minor number of firmware version 35 35 + * @fw_patch: patch of firmware version 36 36 + * @api_branch: brancch identifier of API version 37 37 + * @api_major: major number of API version 38 38 + * @api_minor: minor number of API version 39 39 + * @api_patch: patch of API version 40 40 + */ 41 41 + struct libie_aqc_get_ver { 42 42 + __le32 rom_ver; 43 43 + __le32 fw_build; 44 44 + u8 fw_branch; 45 45 + u8 fw_major; 46 46 + u8 fw_minor; 47 47 + u8 fw_patch; 48 48 + u8 api_branch; 49 49 + u8 api_major; 50 50 + u8 api_minor; 51 51 + u8 api_patch; 52 52 + }; 53 53 + LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_get_ver); 54 54 + 55 55 + /** 56 56 + * struct libie_aqc_driver_ver - Used in command send driver version 57 57 + * (indirect 0x0002) 58 58 + * @major_ver: driver major version 59 59 + * @minor_ver: driver minor version 60 60 + * @build_ver: driver build version 61 61 + * @subbuild_ver: driver subbuild version 62 62 + * @reserved: for feature use 63 63 + * @addr_high: high part of response address buff 64 64 + * @addr_low: low part of response address buff 65 65 + */ 66 66 + struct libie_aqc_driver_ver { 67 67 + u8 major_ver; 68 68 + u8 minor_ver; 69 69 + u8 build_ver; 70 70 + u8 subbuild_ver; 71 71 + u8 reserved[4]; 72 72 + __le32 addr_high; 73 73 + __le32 addr_low; 74 74 + }; 75 75 + LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_driver_ver); 76 76 + 77 77 + enum libie_aq_res_id { 78 78 + LIBIE_AQC_RES_ID_NVM = 1, 79 79 + LIBIE_AQC_RES_ID_SDP = 2, 80 80 + LIBIE_AQC_RES_ID_CHNG_LOCK = 3, 81 81 + LIBIE_AQC_RES_ID_GLBL_LOCK = 4, 82 82 + }; 83 83 + 84 84 + enum libie_aq_res_access_type { 85 85 + LIBIE_AQC_RES_ACCESS_READ = 1, 86 86 + LIBIE_AQC_RES_ACCESS_WRITE = 2, 87 87 + }; 88 88 + 89 89 + #define LIBIE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 90 90 + #define LIBIE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 91 91 + #define LIBIE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 92 92 + #define LIBIE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 93 93 + 94 94 + #define LIBIE_AQ_RES_GLBL_SUCCESS 0 95 95 + #define LIBIE_AQ_RES_GLBL_IN_PROG 1 96 96 + #define LIBIE_AQ_RES_GLBL_DONE 2 97 97 + 98 98 + /** 99 99 + * struct libie_aqc_req_res - Request resource ownership 100 100 + * @res_id: resource ID (look at enum definition above) 101 101 + * @access_type: read or write (enum definition above) 102 102 + * @timeout: Upon successful completion, FW writes this value and driver is 103 103 + * expected to release resource before timeout. This value is provided in 104 104 + * milliseconds. 105 105 + * @res_number: for SDP, this is the pin ID of the SDP 106 106 + * @status: status only used for LIBIE_AQC_RES_ID_GLBL_LOCK, for others reserved 107 107 + * @reserved: reserved for future use 108 108 + * 109 109 + * Used in commands: 110 110 + * request resource ownership (direct 0x0008) 111 111 + * request resource ownership (direct 0x0009) 112 112 + */ 113 113 + struct libie_aqc_req_res { 114 114 + __le16 res_id; 115 115 + __le16 access_type; 116 116 + 117 117 + __le32 timeout; 118 118 + __le32 res_number; 119 119 + __le16 status; 120 120 + u8 reserved[2]; 121 121 + }; 122 122 + LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_req_res); 123 123 + 124 124 + /** 125 125 + * struct libie_aqc_list_caps - Getting capabilities 126 126 + * @cmd_flags: command flags 127 127 + * @pf_index: index of PF to get caps from 128 128 + * @reserved: reserved for future use 129 129 + * @count: number of capabilities records 130 130 + * @addr_high: high part of response address buff 131 131 + * @addr_low: low part of response address buff 132 132 + * 133 133 + * Used in commands: 134 134 + * get function capabilities (indirect 0x000A) 135 135 + * get device capabilities (indirect 0x000B) 136 136 + */ 137 137 + struct libie_aqc_list_caps { 138 138 + u8 cmd_flags; 139 139 + u8 pf_index; 140 140 + u8 reserved[2]; 141 141 + __le32 count; 142 142 + __le32 addr_high; 143 143 + __le32 addr_low; 144 144 + }; 145 145 + LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_list_caps); 146 146 + 147 147 + /* Device/Function buffer entry, repeated per reported capability */ 148 148 + #define LIBIE_AQC_CAPS_SWITCH_MODE 0x0001 149 149 + #define LIBIE_AQC_CAPS_MNG_MODE 0x0002 150 150 + #define LIBIE_AQC_CAPS_NPAR_ACTIVE 0x0003 151 151 + #define LIBIE_AQC_CAPS_OS2BMC_CAP 0x0004 152 152 + #define LIBIE_AQC_CAPS_VALID_FUNCTIONS 0x0005 153 153 + #define LIBIE_AQC_MAX_VALID_FUNCTIONS 0x8 154 154 + #define LIBIE_AQC_CAPS_SRIOV 0x0012 155 155 + #define LIBIE_AQC_CAPS_VF 0x0013 156 156 + #define LIBIE_AQC_CAPS_VMDQ 0x0014 157 157 + #define LIBIE_AQC_CAPS_8021QBG 0x0015 158 158 + #define LIBIE_AQC_CAPS_8021QBR 0x0016 159 159 + #define LIBIE_AQC_CAPS_VSI 0x0017 160 160 + #define LIBIE_AQC_CAPS_DCB 0x0018 161 161 + #define LIBIE_AQC_CAPS_FCOE 0x0021 162 162 + #define LIBIE_AQC_CAPS_ISCSI 0x0022 163 163 + #define LIBIE_AQC_CAPS_RSS 0x0040 164 164 + #define LIBIE_AQC_CAPS_RXQS 0x0041 165 165 + #define LIBIE_AQC_CAPS_TXQS 0x0042 166 166 + #define LIBIE_AQC_CAPS_MSIX 0x0043 167 167 + #define LIBIE_AQC_CAPS_VF_MSIX 0x0044 168 168 + #define LIBIE_AQC_CAPS_FD 0x0045 169 169 + #define LIBIE_AQC_CAPS_1588 0x0046 170 170 + #define LIBIE_AQC_CAPS_MAX_MTU 0x0047 171 171 + #define LIBIE_AQC_CAPS_NVM_VER 0x0048 172 172 + #define LIBIE_AQC_CAPS_PENDING_NVM_VER 0x0049 173 173 + #define LIBIE_AQC_CAPS_OROM_VER 0x004A 174 174 + #define LIBIE_AQC_CAPS_PENDING_OROM_VER 0x004B 175 175 + #define LIBIE_AQC_CAPS_NET_VER 0x004C 176 176 + #define LIBIE_AQC_CAPS_PENDING_NET_VER 0x004D 177 177 + #define LIBIE_AQC_CAPS_RDMA 0x0051 178 178 + #define LIBIE_AQC_CAPS_LED 0x0061 179 179 + #define LIBIE_AQC_CAPS_SDP 0x0062 180 180 + #define LIBIE_AQC_CAPS_MDIO 0x0063 181 181 + #define LIBIE_AQC_CAPS_WSR_PROT 0x0064 182 182 + #define LIBIE_AQC_CAPS_SENSOR_READING 0x0067 183 183 + #define LIBIE_AQC_INLINE_IPSEC 0x0070 184 184 + #define LIBIE_AQC_CAPS_NUM_ENABLED_PORTS 0x0072 185 185 + #define LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 186 186 + #define LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 187 187 + #define LIBIE_AQC_CAPS_NVM_MGMT 0x0080 188 188 + #define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 189 189 + #define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 190 190 + #define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 191 191 + #define LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 192 192 + #define LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 193 193 + #define LIBIE_AQC_CAPS_NAC_TOPOLOGY 0x0087 194 194 + #define LIBIE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 195 195 + #define LIBIE_AQC_BIT_ROCEV2_LAG 0x01 196 196 + #define LIBIE_AQC_BIT_SRIOV_LAG 0x02 197 197 + #define LIBIE_AQC_CAPS_FLEX10 0x00F1 198 198 + #define LIBIE_AQC_CAPS_CEM 0x00F2 199 199 + 200 200 + /** 201 201 + * struct libie_aqc_list_caps_elem - Getting list of caps elements 202 202 + * @cap: one from the defines list above 203 203 + * @major_ver: major version 204 204 + * @minor_ver: minor version 205 205 + * @number: number of resources described by this capability 206 206 + * @logical_id: logical ID, only meaningful for some types of resources 207 207 + * @phys_id: physical ID, only meaningful for some types of resources 208 208 + * @rsvd1: reserved for future use 209 209 + * @rsvd2: reserved for future use 210 210 + */ 211 211 + struct libie_aqc_list_caps_elem { 212 212 + __le16 cap; 213 213 + 214 214 + u8 major_ver; 215 215 + u8 minor_ver; 216 216 + __le32 number; 217 217 + __le32 logical_id; 218 218 + __le32 phys_id; 219 219 + __le64 rsvd1; 220 220 + __le64 rsvd2; 221 221 + }; 222 222 + LIBIE_CHECK_STRUCT_LEN(32, libie_aqc_list_caps_elem); 223 223 + 224 224 + /** 225 225 + * struct libie_aq_desc - Admin Queue (AQ) descriptor 226 226 + * @flags: LIBIE_AQ_FLAG_* flags 227 227 + * @opcode: AQ command opcode 228 228 + * @datalen: length in bytes of indirect/external data buffer 229 229 + * @retval: return value from firmware 230 230 + * @cookie_high: opaque data high-half 231 231 + * @cookie_low: opaque data low-half 232 232 + * @params: command-specific parameters 233 233 + * 234 234 + * Descriptor format for commands the driver posts on the Admin Transmit Queue 235 235 + * (ATQ). The firmware writes back onto the command descriptor and returns 236 236 + * the result of the command. Asynchronous events that are not an immediate 237 237 + * result of the command are written to the Admin Receive Queue (ARQ) using 238 238 + * the same descriptor format. Descriptors are in little-endian notation with 239 239 + * 32-bit words. 240 240 + */ 241 241 + struct libie_aq_desc { 242 242 + __le16 flags; 243 243 + __le16 opcode; 244 244 + __le16 datalen; 245 245 + __le16 retval; 246 246 + __le32 cookie_high; 247 247 + __le32 cookie_low; 248 248 + union { 249 249 + u8 raw[16]; 250 250 + struct libie_aqc_generic generic; 251 251 + struct libie_aqc_get_ver get_ver; 252 252 + struct libie_aqc_driver_ver driver_ver; 253 253 + struct libie_aqc_req_res res_owner; 254 254 + struct libie_aqc_list_caps get_cap; 255 255 + } params; 256 256 + }; 257 257 + LIBIE_CHECK_STRUCT_LEN(32, libie_aq_desc); 258 258 + 259 259 + /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 260 260 + #define LIBIE_AQ_LG_BUF 512 261 261 + 262 262 + /* Flags sub-structure 263 263 + * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 264 264 + * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 265 265 + */ 266 266 + #define LIBIE_AQ_FLAG_DD BIT(0) /* 0x1 */ 267 267 + #define LIBIE_AQ_FLAG_CMP BIT(1) /* 0x2 */ 268 268 + #define LIBIE_AQ_FLAG_ERR BIT(2) /* 0x4 */ 269 269 + #define LIBIE_AQ_FLAG_VFE BIT(3) /* 0x8 */ 270 270 + #define LIBIE_AQ_FLAG_LB BIT(9) /* 0x200 */ 271 271 + #define LIBIE_AQ_FLAG_RD BIT(10) /* 0x400 */ 272 272 + #define LIBIE_AQ_FLAG_VFC BIT(11) /* 0x800 */ 273 273 + #define LIBIE_AQ_FLAG_BUF BIT(12) /* 0x1000 */ 274 274 + #define LIBIE_AQ_FLAG_SI BIT(13) /* 0x2000 */ 275 275 + #define LIBIE_AQ_FLAG_EI BIT(14) /* 0x4000 */ 276 276 + #define LIBIE_AQ_FLAG_FE BIT(15) /* 0x8000 */ 277 277 + 278 278 + /* error codes */ 279 279 + enum libie_aq_err { 280 280 + LIBIE_AQ_RC_OK = 0, /* Success */ 281 281 + LIBIE_AQ_RC_EPERM = 1, /* Operation not permitted */ 282 282 + LIBIE_AQ_RC_ENOENT = 2, /* No such element */ 283 283 + LIBIE_AQ_RC_ESRCH = 3, /* Bad opcode */ 284 284 + LIBIE_AQ_RC_EIO = 5, /* I/O error */ 285 285 + LIBIE_AQ_RC_EAGAIN = 8, /* Try again */ 286 286 + LIBIE_AQ_RC_ENOMEM = 9, /* Out of memory */ 287 287 + LIBIE_AQ_RC_EACCES = 10, /* Permission denied */ 288 288 + LIBIE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 289 289 + LIBIE_AQ_RC_EEXIST = 13, /* Object already exists */ 290 290 + LIBIE_AQ_RC_EINVAL = 14, /* Invalid argument */ 291 291 + LIBIE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 292 292 + LIBIE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 293 293 + LIBIE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 294 294 + LIBIE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 295 295 + LIBIE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 296 296 + LIBIE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 297 297 + LIBIE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 298 298 + LIBIE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 299 299 + }; 300 300 + 301 301 + static inline void *libie_aq_raw(struct libie_aq_desc *desc) 302 302 + { 303 303 + return &desc->params.raw; 304 304 + } 305 305 + 306 306 + const char *libie_aq_str(enum libie_aq_err err); 307 307 + 308 308 + #endif /* __LIBIE_ADMINQ_H */