Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - relocate bank state helper functions
The existing implementation of bank state management functions,
including saving and restoring state, is located within 4xxx device
files. However, these functions do not contain GEN4-specific code and
are applicable to other QAT generations.
Relocate the bank state management functions to a new file,
adf_bank_state.c, and rename them removing the `gen4` prefix. This change
enables the reuse of such functions across different QAT generations.
Add documentation to bank state related functions that were
moved from QAT 4xxx specific files to common files.
This does not introduce any functional change.
Signed-off-by: Małgorzata Mielnik <malgorzata.mielnik@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Małgorzata Mielnik
and committed by
Herbert Xu
e9eec291
18126fdf
+258
-209
+3
-2
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+3
-2
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
···
3
3
#include <linux/iopoll.h>
4
4
#include <adf_accel_devices.h>
5
5
#include <adf_admin.h>
6
+
#include <adf_bank_state.h>
6
7
#include <adf_cfg.h>
7
8
#include <adf_cfg_services.h>
8
9
#include <adf_clock.h>
···
449
448
hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
450
449
hw_data->disable_iov = adf_disable_sriov;
451
450
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
452
-
hw_data->bank_state_save = adf_gen4_bank_state_save;
453
-
hw_data->bank_state_restore = adf_gen4_bank_state_restore;
451
+
hw_data->bank_state_save = adf_bank_state_save;
452
+
hw_data->bank_state_restore = adf_bank_state_restore;
454
453
hw_data->enable_pm = adf_gen4_enable_pm;
455
454
hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;
456
455
hw_data->dev_config = adf_gen4_dev_config;
+1
drivers/crypto/intel/qat/qat_common/Makefile
+1
drivers/crypto/intel/qat/qat_common/Makefile
+238
drivers/crypto/intel/qat/qat_common/adf_bank_state.c
+238
drivers/crypto/intel/qat/qat_common/adf_bank_state.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright(c) 2025 Intel Corporation */
3
+
4
+
#define pr_fmt(fmt) "QAT: " fmt
5
+
6
+
#include <linux/bits.h>
7
+
#include <linux/dev_printk.h>
8
+
#include <linux/printk.h>
9
+
#include "adf_accel_devices.h"
10
+
#include "adf_bank_state.h"
11
+
#include "adf_common_drv.h"
12
+
13
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/* Ring interrupt masks */
14
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#define ADF_RP_INT_SRC_SEL_F_RISE_MASK GENMASK(1, 0)
15
+
#define ADF_RP_INT_SRC_SEL_F_FALL_MASK GENMASK(2, 0)
16
+
#define ADF_RP_INT_SRC_SEL_RANGE_WIDTH 4
17
+
18
+
static inline int check_stat(u32 (*op)(void __iomem *, u32), u32 expect_val,
19
+
const char *name, void __iomem *base, u32 bank)
20
+
{
21
+
u32 actual_val = op(base, bank);
22
+
23
+
if (expect_val == actual_val)
24
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return 0;
25
+
26
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pr_err("Fail to restore %s register. Expected %#x, actual %#x\n",
27
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name, expect_val, actual_val);
28
+
29
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return -EINVAL;
30
+
}
31
+
32
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static void bank_state_save(struct adf_hw_csr_ops *ops, void __iomem *base,
33
+
u32 bank, struct bank_state *state, u32 num_rings)
34
+
{
35
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u32 i;
36
+
37
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state->ringstat0 = ops->read_csr_stat(base, bank);
38
+
state->ringuostat = ops->read_csr_uo_stat(base, bank);
39
+
state->ringestat = ops->read_csr_e_stat(base, bank);
40
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state->ringnestat = ops->read_csr_ne_stat(base, bank);
41
+
state->ringnfstat = ops->read_csr_nf_stat(base, bank);
42
+
state->ringfstat = ops->read_csr_f_stat(base, bank);
43
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state->ringcstat0 = ops->read_csr_c_stat(base, bank);
44
+
state->iaintflagen = ops->read_csr_int_en(base, bank);
45
+
state->iaintflagreg = ops->read_csr_int_flag(base, bank);
46
+
state->iaintflagsrcsel0 = ops->read_csr_int_srcsel(base, bank);
47
+
state->iaintcolen = ops->read_csr_int_col_en(base, bank);
48
+
state->iaintcolctl = ops->read_csr_int_col_ctl(base, bank);
49
+
state->iaintflagandcolen = ops->read_csr_int_flag_and_col(base, bank);
50
+
state->ringexpstat = ops->read_csr_exp_stat(base, bank);
51
+
state->ringexpintenable = ops->read_csr_exp_int_en(base, bank);
52
+
state->ringsrvarben = ops->read_csr_ring_srv_arb_en(base, bank);
53
+
54
+
for (i = 0; i < num_rings; i++) {
55
+
state->rings[i].head = ops->read_csr_ring_head(base, bank, i);
56
+
state->rings[i].tail = ops->read_csr_ring_tail(base, bank, i);
57
+
state->rings[i].config = ops->read_csr_ring_config(base, bank, i);
58
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state->rings[i].base = ops->read_csr_ring_base(base, bank, i);
59
+
}
60
+
}
61
+
62
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static int bank_state_restore(struct adf_hw_csr_ops *ops, void __iomem *base,
63
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u32 bank, struct bank_state *state, u32 num_rings,
64
+
int tx_rx_gap)
65
+
{
66
+
u32 val, tmp_val, i;
67
+
int ret;
68
+
69
+
for (i = 0; i < num_rings; i++)
70
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ops->write_csr_ring_base(base, bank, i, state->rings[i].base);
71
+
72
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for (i = 0; i < num_rings; i++)
73
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ops->write_csr_ring_config(base, bank, i, state->rings[i].config);
74
+
75
+
for (i = 0; i < num_rings / 2; i++) {
76
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int tx = i * (tx_rx_gap + 1);
77
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int rx = tx + tx_rx_gap;
78
+
79
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ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);
80
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ops->write_csr_ring_tail(base, bank, tx, state->rings[tx].tail);
81
+
82
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/*
83
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* The TX ring head needs to be updated again to make sure that
84
+
* the HW will not consider the ring as full when it is empty
85
+
* and the correct state flags are set to match the recovered state.
86
+
*/
87
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if (state->ringestat & BIT(tx)) {
88
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val = ops->read_csr_int_srcsel(base, bank);
89
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val |= ADF_RP_INT_SRC_SEL_F_RISE_MASK;
90
+
ops->write_csr_int_srcsel_w_val(base, bank, val);
91
+
ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);
92
+
}
93
+
94
+
ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);
95
+
val = ops->read_csr_int_srcsel(base, bank);
96
+
val |= ADF_RP_INT_SRC_SEL_F_RISE_MASK << ADF_RP_INT_SRC_SEL_RANGE_WIDTH;
97
+
ops->write_csr_int_srcsel_w_val(base, bank, val);
98
+
99
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ops->write_csr_ring_head(base, bank, rx, state->rings[rx].head);
100
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val = ops->read_csr_int_srcsel(base, bank);
101
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val |= ADF_RP_INT_SRC_SEL_F_FALL_MASK << ADF_RP_INT_SRC_SEL_RANGE_WIDTH;
102
+
ops->write_csr_int_srcsel_w_val(base, bank, val);
103
+
104
+
/*
105
+
* The RX ring tail needs to be updated again to make sure that
106
+
* the HW will not consider the ring as empty when it is full
107
+
* and the correct state flags are set to match the recovered state.
108
+
*/
109
+
if (state->ringfstat & BIT(rx))
110
+
ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);
111
+
}
112
+
113
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ops->write_csr_int_flag_and_col(base, bank, state->iaintflagandcolen);
114
+
ops->write_csr_int_en(base, bank, state->iaintflagen);
115
+
ops->write_csr_int_col_en(base, bank, state->iaintcolen);
116
+
ops->write_csr_int_srcsel_w_val(base, bank, state->iaintflagsrcsel0);
117
+
ops->write_csr_exp_int_en(base, bank, state->ringexpintenable);
118
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ops->write_csr_int_col_ctl(base, bank, state->iaintcolctl);
119
+
120
+
/*
121
+
* Verify whether any exceptions were raised during the bank save process.
122
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* If exceptions occurred, the status and exception registers cannot
123
+
* be directly restored. Consequently, further restoration is not
124
+
* feasible, and the current state of the ring should be maintained.
125
+
*/
126
+
val = state->ringexpstat;
127
+
if (val) {
128
+
pr_info("Bank %u state not fully restored due to exception in saved state (%#x)\n",
129
+
bank, val);
130
+
return 0;
131
+
}
132
+
133
+
/* Ensure that the restoration process completed without exceptions */
134
+
tmp_val = ops->read_csr_exp_stat(base, bank);
135
+
if (tmp_val) {
136
+
pr_err("Bank %u restored with exception: %#x\n", bank, tmp_val);
137
+
return -EFAULT;
138
+
}
139
+
140
+
ops->write_csr_ring_srv_arb_en(base, bank, state->ringsrvarben);
141
+
142
+
/* Check that all ring statuses match the saved state. */
143
+
ret = check_stat(ops->read_csr_stat, state->ringstat0, "ringstat",
144
+
base, bank);
145
+
if (ret)
146
+
return ret;
147
+
148
+
ret = check_stat(ops->read_csr_e_stat, state->ringestat, "ringestat",
149
+
base, bank);
150
+
if (ret)
151
+
return ret;
152
+
153
+
ret = check_stat(ops->read_csr_ne_stat, state->ringnestat, "ringnestat",
154
+
base, bank);
155
+
if (ret)
156
+
return ret;
157
+
158
+
ret = check_stat(ops->read_csr_nf_stat, state->ringnfstat, "ringnfstat",
159
+
base, bank);
160
+
if (ret)
161
+
return ret;
162
+
163
+
ret = check_stat(ops->read_csr_f_stat, state->ringfstat, "ringfstat",
164
+
base, bank);
165
+
if (ret)
166
+
return ret;
167
+
168
+
ret = check_stat(ops->read_csr_c_stat, state->ringcstat0, "ringcstat",
169
+
base, bank);
170
+
if (ret)
171
+
return ret;
172
+
173
+
return 0;
174
+
}
175
+
176
+
/**
177
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* adf_bank_state_save() - save state of bank-related registers
178
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* @accel_dev: Pointer to the device structure
179
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* @bank_number: Bank number
180
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* @state: Pointer to bank state structure
181
+
*
182
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* This function saves the state of a bank by reading the bank CSRs and
183
+
* writing them in the @state structure.
184
+
*
185
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* Returns 0 on success, error code otherwise
186
+
*/
187
+
int adf_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
188
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struct bank_state *state)
189
+
{
190
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struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
191
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
192
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void __iomem *csr_base = adf_get_etr_base(accel_dev);
193
+
194
+
if (bank_number >= hw_data->num_banks || !state)
195
+
return -EINVAL;
196
+
197
+
dev_dbg(&GET_DEV(accel_dev), "Saving state of bank %d\n", bank_number);
198
+
199
+
bank_state_save(csr_ops, csr_base, bank_number, state,
200
+
hw_data->num_rings_per_bank);
201
+
202
+
return 0;
203
+
}
204
+
EXPORT_SYMBOL_GPL(adf_bank_state_save);
205
+
206
+
/**
207
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* adf_bank_state_restore() - restore state of bank-related registers
208
+
* @accel_dev: Pointer to the device structure
209
+
* @bank_number: Bank number
210
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* @state: Pointer to bank state structure
211
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*
212
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* This function attempts to restore the state of a bank by writing the
213
+
* bank CSRs to the values in the state structure.
214
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*
215
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* Returns 0 on success, error code otherwise
216
+
*/
217
+
int adf_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number,
218
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struct bank_state *state)
219
+
{
220
+
struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
221
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
222
+
void __iomem *csr_base = adf_get_etr_base(accel_dev);
223
+
int ret;
224
+
225
+
if (bank_number >= hw_data->num_banks || !state)
226
+
return -EINVAL;
227
+
228
+
dev_dbg(&GET_DEV(accel_dev), "Restoring state of bank %d\n", bank_number);
229
+
230
+
ret = bank_state_restore(csr_ops, csr_base, bank_number, state,
231
+
hw_data->num_rings_per_bank, hw_data->tx_rx_gap);
232
+
if (ret)
233
+
dev_err(&GET_DEV(accel_dev),
234
+
"Unable to restore state of bank %d\n", bank_number);
235
+
236
+
return ret;
237
+
}
238
+
EXPORT_SYMBOL_GPL(adf_bank_state_restore);
+16
drivers/crypto/intel/qat/qat_common/adf_bank_state.h
+16
drivers/crypto/intel/qat/qat_common/adf_bank_state.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright(c) 2025 Intel Corporation */
3
+
#ifndef ADF_BANK_STATE_H_
4
+
#define ADF_BANK_STATE_H_
5
+
6
+
#include <linux/types.h>
7
+
8
+
struct adf_accel_dev;
9
+
struct bank_state;
10
+
11
+
int adf_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number,
12
+
struct bank_state *state);
13
+
int adf_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
14
+
struct bank_state *state);
15
+
16
+
#endif
-200
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
-200
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
···
491
491
return ret;
492
492
}
493
493
494
-
static void bank_state_save(struct adf_hw_csr_ops *ops, void __iomem *base,
495
-
u32 bank, struct bank_state *state, u32 num_rings)
496
-
{
497
-
u32 i;
498
-
499
-
state->ringstat0 = ops->read_csr_stat(base, bank);
500
-
state->ringuostat = ops->read_csr_uo_stat(base, bank);
501
-
state->ringestat = ops->read_csr_e_stat(base, bank);
502
-
state->ringnestat = ops->read_csr_ne_stat(base, bank);
503
-
state->ringnfstat = ops->read_csr_nf_stat(base, bank);
504
-
state->ringfstat = ops->read_csr_f_stat(base, bank);
505
-
state->ringcstat0 = ops->read_csr_c_stat(base, bank);
506
-
state->iaintflagen = ops->read_csr_int_en(base, bank);
507
-
state->iaintflagreg = ops->read_csr_int_flag(base, bank);
508
-
state->iaintflagsrcsel0 = ops->read_csr_int_srcsel(base, bank);
509
-
state->iaintcolen = ops->read_csr_int_col_en(base, bank);
510
-
state->iaintcolctl = ops->read_csr_int_col_ctl(base, bank);
511
-
state->iaintflagandcolen = ops->read_csr_int_flag_and_col(base, bank);
512
-
state->ringexpstat = ops->read_csr_exp_stat(base, bank);
513
-
state->ringexpintenable = ops->read_csr_exp_int_en(base, bank);
514
-
state->ringsrvarben = ops->read_csr_ring_srv_arb_en(base, bank);
515
-
516
-
for (i = 0; i < num_rings; i++) {
517
-
state->rings[i].head = ops->read_csr_ring_head(base, bank, i);
518
-
state->rings[i].tail = ops->read_csr_ring_tail(base, bank, i);
519
-
state->rings[i].config = ops->read_csr_ring_config(base, bank, i);
520
-
state->rings[i].base = ops->read_csr_ring_base(base, bank, i);
521
-
}
522
-
}
523
-
524
-
static inline int check_stat(u32 (*op)(void __iomem *, u32), u32 expect_val,
525
-
const char *name, void __iomem *base, u32 bank)
526
-
{
527
-
u32 actual_val = op(base, bank);
528
-
529
-
if (expect_val == actual_val)
530
-
return 0;
531
-
532
-
pr_err("Fail to restore %s register. Expected %#x, actual %#x\n",
533
-
name, expect_val, actual_val);
534
-
535
-
return -EINVAL;
536
-
}
537
-
538
-
static int bank_state_restore(struct adf_hw_csr_ops *ops, void __iomem *base,
539
-
u32 bank, struct bank_state *state, u32 num_rings,
540
-
int tx_rx_gap)
541
-
{
542
-
u32 val, tmp_val, i;
543
-
int ret;
544
-
545
-
for (i = 0; i < num_rings; i++)
546
-
ops->write_csr_ring_base(base, bank, i, state->rings[i].base);
547
-
548
-
for (i = 0; i < num_rings; i++)
549
-
ops->write_csr_ring_config(base, bank, i, state->rings[i].config);
550
-
551
-
for (i = 0; i < num_rings / 2; i++) {
552
-
int tx = i * (tx_rx_gap + 1);
553
-
int rx = tx + tx_rx_gap;
554
-
555
-
ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);
556
-
ops->write_csr_ring_tail(base, bank, tx, state->rings[tx].tail);
557
-
558
-
/*
559
-
* The TX ring head needs to be updated again to make sure that
560
-
* the HW will not consider the ring as full when it is empty
561
-
* and the correct state flags are set to match the recovered state.
562
-
*/
563
-
if (state->ringestat & BIT(tx)) {
564
-
val = ops->read_csr_int_srcsel(base, bank);
565
-
val |= ADF_RP_INT_SRC_SEL_F_RISE_MASK;
566
-
ops->write_csr_int_srcsel_w_val(base, bank, val);
567
-
ops->write_csr_ring_head(base, bank, tx, state->rings[tx].head);
568
-
}
569
-
570
-
ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);
571
-
val = ops->read_csr_int_srcsel(base, bank);
572
-
val |= ADF_RP_INT_SRC_SEL_F_RISE_MASK << ADF_RP_INT_SRC_SEL_RANGE_WIDTH;
573
-
ops->write_csr_int_srcsel_w_val(base, bank, val);
574
-
575
-
ops->write_csr_ring_head(base, bank, rx, state->rings[rx].head);
576
-
val = ops->read_csr_int_srcsel(base, bank);
577
-
val |= ADF_RP_INT_SRC_SEL_F_FALL_MASK << ADF_RP_INT_SRC_SEL_RANGE_WIDTH;
578
-
ops->write_csr_int_srcsel_w_val(base, bank, val);
579
-
580
-
/*
581
-
* The RX ring tail needs to be updated again to make sure that
582
-
* the HW will not consider the ring as empty when it is full
583
-
* and the correct state flags are set to match the recovered state.
584
-
*/
585
-
if (state->ringfstat & BIT(rx))
586
-
ops->write_csr_ring_tail(base, bank, rx, state->rings[rx].tail);
587
-
}
588
-
589
-
ops->write_csr_int_flag_and_col(base, bank, state->iaintflagandcolen);
590
-
ops->write_csr_int_en(base, bank, state->iaintflagen);
591
-
ops->write_csr_int_col_en(base, bank, state->iaintcolen);
592
-
ops->write_csr_int_srcsel_w_val(base, bank, state->iaintflagsrcsel0);
593
-
ops->write_csr_exp_int_en(base, bank, state->ringexpintenable);
594
-
ops->write_csr_int_col_ctl(base, bank, state->iaintcolctl);
595
-
596
-
/*
597
-
* Verify whether any exceptions were raised during the bank save process.
598
-
* If exceptions occurred, the status and exception registers cannot
599
-
* be directly restored. Consequently, further restoration is not
600
-
* feasible, and the current state of the ring should be maintained.
601
-
*/
602
-
val = state->ringexpstat;
603
-
if (val) {
604
-
pr_info("Bank %u state not fully restored due to exception in saved state (%#x)\n",
605
-
bank, val);
606
-
return 0;
607
-
}
608
-
609
-
/* Ensure that the restoration process completed without exceptions */
610
-
tmp_val = ops->read_csr_exp_stat(base, bank);
611
-
if (tmp_val) {
612
-
pr_err("Bank %u restored with exception: %#x\n", bank, tmp_val);
613
-
return -EFAULT;
614
-
}
615
-
616
-
ops->write_csr_ring_srv_arb_en(base, bank, state->ringsrvarben);
617
-
618
-
/* Check that all ring statuses match the saved state. */
619
-
ret = check_stat(ops->read_csr_stat, state->ringstat0, "ringstat",
620
-
base, bank);
621
-
if (ret)
622
-
return ret;
623
-
624
-
ret = check_stat(ops->read_csr_e_stat, state->ringestat, "ringestat",
625
-
base, bank);
626
-
if (ret)
627
-
return ret;
628
-
629
-
ret = check_stat(ops->read_csr_ne_stat, state->ringnestat, "ringnestat",
630
-
base, bank);
631
-
if (ret)
632
-
return ret;
633
-
634
-
ret = check_stat(ops->read_csr_nf_stat, state->ringnfstat, "ringnfstat",
635
-
base, bank);
636
-
if (ret)
637
-
return ret;
638
-
639
-
ret = check_stat(ops->read_csr_f_stat, state->ringfstat, "ringfstat",
640
-
base, bank);
641
-
if (ret)
642
-
return ret;
643
-
644
-
ret = check_stat(ops->read_csr_c_stat, state->ringcstat0, "ringcstat",
645
-
base, bank);
646
-
if (ret)
647
-
return ret;
648
-
649
-
return 0;
650
-
}
651
-
652
-
int adf_gen4_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
653
-
struct bank_state *state)
654
-
{
655
-
struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
656
-
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
657
-
void __iomem *csr_base = adf_get_etr_base(accel_dev);
658
-
659
-
if (bank_number >= hw_data->num_banks || !state)
660
-
return -EINVAL;
661
-
662
-
dev_dbg(&GET_DEV(accel_dev), "Saving state of bank %d\n", bank_number);
663
-
664
-
bank_state_save(csr_ops, csr_base, bank_number, state,
665
-
hw_data->num_rings_per_bank);
666
-
667
-
return 0;
668
-
}
669
-
EXPORT_SYMBOL_GPL(adf_gen4_bank_state_save);
670
-
671
-
int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number,
672
-
struct bank_state *state)
673
-
{
674
-
struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
675
-
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
676
-
void __iomem *csr_base = adf_get_etr_base(accel_dev);
677
-
int ret;
678
-
679
-
if (bank_number >= hw_data->num_banks || !state)
680
-
return -EINVAL;
681
-
682
-
dev_dbg(&GET_DEV(accel_dev), "Restoring state of bank %d\n", bank_number);
683
-
684
-
ret = bank_state_restore(csr_ops, csr_base, bank_number, state,
685
-
hw_data->num_rings_per_bank, hw_data->tx_rx_gap);
686
-
if (ret)
687
-
dev_err(&GET_DEV(accel_dev),
688
-
"Unable to restore state of bank %d\n", bank_number);
689
-
690
-
return ret;
691
-
}
692
-
EXPORT_SYMBOL_GPL(adf_gen4_bank_state_restore);
693
-
694
494
static int adf_gen4_build_comp_block(void *ctx, enum adf_dc_algo algo)
695
495
{
696
496
struct icp_qat_fw_comp_req *req_tmpl = ctx;
-7
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
-7
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
···
84
84
#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)
85
85
86
86
/* Ring interrupt */
87
-
#define ADF_RP_INT_SRC_SEL_F_RISE_MASK GENMASK(1, 0)
88
-
#define ADF_RP_INT_SRC_SEL_F_FALL_MASK GENMASK(2, 0)
89
-
#define ADF_RP_INT_SRC_SEL_RANGE_WIDTH 4
90
87
#define ADF_COALESCED_POLL_TIMEOUT_US (1 * USEC_PER_SEC)
91
88
#define ADF_COALESCED_POLL_DELAY_US 1000
92
89
#define ADF_WQM_CSR_RPINTSOU(bank) (0x200000 + ((bank) << 12))
···
173
176
u32 bank_number, int timeout_us);
174
177
void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev,
175
178
u32 bank_number);
176
-
int adf_gen4_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
177
-
struct bank_state *state);
178
-
int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev,
179
-
u32 bank_number, struct bank_state *state);
180
179
bool adf_gen4_services_supported(unsigned long service_mask);
181
180
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
182
181