tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'cxl-fixes-6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

Pull Compute Express Link fixes from Dave Jiang:
"A small collection of CXL fixes. In addition to some misc fixes for
the CXL subsystem, a number of fixes for CXL extended linear cache
support are included to make it functional again.

- Avoid missing port component registers setup due to dport
enumeration failure

- Add check for no entries in cxl_feature_info to address accessing
invalid pointer.

- Use %pa printk format to emit resource_size_t in
validate_region_offset()

CXL extended linear cache support fixes:

- Fix setup of memory resource in cxl_acpi_set_cache_size()

- Set range param for region_res_match_cxl_range() as const
(addresses a compile warning for match_region_by_range() fix)

- Fix match_region_by_range() to use region_res_match_cxl_range()

- Subtract to find an hpa_alias0 in cxl_poison events to correct the
alias math calculation"

* tag 'cxl-fixes-6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
cxl/trace: Subtract to find an hpa_alias0 in cxl_poison events
cxl/region: Use %pa printk format to emit resource_size_t
cxl: Fix match_region_by_range() to use region_res_match_cxl_range()
cxl: Set range param for region_res_match_cxl_range() as const
cxl/acpi: Fix setup of memory resource in cxl_acpi_set_cache_size()
cxl/features: Add check for no entries in cxl_feature_info
cxl/port: Avoid missing port component registers setup

Linus Torvalds ea0bdf2b 2953fb65

+23 -21
+1 -1
drivers/cxl/acpi.c
··· 348 348 struct resource res; 349 349 int nid, rc; 350 350 351 - res = DEFINE_RES(start, size, 0); 351 + res = DEFINE_RES_MEM(start, size); 352 352 nid = phys_to_target_node(start); 353 353 354 354 rc = hmat_get_extended_linear_cache_size(&res, nid, &cache_size);
+3
drivers/cxl/core/features.c
··· 371 371 { 372 372 struct cxl_feat_entry *feat; 373 373 374 + if (!cxlfs || !cxlfs->entries) 375 + return ERR_PTR(-EOPNOTSUPP); 376 + 374 377 for (int i = 0; i < cxlfs->entries->num_features; i++) { 375 378 feat = &cxlfs->entries->ent[i]; 376 379 if (uuid_equal(uuid, &feat->uuid))
+14 -12
drivers/cxl/core/port.c
··· 1182 1182 if (rc) 1183 1183 return ERR_PTR(rc); 1184 1184 1185 + /* 1186 + * Setup port register if this is the first dport showed up. Having 1187 + * a dport also means that there is at least 1 active link. 1188 + */ 1189 + if (port->nr_dports == 1 && 1190 + port->component_reg_phys != CXL_RESOURCE_NONE) { 1191 + rc = cxl_port_setup_regs(port, port->component_reg_phys); 1192 + if (rc) { 1193 + xa_erase(&port->dports, (unsigned long)dport->dport_dev); 1194 + return ERR_PTR(rc); 1195 + } 1196 + port->component_reg_phys = CXL_RESOURCE_NONE; 1197 + } 1198 + 1185 1199 get_device(dport_dev); 1186 1200 rc = devm_add_action_or_reset(host, cxl_dport_remove, dport); 1187 1201 if (rc) ··· 1213 1199 dport->link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev)); 1214 1200 1215 1201 cxl_debugfs_create_dport_dir(dport); 1216 - 1217 - /* 1218 - * Setup port register if this is the first dport showed up. Having 1219 - * a dport also means that there is at least 1 active link. 1220 - */ 1221 - if (port->nr_dports == 1 && 1222 - port->component_reg_phys != CXL_RESOURCE_NONE) { 1223 - rc = cxl_port_setup_regs(port, port->component_reg_phys); 1224 - if (rc) 1225 - return ERR_PTR(rc); 1226 - port->component_reg_phys = CXL_RESOURCE_NONE; 1227 - } 1228 1202 1229 1203 return dport; 1230 1204 }
+4 -7
drivers/cxl/core/region.c
··· 839 839 } 840 840 841 841 static bool region_res_match_cxl_range(const struct cxl_region_params *p, 842 - struct range *range) 842 + const struct range *range) 843 843 { 844 844 if (!p->res) 845 845 return false; ··· 3398 3398 p = &cxlr->params; 3399 3399 3400 3400 guard(rwsem_read)(&cxl_rwsem.region); 3401 - if (p->res && p->res->start == r->start && p->res->end == r->end) 3402 - return 1; 3403 - 3404 - return 0; 3401 + return region_res_match_cxl_range(p, r); 3405 3402 } 3406 3403 3407 3404 static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr, ··· 3663 3666 3664 3667 if (offset < p->cache_size) { 3665 3668 dev_err(&cxlr->dev, 3666 - "Offset %#llx is within extended linear cache %pr\n", 3669 + "Offset %#llx is within extended linear cache %pa\n", 3667 3670 offset, &p->cache_size); 3668 3671 return -EINVAL; 3669 3672 } 3670 3673 3671 3674 region_size = resource_size(p->res); 3672 3675 if (offset >= region_size) { 3673 - dev_err(&cxlr->dev, "Offset %#llx exceeds region size %pr\n", 3676 + dev_err(&cxlr->dev, "Offset %#llx exceeds region size %pa\n", 3674 3677 offset, &region_size); 3675 3678 return -EINVAL; 3676 3679 }
+1 -1
drivers/cxl/core/trace.h
··· 1068 1068 __entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd, 1069 1069 __entry->dpa); 1070 1070 if (__entry->hpa != ULLONG_MAX && cxlr->params.cache_size) 1071 - __entry->hpa_alias0 = __entry->hpa + 1071 + __entry->hpa_alias0 = __entry->hpa - 1072 1072 cxlr->params.cache_size; 1073 1073 else 1074 1074 __entry->hpa_alias0 = ULLONG_MAX;