Merge tag 'spi-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

+82

Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2025 Amlogic, Inc. All rights reserved 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: SPI flash controller for Amlogic ARM SoCs 9 + 10 + maintainers: 11 + - Liang Yang <liang.yang@amlogic.com> 12 + - Feng Chen <feng.chen@amlogic.com> 13 + - Xianwei Zhao <xianwei.zhao@amlogic.com> 14 + 15 + description: 16 + The Amlogic SPI flash controller is an extended version of the Amlogic NAND 17 + flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the Host 18 + ECC HW engine could be enabled). 19 + 20 + allOf: 21 + - $ref: /schemas/spi/spi-controller.yaml# 22 + 23 + properties: 24 + compatible: 25 + const: amlogic,a4-spifc 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + clocks: 31 + items: 32 + - description: clock apb gate 33 + - description: clock used for the controller 34 + 35 + clock-names: 36 + items: 37 + - const: gate 38 + - const: core 39 + 40 + interrupts: 41 + maxItems: 1 42 + 43 + amlogic,rx-adj: 44 + description: 45 + Number of clock cycles by which sampling is delayed. 46 + $ref: /schemas/types.yaml#/definitions/uint32 47 + enum: [0, 1, 2, 3] 48 + default: 0 49 + 50 + required: 51 + - compatible 52 + - reg 53 + - clocks 54 + - clock-names 55 + 56 + unevaluatedProperties: false 57 + 58 + examples: 59 + - | 60 + sfc0: spi@fe08d000 { 61 + compatible = "amlogic,a4-spifc"; 62 + reg = <0xfe08d000 0x800>; 63 + clocks = <&clkc_periphs 31>, 64 + <&clkc_periphs 102>; 65 + clock-names = "gate", "core"; 66 + 67 + pinctrl-0 = <&spiflash_default>; 68 + pinctrl-names = "default"; 69 + 70 + #address-cells = <1>; 71 + #size-cells = <0>; 72 + 73 + flash@0 { 74 + compatible = "spi-nand"; 75 + reg = <0>; 76 + #address-cells = <1>; 77 + #size-cells = <1>; 78 + nand-ecc-engine = <&sfc0>; 79 + nand-ecc-strength = <8>; 80 + nand-ecc-step-size = <512>; 81 + }; 82 + };

+8 -3

Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml

··· 31 31 maxItems: 1 32 32 33 33 clock-names: 34 - contains: 35 - const: spi_clk 34 + items: 35 + - const: spi_clk 36 + - const: spi_gclk 37 + minItems: 1 36 38 37 39 clocks: 38 - maxItems: 1 40 + items: 41 + - description: Peripheral Bus clock 42 + - description: Programmable Generic clock 43 + minItems: 1 39 44 40 45 dmas: 41 46 items:

+3

Documentation/devicetree/bindings/spi/atmel,quadspi.yaml

··· 17 17 enum: 18 18 - atmel,sama5d2-qspi 19 19 - microchip,sam9x60-qspi 20 + - microchip,sam9x7-ospi 21 + - microchip,sama7d65-qspi 22 + - microchip,sama7d65-ospi 20 23 - microchip,sama7g5-qspi 21 24 - microchip,sama7g5-ospi 22 25

-1

Documentation/devicetree/bindings/spi/samsung,spi.yaml

··· 18 18 oneOf: 19 19 - enum: 20 20 - google,gs101-spi 21 - - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 22 21 - samsung,s3c6410-spi 23 22 - samsung,s5pv210-spi # for S5PV210 and S5PC110 24 23 - samsung,exynos4210-spi

+18 -7

MAINTAINERS

··· 1318 1318 F: Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml 1319 1319 F: drivers/rtc/rtc-amlogic-a4.c 1320 1320 1321 + AMLOGIC SPIFC DRIVER 1322 + M: Liang Yang <liang.yang@amlogic.com> 1323 + M: Feng Chen <feng.chen@amlogic.com> 1324 + M: Xianwei Zhao <xianwei.zhao@amlogic.com> 1325 + L: linux-amlogic@lists.infradead.org 1326 + L: linux-spi@vger.kernel.org 1327 + S: Maintained 1328 + F: Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml 1329 + F: drivers/spi/spi-amlogic-spifc-a4.c 1330 + 1321 1331 AMLOGIC SPISG DRIVER 1322 1332 M: Sunny Luo <sunny.luo@amlogic.com> 1323 1333 M: Xianwei Zhao <xianwei.zhao@amlogic.com> ··· 25748 25738 T: git https://github.com/srcres258/linux-doc.git doc-zh-tw 25749 25739 F: Documentation/translations/zh_TW/ 25750 25740 25751 - TRIGGER SOURCE - ADI UTIL SIGMA DELTA SPI 25752 - M: David Lechner <dlechner@baylibre.com> 25753 - S: Maintained 25754 - F: Documentation/devicetree/bindings/trigger-source/adi,util-sigma-delta-spi.yaml 25755 - 25756 25741 TRIGGER SOURCE 25757 25742 M: David Lechner <dlechner@baylibre.com> 25758 25743 S: Maintained 25759 - F: Documentation/devicetree/bindings/trigger-source/gpio-trigger.yaml 25760 - F: Documentation/devicetree/bindings/trigger-source/pwm-trigger.yaml 25744 + F: Documentation/devicetree/bindings/trigger-source/* 25761 25745 25762 25746 TRUSTED SECURITY MODULE (TSM) INFRASTRUCTURE 25763 25747 M: Dan Williams <dan.j.williams@intel.com> ··· 26900 26896 S: Maintained 26901 26897 F: include/uapi/linux/virtio_snd.h 26902 26898 F: sound/virtio/* 26899 + 26900 + VIRTIO SPI DRIVER 26901 + M: Haixu Cui <quic_haixcui@quicinc.com> 26902 + L: virtualization@lists.linux.dev 26903 + S: Maintained 26904 + F: drivers/spi/spi-virtio.c 26905 + F: include/uapi/linux/virtio_spi.h 26903 26906 26904 26907 VIRTUAL BOX GUEST DEVICE DRIVER 26905 26908 M: Hans de Goede <hansg@kernel.org>

+23 -1

drivers/spi/Kconfig

··· 99 99 This enables master mode support for the SPIFC (SPI flash 100 100 controller) available in Amlogic A1 (A113L SoC). 101 101 102 + config SPI_AMLOGIC_SPIFC_A4 103 + tristate "Amlogic A4 SPI Flash controller" 104 + depends on ARCH_MESON || COMPILE_TEST 105 + select REGMAP_MMIO 106 + help 107 + This enables SPI mode on the NAND Flash Controller of Amlogic 108 + ARM SoCs. It supports SPI Nor Flash and SPI NAND Flash (Could 109 + enable Host ECC HW engine). The controller implements the 110 + SPI-MEM interface, it doesn't support generic SPI. 111 + 102 112 config SPI_AMLOGIC_SPISG 103 113 tristate "Amlogic SPISG controller" 104 114 depends on COMMON_CLK ··· 926 916 927 917 config SPI_RB4XX 928 918 tristate "Mikrotik RB4XX SPI master" 929 - depends on SPI_MASTER && ATH79 919 + depends on SPI_MASTER && (ATH79 || COMPILE_TEST) 920 + depends on OF 930 921 help 931 922 SPI controller driver for the Mikrotik RB4xx series boards. 932 923 ··· 1234 1223 This driver supports SCSSI only. 1235 1224 1236 1225 If your SoC supports SCSSI, say Y here. 1226 + 1227 + config SPI_VIRTIO 1228 + tristate "Virtio SPI Controller" 1229 + depends on SPI_MASTER && VIRTIO 1230 + help 1231 + If you say yes to this option, support will be included for the virtio 1232 + SPI controller driver. The hardware can be emulated by any device model 1233 + software according to the virtio protocol. 1234 + 1235 + This driver can also be built as a module. If so, the module 1236 + will be called spi-virtio. 1237 1237 1238 1238 config SPI_XCOMM 1239 1239 tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"

+2

drivers/spi/Makefile

··· 20 20 obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o 21 21 obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o 22 22 obj-$(CONFIG_SPI_AMLOGIC_SPIFC_A1) += spi-amlogic-spifc-a1.o 23 + obj-$(CONFIG_SPI_AMLOGIC_SPIFC_A4) += spi-amlogic-spifc-a4.o 23 24 obj-$(CONFIG_SPI_AMLOGIC_SPISG) += spi-amlogic-spisg.o 24 25 obj-$(CONFIG_SPI_APPLE) += spi-apple.o 25 26 obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o ··· 159 158 obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o 160 159 obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o 161 160 obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o 161 + obj-$(CONFIG_SPI_VIRTIO) += spi-virtio.o 162 162 obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o 163 163 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o 164 164 obj-$(CONFIG_SPI_XLP) += spi-xlp.o

+102 -32

drivers/spi/atmel-quadspi.c

··· 63 63 64 64 #define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 65 65 #define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 66 + #define SAM9X7_QSPI_MAX_SPEED_HZ 100000000 66 67 67 68 /* Bitfields in QSPI_CR (Control Register) */ 68 69 #define QSPI_CR_QSPIEN BIT(0) ··· 263 262 bool has_ricr; 264 263 bool octal; 265 264 bool has_dma; 265 + bool has_2xgclk; 266 + bool has_padcalib; 267 + bool has_dllon; 266 268 }; 267 269 268 270 struct atmel_qspi_ops; ··· 1031 1027 aq, QSPI_PCALCFG); 1032 1028 1033 1029 /* DLL On + start calibration. */ 1034 - atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); 1030 + if (aq->caps->has_dllon) 1031 + atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); 1032 + /* If there is no DLL support only start calibration. */ 1033 + else 1034 + atmel_qspi_write(QSPI_CR_STPCAL, aq, QSPI_CR); 1035 1035 1036 - /* Check synchronization status before updating configuration. */ 1037 - ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1038 - (val & QSPI_SR2_DLOCK) && 1039 - !(val & QSPI_SR2_CALBSY), 40, 1040 - ATMEL_QSPI_TIMEOUT); 1036 + /* 1037 + * Check DLL clock lock and synchronization status before updating 1038 + * configuration. 1039 + */ 1040 + if (aq->caps->has_dllon) 1041 + ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1042 + (val & QSPI_SR2_DLOCK) && 1043 + !(val & QSPI_SR2_CALBSY), 40, 1044 + ATMEL_QSPI_TIMEOUT); 1045 + else 1046 + ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1047 + !(val & QSPI_SR2_CALBSY), 40, 1048 + ATMEL_QSPI_TIMEOUT); 1041 1049 1042 1050 /* Refresh analogic blocks every 1 ms.*/ 1043 1051 atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, ··· 1065 1049 int ret; 1066 1050 1067 1051 /* Disable DLL before setting GCLK */ 1068 - status = atmel_qspi_read(aq, QSPI_SR2); 1069 - if (status & QSPI_SR2_DLOCK) { 1070 - atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); 1052 + if (aq->caps->has_dllon) { 1053 + status = atmel_qspi_read(aq, QSPI_SR2); 1054 + if (status & QSPI_SR2_DLOCK) { 1055 + atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); 1056 + ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1057 + !(val & QSPI_SR2_DLOCK), 40, 1058 + ATMEL_QSPI_TIMEOUT); 1059 + if (ret) 1060 + return ret; 1061 + } 1071 1062 1072 - ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1073 - !(val & QSPI_SR2_DLOCK), 40, 1074 - ATMEL_QSPI_TIMEOUT); 1075 - if (ret) 1076 - return ret; 1063 + if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) 1064 + atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); 1065 + else 1066 + atmel_qspi_write(0, aq, QSPI_DLLCFG); 1077 1067 } 1078 1068 1079 - if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) 1080 - atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); 1069 + if (aq->caps->has_2xgclk) 1070 + ret = clk_set_rate(aq->gclk, 2 * aq->target_max_speed_hz); 1081 1071 else 1082 - atmel_qspi_write(0, aq, QSPI_DLLCFG); 1072 + ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); 1083 1073 1084 - ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); 1085 1074 if (ret) { 1086 1075 dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); 1087 1076 return ret; ··· 1109 1088 if (ret) 1110 1089 return ret; 1111 1090 1112 - if (aq->caps->octal) { 1091 + /* 1092 + * Check if the SoC supports pad calibration in Octal SPI mode. 1093 + * Proceed only if both the capabilities are true. 1094 + */ 1095 + if (aq->caps->octal && aq->caps->has_padcalib) { 1113 1096 ret = atmel_qspi_set_pad_calibration(aq); 1114 1097 if (ret) 1115 1098 return ret; 1116 - } else { 1099 + /* Start DLL on only if the SoC supports the same */ 1100 + } else if (aq->caps->has_dllon) { 1117 1101 atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); 1118 1102 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1119 1103 (val & QSPI_SR2_DLOCK), 40, ··· 1484 1458 1485 1459 clk_disable_unprepare(aq->gclk); 1486 1460 1487 - atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); 1488 - ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1489 - !(val & QSPI_SR2_DLOCK), 40, 1490 - ATMEL_QSPI_TIMEOUT); 1491 - if (ret) 1492 - return ret; 1461 + if (aq->caps->has_dllon) { 1462 + atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); 1463 + ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1464 + !(val & QSPI_SR2_DLOCK), 40, 1465 + ATMEL_QSPI_TIMEOUT); 1466 + if (ret) 1467 + return ret; 1468 + } 1493 1469 1494 - ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, 1495 - !(val & QSPI_SR2_CALBSY), 40, 1496 - ATMEL_QSPI_TIMEOUT); 1497 - if (ret) 1498 - return ret; 1499 - 1470 + if (aq->caps->has_padcalib) 1471 + return readl_poll_timeout(aq->regs + QSPI_SR2, val, 1472 + !(val & QSPI_SR2_CALBSY), 40, 1473 + ATMEL_QSPI_TIMEOUT); 1500 1474 return 0; 1501 1475 } 1502 1476 ··· 1628 1602 .has_ricr = true, 1629 1603 }; 1630 1604 1605 + static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps = { 1606 + .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ, 1607 + .has_gclk = true, 1608 + .octal = true, 1609 + .has_dma = true, 1610 + .has_2xgclk = true, 1611 + .has_padcalib = false, 1612 + .has_dllon = false, 1613 + }; 1614 + 1615 + static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps = { 1616 + .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, 1617 + .has_gclk = true, 1618 + .octal = true, 1619 + .has_dma = true, 1620 + .has_2xgclk = true, 1621 + .has_padcalib = true, 1622 + .has_dllon = false, 1623 + }; 1624 + 1625 + static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps = { 1626 + .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, 1627 + .has_gclk = true, 1628 + .has_dma = true, 1629 + .has_2xgclk = true, 1630 + .has_dllon = false, 1631 + }; 1632 + 1631 1633 static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { 1632 1634 .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, 1633 1635 .has_gclk = true, 1634 1636 .octal = true, 1635 1637 .has_dma = true, 1638 + .has_padcalib = true, 1639 + .has_dllon = true, 1636 1640 }; 1637 1641 1638 1642 static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = { 1639 1643 .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, 1640 1644 .has_gclk = true, 1641 1645 .has_dma = true, 1646 + .has_dllon = true, 1642 1647 }; 1643 1648 1644 1649 static const struct of_device_id atmel_qspi_dt_ids[] = { ··· 1689 1632 .compatible = "microchip,sama7g5-qspi", 1690 1633 .data = &atmel_sama7g5_qspi_caps, 1691 1634 }, 1635 + { 1636 + .compatible = "microchip,sam9x7-ospi", 1637 + .data = &atmel_sam9x7_ospi_caps, 1638 + }, 1639 + { 1640 + .compatible = "microchip,sama7d65-ospi", 1641 + .data = &atmel_sama7d65_ospi_caps, 1642 + }, 1643 + { 1644 + .compatible = "microchip,sama7d65-qspi", 1645 + .data = &atmel_sama7d65_qspi_caps, 1646 + }, 1647 + 1692 1648 1693 1649 { /* sentinel */ } 1694 1650 };

-1

drivers/spi/spi-altera-platform.c

··· 30 30 .reg_bits = 32, 31 31 .reg_stride = 4, 32 32 .val_bits = 32, 33 - .fast_io = true, 34 33 }; 35 34 36 35 static int altera_spi_probe(struct platform_device *pdev)

+2 -3

drivers/spi/spi-amd-pci.c

··· 38 38 /* Allocate storage for host and driver private data */ 39 39 host = devm_spi_alloc_host(dev, sizeof(struct amd_spi)); 40 40 if (!host) 41 - return dev_err_probe(dev, -ENOMEM, "Error allocating SPI host\n"); 41 + return -ENOMEM; 42 42 43 43 amd_spi = spi_controller_get_devdata(host); 44 44 ··· 47 47 amd_spi->io_remap_addr = devm_ioremap(dev, io_base_addr, AMD_HID2_MEM_SIZE); 48 48 49 49 if (!amd_spi->io_remap_addr) 50 - return dev_err_probe(dev, -ENOMEM, 51 - "ioremap of SPI registers failed\n"); 50 + return -ENOMEM; 52 51 53 52 dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); 54 53

+1 -1

drivers/spi/spi-amd.c

··· 857 857 /* Allocate storage for host and driver private data */ 858 858 host = devm_spi_alloc_host(dev, sizeof(struct amd_spi)); 859 859 if (!host) 860 - return dev_err_probe(dev, -ENOMEM, "Error allocating SPI host\n"); 860 + return -ENOMEM; 861 861 862 862 amd_spi = spi_controller_get_devdata(host); 863 863 amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);

+1222

drivers/spi/spi-amlogic-spifc-a4.c

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 + /* 3 + * Copyright (C) 2025 Amlogic, Inc. All rights reserved 4 + * 5 + * Driver for the SPI Mode of Amlogic Flash Controller 6 + * Authors: 7 + * Liang Yang <liang.yang@amlogic.com> 8 + * Feng Chen <feng.chen@amlogic.com> 9 + * Xianwei Zhao <xianwei.zhao@amlogic.com> 10 + */ 11 + 12 + #include <linux/platform_device.h> 13 + #include <linux/clk-provider.h> 14 + #include <linux/dma-mapping.h> 15 + #include <linux/bitfield.h> 16 + #include <linux/module.h> 17 + #include <linux/slab.h> 18 + #include <linux/of.h> 19 + #include <linux/clk.h> 20 + #include <linux/delay.h> 21 + #include <linux/bitops.h> 22 + #include <linux/regmap.h> 23 + #include <linux/mtd/spinand.h> 24 + #include <linux/spi/spi-mem.h> 25 + 26 + #define SFC_CMD 0x00 27 + #define SFC_CFG 0x04 28 + #define SFC_DADR 0x08 29 + #define SFC_IADR 0x0c 30 + #define SFC_BUF 0x10 31 + #define SFC_INFO 0x14 32 + #define SFC_DC 0x18 33 + #define SFC_ADR 0x1c 34 + #define SFC_DL 0x20 35 + #define SFC_DH 0x24 36 + #define SFC_CADR 0x28 37 + #define SFC_SADR 0x2c 38 + #define SFC_RX_IDX 0x34 39 + #define SFC_RX_DAT 0x38 40 + #define SFC_SPI_CFG 0x40 41 + 42 + /* settings in SFC_CMD */ 43 + 44 + /* 4 bits support 4 chip select, high false, low select but spi support 2*/ 45 + #define CHIP_SELECT_MASK GENMASK(13, 10) 46 + #define CS_NONE 0xf 47 + #define CS_0 0xe 48 + #define CS_1 0xd 49 + 50 + #define CLE (0x5 << 14) 51 + #define ALE (0x6 << 14) 52 + #define DWR (0x4 << 14) 53 + #define DRD (0x8 << 14) 54 + #define DUMMY (0xb << 14) 55 + #define IDLE (0xc << 14) 56 + #define IDLE_CYCLE_MASK GENMASK(9, 0) 57 + #define EXT_CYCLE_MASK GENMASK(9, 0) 58 + 59 + #define OP_M2N ((0 << 17) | (2 << 20)) 60 + #define OP_N2M ((1 << 17) | (2 << 20)) 61 + #define OP_STS ((3 << 17) | (2 << 20)) 62 + #define OP_ADL ((0 << 16) | (3 << 20)) 63 + #define OP_ADH ((1 << 16) | (3 << 20)) 64 + #define OP_AIL ((2 << 16) | (3 << 20)) 65 + #define OP_AIH ((3 << 16) | (3 << 20)) 66 + #define OP_ASL ((4 << 16) | (3 << 20)) 67 + #define OP_ASH ((5 << 16) | (3 << 20)) 68 + #define OP_SEED ((8 << 16) | (3 << 20)) 69 + #define SEED_MASK GENMASK(14, 0) 70 + #define ENABLE_RANDOM BIT(19) 71 + 72 + #define CMD_COMMAND(cs_sel, cmd) (CLE | ((cs_sel) << 10) | (cmd)) 73 + #define CMD_ADDR(cs_sel, addr) (ALE | ((cs_sel) << 10) | (addr)) 74 + #define CMD_DUMMY(cs_sel, cyc) (DUMMY | ((cs_sel) << 10) | ((cyc) & EXT_CYCLE_MASK)) 75 + #define CMD_IDLE(cs_sel, cyc) (IDLE | ((cs_sel) << 10) | ((cyc) & IDLE_CYCLE_MASK)) 76 + #define CMD_MEM2NAND(bch, pages) (OP_M2N | ((bch) << 14) | (pages)) 77 + #define CMD_NAND2MEM(bch, pages) (OP_N2M | ((bch) << 14) | (pages)) 78 + #define CMD_DATA_ADDRL(addr) (OP_ADL | ((addr) & 0xffff)) 79 + #define CMD_DATA_ADDRH(addr) (OP_ADH | (((addr) >> 16) & 0xffff)) 80 + #define CMD_INFO_ADDRL(addr) (OP_AIL | ((addr) & 0xffff)) 81 + #define CMD_INFO_ADDRH(addr) (OP_AIH | (((addr) >> 16) & 0xffff)) 82 + #define CMD_SEED(seed) (OP_SEED | ((seed) & SEED_MASK)) 83 + 84 + #define GET_CMD_SIZE(x) (((x) >> 22) & GENMASK(4, 0)) 85 + 86 + #define DEFAULT_PULLUP_CYCLE 2 87 + #define CS_SETUP_CYCLE 1 88 + #define CS_HOLD_CYCLE 2 89 + #define DEFAULT_BUS_CYCLE 4 90 + 91 + #define RAW_SIZE GENMASK(13, 0) 92 + #define RAW_SIZE_BW 14 93 + 94 + #define DMA_ADDR_ALIGN 8 95 + 96 + /* Bit fields in SFC_SPI_CFG */ 97 + #define SPI_MODE_EN BIT(31) 98 + #define RAW_EXT_SIZE GENMASK(29, 18) 99 + #define ADDR_LANE GENMASK(17, 16) 100 + #define CPOL BIT(15) 101 + #define CPHA BIT(14) 102 + #define EN_HOLD BIT(13) 103 + #define EN_WP BIT(12) 104 + #define TXADJ GENMASK(11, 8) 105 + #define RXADJ GENMASK(7, 4) 106 + #define CMD_LANE GENMASK(3, 2) 107 + #define DATA_LANE GENMASK(1, 0) 108 + #define LANE_MAX 0x3 109 + 110 + /* raw ext size[25:14] + raw size[13:0] */ 111 + #define RAW_MAX_RW_SIZE_MASK GENMASK(25, 0) 112 + 113 + /* Ecc fields */ 114 + #define ECC_COMPLETE BIT(31) 115 + #define ECC_UNCORRECTABLE 0x3f 116 + #define ECC_ERR_CNT(x) (((x) >> 24) & 0x3f) 117 + #define ECC_ZERO_CNT(x) (((x) >> 16) & 0x3f) 118 + 119 + #define ECC_BCH8_512 1 120 + #define ECC_BCH8_1K 2 121 + #define ECC_BCH8_PARITY_BYTES 14 122 + #define ECC_BCH8_USER_BYTES 2 123 + #define ECC_BCH8_INFO_BYTES (ECC_BCH8_USER_BYTES + ECC_BCH8_PARITY_BYTES) 124 + #define ECC_BCH8_STRENGTH 8 125 + #define ECC_BCH8_DEFAULT_STEP 512 126 + #define ECC_DEFAULT_BCH_MODE ECC_BCH8_512 127 + #define ECC_PER_INFO_BYTE 8 128 + #define ECC_PATTERN 0x5a 129 + #define ECC_BCH_MAX_SECT_SIZE 63 130 + /* soft flags for sfc */ 131 + #define SFC_HWECC BIT(0) 132 + #define SFC_DATA_RANDOM BIT(1) 133 + #define SFC_DATA_ONLY BIT(2) 134 + #define SFC_OOB_ONLY BIT(3) 135 + #define SFC_DATA_OOB BIT(4) 136 + #define SFC_AUTO_OOB BIT(5) 137 + #define SFC_RAW_RW BIT(6) 138 + #define SFC_XFER_MDOE_MASK GENMASK(6, 2) 139 + 140 + #define SFC_DATABUF_SIZE 8192 141 + #define SFC_INFOBUF_SIZE 256 142 + #define SFC_BUF_SIZE (SFC_DATABUF_SIZE + SFC_INFOBUF_SIZE) 143 + 144 + /* !!! PCB and SPI-NAND chip limitations */ 145 + #define SFC_MAX_FREQUENCY (250 * 1000 * 1000) 146 + #define SFC_MIN_FREQUENCY (4 * 1000 * 1000) 147 + #define SFC_BUS_DEFAULT_CLK 40000000 148 + #define SFC_MAX_CS_NUM 2 149 + 150 + /* SPI-FLASH R/W operation cmd */ 151 + #define SPIFLASH_RD_OCTALIO 0xcb 152 + #define SPIFLASH_RD_OCTAL 0x8b 153 + #define SPIFLASH_RD_QUADIO 0xeb 154 + #define SPIFLASH_RD_QUAD 0x6b 155 + #define SPIFLASH_RD_DUALIO 0xbb 156 + #define SPIFLASH_RD_DUAL 0x3b 157 + #define SPIFLASH_RD_FAST 0x0b 158 + #define SPIFLASH_RD 0x03 159 + #define SPIFLASH_WR_OCTALIO 0xC2 160 + #define SPIFLASH_WR_OCTAL 0x82 161 + #define SPIFLASH_WR_QUAD 0x32 162 + #define SPIFLASH_WR 0x02 163 + #define SPIFLASH_UP_QUAD 0x34 164 + #define SPIFLASH_UP 0x84 165 + 166 + struct aml_sfc_ecc_cfg { 167 + u32 stepsize; 168 + u32 nsteps; 169 + u32 strength; 170 + u32 oobsize; 171 + u32 bch; 172 + }; 173 + 174 + struct aml_ecc_stats { 175 + u32 corrected; 176 + u32 bitflips; 177 + u32 failed; 178 + }; 179 + 180 + struct aml_sfc_caps { 181 + struct aml_sfc_ecc_cfg *ecc_caps; 182 + u32 num_ecc_caps; 183 + }; 184 + 185 + struct aml_sfc { 186 + struct device *dev; 187 + struct clk *gate_clk; 188 + struct clk *core_clk; 189 + struct spi_controller *ctrl; 190 + struct regmap *regmap_base; 191 + const struct aml_sfc_caps *caps; 192 + struct nand_ecc_engine ecc_eng; 193 + struct aml_ecc_stats ecc_stats; 194 + dma_addr_t daddr; 195 + dma_addr_t iaddr; 196 + u32 info_bytes; 197 + u32 bus_rate; 198 + u32 flags; 199 + u32 rx_adj; 200 + u32 cs_sel; 201 + u8 *data_buf; 202 + __le64 *info_buf; 203 + u8 *priv; 204 + }; 205 + 206 + #define AML_ECC_DATA(sz, s, b) { .stepsize = (sz), .strength = (s), .bch = (b) } 207 + 208 + static struct aml_sfc_ecc_cfg aml_a113l2_ecc_caps[] = { 209 + AML_ECC_DATA(512, 8, ECC_BCH8_512), 210 + AML_ECC_DATA(1024, 8, ECC_BCH8_1K), 211 + }; 212 + 213 + static const struct aml_sfc_caps aml_a113l2_sfc_caps = { 214 + .ecc_caps = aml_a113l2_ecc_caps, 215 + .num_ecc_caps = ARRAY_SIZE(aml_a113l2_ecc_caps) 216 + }; 217 + 218 + static struct aml_sfc *nand_to_aml_sfc(struct nand_device *nand) 219 + { 220 + struct nand_ecc_engine *eng = nand->ecc.engine; 221 + 222 + return container_of(eng, struct aml_sfc, ecc_eng); 223 + } 224 + 225 + static inline void *aml_sfc_to_ecc_ctx(struct aml_sfc *sfc) 226 + { 227 + return sfc->priv; 228 + } 229 + 230 + static int aml_sfc_wait_cmd_finish(struct aml_sfc *sfc, u64 timeout_ms) 231 + { 232 + u32 cmd_size = 0; 233 + int ret; 234 + 235 + /* 236 + * The SPINAND flash controller employs a two-stage pipeline: 237 + * 1) command prefetch; 2) command execution. 238 + * 239 + * All commands are stored in the FIFO, with one prefetched for execution. 240 + * 241 + * There are cases where the FIFO is detected as empty, yet a command may 242 + * still be in execution and a prefetched command pending execution. 243 + * 244 + * So, send two idle commands to ensure all previous commands have 245 + * been executed. 246 + */ 247 + regmap_write(sfc->regmap_base, SFC_CMD, CMD_IDLE(sfc->cs_sel, 0)); 248 + regmap_write(sfc->regmap_base, SFC_CMD, CMD_IDLE(sfc->cs_sel, 0)); 249 + 250 + /* Wait for the FIFO to empty. */ 251 + ret = regmap_read_poll_timeout(sfc->regmap_base, SFC_CMD, cmd_size, 252 + !GET_CMD_SIZE(cmd_size), 253 + 10, timeout_ms * 1000); 254 + if (ret) 255 + dev_err(sfc->dev, "wait for empty CMD FIFO time out\n"); 256 + 257 + return ret; 258 + } 259 + 260 + static int aml_sfc_pre_transfer(struct aml_sfc *sfc, u32 idle_cycle, u32 cs2clk_cycle) 261 + { 262 + int ret; 263 + 264 + ret = regmap_write(sfc->regmap_base, SFC_CMD, CMD_IDLE(CS_NONE, idle_cycle)); 265 + if (ret) 266 + return ret; 267 + 268 + return regmap_write(sfc->regmap_base, SFC_CMD, CMD_IDLE(sfc->cs_sel, cs2clk_cycle)); 269 + } 270 + 271 + static int aml_sfc_end_transfer(struct aml_sfc *sfc, u32 clk2cs_cycle) 272 + { 273 + int ret; 274 + 275 + ret = regmap_write(sfc->regmap_base, SFC_CMD, CMD_IDLE(sfc->cs_sel, clk2cs_cycle)); 276 + if (ret) 277 + return ret; 278 + 279 + return aml_sfc_wait_cmd_finish(sfc, 0); 280 + } 281 + 282 + static int aml_sfc_set_bus_width(struct aml_sfc *sfc, u8 buswidth, u32 mask) 283 + { 284 + int i; 285 + u32 conf = 0; 286 + 287 + for (i = 0; i <= LANE_MAX; i++) { 288 + if (buswidth == 1 << i) { 289 + conf = i << __bf_shf(mask); 290 + return regmap_update_bits(sfc->regmap_base, SFC_SPI_CFG, 291 + mask, conf); 292 + } 293 + } 294 + 295 + return 0; 296 + } 297 + 298 + static int aml_sfc_send_cmd(struct aml_sfc *sfc, const struct spi_mem_op *op) 299 + { 300 + int i, ret; 301 + u8 val; 302 + 303 + ret = aml_sfc_set_bus_width(sfc, op->cmd.buswidth, CMD_LANE); 304 + if (ret) 305 + return ret; 306 + 307 + for (i = 0; i < op->cmd.nbytes; i++) { 308 + val = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; 309 + ret = regmap_write(sfc->regmap_base, SFC_CMD, CMD_COMMAND(sfc->cs_sel, val)); 310 + if (ret) 311 + return ret; 312 + } 313 + 314 + return 0; 315 + } 316 + 317 + static int aml_sfc_send_addr(struct aml_sfc *sfc, const struct spi_mem_op *op) 318 + { 319 + int i, ret; 320 + u8 val; 321 + 322 + ret = aml_sfc_set_bus_width(sfc, op->addr.buswidth, ADDR_LANE); 323 + if (ret) 324 + return ret; 325 + 326 + for (i = 0; i < op->addr.nbytes; i++) { 327 + val = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; 328 + 329 + ret = regmap_write(sfc->regmap_base, SFC_CMD, CMD_ADDR(sfc->cs_sel, val)); 330 + if (ret) 331 + return ret; 332 + } 333 + 334 + return 0; 335 + } 336 + 337 + static bool aml_sfc_is_xio_op(const struct spi_mem_op *op) 338 + { 339 + switch (op->cmd.opcode) { 340 + case SPIFLASH_RD_OCTALIO: 341 + case SPIFLASH_RD_QUADIO: 342 + case SPIFLASH_RD_DUALIO: 343 + return true; 344 + default: 345 + break; 346 + } 347 + 348 + return false; 349 + } 350 + 351 + static int aml_sfc_send_cmd_addr_dummy(struct aml_sfc *sfc, const struct spi_mem_op *op) 352 + { 353 + u32 dummy_cycle, cmd; 354 + int ret; 355 + 356 + ret = aml_sfc_send_cmd(sfc, op); 357 + if (ret) 358 + return ret; 359 + 360 + ret = aml_sfc_send_addr(sfc, op); 361 + if (ret) 362 + return ret; 363 + 364 + if (op->dummy.nbytes) { 365 + /* Dummy buswidth configuration is not supported */ 366 + if (aml_sfc_is_xio_op(op)) 367 + dummy_cycle = op->dummy.nbytes * 8 / op->data.buswidth; 368 + else 369 + dummy_cycle = op->dummy.nbytes * 8; 370 + cmd = CMD_DUMMY(sfc->cs_sel, dummy_cycle - 1); 371 + return regmap_write(sfc->regmap_base, SFC_CMD, cmd); 372 + } 373 + 374 + return 0; 375 + } 376 + 377 + static bool aml_sfc_is_snand_hwecc_page_op(struct aml_sfc *sfc, const struct spi_mem_op *op) 378 + { 379 + switch (op->cmd.opcode) { 380 + /* SPINAND read from cache cmd */ 381 + case SPIFLASH_RD_QUADIO: 382 + case SPIFLASH_RD_QUAD: 383 + case SPIFLASH_RD_DUALIO: 384 + case SPIFLASH_RD_DUAL: 385 + case SPIFLASH_RD_FAST: 386 + case SPIFLASH_RD: 387 + /* SPINAND write to cache cmd */ 388 + case SPIFLASH_WR_QUAD: 389 + case SPIFLASH_WR: 390 + case SPIFLASH_UP_QUAD: 391 + case SPIFLASH_UP: 392 + if (sfc->flags & SFC_HWECC) 393 + return true; 394 + else 395 + return false; 396 + default: 397 + break; 398 + } 399 + 400 + return false; 401 + } 402 + 403 + static int aml_sfc_dma_buffer_setup(struct aml_sfc *sfc, void *databuf, 404 + int datalen, void *infobuf, int infolen, 405 + enum dma_data_direction dir) 406 + { 407 + u32 cmd = 0; 408 + int ret; 409 + 410 + sfc->daddr = dma_map_single(sfc->dev, databuf, datalen, dir); 411 + ret = dma_mapping_error(sfc->dev, sfc->daddr); 412 + if (ret) { 413 + dev_err(sfc->dev, "DMA mapping error\n"); 414 + goto out_map_data; 415 + } 416 + 417 + cmd = CMD_DATA_ADDRL(sfc->daddr); 418 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 419 + if (ret) 420 + goto out_map_data; 421 + 422 + cmd = CMD_DATA_ADDRH(sfc->daddr); 423 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 424 + if (ret) 425 + goto out_map_data; 426 + 427 + if (infobuf) { 428 + sfc->iaddr = dma_map_single(sfc->dev, infobuf, infolen, dir); 429 + ret = dma_mapping_error(sfc->dev, sfc->iaddr); 430 + if (ret) { 431 + dev_err(sfc->dev, "DMA mapping error\n"); 432 + dma_unmap_single(sfc->dev, sfc->daddr, datalen, dir); 433 + goto out_map_data; 434 + } 435 + 436 + sfc->info_bytes = infolen; 437 + cmd = CMD_INFO_ADDRL(sfc->iaddr); 438 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 439 + if (ret) 440 + goto out_map_info; 441 + 442 + cmd = CMD_INFO_ADDRH(sfc->iaddr); 443 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 444 + if (ret) 445 + goto out_map_info; 446 + } 447 + 448 + return 0; 449 + 450 + out_map_info: 451 + dma_unmap_single(sfc->dev, sfc->iaddr, datalen, dir); 452 + out_map_data: 453 + dma_unmap_single(sfc->dev, sfc->daddr, datalen, dir); 454 + 455 + return ret; 456 + } 457 + 458 + static void aml_sfc_dma_buffer_release(struct aml_sfc *sfc, 459 + int datalen, int infolen, 460 + enum dma_data_direction dir) 461 + { 462 + dma_unmap_single(sfc->dev, sfc->daddr, datalen, dir); 463 + if (infolen) { 464 + dma_unmap_single(sfc->dev, sfc->iaddr, infolen, dir); 465 + sfc->info_bytes = 0; 466 + } 467 + } 468 + 469 + static bool aml_sfc_dma_buffer_is_safe(const void *buffer) 470 + { 471 + if ((uintptr_t)buffer % DMA_ADDR_ALIGN) 472 + return false; 473 + 474 + if (virt_addr_valid(buffer)) 475 + return true; 476 + 477 + return false; 478 + } 479 + 480 + static void *aml_get_dma_safe_input_buf(const struct spi_mem_op *op) 481 + { 482 + if (aml_sfc_dma_buffer_is_safe(op->data.buf.in)) 483 + return op->data.buf.in; 484 + 485 + return kzalloc(op->data.nbytes, GFP_KERNEL); 486 + } 487 + 488 + static void aml_sfc_put_dma_safe_input_buf(const struct spi_mem_op *op, void *buf) 489 + { 490 + if (WARN_ON(op->data.dir != SPI_MEM_DATA_IN) || WARN_ON(!buf)) 491 + return; 492 + 493 + if (buf == op->data.buf.in) 494 + return; 495 + 496 + memcpy(op->data.buf.in, buf, op->data.nbytes); 497 + kfree(buf); 498 + } 499 + 500 + static void *aml_sfc_get_dma_safe_output_buf(const struct spi_mem_op *op) 501 + { 502 + if (aml_sfc_dma_buffer_is_safe(op->data.buf.out)) 503 + return (void *)op->data.buf.out; 504 + 505 + return kmemdup(op->data.buf.out, op->data.nbytes, GFP_KERNEL); 506 + } 507 + 508 + static void aml_sfc_put_dma_safe_output_buf(const struct spi_mem_op *op, const void *buf) 509 + { 510 + if (WARN_ON(op->data.dir != SPI_MEM_DATA_OUT) || WARN_ON(!buf)) 511 + return; 512 + 513 + if (buf != op->data.buf.out) 514 + kfree(buf); 515 + } 516 + 517 + static u64 aml_sfc_cal_timeout_cycle(struct aml_sfc *sfc, const struct spi_mem_op *op) 518 + { 519 + u64 ms; 520 + 521 + /* For each byte we wait for (8 cycles / buswidth) of the SPI clock. */ 522 + ms = 8 * MSEC_PER_SEC * op->data.nbytes / op->data.buswidth; 523 + do_div(ms, sfc->bus_rate / DEFAULT_BUS_CYCLE); 524 + 525 + /* 526 + * Double the value and add a 200 ms tolerance to compensate for 527 + * the impact of specific CS hold time, CS setup time sequences, 528 + * controller burst gaps, and other related timing variations. 529 + */ 530 + ms += ms + 200; 531 + 532 + if (ms > UINT_MAX) 533 + ms = UINT_MAX; 534 + 535 + return ms; 536 + } 537 + 538 + static void aml_sfc_check_ecc_pages_valid(struct aml_sfc *sfc, bool raw) 539 + { 540 + struct aml_sfc_ecc_cfg *ecc_cfg; 541 + __le64 *info; 542 + int ret; 543 + 544 + info = sfc->info_buf; 545 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 546 + info += raw ? 0 : ecc_cfg->nsteps - 1; 547 + 548 + do { 549 + usleep_range(10, 15); 550 + /* info is updated by nfc dma engine*/ 551 + smp_rmb(); 552 + dma_sync_single_for_cpu(sfc->dev, sfc->iaddr, sfc->info_bytes, 553 + DMA_FROM_DEVICE); 554 + ret = le64_to_cpu(*info) & ECC_COMPLETE; 555 + } while (!ret); 556 + } 557 + 558 + static int aml_sfc_raw_io_op(struct aml_sfc *sfc, const struct spi_mem_op *op) 559 + { 560 + void *buf = NULL; 561 + int ret; 562 + bool is_datain = false; 563 + u32 cmd = 0, conf; 564 + u64 timeout_ms; 565 + 566 + if (!op->data.nbytes) 567 + goto end_xfer; 568 + 569 + conf = (op->data.nbytes >> RAW_SIZE_BW) << __bf_shf(RAW_EXT_SIZE); 570 + ret = regmap_update_bits(sfc->regmap_base, SFC_SPI_CFG, RAW_EXT_SIZE, conf); 571 + if (ret) 572 + goto err_out; 573 + 574 + if (op->data.dir == SPI_MEM_DATA_IN) { 575 + is_datain = true; 576 + 577 + buf = aml_get_dma_safe_input_buf(op); 578 + if (!buf) { 579 + ret = -ENOMEM; 580 + goto err_out; 581 + } 582 + 583 + cmd |= CMD_NAND2MEM(0, (op->data.nbytes & RAW_SIZE)); 584 + } else if (op->data.dir == SPI_MEM_DATA_OUT) { 585 + is_datain = false; 586 + 587 + buf = aml_sfc_get_dma_safe_output_buf(op); 588 + if (!buf) { 589 + ret = -ENOMEM; 590 + goto err_out; 591 + } 592 + 593 + cmd |= CMD_MEM2NAND(0, (op->data.nbytes & RAW_SIZE)); 594 + } else { 595 + goto end_xfer; 596 + } 597 + 598 + ret = aml_sfc_dma_buffer_setup(sfc, buf, op->data.nbytes, 599 + is_datain ? sfc->info_buf : NULL, 600 + is_datain ? ECC_PER_INFO_BYTE : 0, 601 + is_datain ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 602 + if (ret) 603 + goto err_out; 604 + 605 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 606 + if (ret) 607 + goto err_out; 608 + 609 + timeout_ms = aml_sfc_cal_timeout_cycle(sfc, op); 610 + ret = aml_sfc_wait_cmd_finish(sfc, timeout_ms); 611 + if (ret) 612 + goto err_out; 613 + 614 + if (is_datain) 615 + aml_sfc_check_ecc_pages_valid(sfc, 1); 616 + 617 + if (op->data.dir == SPI_MEM_DATA_IN) 618 + aml_sfc_put_dma_safe_input_buf(op, buf); 619 + else if (op->data.dir == SPI_MEM_DATA_OUT) 620 + aml_sfc_put_dma_safe_output_buf(op, buf); 621 + 622 + aml_sfc_dma_buffer_release(sfc, op->data.nbytes, 623 + is_datain ? ECC_PER_INFO_BYTE : 0, 624 + is_datain ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 625 + 626 + end_xfer: 627 + return aml_sfc_end_transfer(sfc, CS_HOLD_CYCLE); 628 + 629 + err_out: 630 + return ret; 631 + } 632 + 633 + static void aml_sfc_set_user_byte(struct aml_sfc *sfc, __le64 *info_buf, u8 *oob_buf, bool auto_oob) 634 + { 635 + struct aml_sfc_ecc_cfg *ecc_cfg; 636 + __le64 *info; 637 + int i, count, step_size; 638 + 639 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 640 + 641 + step_size = auto_oob ? ECC_BCH8_INFO_BYTES : ECC_BCH8_USER_BYTES; 642 + 643 + for (i = 0, count = 0; i < ecc_cfg->nsteps; i++, count += step_size) { 644 + info = &info_buf[i]; 645 + *info &= cpu_to_le64(~0xffff); 646 + *info |= cpu_to_le64((oob_buf[count + 1] << 8) + oob_buf[count]); 647 + } 648 + } 649 + 650 + static void aml_sfc_get_user_byte(struct aml_sfc *sfc, __le64 *info_buf, u8 *oob_buf) 651 + { 652 + struct aml_sfc_ecc_cfg *ecc_cfg; 653 + __le64 *info; 654 + int i, count; 655 + 656 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 657 + 658 + for (i = 0, count = 0; i < ecc_cfg->nsteps; i++, count += ECC_BCH8_INFO_BYTES) { 659 + info = &info_buf[i]; 660 + oob_buf[count] = le64_to_cpu(*info); 661 + oob_buf[count + 1] = le64_to_cpu(*info) >> 8; 662 + } 663 + } 664 + 665 + static int aml_sfc_check_hwecc_status(struct aml_sfc *sfc, __le64 *info_buf) 666 + { 667 + struct aml_sfc_ecc_cfg *ecc_cfg; 668 + __le64 *info; 669 + u32 i, max_bitflips = 0, per_sector_bitflips = 0; 670 + 671 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 672 + 673 + sfc->ecc_stats.failed = 0; 674 + sfc->ecc_stats.bitflips = 0; 675 + sfc->ecc_stats.corrected = 0; 676 + 677 + for (i = 0, info = info_buf; i < ecc_cfg->nsteps; i++, info++) { 678 + if (ECC_ERR_CNT(le64_to_cpu(*info)) != ECC_UNCORRECTABLE) { 679 + per_sector_bitflips = ECC_ERR_CNT(le64_to_cpu(*info)); 680 + max_bitflips = max_t(u32, max_bitflips, per_sector_bitflips); 681 + sfc->ecc_stats.corrected += per_sector_bitflips; 682 + continue; 683 + } 684 + 685 + return -EBADMSG; 686 + } 687 + 688 + return max_bitflips; 689 + } 690 + 691 + static int aml_sfc_read_page_hwecc(struct aml_sfc *sfc, const struct spi_mem_op *op) 692 + { 693 + struct aml_sfc_ecc_cfg *ecc_cfg; 694 + int ret, data_len, info_len; 695 + u32 page_size, cmd = 0; 696 + u64 timeout_ms; 697 + 698 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 699 + 700 + page_size = ecc_cfg->stepsize * ecc_cfg->nsteps; 701 + data_len = page_size + ecc_cfg->oobsize; 702 + info_len = ecc_cfg->nsteps * ECC_PER_INFO_BYTE; 703 + 704 + ret = aml_sfc_dma_buffer_setup(sfc, sfc->data_buf, data_len, 705 + sfc->info_buf, info_len, DMA_FROM_DEVICE); 706 + if (ret) 707 + goto err_out; 708 + 709 + cmd |= CMD_NAND2MEM(ecc_cfg->bch, ecc_cfg->nsteps); 710 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 711 + if (ret) 712 + goto err_out; 713 + 714 + timeout_ms = aml_sfc_cal_timeout_cycle(sfc, op); 715 + ret = aml_sfc_wait_cmd_finish(sfc, timeout_ms); 716 + if (ret) 717 + goto err_out; 718 + 719 + aml_sfc_check_ecc_pages_valid(sfc, 0); 720 + aml_sfc_dma_buffer_release(sfc, data_len, info_len, DMA_FROM_DEVICE); 721 + 722 + /* check ecc status here */ 723 + ret = aml_sfc_check_hwecc_status(sfc, sfc->info_buf); 724 + if (ret < 0) 725 + sfc->ecc_stats.failed++; 726 + else 727 + sfc->ecc_stats.bitflips = ret; 728 + 729 + if (sfc->flags & SFC_DATA_ONLY) { 730 + memcpy(op->data.buf.in, sfc->data_buf, page_size); 731 + } else if (sfc->flags & SFC_OOB_ONLY) { 732 + aml_sfc_get_user_byte(sfc, sfc->info_buf, op->data.buf.in); 733 + } else if (sfc->flags & SFC_DATA_OOB) { 734 + memcpy(op->data.buf.in, sfc->data_buf, page_size); 735 + aml_sfc_get_user_byte(sfc, sfc->info_buf, op->data.buf.in + page_size); 736 + } 737 + 738 + return aml_sfc_end_transfer(sfc, CS_HOLD_CYCLE); 739 + 740 + err_out: 741 + return ret; 742 + } 743 + 744 + static int aml_sfc_write_page_hwecc(struct aml_sfc *sfc, const struct spi_mem_op *op) 745 + { 746 + struct aml_sfc_ecc_cfg *ecc_cfg; 747 + int ret, data_len, info_len; 748 + u32 page_size, cmd = 0; 749 + u64 timeout_ms; 750 + 751 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 752 + 753 + page_size = ecc_cfg->stepsize * ecc_cfg->nsteps; 754 + data_len = page_size + ecc_cfg->oobsize; 755 + info_len = ecc_cfg->nsteps * ECC_PER_INFO_BYTE; 756 + 757 + memset(sfc->info_buf, ECC_PATTERN, ecc_cfg->oobsize); 758 + memcpy(sfc->data_buf, op->data.buf.out, page_size); 759 + 760 + if (!(sfc->flags & SFC_DATA_ONLY)) { 761 + if (sfc->flags & SFC_AUTO_OOB) 762 + aml_sfc_set_user_byte(sfc, sfc->info_buf, 763 + (u8 *)op->data.buf.out + page_size, 1); 764 + else 765 + aml_sfc_set_user_byte(sfc, sfc->info_buf, 766 + (u8 *)op->data.buf.out + page_size, 0); 767 + } 768 + 769 + ret = aml_sfc_dma_buffer_setup(sfc, sfc->data_buf, data_len, 770 + sfc->info_buf, info_len, DMA_TO_DEVICE); 771 + if (ret) 772 + goto err_out; 773 + 774 + cmd |= CMD_MEM2NAND(ecc_cfg->bch, ecc_cfg->nsteps); 775 + ret = regmap_write(sfc->regmap_base, SFC_CMD, cmd); 776 + if (ret) 777 + goto err_out; 778 + 779 + timeout_ms = aml_sfc_cal_timeout_cycle(sfc, op); 780 + 781 + ret = aml_sfc_wait_cmd_finish(sfc, timeout_ms); 782 + if (ret) 783 + goto err_out; 784 + 785 + aml_sfc_dma_buffer_release(sfc, data_len, info_len, DMA_TO_DEVICE); 786 + 787 + return aml_sfc_end_transfer(sfc, CS_HOLD_CYCLE); 788 + 789 + err_out: 790 + return ret; 791 + } 792 + 793 + static int aml_sfc_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 794 + { 795 + struct aml_sfc *sfc; 796 + struct spi_device *spi; 797 + struct aml_sfc_ecc_cfg *ecc_cfg; 798 + int ret; 799 + 800 + sfc = spi_controller_get_devdata(mem->spi->controller); 801 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 802 + spi = mem->spi; 803 + sfc->cs_sel = spi->chip_select[0] ? CS_1 : CS_0; 804 + 805 + dev_dbg(sfc->dev, "cmd:0x%02x - addr:%08llX@%d:%u - dummy:%d:%u - data:%d:%u", 806 + op->cmd.opcode, op->addr.val, op->addr.buswidth, op->addr.nbytes, 807 + op->dummy.buswidth, op->dummy.nbytes, op->data.buswidth, op->data.nbytes); 808 + 809 + ret = aml_sfc_pre_transfer(sfc, DEFAULT_PULLUP_CYCLE, CS_SETUP_CYCLE); 810 + if (ret) 811 + return ret; 812 + 813 + ret = aml_sfc_send_cmd_addr_dummy(sfc, op); 814 + if (ret) 815 + return ret; 816 + 817 + ret = aml_sfc_set_bus_width(sfc, op->data.buswidth, DATA_LANE); 818 + if (ret) 819 + return ret; 820 + 821 + if (aml_sfc_is_snand_hwecc_page_op(sfc, op) && 822 + ecc_cfg && !(sfc->flags & SFC_RAW_RW)) { 823 + if (op->data.dir == SPI_MEM_DATA_IN) 824 + return aml_sfc_read_page_hwecc(sfc, op); 825 + else 826 + return aml_sfc_write_page_hwecc(sfc, op); 827 + } 828 + 829 + return aml_sfc_raw_io_op(sfc, op); 830 + } 831 + 832 + static int aml_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 833 + { 834 + struct aml_sfc *sfc; 835 + struct aml_sfc_ecc_cfg *ecc_cfg; 836 + 837 + sfc = spi_controller_get_devdata(mem->spi->controller); 838 + ecc_cfg = aml_sfc_to_ecc_ctx(sfc); 839 + 840 + if (aml_sfc_is_snand_hwecc_page_op(sfc, op) && ecc_cfg) { 841 + if (op->data.nbytes > ecc_cfg->stepsize * ECC_BCH_MAX_SECT_SIZE) 842 + return -EOPNOTSUPP; 843 + } else if (op->data.nbytes & ~RAW_MAX_RW_SIZE_MASK) { 844 + return -EOPNOTSUPP; 845 + } 846 + 847 + return 0; 848 + } 849 + 850 + static const struct spi_controller_mem_ops aml_sfc_mem_ops = { 851 + .adjust_op_size = aml_sfc_adjust_op_size, 852 + .exec_op = aml_sfc_exec_op, 853 + }; 854 + 855 + static int aml_sfc_layout_ecc(struct mtd_info *mtd, int section, 856 + struct mtd_oob_region *oobregion) 857 + { 858 + struct nand_device *nand = mtd_to_nanddev(mtd); 859 + 860 + if (section >= nand->ecc.ctx.nsteps) 861 + return -ERANGE; 862 + 863 + oobregion->offset = ECC_BCH8_USER_BYTES + (section * ECC_BCH8_INFO_BYTES); 864 + oobregion->length = ECC_BCH8_PARITY_BYTES; 865 + 866 + return 0; 867 + } 868 + 869 + static int aml_sfc_ooblayout_free(struct mtd_info *mtd, int section, 870 + struct mtd_oob_region *oobregion) 871 + { 872 + struct nand_device *nand = mtd_to_nanddev(mtd); 873 + 874 + if (section >= nand->ecc.ctx.nsteps) 875 + return -ERANGE; 876 + 877 + oobregion->offset = section * ECC_BCH8_INFO_BYTES; 878 + oobregion->length = ECC_BCH8_USER_BYTES; 879 + 880 + return 0; 881 + } 882 + 883 + static const struct mtd_ooblayout_ops aml_sfc_ooblayout_ops = { 884 + .ecc = aml_sfc_layout_ecc, 885 + .free = aml_sfc_ooblayout_free, 886 + }; 887 + 888 + static int aml_spi_settings(struct aml_sfc *sfc, struct spi_device *spi) 889 + { 890 + u32 conf = 0; 891 + 892 + if (spi->mode & SPI_CPHA) 893 + conf |= CPHA; 894 + 895 + if (spi->mode & SPI_CPOL) 896 + conf |= CPOL; 897 + 898 + conf |= FIELD_PREP(RXADJ, sfc->rx_adj); 899 + conf |= EN_HOLD | EN_WP; 900 + return regmap_update_bits(sfc->regmap_base, SFC_SPI_CFG, 901 + CPHA | CPOL | RXADJ | 902 + EN_HOLD | EN_WP, conf); 903 + } 904 + 905 + static int aml_set_spi_clk(struct aml_sfc *sfc, struct spi_device *spi) 906 + { 907 + u32 speed_hz; 908 + int ret; 909 + 910 + if (spi->max_speed_hz > SFC_MAX_FREQUENCY) 911 + speed_hz = SFC_MAX_FREQUENCY; 912 + else if (!spi->max_speed_hz) 913 + speed_hz = SFC_BUS_DEFAULT_CLK; 914 + else if (spi->max_speed_hz < SFC_MIN_FREQUENCY) 915 + speed_hz = SFC_MIN_FREQUENCY; 916 + else 917 + speed_hz = spi->max_speed_hz; 918 + 919 + /* The SPI clock is generated by dividing the bus clock by four by default. */ 920 + ret = regmap_write(sfc->regmap_base, SFC_CFG, (DEFAULT_BUS_CYCLE - 1)); 921 + if (ret) { 922 + dev_err(sfc->dev, "failed to set bus cycle\n"); 923 + return ret; 924 + } 925 + 926 + return clk_set_rate(sfc->core_clk, speed_hz * DEFAULT_BUS_CYCLE); 927 + } 928 + 929 + static int aml_sfc_setup(struct spi_device *spi) 930 + { 931 + struct aml_sfc *sfc; 932 + int ret; 933 + 934 + sfc = spi_controller_get_devdata(spi->controller); 935 + ret = aml_spi_settings(sfc, spi); 936 + if (ret) 937 + return ret; 938 + 939 + ret = aml_set_spi_clk(sfc, spi); 940 + if (ret) 941 + return ret; 942 + 943 + sfc->bus_rate = clk_get_rate(sfc->core_clk); 944 + 945 + return 0; 946 + } 947 + 948 + static int aml_sfc_ecc_init_ctx(struct nand_device *nand) 949 + { 950 + struct mtd_info *mtd = nanddev_to_mtd(nand); 951 + struct aml_sfc *sfc = nand_to_aml_sfc(nand); 952 + struct aml_sfc_ecc_cfg *ecc_cfg; 953 + const struct aml_sfc_caps *caps = sfc->caps; 954 + struct aml_sfc_ecc_cfg *ecc_caps = caps->ecc_caps; 955 + int i, ecc_strength, ecc_step_size; 956 + 957 + ecc_step_size = nand->ecc.user_conf.step_size; 958 + ecc_strength = nand->ecc.user_conf.strength; 959 + 960 + for (i = 0; i < caps->num_ecc_caps; i++) { 961 + if (ecc_caps[i].stepsize == ecc_step_size) { 962 + nand->ecc.ctx.conf.step_size = ecc_step_size; 963 + nand->ecc.ctx.conf.flags |= BIT(ecc_caps[i].bch); 964 + } 965 + 966 + if (ecc_caps[i].strength == ecc_strength) 967 + nand->ecc.ctx.conf.strength = ecc_strength; 968 + } 969 + 970 + if (!nand->ecc.ctx.conf.step_size) { 971 + nand->ecc.ctx.conf.step_size = ECC_BCH8_DEFAULT_STEP; 972 + nand->ecc.ctx.conf.flags |= BIT(ECC_DEFAULT_BCH_MODE); 973 + } 974 + 975 + if (!nand->ecc.ctx.conf.strength) 976 + nand->ecc.ctx.conf.strength = ECC_BCH8_STRENGTH; 977 + 978 + nand->ecc.ctx.nsteps = nand->memorg.pagesize / nand->ecc.ctx.conf.step_size; 979 + nand->ecc.ctx.total = nand->ecc.ctx.nsteps * ECC_BCH8_PARITY_BYTES; 980 + 981 + /* Verify the page size and OOB size against the SFC requirements. */ 982 + if ((nand->memorg.pagesize % nand->ecc.ctx.conf.step_size) || 983 + (nand->memorg.oobsize < (nand->ecc.ctx.total + 984 + nand->ecc.ctx.nsteps * ECC_BCH8_USER_BYTES))) 985 + return -EOPNOTSUPP; 986 + 987 + nand->ecc.ctx.conf.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 988 + 989 + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); 990 + if (!ecc_cfg) 991 + return -ENOMEM; 992 + 993 + ecc_cfg->stepsize = nand->ecc.ctx.conf.step_size; 994 + ecc_cfg->nsteps = nand->ecc.ctx.nsteps; 995 + ecc_cfg->strength = nand->ecc.ctx.conf.strength; 996 + ecc_cfg->oobsize = nand->memorg.oobsize; 997 + ecc_cfg->bch = nand->ecc.ctx.conf.flags & BIT(ECC_DEFAULT_BCH_MODE) ? 1 : 2; 998 + 999 + nand->ecc.ctx.priv = ecc_cfg; 1000 + sfc->priv = (void *)ecc_cfg; 1001 + mtd_set_ooblayout(mtd, &aml_sfc_ooblayout_ops); 1002 + 1003 + sfc->flags |= SFC_HWECC; 1004 + 1005 + return 0; 1006 + } 1007 + 1008 + static void aml_sfc_ecc_cleanup_ctx(struct nand_device *nand) 1009 + { 1010 + struct aml_sfc *sfc = nand_to_aml_sfc(nand); 1011 + 1012 + sfc->flags &= ~(SFC_HWECC); 1013 + kfree(nand->ecc.ctx.priv); 1014 + sfc->priv = NULL; 1015 + } 1016 + 1017 + static int aml_sfc_ecc_prepare_io_req(struct nand_device *nand, 1018 + struct nand_page_io_req *req) 1019 + { 1020 + struct aml_sfc *sfc = nand_to_aml_sfc(nand); 1021 + struct spinand_device *spinand = nand_to_spinand(nand); 1022 + 1023 + sfc->flags &= ~SFC_XFER_MDOE_MASK; 1024 + 1025 + if (req->datalen && !req->ooblen) 1026 + sfc->flags |= SFC_DATA_ONLY; 1027 + else if (!req->datalen && req->ooblen) 1028 + sfc->flags |= SFC_OOB_ONLY; 1029 + else if (req->datalen && req->ooblen) 1030 + sfc->flags |= SFC_DATA_OOB; 1031 + 1032 + if (req->mode == MTD_OPS_RAW) 1033 + sfc->flags |= SFC_RAW_RW; 1034 + else if (req->mode == MTD_OPS_AUTO_OOB) 1035 + sfc->flags |= SFC_AUTO_OOB; 1036 + 1037 + memset(spinand->oobbuf, 0xff, nanddev_per_page_oobsize(nand)); 1038 + 1039 + return 0; 1040 + } 1041 + 1042 + static int aml_sfc_ecc_finish_io_req(struct nand_device *nand, 1043 + struct nand_page_io_req *req) 1044 + { 1045 + struct aml_sfc *sfc = nand_to_aml_sfc(nand); 1046 + struct mtd_info *mtd = nanddev_to_mtd(nand); 1047 + 1048 + if (req->mode == MTD_OPS_RAW || req->type == NAND_PAGE_WRITE) 1049 + return 0; 1050 + 1051 + if (sfc->ecc_stats.failed) 1052 + mtd->ecc_stats.failed++; 1053 + 1054 + mtd->ecc_stats.corrected += sfc->ecc_stats.corrected; 1055 + 1056 + return sfc->ecc_stats.failed ? -EBADMSG : sfc->ecc_stats.bitflips; 1057 + } 1058 + 1059 + static const struct spi_controller_mem_caps aml_sfc_mem_caps = { 1060 + .ecc = true, 1061 + }; 1062 + 1063 + static const struct nand_ecc_engine_ops aml_sfc_ecc_engine_ops = { 1064 + .init_ctx = aml_sfc_ecc_init_ctx, 1065 + .cleanup_ctx = aml_sfc_ecc_cleanup_ctx, 1066 + .prepare_io_req = aml_sfc_ecc_prepare_io_req, 1067 + .finish_io_req = aml_sfc_ecc_finish_io_req, 1068 + }; 1069 + 1070 + static int aml_sfc_clk_init(struct aml_sfc *sfc) 1071 + { 1072 + sfc->gate_clk = devm_clk_get_enabled(sfc->dev, "gate"); 1073 + if (IS_ERR(sfc->gate_clk)) { 1074 + dev_err(sfc->dev, "unable to enable gate clk\n"); 1075 + return PTR_ERR(sfc->gate_clk); 1076 + } 1077 + 1078 + sfc->core_clk = devm_clk_get_enabled(sfc->dev, "core"); 1079 + if (IS_ERR(sfc->core_clk)) { 1080 + dev_err(sfc->dev, "unable to enable core clk\n"); 1081 + return PTR_ERR(sfc->core_clk); 1082 + } 1083 + 1084 + return clk_set_rate(sfc->core_clk, SFC_BUS_DEFAULT_CLK); 1085 + } 1086 + 1087 + static int aml_sfc_disable_clk(struct aml_sfc *sfc) 1088 + { 1089 + clk_disable_unprepare(sfc->core_clk); 1090 + clk_disable_unprepare(sfc->gate_clk); 1091 + 1092 + return 0; 1093 + } 1094 + 1095 + static int aml_sfc_probe(struct platform_device *pdev) 1096 + { 1097 + struct device_node *np = pdev->dev.of_node; 1098 + struct device *dev = &pdev->dev; 1099 + struct spi_controller *ctrl; 1100 + struct aml_sfc *sfc; 1101 + void __iomem *reg_base; 1102 + int ret; 1103 + u32 val = 0; 1104 + 1105 + const struct regmap_config core_config = { 1106 + .reg_bits = 32, 1107 + .val_bits = 32, 1108 + .reg_stride = 4, 1109 + .max_register = SFC_SPI_CFG, 1110 + }; 1111 + 1112 + ctrl = devm_spi_alloc_host(dev, sizeof(*sfc)); 1113 + if (!ctrl) 1114 + return -ENOMEM; 1115 + platform_set_drvdata(pdev, ctrl); 1116 + 1117 + sfc = spi_controller_get_devdata(ctrl); 1118 + sfc->dev = dev; 1119 + sfc->ctrl = ctrl; 1120 + 1121 + sfc->caps = of_device_get_match_data(dev); 1122 + if (!sfc->caps) 1123 + return dev_err_probe(dev, -ENODEV, "failed to get device data\n"); 1124 + 1125 + reg_base = devm_platform_ioremap_resource(pdev, 0); 1126 + if (IS_ERR(reg_base)) 1127 + return PTR_ERR(reg_base); 1128 + 1129 + sfc->regmap_base = devm_regmap_init_mmio(dev, reg_base, &core_config); 1130 + if (IS_ERR(sfc->regmap_base)) 1131 + return dev_err_probe(dev, PTR_ERR(sfc->regmap_base), 1132 + "failed to init sfc base regmap\n"); 1133 + 1134 + sfc->data_buf = devm_kzalloc(dev, SFC_BUF_SIZE, GFP_KERNEL); 1135 + if (!sfc->data_buf) 1136 + return -ENOMEM; 1137 + sfc->info_buf = (__le64 *)(sfc->data_buf + SFC_DATABUF_SIZE); 1138 + 1139 + ret = aml_sfc_clk_init(sfc); 1140 + if (ret) 1141 + return dev_err_probe(dev, ret, "failed to initialize SFC clock\n"); 1142 + 1143 + /* Enable Amlogic flash controller spi mode */ 1144 + ret = regmap_write(sfc->regmap_base, SFC_SPI_CFG, SPI_MODE_EN); 1145 + if (ret) { 1146 + dev_err(dev, "failed to enable SPI mode\n"); 1147 + goto err_out; 1148 + } 1149 + 1150 + ret = dma_set_mask(sfc->dev, DMA_BIT_MASK(32)); 1151 + if (ret) { 1152 + dev_err(sfc->dev, "failed to set dma mask\n"); 1153 + goto err_out; 1154 + } 1155 + 1156 + sfc->ecc_eng.dev = &pdev->dev; 1157 + sfc->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; 1158 + sfc->ecc_eng.ops = &aml_sfc_ecc_engine_ops; 1159 + sfc->ecc_eng.priv = sfc; 1160 + 1161 + ret = nand_ecc_register_on_host_hw_engine(&sfc->ecc_eng); 1162 + if (ret) { 1163 + dev_err(&pdev->dev, "failed to register Aml host ecc engine.\n"); 1164 + goto err_out; 1165 + } 1166 + 1167 + ret = of_property_read_u32(np, "amlogic,rx-adj", &val); 1168 + if (!ret) 1169 + sfc->rx_adj = val; 1170 + 1171 + ctrl->dev.of_node = np; 1172 + ctrl->mem_ops = &aml_sfc_mem_ops; 1173 + ctrl->mem_caps = &aml_sfc_mem_caps; 1174 + ctrl->setup = aml_sfc_setup; 1175 + ctrl->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | 1176 + SPI_RX_DUAL | SPI_TX_OCTAL | SPI_RX_OCTAL; 1177 + ctrl->max_speed_hz = SFC_MAX_FREQUENCY; 1178 + ctrl->min_speed_hz = SFC_MIN_FREQUENCY; 1179 + ctrl->num_chipselect = SFC_MAX_CS_NUM; 1180 + 1181 + ret = devm_spi_register_controller(dev, ctrl); 1182 + if (ret) 1183 + goto err_out; 1184 + 1185 + return 0; 1186 + 1187 + err_out: 1188 + aml_sfc_disable_clk(sfc); 1189 + 1190 + return ret; 1191 + } 1192 + 1193 + static void aml_sfc_remove(struct platform_device *pdev) 1194 + { 1195 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 1196 + struct aml_sfc *sfc = spi_controller_get_devdata(ctlr); 1197 + 1198 + aml_sfc_disable_clk(sfc); 1199 + } 1200 + 1201 + static const struct of_device_id aml_sfc_of_match[] = { 1202 + { 1203 + .compatible = "amlogic,a4-spifc", 1204 + .data = &aml_a113l2_sfc_caps 1205 + }, 1206 + {}, 1207 + }; 1208 + MODULE_DEVICE_TABLE(of, aml_sfc_of_match); 1209 + 1210 + static struct platform_driver aml_sfc_driver = { 1211 + .driver = { 1212 + .name = "aml_sfc", 1213 + .of_match_table = aml_sfc_of_match, 1214 + }, 1215 + .probe = aml_sfc_probe, 1216 + .remove = aml_sfc_remove, 1217 + }; 1218 + module_platform_driver(aml_sfc_driver); 1219 + 1220 + MODULE_DESCRIPTION("Amlogic SPI Flash Controller driver"); 1221 + MODULE_AUTHOR("Feng Chen <feng.chen@amlogic.com>"); 1222 + MODULE_LICENSE("Dual MIT/GPL");

+2 -2

drivers/spi/spi-amlogic-spisg.c

··· 662 662 663 663 clk_disable_unprepare(spisg->pclk); 664 664 665 - tbl = devm_kzalloc(dev, sizeof(struct clk_div_table) * (DIV_NUM + 1), GFP_KERNEL); 665 + tbl = devm_kcalloc(dev, (DIV_NUM + 1), sizeof(*tbl), GFP_KERNEL); 666 666 if (!tbl) 667 667 return -ENOMEM; 668 668 ··· 733 733 else 734 734 ctlr = spi_alloc_host(dev, sizeof(*spisg)); 735 735 if (!ctlr) 736 - return dev_err_probe(dev, -ENOMEM, "controller allocation failed\n"); 736 + return -ENOMEM; 737 737 738 738 spisg = spi_controller_get_devdata(ctlr); 739 739 spisg->controller = ctlr;

+58 -20

drivers/spi/spi-atmel.c

··· 256 256 void __iomem *regs; 257 257 int irq; 258 258 struct clk *clk; 259 + struct clk *gclk; 259 260 struct platform_device *pdev; 260 261 unsigned long spi_clk; 261 262 ··· 398 397 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 399 398 */ 400 399 spi_writel(as, CSR0, asd->csr); 401 - if (as->caps.has_wdrbt) { 402 - spi_writel(as, MR, 403 - SPI_BF(PCS, ~(0x01 << chip_select)) 404 - | SPI_BIT(WDRBT) 405 - | SPI_BIT(MODFDIS) 406 - | SPI_BIT(MSTR)); 407 - } else { 408 - spi_writel(as, MR, 409 - SPI_BF(PCS, ~(0x01 << chip_select)) 410 - | SPI_BIT(MODFDIS) 411 - | SPI_BIT(MSTR)); 412 - } 413 400 414 401 mr = spi_readl(as, MR); 402 + mr = SPI_BFINS(PCS, ~(0x01 << chip_select), mr); 403 + spi_writel(as, MR, mr); 415 404 416 405 /* 417 406 * Ensures the clock polarity is valid before we actually ··· 1481 1490 1482 1491 static void atmel_spi_init(struct atmel_spi *as) 1483 1492 { 1493 + u32 mr = 0; 1494 + 1484 1495 spi_writel(as, CR, SPI_BIT(SWRST)); 1485 1496 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1486 1497 ··· 1490 1497 if (as->fifo_size) 1491 1498 spi_writel(as, CR, SPI_BIT(FIFOEN)); 1492 1499 1493 - if (as->caps.has_wdrbt) { 1494 - spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1495 - | SPI_BIT(MSTR)); 1496 - } else { 1497 - spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1498 - } 1500 + /* 1501 + * If GCLK is selected as the source clock for the bit rate generation 1502 + * Enable the BRSRCCLK/FDIV/DIV32 bit 1503 + */ 1504 + if (as->gclk) 1505 + mr |= SPI_BIT(FDIV); 1506 + 1507 + if (as->caps.has_wdrbt) 1508 + mr |= SPI_BIT(WDRBT); 1509 + 1510 + spi_writel(as, MR, mr | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); 1499 1511 1500 1512 if (as->use_pdc) 1501 1513 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); ··· 1563 1565 as->phybase = regs->start; 1564 1566 as->irq = irq; 1565 1567 as->clk = clk; 1568 + as->gclk = devm_clk_get_optional(&pdev->dev, "spi_gclk"); 1569 + if (IS_ERR(as->gclk)) { 1570 + ret = PTR_ERR(as->gclk); 1571 + goto out_unmap_regs; 1572 + } 1566 1573 1567 1574 init_completion(&as->xfer_completion); 1568 1575 ··· 1628 1625 if (ret) 1629 1626 goto out_free_irq; 1630 1627 1631 - as->spi_clk = clk_get_rate(clk); 1628 + /* 1629 + * In cases where the peripheral clock is higher,the FLEX_SPI_CSRx.SCBR 1630 + * exceeds the threshold (SCBR ≤ 255), the GCLK is used as the source clock 1631 + * for the SPCK (SPI Serial Clock) bit rate generation 1632 + */ 1633 + if (as->gclk) { 1634 + ret = clk_prepare_enable(as->gclk); 1635 + if (ret) 1636 + goto out_disable_clk; 1637 + as->spi_clk = clk_get_rate(as->gclk); 1638 + } else { 1639 + as->spi_clk = clk_get_rate(clk); 1640 + } 1632 1641 1633 1642 as->fifo_size = 0; 1634 1643 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", ··· 1675 1660 1676 1661 spi_writel(as, CR, SPI_BIT(SWRST)); 1677 1662 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1663 + clk_disable_unprepare(as->gclk); 1664 + out_disable_clk: 1678 1665 clk_disable_unprepare(clk); 1679 1666 out_free_irq: 1680 1667 out_unmap_regs: ··· 1712 1695 spin_unlock_irq(&as->lock); 1713 1696 1714 1697 clk_disable_unprepare(as->clk); 1698 + if (as->gclk) 1699 + clk_disable_unprepare(as->gclk); 1715 1700 1716 1701 pm_runtime_put_noidle(&pdev->dev); 1717 1702 pm_runtime_disable(&pdev->dev); ··· 1725 1706 struct atmel_spi *as = spi_controller_get_devdata(host); 1726 1707 1727 1708 clk_disable_unprepare(as->clk); 1709 + if (as->gclk) 1710 + clk_disable_unprepare(as->gclk); 1728 1711 pinctrl_pm_select_sleep_state(dev); 1729 1712 1730 1713 return 0; ··· 1736 1715 { 1737 1716 struct spi_controller *host = dev_get_drvdata(dev); 1738 1717 struct atmel_spi *as = spi_controller_get_devdata(host); 1718 + int ret; 1739 1719 1740 1720 pinctrl_pm_select_default_state(dev); 1741 1721 1742 - return clk_prepare_enable(as->clk); 1722 + ret = clk_prepare_enable(as->clk); 1723 + if (ret) 1724 + return ret; 1725 + if (as->gclk) { 1726 + ret = clk_prepare_enable(as->gclk); 1727 + if (ret) 1728 + return ret; 1729 + } 1730 + 1731 + return 0; 1743 1732 } 1744 1733 1745 1734 static int atmel_spi_suspend(struct device *dev) ··· 1777 1746 ret = clk_prepare_enable(as->clk); 1778 1747 if (ret) 1779 1748 return ret; 1749 + if (as->gclk) { 1750 + ret = clk_prepare_enable(as->gclk); 1751 + if (ret) 1752 + return ret; 1753 + } 1780 1754 1781 1755 atmel_spi_init(as); 1782 1756 1783 1757 clk_disable_unprepare(as->clk); 1758 + if (as->gclk) 1759 + clk_disable_unprepare(as->gclk); 1784 1760 1785 1761 if (!pm_runtime_suspended(dev)) { 1786 1762 ret = atmel_spi_runtime_resume(dev);

+7 -10

drivers/spi/spi-axi-spi-engine.c

··· 1050 1050 return -ENODEV; 1051 1051 } 1052 1052 1053 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 1) { 1053 + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { 1054 1054 unsigned int sizes = readl(spi_engine->base + 1055 1055 SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); 1056 1056 ··· 1064 1064 } 1065 1065 1066 1066 /* IP v1.5 dropped the requirement for SYNC in offload messages. */ 1067 - spi_engine->offload_requires_sync = ADI_AXI_PCORE_VER_MINOR(version) < 5; 1067 + spi_engine->offload_requires_sync = !adi_axi_pcore_ver_gteq(version, 1, 5); 1068 1068 1069 1069 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET); 1070 1070 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); ··· 1091 1091 host->put_offload = spi_engine_put_offload; 1092 1092 host->num_chipselect = 8; 1093 1093 1094 - /* Some features depend of the IP core version. */ 1095 - if (ADI_AXI_PCORE_VER_MAJOR(version) >= 1) { 1096 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) { 1097 - host->mode_bits |= SPI_CS_HIGH; 1098 - host->setup = spi_engine_setup; 1099 - } 1100 - if (ADI_AXI_PCORE_VER_MINOR(version) >= 3) 1101 - host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; 1094 + if (adi_axi_pcore_ver_gteq(version, 1, 2)) { 1095 + host->mode_bits |= SPI_CS_HIGH; 1096 + host->setup = spi_engine_setup; 1102 1097 } 1098 + if (adi_axi_pcore_ver_gteq(version, 1, 3)) 1099 + host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; 1103 1100 1104 1101 if (host->max_speed_hz == 0) 1105 1102 return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");

+1 -1

drivers/spi/spi-bcm2835.c

··· 622 622 /* reset fifo and HW */ 623 623 bcm2835_spi_reset_hw(bs); 624 624 625 - /* and mark as completed */; 625 + /* and mark as completed */ 626 626 spi_finalize_current_transfer(ctlr); 627 627 } 628 628

+22 -14

drivers/spi/spi-cadence-quadspi.c

··· 33 33 #define CQSPI_NAME "cadence-qspi" 34 34 #define CQSPI_MAX_CHIPSELECT 4 35 35 36 - static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); 36 + static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); 37 37 38 38 /* Quirks */ 39 39 #define CQSPI_NEEDS_WR_DELAY BIT(0) ··· 336 336 { 337 337 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 338 338 339 - return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 339 + return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB); 340 340 } 341 341 342 342 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) ··· 572 572 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 573 573 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 574 574 575 - reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 575 + reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB); 576 576 577 577 /* 0 means 1 byte. */ 578 578 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) ··· 580 580 581 581 /* setup ADDR BIT field */ 582 582 if (op->addr.nbytes) { 583 - reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 583 + reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 584 584 reg |= ((op->addr.nbytes - 1) & 585 585 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 586 586 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; ··· 647 647 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 648 648 649 649 if (op->addr.nbytes) { 650 - reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 650 + reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 651 651 reg |= ((op->addr.nbytes - 1) & 652 652 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 653 653 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; ··· 656 656 } 657 657 658 658 if (n_tx) { 659 - reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 659 + reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB); 660 660 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 661 661 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 662 662 data = 0; ··· 720 720 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 721 721 reg |= (op->addr.nbytes - 1); 722 722 writel(reg, reg_base + CQSPI_REG_SIZE); 723 + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 723 724 return 0; 724 725 } 725 726 ··· 766 765 reinit_completion(&cqspi->transfer_complete); 767 766 writel(CQSPI_REG_INDIRECTRD_START_MASK, 768 767 reg_base + CQSPI_REG_INDIRECTRD); 768 + readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ 769 769 770 770 while (remaining > 0) { 771 771 if (use_irq && ··· 1065 1063 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1066 1064 reg |= (op->addr.nbytes - 1); 1067 1065 writel(reg, reg_base + CQSPI_REG_SIZE); 1066 + readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 1068 1067 return 0; 1069 1068 } 1070 1069 ··· 1094 1091 reinit_completion(&cqspi->transfer_complete); 1095 1092 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1096 1093 reg_base + CQSPI_REG_INDIRECTWR); 1094 + readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ 1095 + 1097 1096 /* 1098 1097 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1099 1098 * Controller programming sequence, couple of cycles of ··· 1192 1187 * CS2 to 4b'1011 1193 1188 * CS3 to 4b'0111 1194 1189 */ 1195 - chip_select = 0xF & ~(1 << chip_select); 1190 + chip_select = 0xF & ~BIT(chip_select); 1196 1191 } 1197 1192 1198 1193 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK ··· 1278 1273 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1279 1274 1280 1275 if (bypass) 1281 - reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1276 + reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1282 1277 else 1283 - reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1278 + reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1284 1279 1285 1280 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1286 1281 << CQSPI_REG_READCAPTURE_DELAY_LSB); ··· 1727 1722 1728 1723 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1729 1724 { 1730 - unsigned int max_cs = cqspi->num_chipselect - 1; 1731 1725 struct platform_device *pdev = cqspi->pdev; 1732 1726 struct device *dev = &pdev->dev; 1733 1727 struct cqspi_flash_pdata *f_pdata; 1734 - unsigned int cs; 1735 - int ret; 1728 + int ret, cs, max_cs = -1; 1736 1729 1737 1730 /* Get flash device data */ 1738 1731 for_each_available_child_of_node_scoped(dev->of_node, np) { ··· 1743 1740 if (cs >= cqspi->num_chipselect) { 1744 1741 dev_err(dev, "Chip select %d out of range.\n", cs); 1745 1742 return -EINVAL; 1746 - } else if (cs < max_cs) { 1747 - max_cs = cs; 1748 1743 } 1744 + 1745 + max_cs = max_t(int, cs, max_cs); 1749 1746 1750 1747 f_pdata = &cqspi->f_pdata[cs]; 1751 1748 f_pdata->cqspi = cqspi; ··· 1754 1751 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1755 1752 if (ret) 1756 1753 return ret; 1754 + } 1755 + 1756 + if (max_cs < 0) { 1757 + dev_err(dev, "No flash device declared\n"); 1758 + return -ENODEV; 1757 1759 } 1758 1760 1759 1761 cqspi->num_chipselect = max_cs + 1;

+161 -69

drivers/spi/spi-fsl-dspi.c

··· 331 331 dma_addr_t rx_dma_phys; 332 332 struct completion cmd_rx_complete; 333 333 struct dma_async_tx_descriptor *rx_desc; 334 + 335 + size_t bufsize; 334 336 }; 335 337 336 338 struct fsl_dspi { ··· 374 372 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); 375 373 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); 376 374 }; 375 + 376 + static void dspi_setup_accel(struct fsl_dspi *dspi); 377 377 378 378 static bool is_s32g_dspi(struct fsl_dspi *data) 379 379 { ··· 472 468 return txdata; 473 469 } 474 470 471 + /* Push one word to the RX buffer from the POPR register (RX FIFO) */ 472 + static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) 473 + { 474 + if (!dspi->rx) 475 + return; 476 + dspi->dev_to_host(dspi, rxdata); 477 + } 478 + 479 + static int dspi_fifo_error(struct fsl_dspi *dspi, u32 spi_sr) 480 + { 481 + if (spi_sr & (SPI_SR_TFUF | SPI_SR_RFOF)) { 482 + dev_err_ratelimited(&dspi->pdev->dev, "FIFO errors:%s%s\n", 483 + spi_sr & SPI_SR_TFUF ? " TX underflow," : "", 484 + spi_sr & SPI_SR_RFOF ? " RX overflow," : ""); 485 + return -EIO; 486 + } 487 + return 0; 488 + } 489 + 490 + #if IS_ENABLED(CONFIG_DMA_ENGINE) 491 + 475 492 /* Prepare one TX FIFO entry (txdata plus cmd) */ 476 493 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) 477 494 { ··· 506 481 return cmd << 16 | data; 507 482 } 508 483 509 - /* Push one word to the RX buffer from the POPR register (RX FIFO) */ 510 - static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) 484 + static size_t dspi_dma_max_datawords(struct fsl_dspi *dspi) 511 485 { 512 - if (!dspi->rx) 513 - return; 514 - dspi->dev_to_host(dspi, rxdata); 486 + /* 487 + * Transfers look like one of these, so we always use a full DMA word 488 + * regardless of SPI word size: 489 + * 490 + * 31 16 15 0 491 + * ----------------------------------------- 492 + * | CONTROL WORD | 16-bit DATA | 493 + * ----------------------------------------- 494 + * or 495 + * ----------------------------------------- 496 + * | CONTROL WORD | UNUSED | 8-bit DATA | 497 + * ----------------------------------------- 498 + */ 499 + return dspi->dma->bufsize / DMA_SLAVE_BUSWIDTH_4_BYTES; 500 + } 501 + 502 + static size_t dspi_dma_transfer_size(struct fsl_dspi *dspi) 503 + { 504 + return dspi->words_in_flight * DMA_SLAVE_BUSWIDTH_4_BYTES; 515 505 } 516 506 517 507 static void dspi_tx_dma_callback(void *arg) 518 508 { 519 509 struct fsl_dspi *dspi = arg; 520 510 struct fsl_dspi_dma *dma = dspi->dma; 511 + struct device *dev = &dspi->pdev->dev; 521 512 513 + dma_sync_single_for_cpu(dev, dma->tx_dma_phys, 514 + dspi_dma_transfer_size(dspi), DMA_TO_DEVICE); 522 515 complete(&dma->cmd_tx_complete); 523 516 } 524 517 ··· 544 501 { 545 502 struct fsl_dspi *dspi = arg; 546 503 struct fsl_dspi_dma *dma = dspi->dma; 504 + struct device *dev = &dspi->pdev->dev; 547 505 int i; 548 506 549 507 if (dspi->rx) { 508 + dma_sync_single_for_cpu(dev, dma->rx_dma_phys, 509 + dspi_dma_transfer_size(dspi), 510 + DMA_FROM_DEVICE); 550 511 for (i = 0; i < dspi->words_in_flight; i++) 551 512 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); 552 513 } ··· 560 513 561 514 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) 562 515 { 516 + size_t size = dspi_dma_transfer_size(dspi); 563 517 struct device *dev = &dspi->pdev->dev; 564 518 struct fsl_dspi_dma *dma = dspi->dma; 565 519 int time_left; 520 + u32 spi_sr; 566 521 int i; 567 522 568 523 for (i = 0; i < dspi->words_in_flight; i++) 569 524 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); 570 525 526 + dma_sync_single_for_device(dev, dma->tx_dma_phys, size, DMA_TO_DEVICE); 571 527 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, 572 - dma->tx_dma_phys, 573 - dspi->words_in_flight * 574 - DMA_SLAVE_BUSWIDTH_4_BYTES, 575 - DMA_MEM_TO_DEV, 576 - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 528 + dma->tx_dma_phys, size, 529 + DMA_MEM_TO_DEV, 530 + DMA_PREP_INTERRUPT | 531 + DMA_CTRL_ACK); 577 532 if (!dma->tx_desc) { 578 533 dev_err(dev, "Not able to get desc for DMA xfer\n"); 579 534 return -EIO; ··· 588 539 return -EINVAL; 589 540 } 590 541 542 + dma_sync_single_for_device(dev, dma->rx_dma_phys, size, 543 + DMA_FROM_DEVICE); 591 544 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, 592 - dma->rx_dma_phys, 593 - dspi->words_in_flight * 594 - DMA_SLAVE_BUSWIDTH_4_BYTES, 595 - DMA_DEV_TO_MEM, 596 - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 545 + dma->rx_dma_phys, size, 546 + DMA_DEV_TO_MEM, 547 + DMA_PREP_INTERRUPT | 548 + DMA_CTRL_ACK); 597 549 if (!dma->rx_desc) { 598 550 dev_err(dev, "Not able to get desc for DMA xfer\n"); 599 551 return -EIO; ··· 615 565 616 566 if (spi_controller_is_target(dspi->ctlr)) { 617 567 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); 618 - return 0; 568 + regmap_read(dspi->regmap, SPI_SR, &spi_sr); 569 + return dspi_fifo_error(dspi, spi_sr); 619 570 } 620 571 621 572 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, ··· 640 589 return 0; 641 590 } 642 591 643 - static void dspi_setup_accel(struct fsl_dspi *dspi); 644 - 645 - static int dspi_dma_xfer(struct fsl_dspi *dspi) 592 + static void dspi_dma_xfer(struct fsl_dspi *dspi) 646 593 { 647 594 struct spi_message *message = dspi->cur_msg; 648 595 struct device *dev = &dspi->pdev->dev; 649 - int ret = 0; 650 596 651 597 /* 652 598 * dspi->len gets decremented by dspi_pop_tx_pushr in ··· 653 605 /* Figure out operational bits-per-word for this chunk */ 654 606 dspi_setup_accel(dspi); 655 607 656 - dspi->words_in_flight = dspi->len / dspi->oper_word_size; 657 - if (dspi->words_in_flight > dspi->devtype_data->fifo_size) 658 - dspi->words_in_flight = dspi->devtype_data->fifo_size; 608 + dspi->words_in_flight = min(dspi->len / dspi->oper_word_size, 609 + dspi_dma_max_datawords(dspi)); 659 610 660 611 message->actual_length += dspi->words_in_flight * 661 612 dspi->oper_word_size; 662 613 663 - ret = dspi_next_xfer_dma_submit(dspi); 664 - if (ret) { 614 + message->status = dspi_next_xfer_dma_submit(dspi); 615 + if (message->status) { 665 616 dev_err(dev, "DMA transfer failed\n"); 666 617 break; 667 618 } 668 619 } 669 - 670 - return ret; 671 620 } 672 621 673 622 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 674 623 { 675 - int dma_bufsize = dspi->devtype_data->fifo_size * 2; 676 624 struct device *dev = &dspi->pdev->dev; 677 625 struct dma_slave_config cfg; 678 626 struct fsl_dspi_dma *dma; ··· 688 644 goto err_tx_channel; 689 645 } 690 646 691 - dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev, 692 - dma_bufsize, &dma->tx_dma_phys, 693 - GFP_KERNEL); 647 + if (spi_controller_is_target(dspi->ctlr)) { 648 + /* 649 + * In target mode we have to be ready to receive the maximum 650 + * that can possibly be transferred at once by EDMA without any 651 + * FIFO underflows. 652 + */ 653 + dma->bufsize = min(dma_get_max_seg_size(dma->chan_rx->device->dev), 654 + dma_get_max_seg_size(dma->chan_tx->device->dev)) * 655 + DMA_SLAVE_BUSWIDTH_4_BYTES; 656 + } else { 657 + dma->bufsize = PAGE_SIZE; 658 + } 659 + 660 + dma->tx_dma_buf = dma_alloc_noncoherent(dma->chan_tx->device->dev, 661 + dma->bufsize, &dma->tx_dma_phys, 662 + DMA_TO_DEVICE, GFP_KERNEL); 694 663 if (!dma->tx_dma_buf) { 695 664 ret = -ENOMEM; 696 665 goto err_tx_dma_buf; 697 666 } 698 667 699 - dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev, 700 - dma_bufsize, &dma->rx_dma_phys, 701 - GFP_KERNEL); 668 + dma->rx_dma_buf = dma_alloc_noncoherent(dma->chan_rx->device->dev, 669 + dma->bufsize, &dma->rx_dma_phys, 670 + DMA_FROM_DEVICE, GFP_KERNEL); 702 671 if (!dma->rx_dma_buf) { 703 672 ret = -ENOMEM; 704 673 goto err_rx_dma_buf; ··· 746 689 return 0; 747 690 748 691 err_slave_config: 749 - dma_free_coherent(dma->chan_rx->device->dev, 750 - dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); 692 + dma_free_noncoherent(dma->chan_rx->device->dev, dma->bufsize, 693 + dma->rx_dma_buf, dma->rx_dma_phys, 694 + DMA_FROM_DEVICE); 751 695 err_rx_dma_buf: 752 - dma_free_coherent(dma->chan_tx->device->dev, 753 - dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); 696 + dma_free_noncoherent(dma->chan_tx->device->dev, dma->bufsize, 697 + dma->tx_dma_buf, dma->tx_dma_phys, DMA_TO_DEVICE); 754 698 err_tx_dma_buf: 755 699 dma_release_channel(dma->chan_tx); 756 700 err_tx_channel: ··· 765 707 766 708 static void dspi_release_dma(struct fsl_dspi *dspi) 767 709 { 768 - int dma_bufsize = dspi->devtype_data->fifo_size * 2; 769 710 struct fsl_dspi_dma *dma = dspi->dma; 770 711 771 712 if (!dma) 772 713 return; 773 714 774 715 if (dma->chan_tx) { 775 - dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize, 776 - dma->tx_dma_buf, dma->tx_dma_phys); 716 + dma_free_noncoherent(dma->chan_tx->device->dev, dma->bufsize, 717 + dma->tx_dma_buf, dma->tx_dma_phys, 718 + DMA_TO_DEVICE); 777 719 dma_release_channel(dma->chan_tx); 778 720 } 779 721 780 722 if (dma->chan_rx) { 781 - dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize, 782 - dma->rx_dma_buf, dma->rx_dma_phys); 723 + dma_free_noncoherent(dma->chan_rx->device->dev, dma->bufsize, 724 + dma->rx_dma_buf, dma->rx_dma_phys, 725 + DMA_FROM_DEVICE); 783 726 dma_release_channel(dma->chan_rx); 784 727 } 785 728 } 729 + #else 730 + static void dspi_dma_xfer(struct fsl_dspi *dspi) 731 + { 732 + dspi->cur_msg->status = -EINVAL; 733 + } 734 + static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 735 + { 736 + dev_err(&dspi->pdev->dev, "DMA support not enabled in kernel\n"); 737 + return -EINVAL; 738 + } 739 + static void dspi_release_dma(struct fsl_dspi *dspi) {} 740 + #endif 786 741 787 742 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 788 743 unsigned long clkrate, bool mtf_enabled) ··· 1057 986 dspi->progress, !dspi->irq); 1058 987 } 1059 988 1060 - static int dspi_rxtx(struct fsl_dspi *dspi) 989 + /* 990 + * Read the previous transfer from the FIFO and transmit the next one. 991 + * 992 + * Returns false if the buffer to be transmitted is empty, and true if there is 993 + * still data to transmit. 994 + */ 995 + static bool dspi_rxtx(struct fsl_dspi *dspi) 1061 996 { 1062 997 dspi_fifo_read(dspi); 1063 998 1064 999 if (!dspi->len) 1065 1000 /* Success! */ 1066 - return 0; 1001 + return false; 1067 1002 1068 1003 dspi_fifo_write(dspi); 1069 1004 1070 - return -EINPROGRESS; 1005 + return true; 1071 1006 } 1072 1007 1073 - static int dspi_poll(struct fsl_dspi *dspi) 1008 + static void dspi_poll(struct fsl_dspi *dspi) 1074 1009 { 1075 - int tries = 1000; 1010 + int tries; 1011 + int err = 0; 1076 1012 u32 spi_sr; 1077 1013 1078 1014 do { 1079 - regmap_read(dspi->regmap, SPI_SR, &spi_sr); 1080 - regmap_write(dspi->regmap, SPI_SR, spi_sr); 1015 + for (tries = 1000; tries > 0; --tries) { 1016 + regmap_read(dspi->regmap, SPI_SR, &spi_sr); 1017 + regmap_write(dspi->regmap, SPI_SR, spi_sr); 1081 1018 1082 - if (spi_sr & SPI_SR_CMDTCF) 1019 + dspi->cur_msg->status = dspi_fifo_error(dspi, spi_sr); 1020 + if (dspi->cur_msg->status) 1021 + return; 1022 + if (spi_sr & SPI_SR_CMDTCF) 1023 + break; 1024 + } 1025 + if (!tries) { 1026 + err = -ETIMEDOUT; 1083 1027 break; 1084 - } while (--tries); 1028 + } 1029 + } while (dspi_rxtx(dspi)); 1085 1030 1086 - if (!tries) 1087 - return -ETIMEDOUT; 1088 - 1089 - return dspi_rxtx(dspi); 1031 + dspi->cur_msg->status = err; 1090 1032 } 1091 1033 1092 1034 static irqreturn_t dspi_interrupt(int irq, void *dev_id) 1093 1035 { 1094 1036 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 1037 + int status; 1095 1038 u32 spi_sr; 1096 1039 1097 1040 regmap_read(dspi->regmap, SPI_SR, &spi_sr); ··· 1114 1029 if (!(spi_sr & SPI_SR_CMDTCF)) 1115 1030 return IRQ_NONE; 1116 1031 1117 - if (dspi_rxtx(dspi) == 0) 1032 + status = dspi_fifo_error(dspi, spi_sr); 1033 + if (status) { 1034 + if (dspi->cur_msg) 1035 + WRITE_ONCE(dspi->cur_msg->status, status); 1118 1036 complete(&dspi->xfer_done); 1037 + return IRQ_HANDLED; 1038 + } 1039 + 1040 + if (dspi_rxtx(dspi) == false) { 1041 + if (dspi->cur_msg) 1042 + WRITE_ONCE(dspi->cur_msg->status, 0); 1043 + complete(&dspi->xfer_done); 1044 + } 1119 1045 1120 1046 return IRQ_HANDLED; 1121 1047 } ··· 1156 1060 struct spi_device *spi = message->spi; 1157 1061 struct spi_transfer *transfer; 1158 1062 bool cs = false; 1159 - int status = 0; 1160 1063 u32 val = 0; 1161 1064 bool cs_change = false; 1162 1065 ··· 1215 1120 dspi->progress, !dspi->irq); 1216 1121 1217 1122 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1218 - status = dspi_dma_xfer(dspi); 1123 + dspi_dma_xfer(dspi); 1219 1124 } else { 1220 1125 /* 1221 1126 * Reinitialize the completion before transferring data ··· 1229 1134 1230 1135 dspi_fifo_write(dspi); 1231 1136 1232 - if (dspi->irq) { 1137 + if (dspi->irq) 1233 1138 wait_for_completion(&dspi->xfer_done); 1234 - } else { 1235 - do { 1236 - status = dspi_poll(dspi); 1237 - } while (status == -EINPROGRESS); 1238 - } 1139 + else 1140 + dspi_poll(dspi); 1239 1141 } 1240 - if (status) 1142 + if (READ_ONCE(message->status)) 1241 1143 break; 1242 1144 1243 1145 spi_transfer_delay_exec(transfer); ··· 1243 1151 dspi_deassert_cs(spi, &cs); 1244 1152 } 1245 1153 1246 - if (status || !cs_change) { 1154 + dspi->cur_msg = NULL; 1155 + if (message->status || !cs_change) { 1247 1156 /* Put DSPI in stop mode */ 1248 1157 regmap_update_bits(dspi->regmap, SPI_MCR, 1249 1158 SPI_MCR_HALT, SPI_MCR_HALT); ··· 1253 1160 ; 1254 1161 } 1255 1162 1256 - message->status = status; 1257 1163 spi_finalize_current_message(ctlr); 1258 1164 1259 - return status; 1165 + return message->status; 1260 1166 } 1261 1167 1262 1168 static int dspi_set_mtf(struct fsl_dspi *dspi)

+4 -4

drivers/spi/spi-fsl-lpspi.c

··· 26 26 #include <linux/spi/spi.h> 27 27 #include <linux/spi/spi_bitbang.h> 28 28 #include <linux/types.h> 29 + #include <linux/minmax.h> 29 30 30 31 #define DRIVER_NAME "fsl_lpspi" 31 32 ··· 486 485 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; 487 486 } 488 487 489 - if (t->len <= fsl_lpspi->txfifosize) 490 - fsl_lpspi->watermark = t->len; 491 - else 492 - fsl_lpspi->watermark = fsl_lpspi->txfifosize; 488 + fsl_lpspi->watermark = min_t(typeof(fsl_lpspi->watermark), 489 + fsl_lpspi->txfifosize, 490 + t->len); 493 491 494 492 if (fsl_lpspi_can_dma(controller, spi, t)) 495 493 fsl_lpspi->usedma = true;

+1 -1

drivers/spi/spi-ljca.c

··· 289 289 }; 290 290 module_auxiliary_driver(ljca_spi_driver); 291 291 292 - MODULE_AUTHOR("Wentong Wu <wentong.wu@intel.com>"); 292 + MODULE_AUTHOR("Wentong Wu"); 293 293 MODULE_AUTHOR("Zhifeng Wang <zhifeng.wang@intel.com>"); 294 294 MODULE_AUTHOR("Lixu Zhang <lixu.zhang@intel.com>"); 295 295 MODULE_DESCRIPTION("Intel La Jolla Cove Adapter USB-SPI driver");

+6 -6

drivers/spi/spi-loopback-test.c

··· 446 446 int i; 447 447 u8 b; 448 448 449 - dev_info(&spi->dev, " spi_msg@%pK\n", msg); 449 + dev_info(&spi->dev, " spi_msg@%p\n", msg); 450 450 if (msg->status) 451 451 dev_info(&spi->dev, " status: %i\n", 452 452 msg->status); ··· 456 456 msg->actual_length); 457 457 458 458 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 459 - dev_info(&spi->dev, " spi_transfer@%pK\n", xfer); 459 + dev_info(&spi->dev, " spi_transfer@%p\n", xfer); 460 460 dev_info(&spi->dev, " len: %i\n", xfer->len); 461 - dev_info(&spi->dev, " tx_buf: %pK\n", xfer->tx_buf); 461 + dev_info(&spi->dev, " tx_buf: %p\n", xfer->tx_buf); 462 462 if (dump_data && xfer->tx_buf) 463 463 spi_test_print_hex_dump(" TX: ", 464 464 xfer->tx_buf, 465 465 xfer->len); 466 466 467 - dev_info(&spi->dev, " rx_buf: %pK\n", xfer->rx_buf); 467 + dev_info(&spi->dev, " rx_buf: %p\n", xfer->rx_buf); 468 468 if (dump_data && xfer->rx_buf) 469 469 spi_test_print_hex_dump(" RX: ", 470 470 xfer->rx_buf, ··· 558 558 /* if still not found then something has modified too much */ 559 559 /* we could list the "closest" transfer here... */ 560 560 dev_err(&spi->dev, 561 - "loopback strangeness - rx changed outside of allowed range at: %pK\n", 561 + "loopback strangeness - rx changed outside of allowed range at: %p\n", 562 562 addr); 563 563 /* do not return, only set ret, 564 564 * so that we list all addresses ··· 696 696 } 697 697 698 698 dev_err(&spi->dev, 699 - "PointerRange [%pK:%pK[ not in range [%pK:%pK[ or [%pK:%pK[\n", 699 + "PointerRange [%p:%p[ not in range [%p:%p[ or [%p:%p[\n", 700 700 *ptr, *ptr + len, 701 701 RX(0), RX(SPI_TEST_MAX_SIZE), 702 702 TX(0), TX(SPI_TEST_MAX_SIZE));

+1 -2

drivers/spi/spi-microchip-core-qspi.c

··· 689 689 690 690 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); 691 691 if (!ctlr) 692 - return dev_err_probe(&pdev->dev, -ENOMEM, 693 - "unable to allocate host for QSPI controller\n"); 692 + return -ENOMEM; 694 693 695 694 qspi = spi_controller_get_devdata(ctlr); 696 695 platform_set_drvdata(pdev, qspi);

+1 -2

drivers/spi/spi-microchip-core.c

··· 534 534 535 535 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); 536 536 if (!host) 537 - return dev_err_probe(&pdev->dev, -ENOMEM, 538 - "unable to allocate host for SPI controller\n"); 537 + return -ENOMEM; 539 538 540 539 platform_set_drvdata(pdev, host); 541 540

+26 -4

drivers/spi/spi-mt65xx.c

··· 563 563 writel(reg_val, mdata->base + SPI_CFG1_REG); 564 564 } 565 565 566 + inline u32 mtk_spi_set_nbit(u32 nbit) 567 + { 568 + switch (nbit) { 569 + default: 570 + pr_warn_once("unknown nbit mode %u. Falling back to single mode\n", 571 + nbit); 572 + fallthrough; 573 + case SPI_NBITS_SINGLE: 574 + return 0x0; 575 + case SPI_NBITS_DUAL: 576 + return 0x1; 577 + case SPI_NBITS_QUAD: 578 + return 0x2; 579 + } 580 + } 581 + 566 582 static void mtk_spi_enable_transfer(struct spi_controller *host) 567 583 { 568 584 u32 cmd; ··· 745 729 746 730 /* prepare xfer direction and duplex mode */ 747 731 if (mdata->dev_comp->ipm_design) { 748 - if (!xfer->tx_buf || !xfer->rx_buf) { 732 + if (xfer->tx_buf && xfer->rx_buf) { 733 + reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN; 734 + } else if (xfer->tx_buf) { 749 735 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 750 - if (xfer->rx_buf) 751 - reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 736 + reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; 737 + reg_val |= mtk_spi_set_nbit(xfer->tx_nbits); 738 + } else { 739 + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 740 + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 741 + reg_val |= mtk_spi_set_nbit(xfer->rx_nbits); 752 742 } 753 743 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); 754 744 } ··· 1181 1159 1182 1160 host = devm_spi_alloc_host(dev, sizeof(*mdata)); 1183 1161 if (!host) 1184 - return dev_err_probe(dev, -ENOMEM, "failed to alloc spi host\n"); 1162 + return -ENOMEM; 1185 1163 1186 1164 host->auto_runtime_pm = true; 1187 1165 host->dev.of_node = dev->of_node;

-1

drivers/spi/spi-mtk-snfi.c

··· 1139 1139 // Prepare for custom write interrupt 1140 1140 nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); 1141 1141 reinit_completion(&snf->op_done); 1142 - ; 1143 1142 1144 1143 // Trigger NFI into custom mode 1145 1144 nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);

+1 -1

drivers/spi/spi-mxs.c

··· 388 388 TXRX_DEASSERT_CS : 0; 389 389 390 390 /* 391 - * Small blocks can be transfered via PIO. 391 + * Small blocks can be transferred via PIO. 392 392 * Measured by empiric means: 393 393 * 394 394 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1

+2 -4

drivers/spi/spi-npcm-fiu.c

··· 13 13 #include <linux/vmalloc.h> 14 14 #include <linux/regmap.h> 15 15 #include <linux/of.h> 16 + #include <linux/minmax.h> 16 17 #include <linux/spi/spi-mem.h> 17 18 #include <linux/mfd/syscon.h> 18 19 ··· 499 498 500 499 do { 501 500 addr = ((u32)op->addr.val + i); 502 - if (currlen < 16) 503 - readlen = currlen; 504 - else 505 - readlen = 16; 501 + readlen = min_t(int, currlen, 16); 506 502 507 503 buf_ptr = data + i; 508 504 ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr,

+99 -18

drivers/spi/spi-nxp-fspi.c

··· 330 330 331 331 /* Access flash memory using IP bus only */ 332 332 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 333 + /* Disable DTR */ 334 + #define FSPI_QUIRK_DISABLE_DTR BIT(1) 333 335 334 336 struct nxp_fspi_devtype_data { 335 337 unsigned int rxfifo; ··· 346 344 .rxfifo = SZ_512, /* (64 * 64 bits) */ 347 345 .txfifo = SZ_1K, /* (128 * 64 bits) */ 348 346 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 349 - .quirks = 0, 347 + .quirks = FSPI_QUIRK_DISABLE_DTR, 350 348 .lut_num = 32, 351 349 .little_endian = true, /* little-endian */ 352 350 }; ··· 401 399 struct mutex lock; 402 400 struct pm_qos_request pm_qos_req; 403 401 int selected; 404 - #define FSPI_NEED_INIT (1 << 0) 402 + #define FSPI_NEED_INIT BIT(0) 403 + #define FSPI_DTR_MODE BIT(1) 405 404 int flags; 406 405 }; 407 406 ··· 562 559 u32 target_lut_reg; 563 560 564 561 /* cmd */ 565 - lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 566 - op->cmd.opcode); 562 + if (op->cmd.dtr) { 563 + lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth), 564 + op->cmd.opcode >> 8); 565 + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR, 566 + LUT_PAD(op->cmd.buswidth), 567 + op->cmd.opcode & 0xFF); 568 + lutidx++; 569 + } else { 570 + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 571 + op->cmd.opcode); 572 + } 567 573 568 574 /* addr bytes */ 569 575 if (op->addr.nbytes) { 570 - lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 576 + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR, 571 577 LUT_PAD(op->addr.buswidth), 572 578 op->addr.nbytes * 8); 573 579 lutidx++; ··· 584 572 585 573 /* dummy bytes, if needed */ 586 574 if (op->dummy.nbytes) { 587 - lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 575 + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY, 588 576 /* 589 577 * Due to FlexSPI controller limitation number of PAD for dummy 590 578 * buswidth needs to be programmed as equal to data buswidth. ··· 599 587 if (op->data.nbytes) { 600 588 lutval[lutidx / 2] |= LUT_DEF(lutidx, 601 589 op->data.dir == SPI_MEM_DATA_IN ? 602 - LUT_NXP_READ : LUT_NXP_WRITE, 590 + (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) : 591 + (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE), 603 592 LUT_PAD(op->data.buswidth), 604 593 0); 605 594 lutidx++; ··· 658 645 return; 659 646 } 660 647 648 + /* 649 + * Sample Clock source selection for Flash Reading 650 + * Four modes defined by fspi: 651 + * mode 0: Dummy Read strobe generated by FlexSPI Controller 652 + * and loopback internally 653 + * mode 1: Dummy Read strobe generated by FlexSPI Controller 654 + * and loopback from DQS pad 655 + * mode 2: Reserved 656 + * mode 3: Flash provided Read strobe and input from DQS pad 657 + * 658 + * fspi default use mode 0 after reset 659 + */ 660 + static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f, 661 + bool op_is_dtr) 662 + { 663 + u32 reg; 664 + 665 + /* 666 + * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read 667 + * strobe and input from DQS pad), otherwise read operaton may 668 + * meet issue. 669 + * This mode require flash device connect the DQS pad on board. 670 + * For other modes, still use mode 0, keep align with before. 671 + * spi_nor_suspend will disable 8D-8D-8D mode, also need to 672 + * change the mode back to mode 0. 673 + */ 674 + reg = fspi_readl(f, f->iobase + FSPI_MCR0); 675 + if (op_is_dtr) 676 + reg |= FSPI_MCR0_RXCLKSRC(3); 677 + else /*select mode 0 */ 678 + reg &= ~FSPI_MCR0_RXCLKSRC(3); 679 + fspi_writel(f, reg, f->iobase + FSPI_MCR0); 680 + } 681 + 661 682 static void nxp_fspi_dll_calibration(struct nxp_fspi *f) 662 683 { 663 684 int ret; ··· 719 672 0, POLL_TOUT, true); 720 673 if (ret) 721 674 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 675 + } 676 + 677 + /* 678 + * Config the DLL register to default value, enable the target clock delay 679 + * line delay cell override mode, and use 1 fixed delay cell in DLL delay 680 + * chain, this is the suggested setting when clock rate < 100MHz. 681 + */ 682 + static void nxp_fspi_dll_override(struct nxp_fspi *f) 683 + { 684 + fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR); 685 + fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR); 722 686 } 723 687 724 688 /* ··· 773 715 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi, 774 716 const struct spi_mem_op *op) 775 717 { 718 + /* flexspi only support one DTR mode: 8D-8D-8D */ 719 + bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr; 776 720 unsigned long rate = op->max_freq; 777 721 int ret; 778 722 uint64_t size_kb; 779 723 780 724 /* 781 725 * Return, if previously selected target device is same as current 782 - * requested target device. 726 + * requested target device. Also the DTR or STR mode do not change. 783 727 */ 784 - if (f->selected == spi_get_chipselect(spi, 0)) 728 + if ((f->selected == spi_get_chipselect(spi, 0)) && 729 + (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr)) 785 730 return; 786 731 787 732 /* Reset FLSHxxCR0 registers */ ··· 800 739 4 * spi_get_chipselect(spi, 0)); 801 740 802 741 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 742 + 743 + nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr); 744 + 745 + if (op_is_dtr) { 746 + f->flags |= FSPI_DTR_MODE; 747 + /* For DTR mode, flexspi will default div 2 and output to device. 748 + * so here to config the root clock to 2 * device rate. 749 + */ 750 + rate = rate * 2; 751 + } else { 752 + f->flags &= ~FSPI_DTR_MODE; 753 + } 803 754 804 755 nxp_fspi_clk_disable_unprep(f); 805 756 ··· 829 756 */ 830 757 if (rate > 100000000) 831 758 nxp_fspi_dll_calibration(f); 759 + else 760 + nxp_fspi_dll_override(f); 832 761 833 762 f->selected = spi_get_chipselect(spi, 0); 834 763 } ··· 1146 1071 /* Disable the module */ 1147 1072 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1148 1073 1149 - /* 1150 - * Config the DLL register to default value, enable the target clock delay 1151 - * line delay cell override mode, and use 1 fixed delay cell in DLL delay 1152 - * chain, this is the suggested setting when clock rate < 100MHz. 1153 - */ 1154 - fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 1155 - fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 1074 + nxp_fspi_dll_override(f); 1156 1075 1157 1076 /* enable module */ 1158 1077 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | ··· 1233 1164 }; 1234 1165 1235 1166 static const struct spi_controller_mem_caps nxp_fspi_mem_caps = { 1167 + .dtr = true, 1168 + .swap16 = false, 1169 + .per_op_freq = true, 1170 + }; 1171 + 1172 + static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = { 1173 + .dtr = false, 1236 1174 .per_op_freq = true, 1237 1175 }; 1238 1176 ··· 1355 1279 ctlr->bus_num = -1; 1356 1280 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1357 1281 ctlr->mem_ops = &nxp_fspi_mem_ops; 1358 - ctlr->mem_caps = &nxp_fspi_mem_caps; 1282 + 1283 + if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR) 1284 + ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr; 1285 + else 1286 + ctlr->mem_caps = &nxp_fspi_mem_caps; 1287 + 1359 1288 ctlr->dev.of_node = np; 1360 1289 1361 1290 ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f); 1362 1291 if (ret) 1363 - return dev_err_probe(dev, ret, "Failed to register nxp_fspi_cleanup\n"); 1292 + return ret; 1364 1293 1365 1294 return devm_spi_register_controller(&pdev->dev, ctlr); 1366 1295 }

+4 -1

drivers/spi/spi-offload-trigger-adi-util-sigma-delta.c

··· 5 5 */ 6 6 7 7 #include <linux/clk.h> 8 - #include <linux/device.h> 8 + #include <linux/dev_printk.h> 9 + #include <linux/err.h> 9 10 #include <linux/mod_devicetable.h> 10 11 #include <linux/module.h> 11 12 #include <linux/platform_device.h> 12 13 #include <linux/property.h> 13 14 #include <linux/spi/offload/provider.h> 15 + #include <linux/spi/offload/types.h> 16 + #include <linux/types.h> 14 17 15 18 static bool adi_util_sigma_delta_match(struct spi_offload_trigger *trigger, 16 19 enum spi_offload_trigger_type type,

+5 -8

drivers/spi/spi-pl022.c

··· 33 33 #include <linux/pm_runtime.h> 34 34 #include <linux/of.h> 35 35 #include <linux/pinctrl/consumer.h> 36 + #include <linux/minmax.h> 36 37 37 38 /* 38 39 * This macro is used to define some register default values. ··· 761 760 * we just feed in this, else we stuff in as much 762 761 * as we can. 763 762 */ 764 - if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 765 - mapbytes = bytesleft; 766 - else 767 - mapbytes = PAGE_SIZE - offset_in_page(bufp); 763 + mapbytes = min_t(int, bytesleft, 764 + PAGE_SIZE - offset_in_page(bufp)); 765 + 768 766 sg_set_page(sg, virt_to_page(bufp), 769 767 mapbytes, offset_in_page(bufp)); 770 768 bufp += mapbytes; ··· 775 775 } else { 776 776 /* Map the dummy buffer on every page */ 777 777 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 778 - if (bytesleft < PAGE_SIZE) 779 - mapbytes = bytesleft; 780 - else 781 - mapbytes = PAGE_SIZE; 778 + mapbytes = min_t(int, bytesleft, PAGE_SIZE); 782 779 sg_set_page(sg, virt_to_page(pl022->dummypage), 783 780 mapbytes, 0); 784 781 bytesleft -= mapbytes;

+1 -1

drivers/spi/spi-pxa2xx.c

··· 1283 1283 else 1284 1284 controller = devm_spi_alloc_host(dev, sizeof(*drv_data)); 1285 1285 if (!controller) 1286 - return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n"); 1286 + return -ENOMEM; 1287 1287 1288 1288 drv_data = spi_controller_get_devdata(controller); 1289 1289 drv_data->controller = controller;

+13 -45

drivers/spi/spi-qpic-snand.c

··· 78 78 }; 79 79 80 80 struct qpic_ecc { 81 - struct device *dev; 82 81 int ecc_bytes_hw; 83 82 int spare_bytes; 84 83 int bbm_size; ··· 94 95 u32 cfg1_raw; 95 96 u32 ecc_buf_cfg; 96 97 u32 ecc_bch_cfg; 97 - u32 clrflashstatus; 98 - u32 clrreadstatus; 99 98 bool bch_enabled; 100 99 }; 101 100 ··· 379 382 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); 380 383 381 384 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203); 382 - ecc_cfg->clrflashstatus = FS_READY_BSY_N; 383 - ecc_cfg->clrreadstatus = 0xc0; 384 385 385 386 conf->step_size = ecc_cfg->step_size; 386 387 conf->strength = ecc_cfg->strength; 387 388 389 + snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N); 390 + snandc->regs->clrreadstatus = cpu_to_le32(0xc0); 388 391 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); 389 392 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); 390 393 ··· 491 494 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 492 495 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 493 496 494 - qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 495 - qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 496 - NAND_BAM_NEXT_SGL); 497 + if (use_ecc) { 498 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 499 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 500 + NAND_BAM_NEXT_SGL); 501 + } else { 502 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 503 + NAND_BAM_NEXT_SGL); 504 + } 497 505 } 498 506 499 507 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) ··· 601 599 snandc->regs->cfg0 = cpu_to_le32(cfg0); 602 600 snandc->regs->cfg1 = cpu_to_le32(cfg1); 603 601 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 604 - snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 605 - snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 606 602 snandc->regs->exec = cpu_to_le32(1); 607 603 608 604 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); ··· 734 734 snandc->regs->cfg0 = cpu_to_le32(cfg0); 735 735 snandc->regs->cfg1 = cpu_to_le32(cfg1); 736 736 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 737 - snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 738 - snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 739 737 snandc->regs->exec = cpu_to_le32(1); 740 738 741 739 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); ··· 848 850 snandc->regs->cfg0 = cpu_to_le32(cfg0); 849 851 snandc->regs->cfg1 = cpu_to_le32(cfg1); 850 852 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 851 - snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 852 - snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 853 853 snandc->regs->exec = cpu_to_le32(1); 854 854 855 855 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); ··· 939 943 snandc->regs->cfg0 = cpu_to_le32(cfg0); 940 944 snandc->regs->cfg1 = cpu_to_le32(cfg1); 941 945 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 942 - snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 943 - snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 944 946 snandc->regs->exec = cpu_to_le32(1); 945 947 946 948 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); ··· 1058 1064 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1059 1065 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1060 1066 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1061 - snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 1062 - snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 1063 1067 snandc->regs->exec = cpu_to_le32(1); 1064 1068 1065 1069 qcom_spi_config_page_write(snandc); ··· 1541 1549 } 1542 1550 1543 1551 snandc->props = dev_data; 1544 - snandc->dev = &pdev->dev; 1545 1552 1546 - snandc->core_clk = devm_clk_get(dev, "core"); 1553 + snandc->core_clk = devm_clk_get_enabled(dev, "core"); 1547 1554 if (IS_ERR(snandc->core_clk)) 1548 1555 return PTR_ERR(snandc->core_clk); 1549 1556 1550 - snandc->aon_clk = devm_clk_get(dev, "aon"); 1557 + snandc->aon_clk = devm_clk_get_enabled(dev, "aon"); 1551 1558 if (IS_ERR(snandc->aon_clk)) 1552 1559 return PTR_ERR(snandc->aon_clk); 1553 1560 1554 - snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom"); 1561 + snandc->qspi->iomacro_clk = devm_clk_get_enabled(dev, "iom"); 1555 1562 if (IS_ERR(snandc->qspi->iomacro_clk)) 1556 1563 return PTR_ERR(snandc->qspi->iomacro_clk); 1557 1564 ··· 1563 1572 DMA_BIDIRECTIONAL, 0); 1564 1573 if (dma_mapping_error(dev, snandc->base_dma)) 1565 1574 return -ENXIO; 1566 - 1567 - ret = clk_prepare_enable(snandc->core_clk); 1568 - if (ret) 1569 - goto err_dis_core_clk; 1570 - 1571 - ret = clk_prepare_enable(snandc->aon_clk); 1572 - if (ret) 1573 - goto err_dis_aon_clk; 1574 - 1575 - ret = clk_prepare_enable(snandc->qspi->iomacro_clk); 1576 - if (ret) 1577 - goto err_dis_iom_clk; 1578 1575 1579 1576 ret = qcom_nandc_alloc(snandc); 1580 1577 if (ret) ··· 1604 1625 err_spi_init: 1605 1626 qcom_nandc_unalloc(snandc); 1606 1627 err_snand_alloc: 1607 - clk_disable_unprepare(snandc->qspi->iomacro_clk); 1608 - err_dis_iom_clk: 1609 - clk_disable_unprepare(snandc->aon_clk); 1610 - err_dis_aon_clk: 1611 - clk_disable_unprepare(snandc->core_clk); 1612 - err_dis_core_clk: 1613 1628 dma_unmap_resource(dev, res->start, resource_size(res), 1614 1629 DMA_BIDIRECTIONAL, 0); 1615 1630 return ret; ··· 1618 1645 spi_unregister_controller(ctlr); 1619 1646 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng); 1620 1647 qcom_nandc_unalloc(snandc); 1621 - 1622 - clk_disable_unprepare(snandc->aon_clk); 1623 - clk_disable_unprepare(snandc->core_clk); 1624 - clk_disable_unprepare(snandc->qspi->iomacro_clk); 1625 - 1626 1648 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), 1627 1649 DMA_BIDIRECTIONAL, 0); 1628 1650 }

+16 -20

drivers/spi/spi-rb4xx.c

··· 16 16 #include <linux/spi/spi.h> 17 17 #include <linux/of.h> 18 18 19 - #include <asm/mach-ath79/ar71xx_regs.h> 19 + #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ 20 + #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ 21 + #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ 22 + #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ 23 + 24 + #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ 25 + 26 + #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ 27 + #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ 28 + #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 20 29 21 30 struct rb4xx_spi { 22 31 void __iomem *base; ··· 72 63 if (value & BIT(1)) 73 64 regval |= AR71XX_SPI_IOC_DO; 74 65 if (value & BIT(0)) 75 - regval |= AR71XX_SPI_IOC_CS2; 66 + regval |= AR71XX_SPI_IOC_CS(2); 76 67 77 68 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); 78 69 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); ··· 98 89 */ 99 90 if (enable) 100 91 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, 101 - AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1); 92 + AR71XX_SPI_IOC_CS(0) | AR71XX_SPI_IOC_CS(1)); 102 93 } 103 94 104 95 static int rb4xx_transfer_one(struct spi_controller *host, ··· 118 109 */ 119 110 if (spi_get_chipselect(spi, 0) == 2) 120 111 /* MMC */ 121 - spi_ioc = AR71XX_SPI_IOC_CS0; 112 + spi_ioc = AR71XX_SPI_IOC_CS(0); 122 113 else 123 114 /* Boot flash and CPLD */ 124 - spi_ioc = AR71XX_SPI_IOC_CS1; 115 + spi_ioc = AR71XX_SPI_IOC_CS(1); 125 116 126 117 tx_buf = t->tx_buf; 127 118 rx_buf = t->rx_buf; ··· 156 147 if (!host) 157 148 return -ENOMEM; 158 149 159 - ahb_clk = devm_clk_get(&pdev->dev, "ahb"); 150 + ahb_clk = devm_clk_get_enabled(&pdev->dev, "ahb"); 160 151 if (IS_ERR(ahb_clk)) 161 152 return PTR_ERR(ahb_clk); 162 153 ··· 172 163 rbspi = spi_controller_get_devdata(host); 173 164 rbspi->base = spi_base; 174 165 rbspi->clk = ahb_clk; 175 - platform_set_drvdata(pdev, rbspi); 176 166 177 167 err = devm_spi_register_controller(&pdev->dev, host); 178 168 if (err) { ··· 179 171 return err; 180 172 } 181 173 182 - err = clk_prepare_enable(ahb_clk); 183 - if (err) 184 - return err; 185 - 186 174 /* Enable SPI */ 187 175 rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); 188 176 189 177 return 0; 190 - } 191 - 192 - static void rb4xx_spi_remove(struct platform_device *pdev) 193 - { 194 - struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); 195 - 196 - clk_disable_unprepare(rbspi->clk); 197 178 } 198 179 199 180 static const struct of_device_id rb4xx_spi_dt_match[] = { ··· 193 196 194 197 static struct platform_driver rb4xx_spi_drv = { 195 198 .probe = rb4xx_spi_probe, 196 - .remove = rb4xx_spi_remove, 197 199 .driver = { 198 200 .name = "rb4xx-spi", 199 - .of_match_table = of_match_ptr(rb4xx_spi_dt_match), 201 + .of_match_table = rb4xx_spi_dt_match, 200 202 }, 201 203 }; 202 204

+6 -6

drivers/spi/spi-rpc-if.c

··· 196 196 pm_runtime_disable(rpc->dev); 197 197 } 198 198 199 - static int __maybe_unused rpcif_spi_suspend(struct device *dev) 199 + static int rpcif_spi_suspend(struct device *dev) 200 200 { 201 201 struct spi_controller *ctlr = dev_get_drvdata(dev); 202 202 203 203 return spi_controller_suspend(ctlr); 204 204 } 205 205 206 - static int __maybe_unused rpcif_spi_resume(struct device *dev) 206 + static int rpcif_spi_resume(struct device *dev) 207 207 { 208 208 struct spi_controller *ctlr = dev_get_drvdata(dev); 209 + 210 + rpcif_hw_init(dev, false); 209 211 210 212 return spi_controller_resume(ctlr); 211 213 } 212 214 213 - static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume); 215 + static DEFINE_SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume); 214 216 215 217 static const struct platform_device_id rpc_if_spi_id_table[] = { 216 218 { .name = "rpc-if-spi" }, ··· 226 224 .id_table = rpc_if_spi_id_table, 227 225 .driver = { 228 226 .name = "rpc-if-spi", 229 - #ifdef CONFIG_PM_SLEEP 230 - .pm = &rpcif_spi_pm_ops, 231 - #endif 227 + .pm = pm_sleep_ptr(&rpcif_spi_pm_ops), 232 228 }, 233 229 }; 234 230 module_platform_driver(rpcif_spi_driver);

+1 -18

drivers/spi/spi-s3c64xx.c

··· 1268 1268 1269 1269 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd)); 1270 1270 if (!host) 1271 - return dev_err_probe(&pdev->dev, -ENOMEM, 1272 - "Unable to allocate SPI Host\n"); 1271 + return -ENOMEM; 1273 1272 1274 1273 platform_set_drvdata(pdev, host); 1275 1274 ··· 1506 1507 s3c64xx_spi_runtime_resume, NULL) 1507 1508 }; 1508 1509 1509 - static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1510 - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1511 - .fifo_lvl_mask = { 0x7f }, 1512 - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1513 - .rx_lvl_offset = 13, 1514 - .tx_st_done = 21, 1515 - .clk_div = 2, 1516 - .high_speed = true, 1517 - }; 1518 - 1519 1510 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1520 1511 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1521 1512 .fifo_lvl_mask = { 0x7f, 0x7F }, ··· 1617 1628 1618 1629 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1619 1630 { 1620 - .name = "s3c2443-spi", 1621 - .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1622 - }, { 1623 1631 .name = "s3c6410-spi", 1624 1632 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1625 1633 }, ··· 1627 1641 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1628 1642 { .compatible = "google,gs101-spi", 1629 1643 .data = &gs101_spi_port_config, 1630 - }, 1631 - { .compatible = "samsung,s3c2443-spi", 1632 - .data = &s3c2443_spi_port_config, 1633 1644 }, 1634 1645 { .compatible = "samsung,s3c6410-spi", 1635 1646 .data = &s3c6410_spi_port_config,

+3 -3

drivers/spi/spi-sunplus-sp7021.c

··· 103 103 104 104 data_status = readl(pspim->s_base + SP7021_DATA_RDY_REG); 105 105 data_status |= SP7021_SLAVE_CLR_INT; 106 - writel(data_status , pspim->s_base + SP7021_DATA_RDY_REG); 106 + writel(data_status, pspim->s_base + SP7021_DATA_RDY_REG); 107 107 complete(&pspim->target_isr); 108 108 return IRQ_HANDLED; 109 109 } ··· 296 296 } 297 297 298 298 static int sp7021_spi_host_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, 299 - struct spi_transfer *xfer) 299 + struct spi_transfer *xfer) 300 300 { 301 301 struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(ctlr); 302 302 unsigned long timeout = msecs_to_jiffies(1000); ··· 360 360 } 361 361 362 362 static int sp7021_spi_target_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, 363 - struct spi_transfer *xfer) 363 + struct spi_transfer *xfer) 364 364 { 365 365 struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(ctlr); 366 366 struct device *dev = pspim->dev;

+431

drivers/spi/spi-virtio.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * SPI bus driver for the Virtio SPI controller 4 + * Copyright (C) 2023 OpenSynergy GmbH 5 + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 6 + */ 7 + 8 + #include <linux/completion.h> 9 + #include <linux/interrupt.h> 10 + #include <linux/io.h> 11 + #include <linux/module.h> 12 + #include <linux/spi/spi.h> 13 + #include <linux/stddef.h> 14 + #include <linux/virtio.h> 15 + #include <linux/virtio_ring.h> 16 + #include <linux/virtio_spi.h> 17 + 18 + #define VIRTIO_SPI_MODE_MASK \ 19 + (SPI_MODE_X_MASK | SPI_CS_HIGH | SPI_LSB_FIRST) 20 + 21 + struct virtio_spi_req { 22 + struct completion completion; 23 + const u8 *tx_buf; 24 + u8 *rx_buf; 25 + struct spi_transfer_head transfer_head ____cacheline_aligned; 26 + struct spi_transfer_result result; 27 + }; 28 + 29 + struct virtio_spi_priv { 30 + /* The virtio device we're associated with */ 31 + struct virtio_device *vdev; 32 + /* Pointer to the virtqueue */ 33 + struct virtqueue *vq; 34 + /* Copy of config space mode_func_supported */ 35 + u32 mode_func_supported; 36 + /* Copy of config space max_freq_hz */ 37 + u32 max_freq_hz; 38 + }; 39 + 40 + static void virtio_spi_msg_done(struct virtqueue *vq) 41 + { 42 + struct virtio_spi_req *req; 43 + unsigned int len; 44 + 45 + while ((req = virtqueue_get_buf(vq, &len))) 46 + complete(&req->completion); 47 + } 48 + 49 + /* 50 + * virtio_spi_set_delays - Set delay parameters for SPI transfer 51 + * 52 + * This function sets various delay parameters for SPI transfer, 53 + * including delay after CS asserted, timing intervals between 54 + * adjacent words within a transfer, delay before and after CS 55 + * deasserted. It converts these delay parameters to nanoseconds 56 + * using spi_delay_to_ns and stores the results in spi_transfer_head 57 + * structure. 58 + * If the conversion fails, the function logs a warning message and 59 + * returns an error code. 60 + * . . . . . . . . . . 61 + * Delay + A + + B + + C + D + E + F + A + 62 + * . . . . . . . . . . 63 + * ___. . . . . . .___.___. . 64 + * CS# |___.______.____.____.___.___| . |___._____________ 65 + * . . . . . . . . . . 66 + * . . . . . . . . . . 67 + * SCLK__.___.___NNN_____NNN__.___.___.___.___.___.___NNN_______ 68 + * 69 + * NOTE: 1st transfer has two words, the delay between these two words are 70 + * 'B' in the diagram. 71 + * 72 + * A => struct spi_device -> cs_setup 73 + * B => max{struct spi_transfer -> word_delay, struct spi_device -> word_delay} 74 + * Note: spi_device and spi_transfer both have word_delay, Linux 75 + * choose the bigger one, refer to _spi_xfer_word_delay_update function 76 + * C => struct spi_transfer -> delay 77 + * D => struct spi_device -> cs_hold 78 + * E => struct spi_device -> cs_inactive 79 + * F => struct spi_transfer -> cs_change_delay 80 + * 81 + * So the corresponding relationship: 82 + * A <===> cs_setup_ns (after CS asserted) 83 + * B <===> word_delay_ns (delay between adjacent words within a transfer) 84 + * C+D <===> cs_delay_hold_ns (before CS deasserted) 85 + * E+F <===> cs_change_delay_inactive_ns (after CS deasserted, these two 86 + * values are also recommended in the Linux driver to be added up) 87 + */ 88 + static int virtio_spi_set_delays(struct spi_transfer_head *th, 89 + struct spi_device *spi, 90 + struct spi_transfer *xfer) 91 + { 92 + int cs_setup; 93 + int cs_word_delay_xfer; 94 + int cs_word_delay_spi; 95 + int delay; 96 + int cs_hold; 97 + int cs_inactive; 98 + int cs_change_delay; 99 + 100 + cs_setup = spi_delay_to_ns(&spi->cs_setup, xfer); 101 + if (cs_setup < 0) { 102 + dev_warn(&spi->dev, "Cannot convert cs_setup\n"); 103 + return cs_setup; 104 + } 105 + th->cs_setup_ns = cpu_to_le32(cs_setup); 106 + 107 + cs_word_delay_xfer = spi_delay_to_ns(&xfer->word_delay, xfer); 108 + if (cs_word_delay_xfer < 0) { 109 + dev_warn(&spi->dev, "Cannot convert cs_word_delay_xfer\n"); 110 + return cs_word_delay_xfer; 111 + } 112 + cs_word_delay_spi = spi_delay_to_ns(&spi->word_delay, xfer); 113 + if (cs_word_delay_spi < 0) { 114 + dev_warn(&spi->dev, "Cannot convert cs_word_delay_spi\n"); 115 + return cs_word_delay_spi; 116 + } 117 + 118 + th->word_delay_ns = cpu_to_le32(max(cs_word_delay_spi, cs_word_delay_xfer)); 119 + 120 + delay = spi_delay_to_ns(&xfer->delay, xfer); 121 + if (delay < 0) { 122 + dev_warn(&spi->dev, "Cannot convert delay\n"); 123 + return delay; 124 + } 125 + cs_hold = spi_delay_to_ns(&spi->cs_hold, xfer); 126 + if (cs_hold < 0) { 127 + dev_warn(&spi->dev, "Cannot convert cs_hold\n"); 128 + return cs_hold; 129 + } 130 + th->cs_delay_hold_ns = cpu_to_le32(delay + cs_hold); 131 + 132 + cs_inactive = spi_delay_to_ns(&spi->cs_inactive, xfer); 133 + if (cs_inactive < 0) { 134 + dev_warn(&spi->dev, "Cannot convert cs_inactive\n"); 135 + return cs_inactive; 136 + } 137 + cs_change_delay = spi_delay_to_ns(&xfer->cs_change_delay, xfer); 138 + if (cs_change_delay < 0) { 139 + dev_warn(&spi->dev, "Cannot convert cs_change_delay\n"); 140 + return cs_change_delay; 141 + } 142 + th->cs_change_delay_inactive_ns = 143 + cpu_to_le32(cs_inactive + cs_change_delay); 144 + 145 + return 0; 146 + } 147 + 148 + static int virtio_spi_transfer_one(struct spi_controller *ctrl, 149 + struct spi_device *spi, 150 + struct spi_transfer *xfer) 151 + { 152 + struct virtio_spi_priv *priv = spi_controller_get_devdata(ctrl); 153 + struct virtio_spi_req *spi_req __free(kfree) = NULL; 154 + struct spi_transfer_head *th; 155 + struct scatterlist sg_out_head, sg_out_payload; 156 + struct scatterlist sg_in_result, sg_in_payload; 157 + struct scatterlist *sgs[4]; 158 + unsigned int outcnt = 0; 159 + unsigned int incnt = 0; 160 + int ret; 161 + 162 + spi_req = kzalloc(sizeof(*spi_req), GFP_KERNEL); 163 + if (!spi_req) 164 + return -ENOMEM; 165 + 166 + init_completion(&spi_req->completion); 167 + 168 + th = &spi_req->transfer_head; 169 + 170 + /* Fill struct spi_transfer_head */ 171 + th->chip_select_id = spi_get_chipselect(spi, 0); 172 + th->bits_per_word = spi->bits_per_word; 173 + th->cs_change = xfer->cs_change; 174 + th->tx_nbits = xfer->tx_nbits; 175 + th->rx_nbits = xfer->rx_nbits; 176 + th->reserved[0] = 0; 177 + th->reserved[1] = 0; 178 + th->reserved[2] = 0; 179 + 180 + static_assert(VIRTIO_SPI_CPHA == SPI_CPHA, 181 + "VIRTIO_SPI_CPHA must match SPI_CPHA"); 182 + static_assert(VIRTIO_SPI_CPOL == SPI_CPOL, 183 + "VIRTIO_SPI_CPOL must match SPI_CPOL"); 184 + static_assert(VIRTIO_SPI_CS_HIGH == SPI_CS_HIGH, 185 + "VIRTIO_SPI_CS_HIGH must match SPI_CS_HIGH"); 186 + static_assert(VIRTIO_SPI_MODE_LSB_FIRST == SPI_LSB_FIRST, 187 + "VIRTIO_SPI_MODE_LSB_FIRST must match SPI_LSB_FIRST"); 188 + 189 + th->mode = cpu_to_le32(spi->mode & VIRTIO_SPI_MODE_MASK); 190 + if (spi->mode & SPI_LOOP) 191 + th->mode |= cpu_to_le32(VIRTIO_SPI_MODE_LOOP); 192 + 193 + th->freq = cpu_to_le32(xfer->speed_hz); 194 + 195 + ret = virtio_spi_set_delays(th, spi, xfer); 196 + if (ret) 197 + goto msg_done; 198 + 199 + /* Set buffers */ 200 + spi_req->tx_buf = xfer->tx_buf; 201 + spi_req->rx_buf = xfer->rx_buf; 202 + 203 + /* Prepare sending of virtio message */ 204 + init_completion(&spi_req->completion); 205 + 206 + sg_init_one(&sg_out_head, th, sizeof(*th)); 207 + sgs[outcnt] = &sg_out_head; 208 + outcnt++; 209 + 210 + if (spi_req->tx_buf) { 211 + sg_init_one(&sg_out_payload, spi_req->tx_buf, xfer->len); 212 + sgs[outcnt] = &sg_out_payload; 213 + outcnt++; 214 + } 215 + 216 + if (spi_req->rx_buf) { 217 + sg_init_one(&sg_in_payload, spi_req->rx_buf, xfer->len); 218 + sgs[outcnt] = &sg_in_payload; 219 + incnt++; 220 + } 221 + 222 + sg_init_one(&sg_in_result, &spi_req->result, 223 + sizeof(struct spi_transfer_result)); 224 + sgs[outcnt + incnt] = &sg_in_result; 225 + incnt++; 226 + 227 + ret = virtqueue_add_sgs(priv->vq, sgs, outcnt, incnt, spi_req, 228 + GFP_KERNEL); 229 + if (ret) 230 + goto msg_done; 231 + 232 + /* Simple implementation: There can be only one transfer in flight */ 233 + virtqueue_kick(priv->vq); 234 + 235 + wait_for_completion(&spi_req->completion); 236 + 237 + /* Read result from message and translate return code */ 238 + switch (spi_req->result.result) { 239 + case VIRTIO_SPI_TRANS_OK: 240 + break; 241 + case VIRTIO_SPI_PARAM_ERR: 242 + ret = -EINVAL; 243 + break; 244 + case VIRTIO_SPI_TRANS_ERR: 245 + ret = -EIO; 246 + break; 247 + default: 248 + ret = -EIO; 249 + break; 250 + } 251 + 252 + msg_done: 253 + if (ret) 254 + ctrl->cur_msg->status = ret; 255 + 256 + return ret; 257 + } 258 + 259 + static void virtio_spi_read_config(struct virtio_device *vdev) 260 + { 261 + struct spi_controller *ctrl = dev_get_drvdata(&vdev->dev); 262 + struct virtio_spi_priv *priv = vdev->priv; 263 + u8 cs_max_number; 264 + u8 tx_nbits_supported; 265 + u8 rx_nbits_supported; 266 + 267 + cs_max_number = virtio_cread8(vdev, offsetof(struct virtio_spi_config, 268 + cs_max_number)); 269 + ctrl->num_chipselect = cs_max_number; 270 + 271 + /* Set the mode bits which are understood by this driver */ 272 + priv->mode_func_supported = 273 + virtio_cread32(vdev, offsetof(struct virtio_spi_config, 274 + mode_func_supported)); 275 + ctrl->mode_bits = priv->mode_func_supported & 276 + (VIRTIO_SPI_CS_HIGH | VIRTIO_SPI_MODE_LSB_FIRST); 277 + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPHA_1) 278 + ctrl->mode_bits |= VIRTIO_SPI_CPHA; 279 + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPOL_1) 280 + ctrl->mode_bits |= VIRTIO_SPI_CPOL; 281 + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LSB_FIRST) 282 + ctrl->mode_bits |= SPI_LSB_FIRST; 283 + if (priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LOOPBACK) 284 + ctrl->mode_bits |= SPI_LOOP; 285 + tx_nbits_supported = 286 + virtio_cread8(vdev, offsetof(struct virtio_spi_config, 287 + tx_nbits_supported)); 288 + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) 289 + ctrl->mode_bits |= SPI_TX_DUAL; 290 + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) 291 + ctrl->mode_bits |= SPI_TX_QUAD; 292 + if (tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) 293 + ctrl->mode_bits |= SPI_TX_OCTAL; 294 + rx_nbits_supported = 295 + virtio_cread8(vdev, offsetof(struct virtio_spi_config, 296 + rx_nbits_supported)); 297 + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) 298 + ctrl->mode_bits |= SPI_RX_DUAL; 299 + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) 300 + ctrl->mode_bits |= SPI_RX_QUAD; 301 + if (rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) 302 + ctrl->mode_bits |= SPI_RX_OCTAL; 303 + 304 + ctrl->bits_per_word_mask = 305 + virtio_cread32(vdev, offsetof(struct virtio_spi_config, 306 + bits_per_word_mask)); 307 + 308 + priv->max_freq_hz = 309 + virtio_cread32(vdev, offsetof(struct virtio_spi_config, 310 + max_freq_hz)); 311 + } 312 + 313 + static int virtio_spi_find_vqs(struct virtio_spi_priv *priv) 314 + { 315 + struct virtqueue *vq; 316 + 317 + vq = virtio_find_single_vq(priv->vdev, virtio_spi_msg_done, "spi-rq"); 318 + if (IS_ERR(vq)) 319 + return PTR_ERR(vq); 320 + priv->vq = vq; 321 + return 0; 322 + } 323 + 324 + /* Function must not be called before virtio_spi_find_vqs() has been run */ 325 + static void virtio_spi_del_vq(void *data) 326 + { 327 + struct virtio_device *vdev = data; 328 + 329 + virtio_reset_device(vdev); 330 + vdev->config->del_vqs(vdev); 331 + } 332 + 333 + static int virtio_spi_probe(struct virtio_device *vdev) 334 + { 335 + struct virtio_spi_priv *priv; 336 + struct spi_controller *ctrl; 337 + int ret; 338 + 339 + ctrl = devm_spi_alloc_host(&vdev->dev, sizeof(*priv)); 340 + if (!ctrl) 341 + return -ENOMEM; 342 + 343 + priv = spi_controller_get_devdata(ctrl); 344 + priv->vdev = vdev; 345 + vdev->priv = priv; 346 + 347 + device_set_node(&ctrl->dev, dev_fwnode(&vdev->dev)); 348 + 349 + dev_set_drvdata(&vdev->dev, ctrl); 350 + 351 + virtio_spi_read_config(vdev); 352 + 353 + ctrl->transfer_one = virtio_spi_transfer_one; 354 + 355 + ret = virtio_spi_find_vqs(priv); 356 + if (ret) 357 + return dev_err_probe(&vdev->dev, ret, "Cannot setup virtqueues\n"); 358 + 359 + /* Register cleanup for virtqueues using devm */ 360 + ret = devm_add_action_or_reset(&vdev->dev, virtio_spi_del_vq, vdev); 361 + if (ret) 362 + return dev_err_probe(&vdev->dev, ret, "Cannot register virtqueue cleanup\n"); 363 + 364 + /* Use devm version to register controller */ 365 + ret = devm_spi_register_controller(&vdev->dev, ctrl); 366 + if (ret) 367 + return dev_err_probe(&vdev->dev, ret, "Cannot register controller\n"); 368 + 369 + return 0; 370 + } 371 + 372 + static int virtio_spi_freeze(struct device *dev) 373 + { 374 + struct spi_controller *ctrl = dev_get_drvdata(dev); 375 + struct virtio_device *vdev = dev_to_virtio(dev); 376 + int ret; 377 + 378 + ret = spi_controller_suspend(ctrl); 379 + if (ret) { 380 + dev_warn(dev, "cannot suspend controller (%d)\n", ret); 381 + return ret; 382 + } 383 + 384 + virtio_spi_del_vq(vdev); 385 + return 0; 386 + } 387 + 388 + static int virtio_spi_restore(struct device *dev) 389 + { 390 + struct spi_controller *ctrl = dev_get_drvdata(dev); 391 + struct virtio_device *vdev = dev_to_virtio(dev); 392 + int ret; 393 + 394 + ret = virtio_spi_find_vqs(vdev->priv); 395 + if (ret) { 396 + dev_err(dev, "problem starting vqueue (%d)\n", ret); 397 + return ret; 398 + } 399 + 400 + ret = spi_controller_resume(ctrl); 401 + if (ret) 402 + dev_err(dev, "problem resuming controller (%d)\n", ret); 403 + 404 + return ret; 405 + } 406 + 407 + static struct virtio_device_id virtio_spi_id_table[] = { 408 + { VIRTIO_ID_SPI, VIRTIO_DEV_ANY_ID }, 409 + {} 410 + }; 411 + MODULE_DEVICE_TABLE(virtio, virtio_spi_id_table); 412 + 413 + static const struct dev_pm_ops virtio_spi_pm_ops = { 414 + .freeze = pm_sleep_ptr(virtio_spi_freeze), 415 + .restore = pm_sleep_ptr(virtio_spi_restore), 416 + }; 417 + 418 + static struct virtio_driver virtio_spi_driver = { 419 + .driver = { 420 + .name = KBUILD_MODNAME, 421 + .pm = &virtio_spi_pm_ops, 422 + }, 423 + .id_table = virtio_spi_id_table, 424 + .probe = virtio_spi_probe, 425 + }; 426 + module_virtio_driver(virtio_spi_driver); 427 + 428 + MODULE_AUTHOR("OpenSynergy GmbH"); 429 + MODULE_AUTHOR("Haixu Cui <quic_haixcui@quicinc.com>"); 430 + MODULE_LICENSE("GPL"); 431 + MODULE_DESCRIPTION("Virtio SPI bus driver");

+35 -50

drivers/spi/spi.c

··· 427 427 if (spi->irq < 0) 428 428 spi->irq = 0; 429 429 430 - ret = dev_pm_domain_attach(dev, PD_FLAG_ATTACH_POWER_ON); 430 + ret = dev_pm_domain_attach(dev, PD_FLAG_ATTACH_POWER_ON | 431 + PD_FLAG_DETACH_POWER_OFF); 431 432 if (ret) 432 433 return ret; 433 434 434 - if (sdrv->probe) { 435 + if (sdrv->probe) 435 436 ret = sdrv->probe(spi); 436 - if (ret) 437 - dev_pm_domain_detach(dev, true); 438 - } 439 437 440 438 return ret; 441 439 } ··· 444 446 445 447 if (sdrv->remove) 446 448 sdrv->remove(to_spi_device(dev)); 447 - 448 - dev_pm_domain_detach(dev, true); 449 449 } 450 450 451 451 static void spi_shutdown(struct device *dev) ··· 586 590 spi->dev.bus = &spi_bus_type; 587 591 spi->dev.release = spidev_release; 588 592 spi->mode = ctlr->buswidth_override_bits; 593 + spi->num_chipselect = 1; 589 594 590 595 device_initialize(&spi->dev); 591 596 return spi; ··· 623 626 */ 624 627 #define SPI_INVALID_CS ((s8)-1) 625 628 626 - static inline bool is_valid_cs(s8 chip_select) 627 - { 628 - return chip_select != SPI_INVALID_CS; 629 - } 630 - 631 629 static inline int spi_dev_check_cs(struct device *dev, 632 630 struct spi_device *spi, u8 idx, 633 631 struct spi_device *new_spi, u8 new_idx) ··· 631 639 u8 idx_new; 632 640 633 641 cs = spi_get_chipselect(spi, idx); 634 - for (idx_new = new_idx; idx_new < SPI_CS_CNT_MAX; idx_new++) { 642 + for (idx_new = new_idx; idx_new < new_spi->num_chipselect; idx_new++) { 635 643 cs_new = spi_get_chipselect(new_spi, idx_new); 636 - if (is_valid_cs(cs) && is_valid_cs(cs_new) && cs == cs_new) { 644 + if (cs == cs_new) { 637 645 dev_err(dev, "chipselect %u already in use\n", cs_new); 638 646 return -EBUSY; 639 647 } ··· 648 656 int status, idx; 649 657 650 658 if (spi->controller == new_spi->controller) { 651 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 659 + for (idx = 0; idx < spi->num_chipselect; idx++) { 652 660 status = spi_dev_check_cs(dev, spi, idx, new_spi, 0); 653 661 if (status) 654 662 return status; ··· 670 678 int status, idx; 671 679 u8 cs; 672 680 673 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 681 + if (spi->num_chipselect > SPI_DEVICE_CS_CNT_MAX) { 682 + dev_err(dev, "num_cs %d > max %d\n", spi->num_chipselect, 683 + SPI_DEVICE_CS_CNT_MAX); 684 + return -EOVERFLOW; 685 + } 686 + 687 + for (idx = 0; idx < spi->num_chipselect; idx++) { 674 688 /* Chipselects are numbered 0..max; validate. */ 675 689 cs = spi_get_chipselect(spi, idx); 676 - if (is_valid_cs(cs) && cs >= ctlr->num_chipselect) { 690 + if (cs >= ctlr->num_chipselect) { 677 691 dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx), 678 692 ctlr->num_chipselect); 679 693 return -EINVAL; ··· 691 693 * For example, spi->chip_select[0] != spi->chip_select[1] and so on. 692 694 */ 693 695 if (!spi_controller_is_target(ctlr)) { 694 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 696 + for (idx = 0; idx < spi->num_chipselect; idx++) { 695 697 status = spi_dev_check_cs(dev, spi, idx, spi, idx + 1); 696 698 if (status) 697 699 return status; 698 700 } 699 701 } 702 + 703 + /* Initialize unused logical CS as invalid */ 704 + for (idx = spi->num_chipselect; idx < SPI_DEVICE_CS_CNT_MAX; idx++) 705 + spi_set_chipselect(spi, idx, SPI_INVALID_CS); 700 706 701 707 /* Set the bus ID string */ 702 708 spi_dev_set_name(spi); ··· 723 721 if (ctlr->cs_gpiods) { 724 722 u8 cs; 725 723 726 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 724 + for (idx = 0; idx < spi->num_chipselect; idx++) { 727 725 cs = spi_get_chipselect(spi, idx); 728 - if (is_valid_cs(cs)) 729 - spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]); 726 + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[cs]); 730 727 } 731 728 } 732 729 ··· 778 777 } 779 778 EXPORT_SYMBOL_GPL(spi_add_device); 780 779 781 - static void spi_set_all_cs_unused(struct spi_device *spi) 782 - { 783 - u8 idx; 784 - 785 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) 786 - spi_set_chipselect(spi, idx, SPI_INVALID_CS); 787 - } 788 - 789 780 /** 790 781 * spi_new_device - instantiate one new SPI device 791 782 * @ctlr: Controller to which device is connected ··· 813 820 WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias)); 814 821 815 822 /* Use provided chip-select for proxy device */ 816 - spi_set_all_cs_unused(proxy); 817 823 spi_set_chipselect(proxy, 0, chip->chip_select); 818 824 819 825 proxy->max_speed_hz = chip->max_speed_hz; ··· 1020 1028 1021 1029 /*-------------------------------------------------------------------------*/ 1022 1030 #define spi_for_each_valid_cs(spi, idx) \ 1023 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) \ 1031 + for (idx = 0; idx < spi->num_chipselect; idx++) \ 1024 1032 if (!(spi->cs_index_mask & BIT(idx))) {} else 1025 1033 1026 1034 static inline bool spi_is_last_cs(struct spi_device *spi) ··· 1076 1084 trace_spi_set_cs(spi, activate); 1077 1085 1078 1086 spi->controller->last_cs_index_mask = spi->cs_index_mask; 1079 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) 1080 - spi->controller->last_cs[idx] = enable ? spi_get_chipselect(spi, 0) : SPI_INVALID_CS; 1087 + for (idx = 0; idx < SPI_DEVICE_CS_CNT_MAX; idx++) { 1088 + if (enable && idx < spi->num_chipselect) 1089 + spi->controller->last_cs[idx] = spi_get_chipselect(spi, 0); 1090 + else 1091 + spi->controller->last_cs[idx] = SPI_INVALID_CS; 1092 + } 1081 1093 1082 1094 spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; 1083 1095 if (spi->controller->last_cs_mode_high) ··· 2354 2358 static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, 2355 2359 struct device_node *nc) 2356 2360 { 2357 - u32 value, cs[SPI_CS_CNT_MAX]; 2361 + u32 value, cs[SPI_DEVICE_CS_CNT_MAX]; 2358 2362 int rc, idx; 2359 2363 2360 2364 /* Mode (clock phase/polarity/etc.) */ ··· 2427 2431 return 0; 2428 2432 } 2429 2433 2430 - if (ctlr->num_chipselect > SPI_CS_CNT_MAX) { 2431 - dev_err(&ctlr->dev, "No. of CS is more than max. no. of supported CS\n"); 2432 - return -EINVAL; 2433 - } 2434 - 2435 - spi_set_all_cs_unused(spi); 2436 - 2437 2434 /* Device address */ 2438 2435 rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1, 2439 - SPI_CS_CNT_MAX); 2436 + SPI_DEVICE_CS_CNT_MAX); 2440 2437 if (rc < 0) { 2441 2438 dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n", 2442 2439 nc, rc); 2443 2440 return rc; 2444 2441 } 2445 - if (rc > ctlr->num_chipselect) { 2446 - dev_err(&ctlr->dev, "%pOF has number of CS > ctlr->num_chipselect (%d)\n", 2447 - nc, rc); 2448 - return rc; 2449 - } 2442 + 2450 2443 if ((of_property_present(nc, "parallel-memories")) && 2451 2444 (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) { 2452 2445 dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n"); 2453 2446 return -EINVAL; 2454 2447 } 2448 + 2449 + spi->num_chipselect = rc; 2455 2450 for (idx = 0; idx < rc; idx++) 2456 2451 spi_set_chipselect(spi, idx, cs[idx]); 2457 2452 ··· 2567 2580 strscpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias)); 2568 2581 2569 2582 /* Use provided chip-select for ancillary device */ 2570 - spi_set_all_cs_unused(ancillary); 2571 2583 spi_set_chipselect(ancillary, 0, chip_select); 2572 2584 2573 2585 /* Take over SPI mode/speed from SPI main device */ ··· 2814 2828 return ERR_PTR(-ENOMEM); 2815 2829 } 2816 2830 2817 - spi_set_all_cs_unused(spi); 2818 2831 spi_set_chipselect(spi, 0, lookup.chip_select); 2819 2832 2820 2833 ACPI_COMPANION_SET(&spi->dev, adev); ··· 3313 3328 } 3314 3329 3315 3330 /* Setting last_cs to SPI_INVALID_CS means no chip selected */ 3316 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) 3331 + for (idx = 0; idx < SPI_DEVICE_CS_CNT_MAX; idx++) 3317 3332 ctlr->last_cs[idx] = SPI_INVALID_CS; 3318 3333 3319 3334 status = device_add(&ctlr->dev);

+21

include/linux/adi-axi-common.h

··· 8 8 * https://wiki.analog.com/resources/fpga/docs/hdl/regmap 9 9 */ 10 10 11 + #include <linux/types.h> 12 + 11 13 #ifndef ADI_AXI_COMMON_H_ 12 14 #define ADI_AXI_COMMON_H_ 13 15 ··· 22 20 #define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff) 23 21 #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) 24 22 #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) 23 + 24 + /** 25 + * adi_axi_pcore_ver_gteq() - check if a version is satisfied 26 + * @version: the full version read from the hardware 27 + * @major: the major version to compare against 28 + * @minor: the minor version to compare against 29 + * 30 + * ADI AXI IP Cores use semantic versioning, so this can be used to check for 31 + * feature availability. 32 + * 33 + * Return: true if the version is greater than or equal to the specified 34 + * major and minor version, false otherwise. 35 + */ 36 + static inline bool adi_axi_pcore_ver_gteq(u32 version, u32 major, u32 minor) 37 + { 38 + return ADI_AXI_PCORE_VER_MAJOR(version) > (major) || 39 + (ADI_AXI_PCORE_VER_MAJOR(version) == (major) && 40 + ADI_AXI_PCORE_VER_MINOR(version) >= (minor)); 41 + } 25 42 26 43 #define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) 27 44 #define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff)

+9 -7

include/linux/spi/spi.h

··· 21 21 #include <uapi/linux/spi/spi.h> 22 22 23 23 /* Max no. of CS supported per spi device */ 24 - #define SPI_CS_CNT_MAX 24 24 + #define SPI_DEVICE_CS_CNT_MAX 4 25 25 26 26 struct dma_chan; 27 27 struct software_node; ··· 170 170 * two delays will be added up. 171 171 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives 172 172 * the corresponding physical CS for logical CS i. 173 + * @num_chipselect: Number of physical chipselects used. 173 174 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array 174 175 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines 175 176 * (optional, NULL when not using a GPIO line) ··· 229 228 struct spi_delay cs_hold; 230 229 struct spi_delay cs_inactive; 231 230 232 - u8 chip_select[SPI_CS_CNT_MAX]; 231 + u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; 232 + u8 num_chipselect; 233 233 234 234 /* 235 235 * Bit mask of the chipselect(s) that the driver need to use from ··· 238 236 * multiple chip selects & memories are connected in parallel 239 237 * then more than one bit need to be set in cs_index_mask. 240 238 */ 241 - u32 cs_index_mask : SPI_CS_CNT_MAX; 239 + u32 cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 242 240 243 - struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ 241 + struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio desc */ 244 242 245 243 /* 246 244 * Likely need more hooks for more protocol options affecting how ··· 317 315 { 318 316 u8 idx; 319 317 320 - for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 318 + for (idx = 0; idx < spi->num_chipselect; idx++) { 321 319 if (spi_get_csgpiod(spi, idx)) 322 320 return true; 323 321 } ··· 721 719 bool auto_runtime_pm; 722 720 bool fallback; 723 721 bool last_cs_mode_high; 724 - s8 last_cs[SPI_CS_CNT_MAX]; 725 - u32 last_cs_index_mask : SPI_CS_CNT_MAX; 722 + s8 last_cs[SPI_DEVICE_CS_CNT_MAX]; 723 + u32 last_cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 726 724 struct completion xfer_completion; 727 725 size_t max_dma_len; 728 726

+1

include/uapi/linux/virtio_ids.h

··· 68 68 #define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ 69 69 #define VIRTIO_ID_BT 40 /* virtio bluetooth */ 70 70 #define VIRTIO_ID_GPIO 41 /* virtio gpio */ 71 + #define VIRTIO_ID_SPI 45 /* virtio spi */ 71 72 72 73 /* 73 74 * Virtio Transitional IDs

+181

include/uapi/linux/virtio_spi.h

··· 1 + /* SPDX-License-Identifier: BSD-3-Clause */ 2 + /* 3 + * Copyright (C) 2023 OpenSynergy GmbH 4 + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 + */ 6 + #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H 7 + #define _LINUX_VIRTIO_VIRTIO_SPI_H 8 + 9 + #include <linux/types.h> 10 + #include <linux/virtio_config.h> 11 + #include <linux/virtio_ids.h> 12 + #include <linux/virtio_types.h> 13 + 14 + /* Sample data on trailing clock edge */ 15 + #define VIRTIO_SPI_CPHA _BITUL(0) 16 + /* Clock is high when IDLE */ 17 + #define VIRTIO_SPI_CPOL _BITUL(1) 18 + /* Chip Select is active high */ 19 + #define VIRTIO_SPI_CS_HIGH _BITUL(2) 20 + /* Transmit LSB first */ 21 + #define VIRTIO_SPI_MODE_LSB_FIRST _BITUL(3) 22 + /* Loopback mode */ 23 + #define VIRTIO_SPI_MODE_LOOP _BITUL(4) 24 + 25 + /** 26 + * struct virtio_spi_config - All config fields are read-only for the 27 + * Virtio SPI driver 28 + * @cs_max_number: maximum number of chipselect the host SPI controller 29 + * supports. 30 + * @cs_change_supported: indicates if the host SPI controller supports to toggle 31 + * chipselect after each transfer in one message: 32 + * 0: unsupported, chipselect will be kept in active state throughout the 33 + * message transaction; 34 + * 1: supported. 35 + * Note: Message here contains a sequence of SPI transfers. 36 + * @tx_nbits_supported: indicates the supported number of bit for writing: 37 + * bit 0: DUAL (2-bit transfer), 1 for supported 38 + * bit 1: QUAD (4-bit transfer), 1 for supported 39 + * bit 2: OCTAL (8-bit transfer), 1 for supported 40 + * other bits are reserved as 0, 1-bit transfer is always supported. 41 + * @rx_nbits_supported: indicates the supported number of bit for reading: 42 + * bit 0: DUAL (2-bit transfer), 1 for supported 43 + * bit 1: QUAD (4-bit transfer), 1 for supported 44 + * bit 2: OCTAL (8-bit transfer), 1 for supported 45 + * other bits are reserved as 0, 1-bit transfer is always supported. 46 + * @bits_per_word_mask: mask indicating which values of bits_per_word are 47 + * supported. If not set, no limitation for bits_per_word. 48 + * @mode_func_supported: indicates the following features are supported or not: 49 + * bit 0-1: CPHA feature 50 + * 0b00: invalid, should support as least one CPHA setting 51 + * 0b01: supports CPHA=0 only 52 + * 0b10: supports CPHA=1 only 53 + * 0b11: supports CPHA=0 and CPHA=1. 54 + * bit 2-3: CPOL feature 55 + * 0b00: invalid, should support as least one CPOL setting 56 + * 0b01: supports CPOL=0 only 57 + * 0b10: supports CPOL=1 only 58 + * 0b11: supports CPOL=0 and CPOL=1. 59 + * bit 4: chipselect active high feature, 0 for unsupported and 1 for 60 + * supported, chipselect active low is supported by default. 61 + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, 62 + * MSB first is supported by default. 63 + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, 64 + * normal mode is supported by default. 65 + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no 66 + * limitation for transfer speed. 67 + * @max_word_delay_ns: the maximum word delay supported, in nanoseconds. 68 + * A value of 0 indicates that word delay is unsupported. 69 + * Each transfer may consist of a sequence of words. 70 + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted, 71 + * in ns unit, 0 means delay is not supported to introduce after chipselect is 72 + * asserted. 73 + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted, 74 + * in ns unit, 0 means delay is not supported to introduce before chipselect 75 + * is deasserted. 76 + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted, 77 + * in ns unit, 0 means delay is not supported to introduce after chipselect is 78 + * deasserted. 79 + */ 80 + struct virtio_spi_config { 81 + __u8 cs_max_number; 82 + __u8 cs_change_supported; 83 + #define VIRTIO_SPI_RX_TX_SUPPORT_DUAL _BITUL(0) 84 + #define VIRTIO_SPI_RX_TX_SUPPORT_QUAD _BITUL(1) 85 + #define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL _BITUL(2) 86 + __u8 tx_nbits_supported; 87 + __u8 rx_nbits_supported; 88 + __le32 bits_per_word_mask; 89 + #define VIRTIO_SPI_MF_SUPPORT_CPHA_0 _BITUL(0) 90 + #define VIRTIO_SPI_MF_SUPPORT_CPHA_1 _BITUL(1) 91 + #define VIRTIO_SPI_MF_SUPPORT_CPOL_0 _BITUL(2) 92 + #define VIRTIO_SPI_MF_SUPPORT_CPOL_1 _BITUL(3) 93 + #define VIRTIO_SPI_MF_SUPPORT_CS_HIGH _BITUL(4) 94 + #define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST _BITUL(5) 95 + #define VIRTIO_SPI_MF_SUPPORT_LOOPBACK _BITUL(6) 96 + __le32 mode_func_supported; 97 + __le32 max_freq_hz; 98 + __le32 max_word_delay_ns; 99 + __le32 max_cs_setup_ns; 100 + __le32 max_cs_hold_ns; 101 + __le32 max_cs_inactive_ns; 102 + }; 103 + 104 + /** 105 + * struct spi_transfer_head - virtio SPI transfer descriptor 106 + * @chip_select_id: chipselect index the SPI transfer used. 107 + * @bits_per_word: the number of bits in each SPI transfer word. 108 + * @cs_change: whether to deselect device after finishing this transfer 109 + * before starting the next transfer, 0 means cs keep asserted and 110 + * 1 means cs deasserted then asserted again. 111 + * @tx_nbits: bus width for write transfer. 112 + * 0,1: bus width is 1, also known as SINGLE 113 + * 2 : bus width is 2, also known as DUAL 114 + * 4 : bus width is 4, also known as QUAD 115 + * 8 : bus width is 8, also known as OCTAL 116 + * other values are invalid. 117 + * @rx_nbits: bus width for read transfer. 118 + * 0,1: bus width is 1, also known as SINGLE 119 + * 2 : bus width is 2, also known as DUAL 120 + * 4 : bus width is 4, also known as QUAD 121 + * 8 : bus width is 8, also known as OCTAL 122 + * other values are invalid. 123 + * @reserved: for future use. 124 + * @mode: SPI transfer mode. 125 + * bit 0: CPHA, determines the timing (i.e. phase) of the data 126 + * bits relative to the clock pulses.For CPHA=0, the 127 + * "out" side changes the data on the trailing edge of the 128 + * preceding clock cycle, while the "in" side captures the data 129 + * on (or shortly after) the leading edge of the clock cycle. 130 + * For CPHA=1, the "out" side changes the data on the leading 131 + * edge of the current clock cycle, while the "in" side 132 + * captures the data on (or shortly after) the trailing edge of 133 + * the clock cycle. 134 + * bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a 135 + * clock which idles at 0, and each cycle consists of a pulse 136 + * of 1. CPOL=1 is a clock which idles at 1, and each cycle 137 + * consists of a pulse of 0. 138 + * bit 2: CS_HIGH, if 1, chip select active high, else active low. 139 + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB 140 + * first, else LSB first. 141 + * bit 4: LOOP, loopback mode. 142 + * @freq: the transfer speed in Hz. 143 + * @word_delay_ns: delay to be inserted between consecutive words of a 144 + * transfer, in ns unit. 145 + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns 146 + * unit. 147 + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted 148 + * for each transfer, in ns unit. 149 + * @cs_change_delay_inactive_ns: delay to be introduced after CS is 150 + * deasserted and before next asserted, in ns unit. 151 + */ 152 + struct spi_transfer_head { 153 + __u8 chip_select_id; 154 + __u8 bits_per_word; 155 + __u8 cs_change; 156 + __u8 tx_nbits; 157 + __u8 rx_nbits; 158 + __u8 reserved[3]; 159 + __le32 mode; 160 + __le32 freq; 161 + __le32 word_delay_ns; 162 + __le32 cs_setup_ns; 163 + __le32 cs_delay_hold_ns; 164 + __le32 cs_change_delay_inactive_ns; 165 + }; 166 + 167 + /** 168 + * struct spi_transfer_result - virtio SPI transfer result 169 + * @result: Transfer result code. 170 + * VIRTIO_SPI_TRANS_OK: Transfer successful. 171 + * VIRTIO_SPI_PARAM_ERR: Parameter error. 172 + * VIRTIO_SPI_TRANS_ERR: Transfer error. 173 + */ 174 + struct spi_transfer_result { 175 + #define VIRTIO_SPI_TRANS_OK 0 176 + #define VIRTIO_SPI_PARAM_ERR 1 177 + #define VIRTIO_SPI_TRANS_ERR 2 178 + __u8 result; 179 + }; 180 + 181 + #endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */

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