Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-04-05' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Pretty quiet week, just some amdgpu and i915 fixes.
i915:
- deadlock fix
- gvt fixes
amdgpu:
- PCIE dpm feature fix
- Powerplay fixes"
* tag 'drm-fixes-2019-04-05' of git://anongit.freedesktop.org/drm/drm:
drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug
drm/i915/gvt: Correct the calculation of plane size
drm/amdgpu: remove unnecessary rlc reset function on gfx9
drm/i915: Always backoff after a drm_modeset_lock() deadlock
drm/i915/gvt: do not let pin count of shadow mm go negative
drm/i915/gvt: do not deliver a workload if its creation fails
drm/amd/display: VBIOS can't be light up HDMI when restart system
drm/amd/powerplay: fix possible hang with 3+ 4K monitors
drm/amd/powerplay: correct data type to avoid overflow
drm/amd/powerplay: add ECC feature bit
drm/amd/amdgpu: fix PCIe dpm feature issue (v3)
+44
-17
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
3625
3625
struct pci_dev *pdev = adev->pdev;
3626
3626
enum pci_bus_speed cur_speed;
3627
3627
enum pcie_link_width cur_width;
3628
+
u32 ret = 1;
3628
3629
3629
3630
*speed = PCI_SPEED_UNKNOWN;
3630
3631
*width = PCIE_LNK_WIDTH_UNKNOWN;
···
3633
3632
while (pdev) {
3634
3633
cur_speed = pcie_get_speed_cap(pdev);
3635
3634
cur_width = pcie_get_width_cap(pdev);
3635
+
ret = pcie_bandwidth_available(adev->pdev, NULL,
3636
+
NULL, &cur_width);
3637
+
if (!ret)
3638
+
cur_width = PCIE_LNK_WIDTH_RESRV;
3636
3639
3637
3640
if (cur_speed != PCI_SPEED_UNKNOWN) {
3638
3641
if (*speed == PCI_SPEED_UNKNOWN)
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+6
drivers/gpu/drm/amd/display/dc/core/dc_link.c
+6
drivers/gpu/drm/amd/display/dc/core/dc_link.c
···
2660
2660
void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2661
2661
{
2662
2662
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2663
+
struct dc_stream_state *stream = pipe_ctx->stream;
2663
2664
2664
2665
core_dc->hwss.blank_stream(pipe_ctx);
2665
2666
2666
2667
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2667
2668
deallocate_mst_payload(pipe_ctx);
2669
+
2670
+
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2671
+
dal_ddc_service_write_scdc_data(
2672
+
stream->link->ddc, 0,
2673
+
stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2668
2674
2669
2675
core_dc->hwss.disable_stream(pipe_ctx, option);
2670
2676
+18
-2
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+18
-2
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
···
91
91
* MP0CLK DS
92
92
*/
93
93
data->registry_data.disallowed_features = 0xE0041C00;
94
+
/* ECC feature should be disabled on old SMUs */
95
+
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
96
+
hwmgr->smu_version = smum_get_argument(hwmgr);
97
+
if (hwmgr->smu_version < 0x282100)
98
+
data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
99
+
94
100
data->registry_data.od_state_in_dc_support = 0;
95
101
data->registry_data.thermal_support = 1;
96
102
data->registry_data.skip_baco_hardware = 0;
···
363
357
data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
364
358
data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
365
359
data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
360
+
data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
366
361
367
362
for (i = 0; i < GNLD_FEATURES_MAX; i++) {
368
363
data->smu_features[i].smu_feature_bitmap =
···
3027
3020
"FCLK_DS",
3028
3021
"MP1CLK_DS",
3029
3022
"MP0CLK_DS",
3030
-
"XGMI"};
3023
+
"XGMI",
3024
+
"ECC"};
3031
3025
static const char *output_title[] = {
3032
3026
"FEATURES",
3033
3027
"BITMASK",
···
3470
3462
struct vega20_single_dpm_table *dpm_table;
3471
3463
bool vblank_too_short = false;
3472
3464
bool disable_mclk_switching;
3465
+
bool disable_fclk_switching;
3473
3466
uint32_t i, latency;
3474
3467
3475
3468
disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
···
3546
3537
if (hwmgr->display_config->nb_pstate_switch_disable)
3547
3538
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3548
3539
3540
+
if ((disable_mclk_switching &&
3541
+
(dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
3542
+
hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
3543
+
disable_fclk_switching = true;
3544
+
else
3545
+
disable_fclk_switching = false;
3546
+
3549
3547
/* fclk */
3550
3548
dpm_table = &(data->dpm_table.fclk_table);
3551
3549
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3552
3550
dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3553
3551
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3554
3552
dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3555
-
if (hwmgr->display_config->nb_pstate_switch_disable)
3553
+
if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
3556
3554
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3557
3555
3558
3556
/* vclk */
+1
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+1
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+3
-2
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+3
-2
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
···
99
99
#define FEATURE_DS_MP1CLK_BIT 30
100
100
#define FEATURE_DS_MP0CLK_BIT 31
101
101
#define FEATURE_XGMI_BIT 32
102
-
#define FEATURE_SPARE_33_BIT 33
102
+
#define FEATURE_ECC_BIT 33
103
103
#define FEATURE_SPARE_34_BIT 34
104
104
#define FEATURE_SPARE_35_BIT 35
105
105
#define FEATURE_SPARE_36_BIT 36
···
165
165
#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
166
166
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
167
167
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
168
-
#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
168
+
#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT )
169
+
#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
169
170
170
171
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
171
172
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
+1
-1
drivers/gpu/drm/i915/gvt/display.c
+1
-1
drivers/gpu/drm/i915/gvt/display.c
+2
-6
drivers/gpu/drm/i915/gvt/dmabuf.c
+2
-6
drivers/gpu/drm/i915/gvt/dmabuf.c
···
238
238
default:
239
239
gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
240
240
}
241
-
242
-
info->size = (((p.stride * p.height * p.bpp) / 8) +
243
-
(PAGE_SIZE - 1)) >> PAGE_SHIFT;
244
241
} else if (plane_id == DRM_PLANE_TYPE_CURSOR) {
245
242
ret = intel_vgpu_decode_cursor_plane(vgpu, &c);
246
243
if (ret)
···
259
262
info->x_hot = UINT_MAX;
260
263
info->y_hot = UINT_MAX;
261
264
}
262
-
263
-
info->size = (((info->stride * c.height * c.bpp) / 8)
264
-
+ (PAGE_SIZE - 1)) >> PAGE_SHIFT;
265
265
} else {
266
266
gvt_vgpu_err("invalid plane id:%d\n", plane_id);
267
267
return -EINVAL;
268
268
}
269
269
270
+
info->size = (info->stride * info->height + PAGE_SIZE - 1)
271
+
>> PAGE_SHIFT;
270
272
if (info->size == 0) {
271
273
gvt_vgpu_err("fb size is zero\n");
272
274
return -EINVAL;
+1
-1
drivers/gpu/drm/i915/gvt/gtt.c
+1
-1
drivers/gpu/drm/i915/gvt/gtt.c
+3
-2
drivers/gpu/drm/i915/gvt/scheduler.c
+3
-2
drivers/gpu/drm/i915/gvt/scheduler.c
···
1486
1486
intel_runtime_pm_put_unchecked(dev_priv);
1487
1487
}
1488
1488
1489
-
if (ret && (vgpu_is_vm_unhealthy(ret))) {
1490
-
enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1489
+
if (ret) {
1490
+
if (vgpu_is_vm_unhealthy(ret))
1491
+
enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1491
1492
intel_vgpu_destroy_workload(workload);
1492
1493
return ERR_PTR(ret);
1493
1494
}
+4
-1
drivers/gpu/drm/i915/i915_debugfs.c
+4
-1
drivers/gpu/drm/i915/i915_debugfs.c
···
4830
4830
ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4831
4831
&ctx);
4832
4832
if (ret) {
4833
-
ret = -EINTR;
4833
+
if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
4834
+
try_again = true;
4835
+
continue;
4836
+
}
4834
4837
break;
4835
4838
}
4836
4839
crtc = connector->state->crtc;