tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-05-10' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly drm fixes, bit bigger than last week, but overall amdgpu/xe
with some ivpu bits and a random few fixes, and dropping the
ttm_backup struct which wrapped struct file and was recently
frowned at.

drm:
- Fix overflow when generating wedged event

ttm:
- Fix documentation
- Remove struct ttm_backup

panel:
- simple: Fix timings for AUO G101EVN010

amdgpu:
- DC FP fixes
- Freesync fix
- DMUB AUX fixes
- VCN fix
- Hibernation fixes
- HDP fixes

xe:
- Prevent PF queue overflow
- Hold all forcewake during mocs test
- Remove GSC flush on reset path
- Fix forcewake put on error path
- Fix runtime warning when building without svm

i915:
- Fix oops on resume after disconnecting DP MST sinks during suspend
- Fix SPLC num_waiters refcounting

ivpu:
- Increase timeouts
- Fix deadlock in cmdq ioctl
- Unlock mutices in correct order

v3d:
- Avoid memory leak in job handling"

* tag 'drm-fixes-2025-05-10' of https://gitlab.freedesktop.org/drm/kernel: (32 commits)
drm/i915/dp: Fix determining SST/MST mode during MTP TU state computation
drm/xe: Add config control for svm flush work
drm/xe: Release force wake first then runtime power
drm/xe/gsc: do not flush the GSC worker from the reset path
drm/xe/tests/mocs: Hold XE_FORCEWAKE_ALL for LNCF regs
drm/xe: Add page queue multiplier
drm/amdgpu/hdp7: use memcfg register to post the write for HDP flush
drm/amdgpu/hdp6: use memcfg register to post the write for HDP flush
drm/amdgpu/hdp5.2: use memcfg register to post the write for HDP flush
drm/amdgpu/hdp5: use memcfg register to post the write for HDP flush
drm/amdgpu/hdp4: use memcfg register to post the write for HDP flush
drm/amdgpu: fix pm notifier handling
Revert "drm/amd: Stop evicting resources on APUs in suspend"
drm/amdgpu/vcn: using separate VCN1_AON_SOC offset
drm/amd/display: Fix wrong handling for AUX_DEFER case
drm/amd/display: Copy AUX read reply data whenever length > 0
drm/amd/display: Remove incorrect checking in dmub aux handler
drm/amd/display: Fix the checking condition in dmub aux handling
drm/amd/display: Shift DMUB AUX reply command if necessary
drm/amd/display: Call FP Protect Before Mode Programming/Mode Support
...

Linus Torvalds ea34704d 50358c25

+285 -195
+1 -1
drivers/accel/ivpu/ivpu_hw.c
··· 119 119 else 120 120 vdev->timeout.autosuspend = 100; 121 121 vdev->timeout.d0i3_entry_msg = 5; 122 - vdev->timeout.state_dump_msg = 10; 122 + vdev->timeout.state_dump_msg = 100; 123 123 } 124 124 } 125 125
+25 -10
drivers/accel/ivpu/ivpu_job.c
··· 681 681 err_erase_xa: 682 682 xa_erase(&vdev->submitted_jobs_xa, job->job_id); 683 683 err_unlock: 684 - mutex_unlock(&vdev->submitted_jobs_lock); 685 684 mutex_unlock(&file_priv->lock); 685 + mutex_unlock(&vdev->submitted_jobs_lock); 686 686 ivpu_rpm_put(vdev); 687 687 return ret; 688 688 } ··· 874 874 int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 875 875 { 876 876 struct ivpu_file_priv *file_priv = file->driver_priv; 877 + struct ivpu_device *vdev = file_priv->vdev; 877 878 struct drm_ivpu_cmdq_create *args = data; 878 879 struct ivpu_cmdq *cmdq; 880 + int ret; 879 881 880 - if (!ivpu_is_capable(file_priv->vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) 882 + if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) 881 883 return -ENODEV; 882 884 883 885 if (args->priority > DRM_IVPU_JOB_PRIORITY_REALTIME) 884 886 return -EINVAL; 887 + 888 + ret = ivpu_rpm_get(vdev); 889 + if (ret < 0) 890 + return ret; 885 891 886 892 mutex_lock(&file_priv->lock); 887 893 ··· 896 890 args->cmdq_id = cmdq->id; 897 891 898 892 mutex_unlock(&file_priv->lock); 893 + 894 + ivpu_rpm_put(vdev); 899 895 900 896 return cmdq ? 0 : -ENOMEM; 901 897 } ··· 908 900 struct ivpu_device *vdev = file_priv->vdev; 909 901 struct drm_ivpu_cmdq_destroy *args = data; 910 902 struct ivpu_cmdq *cmdq; 911 - u32 cmdq_id; 903 + u32 cmdq_id = 0; 912 904 int ret; 913 905 914 906 if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) 915 907 return -ENODEV; 908 + 909 + ret = ivpu_rpm_get(vdev); 910 + if (ret < 0) 911 + return ret; 916 912 917 913 mutex_lock(&file_priv->lock); 918 914 919 915 cmdq = xa_load(&file_priv->cmdq_xa, args->cmdq_id); 920 916 if (!cmdq || cmdq->is_legacy) { 921 917 ret = -ENOENT; 922 - goto err_unlock; 918 + } else { 919 + cmdq_id = cmdq->id; 920 + ivpu_cmdq_destroy(file_priv, cmdq); 921 + ret = 0; 923 922 } 924 923 925 - cmdq_id = cmdq->id; 926 - ivpu_cmdq_destroy(file_priv, cmdq); 927 924 mutex_unlock(&file_priv->lock); 928 - ivpu_cmdq_abort_all_jobs(vdev, file_priv->ctx.id, cmdq_id); 929 - return 0; 930 925 931 - err_unlock: 932 - mutex_unlock(&file_priv->lock); 926 + /* Abort any pending jobs only if cmdq was destroyed */ 927 + if (!ret) 928 + ivpu_cmdq_abort_all_jobs(vdev, file_priv->ctx.id, cmdq_id); 929 + 930 + ivpu_rpm_put(vdev); 931 + 933 932 return ret; 934 933 } 935 934
-2
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1614 1614 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1615 1615 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1616 1616 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1617 - void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1618 1617 #else 1619 1618 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1620 1619 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1621 - static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1622 1620 #endif 1623 1621 1624 1622 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
-18
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
··· 1533 1533 #endif /* CONFIG_AMD_PMC */ 1534 1534 } 1535 1535 1536 - /** 1537 - * amdgpu_choose_low_power_state 1538 - * 1539 - * @adev: amdgpu_device_pointer 1540 - * 1541 - * Choose the target low power state for the GPU 1542 - */ 1543 - void amdgpu_choose_low_power_state(struct amdgpu_device *adev) 1544 - { 1545 - if (adev->in_runpm) 1546 - return; 1547 - 1548 - if (amdgpu_acpi_is_s0ix_active(adev)) 1549 - adev->in_s0ix = true; 1550 - else if (amdgpu_acpi_is_s3_active(adev)) 1551 - adev->in_s3 = true; 1552 - } 1553 - 1554 1536 #endif /* CONFIG_SUSPEND */
+7 -22
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 4907 4907 * @data: data 4908 4908 * 4909 4909 * This function is called when the system is about to suspend or hibernate. 4910 - * It is used to evict resources from the device before the system goes to 4911 - * sleep while there is still access to swap. 4910 + * It is used to set the appropriate flags so that eviction can be optimized 4911 + * in the pm prepare callback. 4912 4912 */ 4913 4913 static int amdgpu_device_pm_notifier(struct notifier_block *nb, unsigned long mode, 4914 4914 void *data) 4915 4915 { 4916 4916 struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, pm_nb); 4917 - int r; 4918 4917 4919 4918 switch (mode) { 4920 4919 case PM_HIBERNATION_PREPARE: 4921 4920 adev->in_s4 = true; 4922 - fallthrough; 4923 - case PM_SUSPEND_PREPARE: 4924 - r = amdgpu_device_evict_resources(adev); 4925 - /* 4926 - * This is considered non-fatal at this time because 4927 - * amdgpu_device_prepare() will also fatally evict resources. 4928 - * See https://gitlab.freedesktop.org/drm/amd/-/issues/3781 4929 - */ 4930 - if (r) 4931 - drm_warn(adev_to_drm(adev), "Failed to evict resources, freeze active processes if problems occur: %d\n", r); 4921 + break; 4922 + case PM_POST_HIBERNATION: 4923 + adev->in_s4 = false; 4932 4924 break; 4933 4925 } 4934 4926 ··· 4941 4949 struct amdgpu_device *adev = drm_to_adev(dev); 4942 4950 int i, r; 4943 4951 4944 - amdgpu_choose_low_power_state(adev); 4945 - 4946 4952 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 4947 4953 return 0; 4948 4954 4949 4955 /* Evict the majority of BOs before starting suspend sequence */ 4950 4956 r = amdgpu_device_evict_resources(adev); 4951 4957 if (r) 4952 - goto unprepare; 4958 + return r; 4953 4959 4954 4960 flush_delayed_work(&adev->gfx.gfx_off_delay_work); 4955 4961 ··· 4958 4968 continue; 4959 4969 r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]); 4960 4970 if (r) 4961 - goto unprepare; 4971 + return r; 4962 4972 } 4963 4973 4964 4974 return 0; 4965 - 4966 - unprepare: 4967 - adev->in_s0ix = adev->in_s3 = adev->in_s4 = false; 4968 - 4969 - return r; 4970 4975 } 4971 4976 4972 4977 /**
+1 -9
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2615 2615 static int amdgpu_pmops_thaw(struct device *dev) 2616 2616 { 2617 2617 struct drm_device *drm_dev = dev_get_drvdata(dev); 2618 - struct amdgpu_device *adev = drm_to_adev(drm_dev); 2619 - int r; 2620 2618 2621 - r = amdgpu_device_resume(drm_dev, true); 2622 - adev->in_s4 = false; 2623 - 2624 - return r; 2619 + return amdgpu_device_resume(drm_dev, true); 2625 2620 } 2626 2621 2627 2622 static int amdgpu_pmops_poweroff(struct device *dev) ··· 2629 2634 static int amdgpu_pmops_restore(struct device *dev) 2630 2635 { 2631 2636 struct drm_device *drm_dev = dev_get_drvdata(dev); 2632 - struct amdgpu_device *adev = drm_to_adev(drm_dev); 2633 - 2634 - adev->in_s4 = false; 2635 2637 2636 2638 return amdgpu_device_resume(drm_dev, true); 2637 2639 }
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
··· 66 66 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 67 67 68 68 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800 69 - #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 70 69 #define VCN_VID_IP_ADDRESS_2_0 0x0 71 70 #define VCN_AON_IP_ADDRESS_2_0 0x30000 72 71
+6 -1
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
··· 41 41 { 42 42 if (!ring || !ring->funcs->emit_wreg) { 43 43 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 44 - RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 44 + /* We just need to read back a register to post the write. 45 + * Reading back the remapped register causes problems on 46 + * some platforms so just read back the memory size register. 47 + */ 48 + if (adev->nbio.funcs->get_memsize) 49 + adev->nbio.funcs->get_memsize(adev); 45 50 } else { 46 51 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 47 52 }
+6 -1
drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
··· 32 32 { 33 33 if (!ring || !ring->funcs->emit_wreg) { 34 34 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 35 - RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 35 + /* We just need to read back a register to post the write. 36 + * Reading back the remapped register causes problems on 37 + * some platforms so just read back the memory size register. 38 + */ 39 + if (adev->nbio.funcs->get_memsize) 40 + adev->nbio.funcs->get_memsize(adev); 36 41 } else { 37 42 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 43 }
+11 -1
drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c
··· 33 33 if (!ring || !ring->funcs->emit_wreg) { 34 34 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 35 35 0); 36 - RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 36 + if (amdgpu_sriov_vf(adev)) { 37 + /* this is fine because SR_IOV doesn't remap the register */ 38 + RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 39 + } else { 40 + /* We just need to read back a register to post the write. 41 + * Reading back the remapped register causes problems on 42 + * some platforms so just read back the memory size register. 43 + */ 44 + if (adev->nbio.funcs->get_memsize) 45 + adev->nbio.funcs->get_memsize(adev); 46 + } 37 47 } else { 38 48 amdgpu_ring_emit_wreg(ring, 39 49 (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
+6 -1
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
··· 35 35 { 36 36 if (!ring || !ring->funcs->emit_wreg) { 37 37 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 - RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 38 + /* We just need to read back a register to post the write. 39 + * Reading back the remapped register causes problems on 40 + * some platforms so just read back the memory size register. 41 + */ 42 + if (adev->nbio.funcs->get_memsize) 43 + adev->nbio.funcs->get_memsize(adev); 39 44 } else { 40 45 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 41 46 }
+6 -1
drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
··· 32 32 { 33 33 if (!ring || !ring->funcs->emit_wreg) { 34 34 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 35 - RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 35 + /* We just need to read back a register to post the write. 36 + * Reading back the remapped register causes problems on 37 + * some platforms so just read back the memory size register. 38 + */ 39 + if (adev->nbio.funcs->get_memsize) 40 + adev->nbio.funcs->get_memsize(adev); 36 41 } else { 37 42 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 43 }
+1
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
··· 39 39 40 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 + #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 42 43 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 44 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
+1
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 39 39 40 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 + #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 42 43 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 44 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
+1
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
··· 40 40 41 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 + #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 43 44 44 45 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45 46 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
+3 -1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
··· 46 46 47 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 + #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 50 51 #define VCN_HARVEST_MMSCH 0 51 52 ··· 615 614 616 615 /* VCN global tiling registers */ 617 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 618 - VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 617 + VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 618 + adev->gfx.config.gb_addr_config, 0, indirect); 619 619 } 620 620 621 621 /**
+1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
··· 45 45 46 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 + #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 48 49 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 50 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
··· 46 46 47 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000) 49 + #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000) 49 50 50 51 #define VCN_HARVEST_MMSCH 0 51 52
+2 -1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
··· 533 533 534 534 /* VCN global tiling registers */ 535 535 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( 536 - VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 536 + VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), 537 + adev->gfx.config.gb_addr_config, 0, indirect); 537 538 538 539 return; 539 540 }
+17 -19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 673 673 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 674 674 675 675 if (acrtc->dm_irq_params.stream && 676 - acrtc->dm_irq_params.vrr_params.supported && 677 - acrtc->dm_irq_params.freesync_config.state == 678 - VRR_STATE_ACTIVE_VARIABLE) { 676 + acrtc->dm_irq_params.vrr_params.supported) { 677 + bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; 678 + bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; 679 + bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; 680 + 679 681 mod_freesync_handle_v_update(adev->dm.freesync_module, 680 682 acrtc->dm_irq_params.stream, 681 683 &acrtc->dm_irq_params.vrr_params); 682 684 683 - dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 684 - &acrtc->dm_irq_params.vrr_params.adjust); 685 + /* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */ 686 + if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { 687 + dc_stream_adjust_vmin_vmax(adev->dm.dc, 688 + acrtc->dm_irq_params.stream, 689 + &acrtc->dm_irq_params.vrr_params.adjust); 690 + } 685 691 } 686 692 687 693 /* ··· 12749 12743 * Transient states before tunneling is enabled could 12750 12744 * lead to this error. We can ignore this for now. 12751 12745 */ 12752 - if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 12746 + if (p_notify->result == AUX_RET_ERROR_PROTOCOL_ERROR) { 12753 12747 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 12754 12748 payload->address, payload->length, 12755 12749 p_notify->result); ··· 12758 12752 goto out; 12759 12753 } 12760 12754 12755 + payload->reply[0] = adev->dm.dmub_notify->aux_reply.command & 0xF; 12756 + if (adev->dm.dmub_notify->aux_reply.command & 0xF0) 12757 + /* The reply is stored in the top nibble of the command. */ 12758 + payload->reply[0] = (adev->dm.dmub_notify->aux_reply.command >> 4) & 0xF; 12761 12759 12762 - payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 12763 - if (!payload->write && p_notify->aux_reply.length && 12764 - (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 12765 - 12766 - if (payload->length != p_notify->aux_reply.length) { 12767 - DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 12768 - p_notify->aux_reply.length, 12769 - payload->address, payload->length); 12770 - *operation_result = AUX_RET_ERROR_INVALID_REPLY; 12771 - goto out; 12772 - } 12773 - 12760 + if (!payload->write && p_notify->aux_reply.length) 12774 12761 memcpy(payload->data, p_notify->aux_reply.data, 12775 12762 p_notify->aux_reply.length); 12776 - } 12777 12763 12778 12764 /* success */ 12779 12765 ret = p_notify->aux_reply.length;
+24 -4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 51 51 52 52 #define PEAK_FACTOR_X1000 1006 53 53 54 + /* 55 + * This function handles both native AUX and I2C-Over-AUX transactions. 56 + */ 54 57 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 55 58 struct drm_dp_aux_msg *msg) 56 59 { ··· 90 87 if (adev->dm.aux_hpd_discon_quirk) { 91 88 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 92 89 operation_result == AUX_RET_ERROR_HPD_DISCON) { 93 - result = 0; 90 + result = msg->size; 94 91 operation_result = AUX_RET_SUCCESS; 95 92 } 96 93 } 97 94 98 - if (payload.write && result >= 0) 99 - result = msg->size; 95 + /* 96 + * result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER 97 + */ 98 + if (payload.write && result >= 0) { 99 + if (result) { 100 + /*one byte indicating partially written bytes. Force 0 to retry*/ 101 + drm_info(adev_to_drm(adev), "amdgpu: AUX partially written\n"); 102 + result = 0; 103 + } else if (!payload.reply[0]) 104 + /*I2C_ACK|AUX_ACK*/ 105 + result = msg->size; 106 + } 100 107 101 - if (result < 0) 108 + if (result < 0) { 102 109 switch (operation_result) { 103 110 case AUX_RET_SUCCESS: 104 111 break; ··· 126 113 result = -ETIMEDOUT; 127 114 break; 128 115 } 116 + 117 + drm_info(adev_to_drm(adev), "amdgpu: DP AUX transfer fail:%d\n", operation_result); 118 + } 119 + 120 + if (payload.reply[0]) 121 + drm_info(adev_to_drm(adev), "amdgpu: AUX reply command not ACK: 0x%02x.", 122 + payload.reply[0]); 129 123 130 124 return result; 131 125 }
+4 -4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
··· 234 234 if (!result) 235 235 return false; 236 236 237 + DC_FP_START(); 237 238 result = dml2_build_mode_programming(mode_programming); 239 + DC_FP_END(); 238 240 if (!result) 239 241 return false; 240 242 ··· 279 277 mode_support->dml2_instance = dml_init->dml2_instance; 280 278 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 281 279 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; 280 + DC_FP_START(); 282 281 is_supported = dml2_check_mode_supported(mode_support); 282 + DC_FP_END(); 283 283 if (!is_supported) 284 284 return false; 285 285 ··· 292 288 { 293 289 bool out = false; 294 290 295 - DC_FP_START(); 296 - 297 291 /* Use dml_validate_only for fast_validate path */ 298 292 if (fast_validate) 299 293 out = dml21_check_mode_support(in_dc, context, dml_ctx); 300 294 else 301 295 out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); 302 - 303 - DC_FP_END(); 304 296 305 297 return out; 306 298 }
+5 -9
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
··· 973 973 } 974 974 } 975 975 976 - static void get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context, struct scaler_data *out) 976 + static struct scaler_data *get_scaler_data_for_plane( 977 + const struct dc_plane_state *in, 978 + struct dc_state *context) 977 979 { 978 980 int i; 979 981 struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe; ··· 996 994 } 997 995 998 996 ASSERT(i < MAX_PIPES); 999 - memcpy(out, &temp_pipe->plane_res.scl_data, sizeof(*out)); 997 + return &temp_pipe->plane_res.scl_data; 1000 998 } 1001 999 1002 1000 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, ··· 1059 1057 const struct dc_plane_state *in, struct dc_state *context, 1060 1058 const struct soc_bounding_box_st *soc) 1061 1059 { 1062 - struct scaler_data *scaler_data = kzalloc(sizeof(*scaler_data), GFP_KERNEL); 1063 - if (!scaler_data) 1064 - return; 1065 - 1066 - get_scaler_data_for_plane(in, context, scaler_data); 1060 + struct scaler_data *scaler_data = get_scaler_data_for_plane(in, context); 1067 1061 1068 1062 out->CursorBPP[location] = dml_cur_32bit; 1069 1063 out->CursorWidth[location] = 256; ··· 1124 1126 out->DynamicMetadataTransmittedBytes[location] = 0; 1125 1127 1126 1128 out->NumberOfCursors[location] = 1; 1127 - 1128 - kfree(scaler_data); 1129 1129 } 1130 1130 1131 1131 static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2,
-6
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
··· 2114 2114 #define REG_STRUCT dccg_regs 2115 2115 dccg_regs_init(); 2116 2116 2117 - DC_FP_START(); 2118 - 2119 2117 ctx->dc_bios->regs = &bios_regs; 2120 2118 2121 2119 pool->base.res_cap = &res_cap_dcn32; ··· 2499 2501 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0)) 2500 2502 dc->config.sdpif_request_limit_words_per_umc = 16; 2501 2503 2502 - DC_FP_END(); 2503 - 2504 2504 return true; 2505 2505 2506 2506 create_fail: 2507 - 2508 - DC_FP_END(); 2509 2507 2510 2508 dcn32_resource_destruct(pool); 2511 2509
+1 -1
drivers/gpu/drm/drm_drv.c
··· 549 549 if (drm_WARN_ONCE(dev, !recovery, "invalid recovery method %u\n", opt)) 550 550 break; 551 551 552 - len += scnprintf(event_string + len, sizeof(event_string), "%s,", recovery); 552 + len += scnprintf(event_string + len, sizeof(event_string) - len, "%s,", recovery); 553 553 } 554 554 555 555 if (recovery)
+1 -1
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 242 242 to_intel_connector(conn_state->connector); 243 243 const struct drm_display_mode *adjusted_mode = 244 244 &crtc_state->hw.adjusted_mode; 245 - bool is_mst = intel_dp->is_mst; 245 + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 246 246 int bpp_x16, slots = -EINVAL; 247 247 int dsc_slice_count = 0; 248 248 int max_dpt_bpp_x16;
+11 -3
drivers/gpu/drm/i915/gt/intel_rps.c
··· 1001 1001 if (rps_uses_slpc(rps)) { 1002 1002 slpc = rps_to_slpc(rps); 1003 1003 1004 + /* Don't decrement num_waiters for req where increment was skipped */ 1005 + if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) 1006 + return; 1007 + 1004 1008 intel_guc_slpc_dec_waiters(slpc); 1005 1009 } else { 1006 1010 atomic_dec(&rps->num_waiters); ··· 1033 1029 if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) 1034 1030 return; 1035 1031 1036 - if (slpc->min_freq_softlimit >= slpc->boost_freq) 1037 - return; 1038 - 1039 1032 /* Return if old value is non zero */ 1040 1033 if (!atomic_fetch_inc(&slpc->num_waiters)) { 1034 + /* 1035 + * Skip queuing boost work if frequency is already boosted, 1036 + * but still increment num_waiters. 1037 + */ 1038 + if (slpc->min_freq_softlimit >= slpc->boost_freq) 1039 + return; 1040 + 1041 1041 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n", 1042 1042 rq->fence.context, rq->fence.seqno); 1043 1043 queue_work(rps_to_gt(rps)->i915->unordered_wq,
+13 -12
drivers/gpu/drm/panel/panel-simple.c
··· 1027 1027 }, 1028 1028 }; 1029 1029 1030 - static const struct drm_display_mode auo_g101evn010_mode = { 1031 - .clock = 68930, 1032 - .hdisplay = 1280, 1033 - .hsync_start = 1280 + 82, 1034 - .hsync_end = 1280 + 82 + 2, 1035 - .htotal = 1280 + 82 + 2 + 84, 1036 - .vdisplay = 800, 1037 - .vsync_start = 800 + 8, 1038 - .vsync_end = 800 + 8 + 2, 1039 - .vtotal = 800 + 8 + 2 + 6, 1030 + static const struct display_timing auo_g101evn010_timing = { 1031 + .pixelclock = { 64000000, 68930000, 85000000 }, 1032 + .hactive = { 1280, 1280, 1280 }, 1033 + .hfront_porch = { 8, 64, 256 }, 1034 + .hback_porch = { 8, 64, 256 }, 1035 + .hsync_len = { 40, 168, 767 }, 1036 + .vactive = { 800, 800, 800 }, 1037 + .vfront_porch = { 4, 8, 100 }, 1038 + .vback_porch = { 4, 8, 100 }, 1039 + .vsync_len = { 8, 16, 223 }, 1040 1040 }; 1041 1041 1042 1042 static const struct panel_desc auo_g101evn010 = { 1043 - .modes = &auo_g101evn010_mode, 1044 - .num_modes = 1, 1043 + .timings = &auo_g101evn010_timing, 1044 + .num_timings = 1, 1045 1045 .bpc = 6, 1046 1046 .size = { 1047 1047 .width = 216, 1048 1048 .height = 135, 1049 1049 }, 1050 1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1051 + .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1051 1052 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 1053 }; 1053 1054
+12 -32
drivers/gpu/drm/ttm/ttm_backup.c
··· 8 8 #include <linux/swap.h> 9 9 10 10 /* 11 - * Casting from randomized struct file * to struct ttm_backup * is fine since 12 - * struct ttm_backup is never defined nor dereferenced. 13 - */ 14 - static struct file *ttm_backup_to_file(struct ttm_backup *backup) 15 - { 16 - return (void *)backup; 17 - } 18 - 19 - static struct ttm_backup *ttm_file_to_backup(struct file *file) 20 - { 21 - return (void *)file; 22 - } 23 - 24 - /* 25 11 * Need to map shmem indices to handle since a handle value 26 12 * of 0 means error, following the swp_entry_t convention. 27 13 */ ··· 26 40 * @backup: The struct backup pointer used to obtain the handle 27 41 * @handle: The handle obtained from the @backup_page function. 28 42 */ 29 - void ttm_backup_drop(struct ttm_backup *backup, pgoff_t handle) 43 + void ttm_backup_drop(struct file *backup, pgoff_t handle) 30 44 { 31 45 loff_t start = ttm_backup_handle_to_shmem_idx(handle); 32 46 33 47 start <<= PAGE_SHIFT; 34 - shmem_truncate_range(file_inode(ttm_backup_to_file(backup)), start, 48 + shmem_truncate_range(file_inode(backup), start, 35 49 start + PAGE_SIZE - 1); 36 50 } 37 51 ··· 41 55 * @backup: The struct backup pointer used to back up the page. 42 56 * @dst: The struct page to copy into. 43 57 * @handle: The handle returned when the page was backed up. 44 - * @intr: Try to perform waits interruptable or at least killable. 58 + * @intr: Try to perform waits interruptible or at least killable. 45 59 * 46 60 * Return: 0 on success, Negative error code on failure, notably 47 61 * -EINTR if @intr was set to true and a signal is pending. 48 62 */ 49 - int ttm_backup_copy_page(struct ttm_backup *backup, struct page *dst, 63 + int ttm_backup_copy_page(struct file *backup, struct page *dst, 50 64 pgoff_t handle, bool intr) 51 65 { 52 - struct file *filp = ttm_backup_to_file(backup); 53 - struct address_space *mapping = filp->f_mapping; 66 + struct address_space *mapping = backup->f_mapping; 54 67 struct folio *from_folio; 55 68 pgoff_t idx = ttm_backup_handle_to_shmem_idx(handle); 56 69 ··· 91 106 * the folio size- and usage. 92 107 */ 93 108 s64 94 - ttm_backup_backup_page(struct ttm_backup *backup, struct page *page, 109 + ttm_backup_backup_page(struct file *backup, struct page *page, 95 110 bool writeback, pgoff_t idx, gfp_t page_gfp, 96 111 gfp_t alloc_gfp) 97 112 { 98 - struct file *filp = ttm_backup_to_file(backup); 99 - struct address_space *mapping = filp->f_mapping; 113 + struct address_space *mapping = backup->f_mapping; 100 114 unsigned long handle = 0; 101 115 struct folio *to_folio; 102 116 int ret; ··· 145 161 * 146 162 * After a call to this function, it's illegal to use the @backup pointer. 147 163 */ 148 - void ttm_backup_fini(struct ttm_backup *backup) 164 + void ttm_backup_fini(struct file *backup) 149 165 { 150 - fput(ttm_backup_to_file(backup)); 166 + fput(backup); 151 167 } 152 168 153 169 /** ··· 178 194 * 179 195 * Create a backup utilizing shmem objects. 180 196 * 181 - * Return: A pointer to a struct ttm_backup on success, 197 + * Return: A pointer to a struct file on success, 182 198 * an error pointer on error. 183 199 */ 184 - struct ttm_backup *ttm_backup_shmem_create(loff_t size) 200 + struct file *ttm_backup_shmem_create(loff_t size) 185 201 { 186 - struct file *filp; 187 - 188 - filp = shmem_file_setup("ttm shmem backup", size, 0); 189 - 190 - return ttm_file_to_backup(filp); 202 + return shmem_file_setup("ttm shmem backup", size, 0); 191 203 }
+3 -3
drivers/gpu/drm/ttm/ttm_pool.c
··· 506 506 * if successful, populate the page-table and dma-address arrays. 507 507 */ 508 508 static int ttm_pool_restore_commit(struct ttm_pool_tt_restore *restore, 509 - struct ttm_backup *backup, 509 + struct file *backup, 510 510 const struct ttm_operation_ctx *ctx, 511 511 struct ttm_pool_alloc_state *alloc) 512 512 ··· 655 655 pgoff_t start_page, pgoff_t end_page) 656 656 { 657 657 struct page **pages = &tt->pages[start_page]; 658 - struct ttm_backup *backup = tt->backup; 658 + struct file *backup = tt->backup; 659 659 pgoff_t i, nr; 660 660 661 661 for (i = start_page; i < end_page; i += nr, pages += nr) { ··· 963 963 long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *tt, 964 964 const struct ttm_backup_flags *flags) 965 965 { 966 - struct ttm_backup *backup = tt->backup; 966 + struct file *backup = tt->backup; 967 967 struct page *page; 968 968 unsigned long handle; 969 969 gfp_t alloc_gfp;
+1 -1
drivers/gpu/drm/ttm/ttm_tt.c
··· 544 544 */ 545 545 int ttm_tt_setup_backup(struct ttm_tt *tt) 546 546 { 547 - struct ttm_backup *backup = 547 + struct file *backup = 548 548 ttm_backup_shmem_create(((loff_t)tt->num_pages) << PAGE_SHIFT); 549 549 550 550 if (WARN_ON_ONCE(!(tt->page_flags & TTM_TT_FLAG_EXTERNAL_MAPPABLE)))
+21 -7
drivers/gpu/drm/v3d/v3d_sched.c
··· 744 744 return DRM_GPU_SCHED_STAT_NOMINAL; 745 745 } 746 746 747 - /* If the current address or return address have changed, then the GPU 748 - * has probably made progress and we should delay the reset. This 749 - * could fail if the GPU got in an infinite loop in the CL, but that 750 - * is pretty unlikely outside of an i-g-t testcase. 751 - */ 747 + static void 748 + v3d_sched_skip_reset(struct drm_sched_job *sched_job) 749 + { 750 + struct drm_gpu_scheduler *sched = sched_job->sched; 751 + 752 + spin_lock(&sched->job_list_lock); 753 + list_add(&sched_job->list, &sched->pending_list); 754 + spin_unlock(&sched->job_list_lock); 755 + } 756 + 752 757 static enum drm_gpu_sched_stat 753 758 v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q, 754 759 u32 *timedout_ctca, u32 *timedout_ctra) ··· 763 758 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q)); 764 759 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q)); 765 760 761 + /* If the current address or return address have changed, then the GPU 762 + * has probably made progress and we should delay the reset. This 763 + * could fail if the GPU got in an infinite loop in the CL, but that 764 + * is pretty unlikely outside of an i-g-t testcase. 765 + */ 766 766 if (*timedout_ctca != ctca || *timedout_ctra != ctra) { 767 767 *timedout_ctca = ctca; 768 768 *timedout_ctra = ctra; 769 + 770 + v3d_sched_skip_reset(sched_job); 769 771 return DRM_GPU_SCHED_STAT_NOMINAL; 770 772 } 771 773 ··· 812 800 struct v3d_dev *v3d = job->base.v3d; 813 801 u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4(v3d->ver)); 814 802 815 - /* If we've made progress, skip reset and let the timer get 816 - * rearmed. 803 + /* If we've made progress, skip reset, add the job to the pending 804 + * list, and let the timer get rearmed. 817 805 */ 818 806 if (job->timedout_batches != batches) { 819 807 job->timedout_batches = batches; 808 + 809 + v3d_sched_skip_reset(sched_job); 820 810 return DRM_GPU_SCHED_STAT_NOMINAL; 821 811 } 822 812
+5 -2
drivers/gpu/drm/xe/tests/xe_mocs.c
··· 46 46 unsigned int fw_ref, i; 47 47 u32 reg_val; 48 48 49 - fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 50 - KUNIT_ASSERT_NE_MSG(test, fw_ref, 0, "Forcewake Failed.\n"); 49 + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 50 + if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 51 + xe_force_wake_put(gt_to_fw(gt), fw_ref); 52 + KUNIT_ASSERT_TRUE_MSG(test, true, "Forcewake Failed.\n"); 53 + } 51 54 52 55 for (i = 0; i < info->num_mocs_regs; i++) { 53 56 if (!(i & 1)) {
+22
drivers/gpu/drm/xe/xe_gsc.c
··· 555 555 flush_work(&gsc->work); 556 556 } 557 557 558 + void xe_gsc_stop_prepare(struct xe_gsc *gsc) 559 + { 560 + struct xe_gt *gt = gsc_to_gt(gsc); 561 + int ret; 562 + 563 + if (!xe_uc_fw_is_loadable(&gsc->fw) || xe_uc_fw_is_in_error_state(&gsc->fw)) 564 + return; 565 + 566 + xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GSC); 567 + 568 + /* 569 + * If the GSC FW load or the proxy init are interrupted, the only way 570 + * to recover it is to do an FLR and reload the GSC from scratch. 571 + * Therefore, let's wait for the init to complete before stopping 572 + * operations. The proxy init is the last step, so we can just wait on 573 + * that 574 + */ 575 + ret = xe_gsc_wait_for_proxy_init_done(gsc); 576 + if (ret) 577 + xe_gt_err(gt, "failed to wait for GSC init completion before uc stop\n"); 578 + } 579 + 558 580 /* 559 581 * wa_14015076503: if the GSC FW is loaded, we need to alert it before doing a 560 582 * GSC engine reset by writing a notification bit in the GS1 register and then
+1
drivers/gpu/drm/xe/xe_gsc.h
··· 16 16 int xe_gsc_init(struct xe_gsc *gsc); 17 17 int xe_gsc_init_post_hwconfig(struct xe_gsc *gsc); 18 18 void xe_gsc_wait_for_worker_completion(struct xe_gsc *gsc); 19 + void xe_gsc_stop_prepare(struct xe_gsc *gsc); 19 20 void xe_gsc_load_start(struct xe_gsc *gsc); 20 21 void xe_gsc_hwe_irq_handler(struct xe_hw_engine *hwe, u16 intr_vec); 21 22
+11
drivers/gpu/drm/xe/xe_gsc_proxy.c
··· 71 71 HECI1_FWSTS1_PROXY_STATE_NORMAL; 72 72 } 73 73 74 + int xe_gsc_wait_for_proxy_init_done(struct xe_gsc *gsc) 75 + { 76 + struct xe_gt *gt = gsc_to_gt(gsc); 77 + 78 + /* Proxy init can take up to 500ms, so wait double that for safety */ 79 + return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), 80 + HECI1_FWSTS1_CURRENT_STATE, 81 + HECI1_FWSTS1_PROXY_STATE_NORMAL, 82 + USEC_PER_SEC, NULL, false); 83 + } 84 + 74 85 static void __gsc_proxy_irq_rmw(struct xe_gsc *gsc, u32 clr, u32 set) 75 86 { 76 87 struct xe_gt *gt = gsc_to_gt(gsc);
+1
drivers/gpu/drm/xe/xe_gsc_proxy.h
··· 12 12 13 13 int xe_gsc_proxy_init(struct xe_gsc *gsc); 14 14 bool xe_gsc_proxy_init_done(struct xe_gsc *gsc); 15 + int xe_gsc_wait_for_proxy_init_done(struct xe_gsc *gsc); 15 16 int xe_gsc_proxy_start(struct xe_gsc *gsc); 16 17 17 18 int xe_gsc_proxy_request_handler(struct xe_gsc *gsc);
+1 -1
drivers/gpu/drm/xe/xe_gt.c
··· 857 857 858 858 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 859 859 860 - xe_uc_stop_prepare(&gt->uc); 860 + xe_uc_suspend_prepare(&gt->uc); 861 861 862 862 xe_force_wake_put(gt_to_fw(gt), fw_ref); 863 863 }
+5 -4
drivers/gpu/drm/xe/xe_gt_debugfs.c
··· 92 92 struct xe_hw_engine *hwe; 93 93 enum xe_hw_engine_id id; 94 94 unsigned int fw_ref; 95 + int ret = 0; 95 96 96 97 xe_pm_runtime_get(xe); 97 98 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 98 99 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 99 - xe_pm_runtime_put(xe); 100 - xe_force_wake_put(gt_to_fw(gt), fw_ref); 101 - return -ETIMEDOUT; 100 + ret = -ETIMEDOUT; 101 + goto fw_put; 102 102 } 103 103 104 104 for_each_hw_engine(hwe, gt, id) 105 105 xe_hw_engine_print(hwe, p); 106 106 107 + fw_put: 107 108 xe_force_wake_put(gt_to_fw(gt), fw_ref); 108 109 xe_pm_runtime_put(xe); 109 110 110 - return 0; 111 + return ret; 111 112 } 112 113 113 114 static int powergate_info(struct xe_gt *gt, struct drm_printer *p)
+9 -2
drivers/gpu/drm/xe/xe_gt_pagefault.c
··· 435 435 num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss, 436 436 XE_MAX_EU_FUSE_BITS) * num_dss; 437 437 438 - /* user can issue separate page faults per EU and per CS */ 438 + /* 439 + * user can issue separate page faults per EU and per CS 440 + * 441 + * XXX: Multiplier required as compute UMD are getting PF queue errors 442 + * without it. Follow on why this multiplier is required. 443 + */ 444 + #define PF_MULTIPLIER 8 439 445 pf_queue->num_dw = 440 - (num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW; 446 + (num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW * PF_MULTIPLIER; 447 + #undef PF_MULTIPLIER 441 448 442 449 pf_queue->gt = gt; 443 450 pf_queue->data = devm_kcalloc(xe->drm.dev, pf_queue->num_dw,
+12
drivers/gpu/drm/xe/xe_svm.c
··· 947 947 return 0; 948 948 } 949 949 #endif 950 + 951 + /** 952 + * xe_svm_flush() - SVM flush 953 + * @vm: The VM. 954 + * 955 + * Flush all SVM actions. 956 + */ 957 + void xe_svm_flush(struct xe_vm *vm) 958 + { 959 + if (xe_vm_in_fault_mode(vm)) 960 + flush_work(&vm->svm.garbage_collector.work); 961 + }
+8
drivers/gpu/drm/xe/xe_svm.h
··· 72 72 int xe_svm_bo_evict(struct xe_bo *bo); 73 73 74 74 void xe_svm_range_debug(struct xe_svm_range *range, const char *operation); 75 + 76 + void xe_svm_flush(struct xe_vm *vm); 77 + 75 78 #else 76 79 static inline bool xe_svm_range_pages_valid(struct xe_svm_range *range) 77 80 { ··· 127 124 void xe_svm_range_debug(struct xe_svm_range *range, const char *operation) 128 125 { 129 126 } 127 + 128 + static inline void xe_svm_flush(struct xe_vm *vm) 129 + { 130 + } 131 + 130 132 #endif 131 133 132 134 /**
+7 -1
drivers/gpu/drm/xe/xe_uc.c
··· 244 244 245 245 void xe_uc_stop_prepare(struct xe_uc *uc) 246 246 { 247 - xe_gsc_wait_for_worker_completion(&uc->gsc); 247 + xe_gsc_stop_prepare(&uc->gsc); 248 248 xe_guc_stop_prepare(&uc->guc); 249 249 } 250 250 ··· 276 276 ret = xe_uc_reset_prepare(uc); 277 277 if (ret) 278 278 goto again; 279 + } 280 + 281 + void xe_uc_suspend_prepare(struct xe_uc *uc) 282 + { 283 + xe_gsc_wait_for_worker_completion(&uc->gsc); 284 + xe_guc_stop_prepare(&uc->guc); 279 285 } 280 286 281 287 int xe_uc_suspend(struct xe_uc *uc)
+1
drivers/gpu/drm/xe/xe_uc.h
··· 18 18 void xe_uc_stop_prepare(struct xe_uc *uc); 19 19 void xe_uc_stop(struct xe_uc *uc); 20 20 int xe_uc_start(struct xe_uc *uc); 21 + void xe_uc_suspend_prepare(struct xe_uc *uc); 21 22 int xe_uc_suspend(struct xe_uc *uc); 22 23 int xe_uc_sanitize_reset(struct xe_uc *uc); 23 24 void xe_uc_declare_wedged(struct xe_uc *uc);
+1 -2
drivers/gpu/drm/xe/xe_vm.c
··· 3312 3312 } 3313 3313 3314 3314 /* Ensure all UNMAPs visible */ 3315 - if (xe_vm_in_fault_mode(vm)) 3316 - flush_work(&vm->svm.garbage_collector.work); 3315 + xe_svm_flush(vm); 3317 3316 3318 3317 err = down_write_killable(&vm->lock); 3319 3318 if (err)
+8 -10
include/drm/ttm/ttm_backup.h
··· 9 9 #include <linux/mm_types.h> 10 10 #include <linux/shmem_fs.h> 11 11 12 - struct ttm_backup; 13 - 14 12 /** 15 13 * ttm_backup_handle_to_page_ptr() - Convert handle to struct page pointer 16 14 * @handle: The handle to convert. 17 15 * 18 16 * Converts an opaque handle received from the 19 - * struct ttm_backoup_ops::backup_page() function to an (invalid) 17 + * ttm_backup_backup_page() function to an (invalid) 20 18 * struct page pointer suitable for a struct page array. 21 19 * 22 20 * Return: An (invalid) struct page pointer. ··· 43 45 * 44 46 * Return: The handle that was previously used in 45 47 * ttm_backup_handle_to_page_ptr() to obtain a struct page pointer, suitable 46 - * for use as argument in the struct ttm_backup_ops drop() or 47 - * copy_backed_up_page() functions. 48 + * for use as argument in the struct ttm_backup_drop() or 49 + * ttm_backup_copy_page() functions. 48 50 */ 49 51 static inline unsigned long 50 52 ttm_backup_page_ptr_to_handle(const struct page *page) ··· 53 55 return (unsigned long)page >> 1; 54 56 } 55 57 56 - void ttm_backup_drop(struct ttm_backup *backup, pgoff_t handle); 58 + void ttm_backup_drop(struct file *backup, pgoff_t handle); 57 59 58 - int ttm_backup_copy_page(struct ttm_backup *backup, struct page *dst, 60 + int ttm_backup_copy_page(struct file *backup, struct page *dst, 59 61 pgoff_t handle, bool intr); 60 62 61 63 s64 62 - ttm_backup_backup_page(struct ttm_backup *backup, struct page *page, 64 + ttm_backup_backup_page(struct file *backup, struct page *page, 63 65 bool writeback, pgoff_t idx, gfp_t page_gfp, 64 66 gfp_t alloc_gfp); 65 67 66 - void ttm_backup_fini(struct ttm_backup *backup); 68 + void ttm_backup_fini(struct file *backup); 67 69 68 70 u64 ttm_backup_bytes_avail(void); 69 71 70 - struct ttm_backup *ttm_backup_shmem_create(loff_t size); 72 + struct file *ttm_backup_shmem_create(loff_t size); 71 73 72 74 #endif
+1 -1
include/drm/ttm/ttm_tt.h
··· 118 118 * ttm_tt_create() callback is responsible for assigning 119 119 * this field. 120 120 */ 121 - struct ttm_backup *backup; 121 + struct file *backup; 122 122 /** 123 123 * @caching: The current caching state of the pages, see enum 124 124 * ttm_caching.