tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'fpga-for-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next

Xu writes:

FPGA Manager changes for 6.6-rc1

- Marco's change fixes kernel-doc warnings.
- Yangtao's change converts to use devm_platform_ioremap_resource().
- Peter's change uses HWMON defined Macros for HWMON interfaces support.
- Rob's change explicitly includes correct DT includes.
- Marco's change adds KUnit tests for FPGA core.
- Xiongfeng's change converts to use pci_find_vsec_capability().
- Ivan's change makes fpga_xxx_class a static const structure.

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: Xu Yilun <yilun.xu@intel.com>

* tag 'fpga-for-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
fpga: region: make fpga_region_class a static const structure
fpga: fpga-mgr: make fpga_mgr_class a static const structure
fpga: bridge: make fpga_bridge_class a static const structure
fpga: dfl-pci: Use pci_find_vsec_capability() to simplify the code
fpga: add configuration for the FPGA KUnit test suites.
fpga: add an initial KUnit suite for the FPGA Region
fpga: add an initial KUnit suite for the FPGA Bridge
fpga: add an initial KUnit suite for the FPGA Manager
fpga: Explicitly include correct DT includes
fpga: socfpga-a10: Convert to devm_platform_ioremap_resource()
fpga: fpga-mgr: altera-pr-ip: Convert to devm_platform_ioremap_resource()
fpga: zynq-fpga: Convert to devm_platform_ioremap_resource()
fpga: fpga-mgr: ts73xx: Convert to devm_platform_ioremap_resource()
fpga: fpga-mgr: socfpga: Convert to devm_platform_ioremap_resource()
fpga: xilinx-pr-decoupler: Convert to devm_platform_ioremap_resource()
fpga: dfl-fme-mgr: Convert to devm_platform_ioremap_resource()
fpga: bridge: Convert to devm_platform_ioremap_resource()
fpga: bridge: fix kernel-doc
fpga: region: fix kernel-doc
fpga: dfl: fme: use SI unit prefix macros

Greg Kroah-Hartman ea40d7d8 b587cb72

+828 -111
+2
drivers/fpga/Kconfig
··· 276 276 FPGA manager driver support for Lattice FPGAs programming over slave 277 277 SPI sysCONFIG interface. 278 278 279 + source "drivers/fpga/tests/Kconfig" 280 + 279 281 endif # FPGA
+3
drivers/fpga/Makefile
··· 55 55 56 56 # Drivers for FPGAs which implement DFL 57 57 obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o 58 + 59 + # KUnit tests 60 + obj-$(CONFIG_FPGA_KUNIT_TESTS) += tests/
+1 -1
drivers/fpga/altera-fpga2sdram.c
··· 27 27 #include <linux/kernel.h> 28 28 #include <linux/mfd/syscon.h> 29 29 #include <linux/module.h> 30 - #include <linux/of_platform.h> 30 + #include <linux/of.h> 31 31 #include <linux/regmap.h> 32 32 33 33 #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
+4 -7
drivers/fpga/altera-freeze-bridge.c
··· 7 7 #include <linux/delay.h> 8 8 #include <linux/io.h> 9 9 #include <linux/kernel.h> 10 - #include <linux/of_device.h> 10 + #include <linux/mod_devicetable.h> 11 11 #include <linux/module.h> 12 + #include <linux/platform_device.h> 12 13 #include <linux/fpga/fpga-bridge.h> 13 14 14 15 #define FREEZE_CSR_STATUS_OFFSET 0 ··· 199 198 .enable_show = altera_freeze_br_enable_show, 200 199 }; 201 200 202 - #ifdef CONFIG_OF 203 201 static const struct of_device_id altera_freeze_br_of_match[] = { 204 202 { .compatible = "altr,freeze-bridge-controller", }, 205 203 {}, 206 204 }; 207 205 MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match); 208 - #endif 209 206 210 207 static int altera_freeze_br_probe(struct platform_device *pdev) 211 208 { ··· 212 213 void __iomem *base_addr; 213 214 struct altera_freeze_br_data *priv; 214 215 struct fpga_bridge *br; 215 - struct resource *res; 216 216 u32 status, revision; 217 217 218 218 if (!np) 219 219 return -ENODEV; 220 220 221 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 222 - base_addr = devm_ioremap_resource(dev, res); 221 + base_addr = devm_platform_ioremap_resource(pdev, 0); 223 222 if (IS_ERR(base_addr)) 224 223 return PTR_ERR(base_addr); 225 224 ··· 267 270 .remove = altera_freeze_br_remove, 268 271 .driver = { 269 272 .name = "altera_freeze_br", 270 - .of_match_table = of_match_ptr(altera_freeze_br_of_match), 273 + .of_match_table = altera_freeze_br_of_match, 271 274 }, 272 275 }; 273 276
+3 -6
drivers/fpga/altera-pr-ip-core-plat.c
··· 9 9 */ 10 10 #include <linux/fpga/altera-pr-ip-core.h> 11 11 #include <linux/module.h> 12 - #include <linux/of_device.h> 12 + #include <linux/mod_devicetable.h> 13 + #include <linux/platform_device.h> 13 14 14 15 static int alt_pr_platform_probe(struct platform_device *pdev) 15 16 { 16 17 struct device *dev = &pdev->dev; 17 18 void __iomem *reg_base; 18 - struct resource *res; 19 19 20 20 /* First mmio base is for register access */ 21 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 22 - 23 - reg_base = devm_ioremap_resource(dev, res); 24 - 21 + reg_base = devm_platform_ioremap_resource(pdev, 0); 25 22 if (IS_ERR(reg_base)) 26 23 return PTR_ERR(reg_base); 27 24
+9 -8
drivers/fpga/dfl-fme-main.c
··· 19 19 #include <linux/kernel.h> 20 20 #include <linux/module.h> 21 21 #include <linux/uaccess.h> 22 + #include <linux/units.h> 22 23 #include <linux/fpga-dfl.h> 23 24 24 25 #include "dfl.h" ··· 232 231 switch (attr) { 233 232 case hwmon_temp_input: 234 233 v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1); 235 - *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000); 234 + *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * MILLI); 236 235 break; 237 236 case hwmon_temp_max: 238 237 v = readq(feature->ioaddr + FME_THERM_THRESHOLD); 239 - *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000); 238 + *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * MILLI); 240 239 break; 241 240 case hwmon_temp_crit: 242 241 v = readq(feature->ioaddr + FME_THERM_THRESHOLD); 243 - *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000); 242 + *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * MILLI); 244 243 break; 245 244 case hwmon_temp_emergency: 246 245 v = readq(feature->ioaddr + FME_THERM_THRESHOLD); 247 - *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000); 246 + *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * MILLI); 248 247 break; 249 248 case hwmon_temp_max_alarm: 250 249 v = readq(feature->ioaddr + FME_THERM_THRESHOLD); ··· 383 382 switch (attr) { 384 383 case hwmon_power_input: 385 384 v = readq(feature->ioaddr + FME_PWR_STATUS); 386 - *val = (long)(FIELD_GET(PWR_CONSUMED, v) * 1000000); 385 + *val = (long)(FIELD_GET(PWR_CONSUMED, v) * MICRO); 387 386 break; 388 387 case hwmon_power_max: 389 388 v = readq(feature->ioaddr + FME_PWR_THRESHOLD); 390 - *val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * 1000000); 389 + *val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * MICRO); 391 390 break; 392 391 case hwmon_power_crit: 393 392 v = readq(feature->ioaddr + FME_PWR_THRESHOLD); 394 - *val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * 1000000); 393 + *val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * MICRO); 395 394 break; 396 395 case hwmon_power_max_alarm: 397 396 v = readq(feature->ioaddr + FME_PWR_THRESHOLD); ··· 416 415 int ret = 0; 417 416 u64 v; 418 417 419 - val = clamp_val(val / 1000000, 0, PWR_THRESHOLD_MAX); 418 + val = clamp_val(val / MICRO, 0, PWR_THRESHOLD_MAX); 420 419 421 420 mutex_lock(&pdata->lock); 422 421
+1 -3
drivers/fpga/dfl-fme-mgr.c
··· 280 280 struct device *dev = &pdev->dev; 281 281 struct fme_mgr_priv *priv; 282 282 struct fpga_manager *mgr; 283 - struct resource *res; 284 283 285 284 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 286 285 if (!priv) ··· 289 290 priv->ioaddr = pdata->ioaddr; 290 291 291 292 if (!priv->ioaddr) { 292 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 293 - priv->ioaddr = devm_ioremap_resource(dev, res); 293 + priv->ioaddr = devm_platform_ioremap_resource(pdev, 0); 294 294 if (IS_ERR(priv->ioaddr)) 295 295 return PTR_ERR(priv->ioaddr); 296 296 }
+4 -11
drivers/fpga/dfl-pci.c
··· 156 156 157 157 static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) 158 158 { 159 - u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res; 160 - int dfl_res_off, i, bars, voff = 0; 159 + u32 bir, offset, dfl_cnt, dfl_res; 160 + int dfl_res_off, i, bars, voff; 161 161 resource_size_t start, len; 162 162 163 - while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) { 164 - vndr_hdr = 0; 165 - pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr); 166 - 167 - if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS && 168 - pcidev->vendor == PCI_VENDOR_ID_INTEL) 169 - break; 170 - } 171 - 163 + voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL, 164 + PCI_VSEC_ID_INTEL_DFLS); 172 165 if (!voff) { 173 166 dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__); 174 167 return -ENODEV;
+24 -24
drivers/fpga/fpga-bridge.c
··· 14 14 #include <linux/spinlock.h> 15 15 16 16 static DEFINE_IDA(fpga_bridge_ida); 17 - static struct class *fpga_bridge_class; 17 + static const struct class fpga_bridge_class; 18 18 19 19 /* Lock for adding/removing bridges to linked lists*/ 20 20 static DEFINE_SPINLOCK(bridge_list_lock); ··· 87 87 /** 88 88 * of_fpga_bridge_get - get an exclusive reference to an fpga bridge 89 89 * 90 - * @np: node pointer of an FPGA bridge 91 - * @info: fpga image specific information 90 + * @np: node pointer of an FPGA bridge. 91 + * @info: fpga image specific information. 92 92 * 93 - * Return fpga_bridge struct if successful. 94 - * Return -EBUSY if someone already has a reference to the bridge. 95 - * Return -ENODEV if @np is not an FPGA Bridge. 93 + * Return: 94 + * * fpga_bridge struct pointer if successful. 95 + * * -EBUSY if someone already has a reference to the bridge. 96 + * * -ENODEV if @np is not an FPGA Bridge or can't take parent driver refcount. 96 97 */ 97 98 struct fpga_bridge *of_fpga_bridge_get(struct device_node *np, 98 99 struct fpga_image_info *info) 99 100 { 100 101 struct device *dev; 101 102 102 - dev = class_find_device_by_of_node(fpga_bridge_class, np); 103 + dev = class_find_device_by_of_node(&fpga_bridge_class, np); 103 104 if (!dev) 104 105 return ERR_PTR(-ENODEV); 105 106 ··· 127 126 { 128 127 struct device *bridge_dev; 129 128 130 - bridge_dev = class_find_device(fpga_bridge_class, NULL, dev, 129 + bridge_dev = class_find_device(&fpga_bridge_class, NULL, dev, 131 130 fpga_bridge_dev_match); 132 131 if (!bridge_dev) 133 132 return ERR_PTR(-ENODEV); ··· 156 155 * fpga_bridges_enable - enable bridges in a list 157 156 * @bridge_list: list of FPGA bridges 158 157 * 159 - * Enable each bridge in the list. If list is empty, do nothing. 158 + * Enable each bridge in the list. If list is empty, do nothing. 160 159 * 161 - * Return 0 for success or empty bridge list; return error code otherwise. 160 + * Return: 0 for success or empty bridge list or an error code otherwise. 162 161 */ 163 162 int fpga_bridges_enable(struct list_head *bridge_list) 164 163 { ··· 180 179 * 181 180 * @bridge_list: list of FPGA bridges 182 181 * 183 - * Disable each bridge in the list. If list is empty, do nothing. 182 + * Disable each bridge in the list. If list is empty, do nothing. 184 183 * 185 - * Return 0 for success or empty bridge list; return error code otherwise. 184 + * Return: 0 for success or empty bridge list or an error code otherwise. 186 185 */ 187 186 int fpga_bridges_disable(struct list_head *bridge_list) 188 187 { ··· 231 230 * 232 231 * Get an exclusive reference to the bridge and it to the list. 233 232 * 234 - * Return 0 for success, error code from of_fpga_bridge_get() otherwise. 233 + * Return: 0 for success, error code from of_fpga_bridge_get() otherwise. 235 234 */ 236 235 int of_fpga_bridge_get_to_list(struct device_node *np, 237 236 struct fpga_image_info *info, ··· 261 260 * 262 261 * Get an exclusive reference to the bridge and it to the list. 263 262 * 264 - * Return 0 for success, error code from fpga_bridge_get() otherwise. 263 + * Return: 0 for success, error code from fpga_bridge_get() otherwise. 265 264 */ 266 265 int fpga_bridge_get_to_list(struct device *dev, 267 266 struct fpga_image_info *info, ··· 360 359 bridge->priv = priv; 361 360 362 361 bridge->dev.groups = br_ops->groups; 363 - bridge->dev.class = fpga_bridge_class; 362 + bridge->dev.class = &fpga_bridge_class; 364 363 bridge->dev.parent = parent; 365 364 bridge->dev.of_node = parent->of_node; 366 365 bridge->dev.id = id; ··· 416 415 kfree(bridge); 417 416 } 418 417 418 + static const struct class fpga_bridge_class = { 419 + .name = "fpga_bridge", 420 + .dev_groups = fpga_bridge_groups, 421 + .dev_release = fpga_bridge_dev_release, 422 + }; 423 + 419 424 static int __init fpga_bridge_dev_init(void) 420 425 { 421 - fpga_bridge_class = class_create("fpga_bridge"); 422 - if (IS_ERR(fpga_bridge_class)) 423 - return PTR_ERR(fpga_bridge_class); 424 - 425 - fpga_bridge_class->dev_groups = fpga_bridge_groups; 426 - fpga_bridge_class->dev_release = fpga_bridge_dev_release; 427 - 428 - return 0; 426 + return class_register(&fpga_bridge_class); 429 427 } 430 428 431 429 static void __exit fpga_bridge_dev_exit(void) 432 430 { 433 - class_destroy(fpga_bridge_class); 431 + class_unregister(&fpga_bridge_class); 434 432 ida_destroy(&fpga_bridge_ida); 435 433 } 436 434
+12 -13
drivers/fpga/fpga-mgr.c
··· 19 19 #include <linux/highmem.h> 20 20 21 21 static DEFINE_IDA(fpga_mgr_ida); 22 - static struct class *fpga_mgr_class; 22 + static const struct class fpga_mgr_class; 23 23 24 24 struct fpga_mgr_devres { 25 25 struct fpga_manager *mgr; ··· 693 693 */ 694 694 struct fpga_manager *fpga_mgr_get(struct device *dev) 695 695 { 696 - struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, 696 + struct device *mgr_dev = class_find_device(&fpga_mgr_class, NULL, dev, 697 697 fpga_mgr_dev_match); 698 698 if (!mgr_dev) 699 699 return ERR_PTR(-ENODEV); ··· 713 713 { 714 714 struct device *dev; 715 715 716 - dev = class_find_device_by_of_node(fpga_mgr_class, node); 716 + dev = class_find_device_by_of_node(&fpga_mgr_class, node); 717 717 if (!dev) 718 718 return ERR_PTR(-ENODEV); 719 719 ··· 809 809 mgr->priv = info->priv; 810 810 mgr->compat_id = info->compat_id; 811 811 812 - mgr->dev.class = fpga_mgr_class; 812 + mgr->dev.class = &fpga_mgr_class; 813 813 mgr->dev.groups = mops->groups; 814 814 mgr->dev.parent = parent; 815 815 mgr->dev.of_node = parent->of_node; ··· 967 967 kfree(mgr); 968 968 } 969 969 970 + static const struct class fpga_mgr_class = { 971 + .name = "fpga_manager", 972 + .dev_groups = fpga_mgr_groups, 973 + .dev_release = fpga_mgr_dev_release, 974 + }; 975 + 970 976 static int __init fpga_mgr_class_init(void) 971 977 { 972 978 pr_info("FPGA manager framework\n"); 973 979 974 - fpga_mgr_class = class_create("fpga_manager"); 975 - if (IS_ERR(fpga_mgr_class)) 976 - return PTR_ERR(fpga_mgr_class); 977 - 978 - fpga_mgr_class->dev_groups = fpga_mgr_groups; 979 - fpga_mgr_class->dev_release = fpga_mgr_dev_release; 980 - 981 - return 0; 980 + return class_register(&fpga_mgr_class); 982 981 } 983 982 984 983 static void __exit fpga_mgr_class_exit(void) 985 984 { 986 - class_destroy(fpga_mgr_class); 985 + class_unregister(&fpga_mgr_class); 987 986 ida_destroy(&fpga_mgr_ida); 988 987 } 989 988
+19 -18
drivers/fpga/fpga-region.c
··· 16 16 #include <linux/spinlock.h> 17 17 18 18 static DEFINE_IDA(fpga_region_ida); 19 - static struct class *fpga_region_class; 19 + static const struct class fpga_region_class; 20 20 21 21 struct fpga_region * 22 22 fpga_region_class_find(struct device *start, const void *data, ··· 24 24 { 25 25 struct device *dev; 26 26 27 - dev = class_find_device(fpga_region_class, start, data, match); 27 + dev = class_find_device(&fpga_region_class, start, data, match); 28 28 if (!dev) 29 29 return NULL; 30 30 ··· 38 38 * 39 39 * Caller should call fpga_region_put() when done with region. 40 40 * 41 - * Return fpga_region struct if successful. 42 - * Return -EBUSY if someone already has a reference to the region. 43 - * Return -ENODEV if @np is not an FPGA Region. 41 + * Return: 42 + * * fpga_region struct if successful. 43 + * * -EBUSY if someone already has a reference to the region. 44 + * * -ENODEV if can't take parent driver module refcount. 44 45 */ 45 46 static struct fpga_region *fpga_region_get(struct fpga_region *region) 46 47 { ··· 92 91 * The caller will need to call fpga_bridges_put() before attempting to 93 92 * reprogram the region. 94 93 * 95 - * Return 0 for success or negative error code. 94 + * Return: 0 for success or negative error code. 96 95 */ 97 96 int fpga_region_program_fpga(struct fpga_region *region) 98 97 { ··· 217 216 mutex_init(&region->mutex); 218 217 INIT_LIST_HEAD(&region->bridge_list); 219 218 220 - region->dev.class = fpga_region_class; 219 + region->dev.class = &fpga_region_class; 221 220 region->dev.parent = parent; 222 221 region->dev.of_node = parent->of_node; 223 222 region->dev.id = id; ··· 288 287 kfree(region); 289 288 } 290 289 290 + static const struct class fpga_region_class = { 291 + .name = "fpga_region", 292 + .dev_groups = fpga_region_groups, 293 + .dev_release = fpga_region_dev_release, 294 + }; 295 + 291 296 /** 292 - * fpga_region_init - init function for fpga_region class 293 - * Creates the fpga_region class and registers a reconfig notifier. 297 + * fpga_region_init - creates the fpga_region class. 298 + * 299 + * Return: 0 on success or ERR_PTR() on error. 294 300 */ 295 301 static int __init fpga_region_init(void) 296 302 { 297 - fpga_region_class = class_create("fpga_region"); 298 - if (IS_ERR(fpga_region_class)) 299 - return PTR_ERR(fpga_region_class); 300 - 301 - fpga_region_class->dev_groups = fpga_region_groups; 302 - fpga_region_class->dev_release = fpga_region_dev_release; 303 - 304 - return 0; 303 + return class_register(&fpga_region_class); 305 304 } 306 305 307 306 static void __exit fpga_region_exit(void) 308 307 { 309 - class_destroy(fpga_region_class); 308 + class_unregister(&fpga_region_class); 310 309 ida_destroy(&fpga_region_ida); 311 310 } 312 311
+1 -1
drivers/fpga/microchip-spi.c
··· 8 8 #include <linux/fpga/fpga-mgr.h> 9 9 #include <linux/iopoll.h> 10 10 #include <linux/module.h> 11 - #include <linux/of_device.h> 11 + #include <linux/of.h> 12 12 #include <linux/spi/spi.h> 13 13 14 14 #define MPF_SPI_ISC_ENABLE 0x0B
+2
drivers/fpga/of-fpga-region.c
··· 12 12 #include <linux/kernel.h> 13 13 #include <linux/list.h> 14 14 #include <linux/module.h> 15 + #include <linux/of.h> 15 16 #include <linux/of_platform.h> 17 + #include <linux/platform_device.h> 16 18 #include <linux/slab.h> 17 19 #include <linux/spinlock.h> 18 20
+2 -5
drivers/fpga/socfpga-a10.c
··· 471 471 struct a10_fpga_priv *priv; 472 472 void __iomem *reg_base; 473 473 struct fpga_manager *mgr; 474 - struct resource *res; 475 474 int ret; 476 475 477 476 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 478 479 return -ENOMEM; 479 480 480 481 /* First mmio base is for register access */ 481 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 482 - reg_base = devm_ioremap_resource(dev, res); 482 + reg_base = devm_platform_ioremap_resource(pdev, 0); 483 483 if (IS_ERR(reg_base)) 484 484 return PTR_ERR(reg_base); 485 485 486 486 /* Second mmio base is for writing FPGA image data */ 487 - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 488 - priv->fpga_data_addr = devm_ioremap_resource(dev, res); 487 + priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1); 489 488 if (IS_ERR(priv->fpga_data_addr)) 490 489 return PTR_ERR(priv->fpga_data_addr); 491 490
+2 -5
drivers/fpga/socfpga.c
··· 545 545 struct device *dev = &pdev->dev; 546 546 struct socfpga_fpga_priv *priv; 547 547 struct fpga_manager *mgr; 548 - struct resource *res; 549 548 int ret; 550 549 551 550 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 552 551 if (!priv) 553 552 return -ENOMEM; 554 553 555 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 556 - priv->fpga_base_addr = devm_ioremap_resource(dev, res); 554 + priv->fpga_base_addr = devm_platform_ioremap_resource(pdev, 0); 557 555 if (IS_ERR(priv->fpga_base_addr)) 558 556 return PTR_ERR(priv->fpga_base_addr); 559 557 560 - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 561 - priv->fpga_data_addr = devm_ioremap_resource(dev, res); 558 + priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1); 562 559 if (IS_ERR(priv->fpga_data_addr)) 563 560 return PTR_ERR(priv->fpga_data_addr); 564 561
+1
drivers/fpga/stratix10-soc.c
··· 10 10 #include <linux/module.h> 11 11 #include <linux/of.h> 12 12 #include <linux/of_platform.h> 13 + #include <linux/platform_device.h> 13 14 14 15 /* 15 16 * FPGA programming requires a higher level of privilege (EL3), per the SoC
+5
drivers/fpga/tests/.kunitconfig
··· 1 + CONFIG_KUNIT=y 2 + CONFIG_FPGA=y 3 + CONFIG_FPGA_REGION=y 4 + CONFIG_FPGA_BRIDGE=y 5 + CONFIG_FPGA_KUNIT_TESTS=y
+11
drivers/fpga/tests/Kconfig
··· 1 + config FPGA_KUNIT_TESTS 2 + tristate "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS 3 + depends on FPGA && FPGA_REGION && FPGA_BRIDGE && KUNIT=y 4 + default KUNIT_ALL_TESTS 5 + help 6 + This builds unit tests for the FPGA subsystem 7 + 8 + For more information on KUnit and unit tests in general, 9 + please refer to the KUnit documentation in Documentation/dev-tools/kunit/. 10 + 11 + If unsure, say N.
+6
drivers/fpga/tests/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + # 3 + # Makefile for KUnit test suites for the FPGA subsystem 4 + # 5 + 6 + obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
+175
drivers/fpga/tests/fpga-bridge-test.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * KUnit test for the FPGA Bridge 4 + * 5 + * Copyright (C) 2023 Red Hat, Inc. 6 + * 7 + * Author: Marco Pagani <marpagan@redhat.com> 8 + */ 9 + 10 + #include <kunit/test.h> 11 + #include <linux/device.h> 12 + #include <linux/fpga/fpga-bridge.h> 13 + #include <linux/module.h> 14 + #include <linux/types.h> 15 + 16 + struct bridge_stats { 17 + bool enable; 18 + }; 19 + 20 + struct bridge_ctx { 21 + struct fpga_bridge *bridge; 22 + struct platform_device *pdev; 23 + struct bridge_stats stats; 24 + }; 25 + 26 + static int op_enable_set(struct fpga_bridge *bridge, bool enable) 27 + { 28 + struct bridge_stats *stats = bridge->priv; 29 + 30 + stats->enable = enable; 31 + 32 + return 0; 33 + } 34 + 35 + /* 36 + * Fake FPGA bridge that implements only the enable_set op to track 37 + * the state. 38 + */ 39 + static const struct fpga_bridge_ops fake_bridge_ops = { 40 + .enable_set = op_enable_set, 41 + }; 42 + 43 + /** 44 + * register_test_bridge() - Register a fake FPGA bridge for testing. 45 + * @test: KUnit test context object. 46 + * 47 + * Return: Context of the newly registered FPGA bridge. 48 + */ 49 + static struct bridge_ctx *register_test_bridge(struct kunit *test) 50 + { 51 + struct bridge_ctx *ctx; 52 + 53 + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); 54 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); 55 + 56 + ctx->pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, NULL, 0); 57 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); 58 + 59 + ctx->bridge = fpga_bridge_register(&ctx->pdev->dev, "Fake FPGA bridge", &fake_bridge_ops, 60 + &ctx->stats); 61 + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); 62 + 63 + return ctx; 64 + } 65 + 66 + static void unregister_test_bridge(struct bridge_ctx *ctx) 67 + { 68 + fpga_bridge_unregister(ctx->bridge); 69 + platform_device_unregister(ctx->pdev); 70 + } 71 + 72 + static void fpga_bridge_test_get(struct kunit *test) 73 + { 74 + struct bridge_ctx *ctx = test->priv; 75 + struct fpga_bridge *bridge; 76 + 77 + bridge = fpga_bridge_get(&ctx->pdev->dev, NULL); 78 + KUNIT_EXPECT_PTR_EQ(test, bridge, ctx->bridge); 79 + 80 + bridge = fpga_bridge_get(&ctx->pdev->dev, NULL); 81 + KUNIT_EXPECT_EQ(test, PTR_ERR(bridge), -EBUSY); 82 + 83 + fpga_bridge_put(ctx->bridge); 84 + } 85 + 86 + static void fpga_bridge_test_toggle(struct kunit *test) 87 + { 88 + struct bridge_ctx *ctx = test->priv; 89 + int ret; 90 + 91 + ret = fpga_bridge_disable(ctx->bridge); 92 + KUNIT_EXPECT_EQ(test, ret, 0); 93 + KUNIT_EXPECT_FALSE(test, ctx->stats.enable); 94 + 95 + ret = fpga_bridge_enable(ctx->bridge); 96 + KUNIT_EXPECT_EQ(test, ret, 0); 97 + KUNIT_EXPECT_TRUE(test, ctx->stats.enable); 98 + } 99 + 100 + /* Test the functions for getting and controlling a list of bridges */ 101 + static void fpga_bridge_test_get_put_list(struct kunit *test) 102 + { 103 + struct list_head bridge_list; 104 + struct bridge_ctx *ctx_0, *ctx_1; 105 + int ret; 106 + 107 + ctx_0 = test->priv; 108 + ctx_1 = register_test_bridge(test); 109 + 110 + INIT_LIST_HEAD(&bridge_list); 111 + 112 + /* Get bridge 0 and add it to the list */ 113 + ret = fpga_bridge_get_to_list(&ctx_0->pdev->dev, NULL, &bridge_list); 114 + KUNIT_EXPECT_EQ(test, ret, 0); 115 + 116 + KUNIT_EXPECT_PTR_EQ(test, ctx_0->bridge, 117 + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); 118 + 119 + /* Get bridge 1 and add it to the list */ 120 + ret = fpga_bridge_get_to_list(&ctx_1->pdev->dev, NULL, &bridge_list); 121 + KUNIT_EXPECT_EQ(test, ret, 0); 122 + 123 + KUNIT_EXPECT_PTR_EQ(test, ctx_1->bridge, 124 + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); 125 + 126 + /* Disable an then enable both bridges from the list */ 127 + ret = fpga_bridges_disable(&bridge_list); 128 + KUNIT_EXPECT_EQ(test, ret, 0); 129 + 130 + KUNIT_EXPECT_FALSE(test, ctx_0->stats.enable); 131 + KUNIT_EXPECT_FALSE(test, ctx_1->stats.enable); 132 + 133 + ret = fpga_bridges_enable(&bridge_list); 134 + KUNIT_EXPECT_EQ(test, ret, 0); 135 + 136 + KUNIT_EXPECT_TRUE(test, ctx_0->stats.enable); 137 + KUNIT_EXPECT_TRUE(test, ctx_1->stats.enable); 138 + 139 + /* Put and remove both bridges from the list */ 140 + fpga_bridges_put(&bridge_list); 141 + 142 + KUNIT_EXPECT_TRUE(test, list_empty(&bridge_list)); 143 + 144 + unregister_test_bridge(ctx_1); 145 + } 146 + 147 + static int fpga_bridge_test_init(struct kunit *test) 148 + { 149 + test->priv = register_test_bridge(test); 150 + 151 + return 0; 152 + } 153 + 154 + static void fpga_bridge_test_exit(struct kunit *test) 155 + { 156 + unregister_test_bridge(test->priv); 157 + } 158 + 159 + static struct kunit_case fpga_bridge_test_cases[] = { 160 + KUNIT_CASE(fpga_bridge_test_get), 161 + KUNIT_CASE(fpga_bridge_test_toggle), 162 + KUNIT_CASE(fpga_bridge_test_get_put_list), 163 + {} 164 + }; 165 + 166 + static struct kunit_suite fpga_bridge_suite = { 167 + .name = "fpga_bridge", 168 + .init = fpga_bridge_test_init, 169 + .exit = fpga_bridge_test_exit, 170 + .test_cases = fpga_bridge_test_cases, 171 + }; 172 + 173 + kunit_test_suite(fpga_bridge_suite); 174 + 175 + MODULE_LICENSE("GPL");
+327
drivers/fpga/tests/fpga-mgr-test.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * KUnit test for the FPGA Manager 4 + * 5 + * Copyright (C) 2023 Red Hat, Inc. 6 + * 7 + * Author: Marco Pagani <marpagan@redhat.com> 8 + */ 9 + 10 + #include <kunit/test.h> 11 + #include <linux/device.h> 12 + #include <linux/fpga/fpga-mgr.h> 13 + #include <linux/module.h> 14 + #include <linux/scatterlist.h> 15 + #include <linux/types.h> 16 + 17 + #define HEADER_FILL 'H' 18 + #define IMAGE_FILL 'P' 19 + #define IMAGE_BLOCK 1024 20 + 21 + #define HEADER_SIZE IMAGE_BLOCK 22 + #define IMAGE_SIZE (IMAGE_BLOCK * 4) 23 + 24 + struct mgr_stats { 25 + bool header_match; 26 + bool image_match; 27 + u32 seq_num; 28 + u32 op_parse_header_seq; 29 + u32 op_write_init_seq; 30 + u32 op_write_seq; 31 + u32 op_write_sg_seq; 32 + u32 op_write_complete_seq; 33 + enum fpga_mgr_states op_parse_header_state; 34 + enum fpga_mgr_states op_write_init_state; 35 + enum fpga_mgr_states op_write_state; 36 + enum fpga_mgr_states op_write_sg_state; 37 + enum fpga_mgr_states op_write_complete_state; 38 + }; 39 + 40 + struct mgr_ctx { 41 + struct fpga_image_info *img_info; 42 + struct fpga_manager *mgr; 43 + struct platform_device *pdev; 44 + struct mgr_stats stats; 45 + }; 46 + 47 + /** 48 + * init_test_buffer() - Allocate and initialize a test image in a buffer. 49 + * @test: KUnit test context object. 50 + * @count: image size in bytes. 51 + * 52 + * Return: pointer to the newly allocated image. 53 + */ 54 + static char *init_test_buffer(struct kunit *test, size_t count) 55 + { 56 + char *buf; 57 + 58 + KUNIT_ASSERT_GE(test, count, HEADER_SIZE); 59 + 60 + buf = kunit_kzalloc(test, count, GFP_KERNEL); 61 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); 62 + 63 + memset(buf, HEADER_FILL, HEADER_SIZE); 64 + memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); 65 + 66 + return buf; 67 + } 68 + 69 + /* 70 + * Check the image header. Do not return an error code if the image check fails 71 + * since, in this case, it is a failure of the FPGA manager itself, not this 72 + * op that tests it. 73 + */ 74 + static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info, 75 + const char *buf, size_t count) 76 + { 77 + struct mgr_stats *stats = mgr->priv; 78 + size_t i; 79 + 80 + stats->op_parse_header_state = mgr->state; 81 + stats->op_parse_header_seq = stats->seq_num++; 82 + 83 + /* Set header_size and data_size for later */ 84 + info->header_size = HEADER_SIZE; 85 + info->data_size = info->count - HEADER_SIZE; 86 + 87 + stats->header_match = true; 88 + for (i = 0; i < info->header_size; i++) { 89 + if (buf[i] != HEADER_FILL) { 90 + stats->header_match = false; 91 + break; 92 + } 93 + } 94 + 95 + return 0; 96 + } 97 + 98 + static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, 99 + const char *buf, size_t count) 100 + { 101 + struct mgr_stats *stats = mgr->priv; 102 + 103 + stats->op_write_init_state = mgr->state; 104 + stats->op_write_init_seq = stats->seq_num++; 105 + 106 + return 0; 107 + } 108 + 109 + /* 110 + * Check the image data. As with op_parse_header, do not return an error code 111 + * if the image check fails. 112 + */ 113 + static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) 114 + { 115 + struct mgr_stats *stats = mgr->priv; 116 + size_t i; 117 + 118 + stats->op_write_state = mgr->state; 119 + stats->op_write_seq = stats->seq_num++; 120 + 121 + stats->image_match = true; 122 + for (i = 0; i < count; i++) { 123 + if (buf[i] != IMAGE_FILL) { 124 + stats->image_match = false; 125 + break; 126 + } 127 + } 128 + 129 + return 0; 130 + } 131 + 132 + /* 133 + * Check the image data, but first skip the header since write_sg will get 134 + * the whole image in sg_table. As with op_parse_header, do not return an 135 + * error code if the image check fails. 136 + */ 137 + static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt) 138 + { 139 + struct mgr_stats *stats = mgr->priv; 140 + struct sg_mapping_iter miter; 141 + char *img; 142 + size_t i; 143 + 144 + stats->op_write_sg_state = mgr->state; 145 + stats->op_write_sg_seq = stats->seq_num++; 146 + 147 + stats->image_match = true; 148 + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); 149 + 150 + if (!sg_miter_skip(&miter, HEADER_SIZE)) { 151 + stats->image_match = false; 152 + goto out; 153 + } 154 + 155 + while (sg_miter_next(&miter)) { 156 + img = miter.addr; 157 + for (i = 0; i < miter.length; i++) { 158 + if (img[i] != IMAGE_FILL) { 159 + stats->image_match = false; 160 + goto out; 161 + } 162 + } 163 + } 164 + out: 165 + sg_miter_stop(&miter); 166 + return 0; 167 + } 168 + 169 + static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) 170 + { 171 + struct mgr_stats *stats = mgr->priv; 172 + 173 + stats->op_write_complete_state = mgr->state; 174 + stats->op_write_complete_seq = stats->seq_num++; 175 + 176 + return 0; 177 + } 178 + 179 + /* 180 + * Fake FPGA manager that implements all ops required to check the programming 181 + * sequence using a single contiguous buffer and a scatter gather table. 182 + */ 183 + static const struct fpga_manager_ops fake_mgr_ops = { 184 + .skip_header = true, 185 + .parse_header = op_parse_header, 186 + .write_init = op_write_init, 187 + .write = op_write, 188 + .write_sg = op_write_sg, 189 + .write_complete = op_write_complete, 190 + }; 191 + 192 + static void fpga_mgr_test_get(struct kunit *test) 193 + { 194 + struct mgr_ctx *ctx = test->priv; 195 + struct fpga_manager *mgr; 196 + 197 + mgr = fpga_mgr_get(&ctx->pdev->dev); 198 + KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr); 199 + 200 + fpga_mgr_put(ctx->mgr); 201 + } 202 + 203 + static void fpga_mgr_test_lock(struct kunit *test) 204 + { 205 + struct mgr_ctx *ctx = test->priv; 206 + int ret; 207 + 208 + ret = fpga_mgr_lock(ctx->mgr); 209 + KUNIT_EXPECT_EQ(test, ret, 0); 210 + 211 + ret = fpga_mgr_lock(ctx->mgr); 212 + KUNIT_EXPECT_EQ(test, ret, -EBUSY); 213 + 214 + fpga_mgr_unlock(ctx->mgr); 215 + } 216 + 217 + /* Check the programming sequence using an image in a buffer */ 218 + static void fpga_mgr_test_img_load_buf(struct kunit *test) 219 + { 220 + struct mgr_ctx *ctx = test->priv; 221 + char *img_buf; 222 + int ret; 223 + 224 + img_buf = init_test_buffer(test, IMAGE_SIZE); 225 + 226 + ctx->img_info->count = IMAGE_SIZE; 227 + ctx->img_info->buf = img_buf; 228 + 229 + ret = fpga_mgr_load(ctx->mgr, ctx->img_info); 230 + KUNIT_EXPECT_EQ(test, ret, 0); 231 + 232 + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); 233 + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); 234 + 235 + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER); 236 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT); 237 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE); 238 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE); 239 + 240 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1); 241 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2); 242 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3); 243 + } 244 + 245 + /* Check the programming sequence using an image in a scatter gather table */ 246 + static void fpga_mgr_test_img_load_sgt(struct kunit *test) 247 + { 248 + struct mgr_ctx *ctx = test->priv; 249 + struct sg_table *sgt; 250 + char *img_buf; 251 + int ret; 252 + 253 + img_buf = init_test_buffer(test, IMAGE_SIZE); 254 + 255 + sgt = kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL); 256 + ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 257 + KUNIT_ASSERT_EQ(test, ret, 0); 258 + sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE); 259 + 260 + ctx->img_info->sgt = sgt; 261 + 262 + ret = fpga_mgr_load(ctx->mgr, ctx->img_info); 263 + KUNIT_EXPECT_EQ(test, ret, 0); 264 + 265 + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); 266 + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); 267 + 268 + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER); 269 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT); 270 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE); 271 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE); 272 + 273 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1); 274 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2); 275 + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3); 276 + 277 + sg_free_table(ctx->img_info->sgt); 278 + } 279 + 280 + static int fpga_mgr_test_init(struct kunit *test) 281 + { 282 + struct mgr_ctx *ctx; 283 + 284 + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); 285 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); 286 + 287 + ctx->pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0); 288 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); 289 + 290 + ctx->mgr = devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager", &fake_mgr_ops, 291 + &ctx->stats); 292 + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); 293 + 294 + ctx->img_info = fpga_image_info_alloc(&ctx->pdev->dev); 295 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info); 296 + 297 + test->priv = ctx; 298 + 299 + return 0; 300 + } 301 + 302 + static void fpga_mgr_test_exit(struct kunit *test) 303 + { 304 + struct mgr_ctx *ctx = test->priv; 305 + 306 + fpga_image_info_free(ctx->img_info); 307 + platform_device_unregister(ctx->pdev); 308 + } 309 + 310 + static struct kunit_case fpga_mgr_test_cases[] = { 311 + KUNIT_CASE(fpga_mgr_test_get), 312 + KUNIT_CASE(fpga_mgr_test_lock), 313 + KUNIT_CASE(fpga_mgr_test_img_load_buf), 314 + KUNIT_CASE(fpga_mgr_test_img_load_sgt), 315 + {} 316 + }; 317 + 318 + static struct kunit_suite fpga_mgr_suite = { 319 + .name = "fpga_mgr", 320 + .init = fpga_mgr_test_init, 321 + .exit = fpga_mgr_test_exit, 322 + .test_cases = fpga_mgr_test_cases, 323 + }; 324 + 325 + kunit_test_suite(fpga_mgr_suite); 326 + 327 + MODULE_LICENSE("GPL");
+211
drivers/fpga/tests/fpga-region-test.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * KUnit test for the FPGA Region 4 + * 5 + * Copyright (C) 2023 Red Hat, Inc. 6 + * 7 + * Author: Marco Pagani <marpagan@redhat.com> 8 + */ 9 + 10 + #include <kunit/test.h> 11 + #include <linux/fpga/fpga-bridge.h> 12 + #include <linux/fpga/fpga-mgr.h> 13 + #include <linux/fpga/fpga-region.h> 14 + #include <linux/module.h> 15 + #include <linux/platform_device.h> 16 + #include <linux/types.h> 17 + 18 + struct mgr_stats { 19 + u32 write_count; 20 + }; 21 + 22 + struct bridge_stats { 23 + bool enable; 24 + u32 cycles_count; 25 + }; 26 + 27 + struct test_ctx { 28 + struct fpga_manager *mgr; 29 + struct platform_device *mgr_pdev; 30 + struct fpga_bridge *bridge; 31 + struct platform_device *bridge_pdev; 32 + struct fpga_region *region; 33 + struct platform_device *region_pdev; 34 + struct bridge_stats bridge_stats; 35 + struct mgr_stats mgr_stats; 36 + }; 37 + 38 + static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) 39 + { 40 + struct mgr_stats *stats = mgr->priv; 41 + 42 + stats->write_count++; 43 + 44 + return 0; 45 + } 46 + 47 + /* 48 + * Fake FPGA manager that implements only the write op to count the number 49 + * of programming cycles. The internals of the programming sequence are 50 + * tested in the Manager suite since they are outside the responsibility 51 + * of the Region. 52 + */ 53 + static const struct fpga_manager_ops fake_mgr_ops = { 54 + .write = op_write, 55 + }; 56 + 57 + static int op_enable_set(struct fpga_bridge *bridge, bool enable) 58 + { 59 + struct bridge_stats *stats = bridge->priv; 60 + 61 + if (!stats->enable && enable) 62 + stats->cycles_count++; 63 + 64 + stats->enable = enable; 65 + 66 + return 0; 67 + } 68 + 69 + /* 70 + * Fake FPGA bridge that implements only enable_set op to count the number 71 + * of activation cycles. 72 + */ 73 + static const struct fpga_bridge_ops fake_bridge_ops = { 74 + .enable_set = op_enable_set, 75 + }; 76 + 77 + static int fake_region_get_bridges(struct fpga_region *region) 78 + { 79 + struct fpga_bridge *bridge = region->priv; 80 + 81 + return fpga_bridge_get_to_list(bridge->dev.parent, region->info, &region->bridge_list); 82 + } 83 + 84 + static int fake_region_match(struct device *dev, const void *data) 85 + { 86 + return dev->parent == data; 87 + } 88 + 89 + static void fpga_region_test_class_find(struct kunit *test) 90 + { 91 + struct test_ctx *ctx = test->priv; 92 + struct fpga_region *region; 93 + 94 + region = fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_region_match); 95 + KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); 96 + } 97 + 98 + /* 99 + * FPGA Region programming test. The Region must call get_bridges() to get 100 + * and control the bridges, and then the Manager for the actual programming. 101 + */ 102 + static void fpga_region_test_program_fpga(struct kunit *test) 103 + { 104 + struct test_ctx *ctx = test->priv; 105 + struct fpga_image_info *img_info; 106 + char img_buf[4]; 107 + int ret; 108 + 109 + img_info = fpga_image_info_alloc(&ctx->mgr_pdev->dev); 110 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, img_info); 111 + 112 + img_info->buf = img_buf; 113 + img_info->count = sizeof(img_buf); 114 + 115 + ctx->region->info = img_info; 116 + ret = fpga_region_program_fpga(ctx->region); 117 + KUNIT_ASSERT_EQ(test, ret, 0); 118 + 119 + KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); 120 + KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); 121 + 122 + fpga_bridges_put(&ctx->region->bridge_list); 123 + 124 + ret = fpga_region_program_fpga(ctx->region); 125 + KUNIT_ASSERT_EQ(test, ret, 0); 126 + 127 + KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); 128 + KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); 129 + 130 + fpga_bridges_put(&ctx->region->bridge_list); 131 + 132 + fpga_image_info_free(img_info); 133 + } 134 + 135 + /* 136 + * The configuration used in this test suite uses a single bridge to 137 + * limit the code under test to a single unit. The functions used by the 138 + * Region for getting and controlling bridges are tested (with a list of 139 + * multiple bridges) in the Bridge suite. 140 + */ 141 + static int fpga_region_test_init(struct kunit *test) 142 + { 143 + struct test_ctx *ctx; 144 + struct fpga_region_info region_info = { 0 }; 145 + 146 + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); 147 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); 148 + 149 + ctx->mgr_pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0); 150 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_pdev); 151 + 152 + ctx->mgr = devm_fpga_mgr_register(&ctx->mgr_pdev->dev, "Fake FPGA Manager", &fake_mgr_ops, 153 + &ctx->mgr_stats); 154 + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); 155 + 156 + ctx->bridge_pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, 157 + NULL, 0); 158 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_pdev); 159 + 160 + ctx->bridge = fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA Bridge", 161 + &fake_bridge_ops, &ctx->bridge_stats); 162 + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); 163 + 164 + ctx->bridge_stats.enable = true; 165 + 166 + ctx->region_pdev = platform_device_register_simple("region_pdev", PLATFORM_DEVID_AUTO, 167 + NULL, 0); 168 + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_pdev); 169 + 170 + region_info.mgr = ctx->mgr; 171 + region_info.priv = ctx->bridge; 172 + region_info.get_bridges = fake_region_get_bridges; 173 + 174 + ctx->region = fpga_region_register_full(&ctx->region_pdev->dev, &region_info); 175 + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); 176 + 177 + test->priv = ctx; 178 + 179 + return 0; 180 + } 181 + 182 + static void fpga_region_test_exit(struct kunit *test) 183 + { 184 + struct test_ctx *ctx = test->priv; 185 + 186 + fpga_region_unregister(ctx->region); 187 + platform_device_unregister(ctx->region_pdev); 188 + 189 + fpga_bridge_unregister(ctx->bridge); 190 + platform_device_unregister(ctx->bridge_pdev); 191 + 192 + platform_device_unregister(ctx->mgr_pdev); 193 + } 194 + 195 + static struct kunit_case fpga_region_test_cases[] = { 196 + KUNIT_CASE(fpga_region_test_class_find), 197 + KUNIT_CASE(fpga_region_test_program_fpga), 198 + 199 + {} 200 + }; 201 + 202 + static struct kunit_suite fpga_region_suite = { 203 + .name = "fpga_mgr", 204 + .init = fpga_region_test_init, 205 + .exit = fpga_region_test_exit, 206 + .test_cases = fpga_region_test_cases, 207 + }; 208 + 209 + kunit_test_suite(fpga_region_suite); 210 + 211 + MODULE_LICENSE("GPL");
+1 -3
drivers/fpga/ts73xx-fpga.c
··· 103 103 struct device *kdev = &pdev->dev; 104 104 struct ts73xx_fpga_priv *priv; 105 105 struct fpga_manager *mgr; 106 - struct resource *res; 107 106 108 107 priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); 109 108 if (!priv) ··· 110 111 111 112 priv->dev = kdev; 112 113 113 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 114 - priv->io_base = devm_ioremap_resource(kdev, res); 114 + priv->io_base = devm_platform_ioremap_resource(pdev, 0); 115 115 if (IS_ERR(priv->io_base)) 116 116 return PTR_ERR(priv->io_base); 117 117
+1 -3
drivers/fpga/xilinx-pr-decoupler.c
··· 108 108 struct xlnx_pr_decoupler_data *priv; 109 109 struct fpga_bridge *br; 110 110 int err; 111 - struct resource *res; 112 111 113 112 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 114 113 if (!priv) ··· 121 122 priv->ipconfig = match->data; 122 123 } 123 124 124 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 125 - priv->io_base = devm_ioremap_resource(&pdev->dev, res); 125 + priv->io_base = devm_platform_ioremap_resource(pdev, 0); 126 126 if (IS_ERR(priv->io_base)) 127 127 return PTR_ERR(priv->io_base); 128 128
+1 -3
drivers/fpga/zynq-fpga.c
··· 555 555 struct device *dev = &pdev->dev; 556 556 struct zynq_fpga_priv *priv; 557 557 struct fpga_manager *mgr; 558 - struct resource *res; 559 558 int err; 560 559 561 560 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 562 563 return -ENOMEM; 563 564 spin_lock_init(&priv->dma_lock); 564 565 565 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 566 - priv->io_base = devm_ioremap_resource(dev, res); 566 + priv->io_base = devm_platform_ioremap_resource(pdev, 0); 567 567 if (IS_ERR(priv->io_base)) 568 568 return PTR_ERR(priv->io_base); 569 569