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phy: qcom: pcie: Determine has_nocsr_reset dynamically

Decide the in-driver logic based on whether the nocsr reset is present
and defer checking the appropriateness of that to dt-bindings to save
on boilerplate.

Reset controller APIs are fine consuming a nullptr, so no additional
checks are necessary there.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Link: https://lore.kernel.org/r/20250411113120.651363-2-quic_wenbyao@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Konrad Dybcio and committed by
Vinod Koul ea57d7fe bdeff6d8

+4 -13
+4 -13
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 3021 3021 3022 3022 bool skip_start_delay; 3023 3023 3024 - bool has_nocsr_reset; 3025 - 3026 3024 /* QMP PHY pipe clock interface rate */ 3027 3025 unsigned long pipe_clock_rate; 3028 3026 ··· 4018 4020 4019 4021 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4020 4022 .phy_status = PHYSTATUS_4_20, 4021 - .has_nocsr_reset = true, 4022 4023 4023 4024 /* 20MHz PHY AUX Clock */ 4024 4025 .aux_clock_rate = 20000000, ··· 4050 4053 4051 4054 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4052 4055 .phy_status = PHYSTATUS_4_20, 4053 - .has_nocsr_reset = true, 4054 4056 4055 4057 /* 20MHz PHY AUX Clock */ 4056 4058 .aux_clock_rate = 20000000, ··· 4169 4173 4170 4174 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4171 4175 .phy_status = PHYSTATUS_4_20, 4172 - .has_nocsr_reset = true, 4173 4176 }; 4174 4177 4175 4178 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { ··· 4202 4207 4203 4208 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4204 4209 .phy_status = PHYSTATUS_4_20, 4205 - .has_nocsr_reset = true, 4206 4210 }; 4207 4211 4208 4212 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { ··· 4233 4239 4234 4240 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4235 4241 .phy_status = PHYSTATUS_4_20, 4236 - .has_nocsr_reset = true, 4237 4242 }; 4238 4243 4239 4244 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { ··· 4550 4557 if (ret) 4551 4558 return dev_err_probe(dev, ret, "failed to get resets\n"); 4552 4559 4553 - if (cfg->has_nocsr_reset) { 4554 - qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 4555 - if (IS_ERR(qmp->nocsr_reset)) 4556 - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 4557 - "failed to get no-csr reset\n"); 4558 - } 4560 + qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); 4561 + if (IS_ERR(qmp->nocsr_reset)) 4562 + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 4563 + "failed to get no-csr reset\n"); 4559 4564 4560 4565 return 0; 4561 4566 }