tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC updates from Ulf Hansson:
"MMC core:
- Fixup processing of SDIO IRQs during system suspend/resume
- Add helper function to indicate if SDIO IRQs is enabled

MMC host:
- bcm2835: Take SWIOTLB memory size limitation into account
- dw_mmc: Improve SDIO IRQs support
- mtk-sd: Various improvements
- mtk-sd: Improve SDIO IRQs support
- sdhci-iproc: Add support for emmc2 of the BCM2711
- sdhci-of-arasan: Add Support for Intel LGM eMMC
- sdhci-of-aspeed: Add support for the ASPEED SD controller
- sdhci-of-esdhc: Deal with erratum A011334 support in ls1028a 1.0 SoC
- sdhci-pci: Prepare to add support of Genesys Logic GL975x
- sdhci-pci: Add another Id for Intel CML
- sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
- sunxi: Add support for H5 compatibles"

* tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (59 commits)
ms_block: fix spelling mistake "randomally" -> "randomly"
mmc: dw_mmc: hi3798cv200: make array degrees static const, makes object smaller
mmc: sdhci: Convert to use sdio_irq_claimed()
mmc: sdhci: Drop redundant code for SDIO IRQs
mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq()
mmc: core: Fixup processing of SDIO IRQs during system suspend/resume
mmc: core: WARN if SDIO IRQs are enabled for non-powered card in suspend
mmc: core: Clarify that the ->ack_sdio_irq() callback is mandatory
mmc: core: Clarify sdio_irq_pending flag for MMC_CAP2_SDIO_IRQ_NOTHREAD
mmc: core: Move code to get pending SDIO IRQs to a function
mmc: mtk-sd: Re-store SDIO IRQs mask at system resume
mmc: dw_mmc: Re-store SDIO IRQs mask at system resume
mmc: core: Add helper function to indicate if SDIO IRQs is enabled
mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue
mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
mmc: sdhci: Fix incorrect switch to HS mode
mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESS
mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
...

Linus Torvalds ea982ba7 7ad67ca5

+963 -315
+12 -6
Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
··· 30 30 - const: allwinner,sun8i-a83t-mmc 31 31 - const: allwinner,sun7i-a20-mmc 32 32 - items: 33 - - const: allwinner,sun50i-h6-emmc 34 - - const: allwinner,sun50i-a64-emmc 35 - - items: 36 - - const: allwinner,sun50i-h6-mmc 37 - - const: allwinner,sun50i-a64-mmc 38 - - items: 39 33 - const: allwinner,sun8i-r40-emmc 40 34 - const: allwinner,sun50i-a64-emmc 41 35 - items: 42 36 - const: allwinner,sun8i-r40-mmc 37 + - const: allwinner,sun50i-a64-mmc 38 + - items: 39 + - const: allwinner,sun50i-h5-emmc 40 + - const: allwinner,sun50i-a64-emmc 41 + - items: 42 + - const: allwinner,sun50i-h5-mmc 43 + - const: allwinner,sun50i-a64-mmc 44 + - items: 45 + - const: allwinner,sun50i-h6-emmc 46 + - const: allwinner,sun50i-a64-emmc 47 + - items: 48 + - const: allwinner,sun50i-h6-mmc 43 49 - const: allwinner,sun50i-a64-mmc 44 50 45 51 reg:
+17
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
··· 17 17 For this device it is strongly suggested to include arasan,soc-ctl-syscon. 18 18 - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY 19 19 Note: This binding has been deprecated and moved to [5]. 20 + - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY 21 + For this device it is strongly suggested to include arasan,soc-ctl-syscon. 20 22 21 23 [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt 22 24 ··· 81 79 phys = <&emmc_phy>; 82 80 phy-names = "phy_arasan"; 83 81 #clock-cells = <0>; 82 + }; 83 + 84 + emmc: sdhci@ec700000 { 85 + compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 86 + reg = <0xec700000 0x300>; 87 + interrupt-parent = <&ioapic1>; 88 + interrupts = <44 1>; 89 + clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, 90 + <&cgu0 LGM_GCLK_EMMC>; 91 + clock-names = "clk_xin", "clk_ahb", "gate"; 92 + clock-output-names = "emmc_cardclock"; 93 + #clock-cells = <0>; 94 + phys = <&emmc_phy>; 95 + phy-names = "phy_arasan"; 96 + arasan,soc-ctl-syscon = <&sysconf>; 84 97 };
+106
Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-or-later 2 + # Copyright 2019 IBM Corp. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: ASPEED SD/SDIO/MMC Controller 9 + 10 + maintainers: 11 + - Andrew Jeffery <andrew@aj.id.au> 12 + - Ryan Chen <ryanchen.aspeed@gmail.com> 13 + 14 + description: |+ 15 + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO 16 + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if 17 + only a single slot is enabled. 18 + 19 + The two slots are supported by a common configuration area. As the SDHCIs for 20 + the slots are dependent on the common configuration area, they are described 21 + as child nodes. 22 + 23 + properties: 24 + compatible: 25 + enum: 26 + - aspeed,ast2400-sd-controller 27 + - aspeed,ast2500-sd-controller 28 + - aspeed,ast2600-sd-controller 29 + reg: 30 + maxItems: 1 31 + description: Common configuration registers 32 + "#address-cells": 33 + const: 1 34 + "#size-cells": 35 + const: 1 36 + ranges: true 37 + clocks: 38 + maxItems: 1 39 + description: The SD/SDIO controller clock gate 40 + 41 + patternProperties: 42 + "^sdhci@[0-9a-f]+$": 43 + type: object 44 + allOf: 45 + - $ref: mmc-controller.yaml 46 + properties: 47 + compatible: 48 + enum: 49 + - aspeed,ast2400-sdhci 50 + - aspeed,ast2500-sdhci 51 + - aspeed,ast2600-sdhci 52 + reg: 53 + maxItems: 1 54 + description: The SDHCI registers 55 + clocks: 56 + maxItems: 1 57 + description: The SD bus clock 58 + interrupts: 59 + maxItems: 1 60 + description: The SD interrupt shared between both slots 61 + sdhci,auto-cmd12: 62 + type: boolean 63 + description: Specifies that controller should use auto CMD12 64 + required: 65 + - compatible 66 + - reg 67 + - clocks 68 + - interrupts 69 + 70 + additionalProperties: false 71 + 72 + required: 73 + - compatible 74 + - reg 75 + - "#address-cells" 76 + - "#size-cells" 77 + - ranges 78 + - clocks 79 + 80 + examples: 81 + - | 82 + #include <dt-bindings/clock/aspeed-clock.h> 83 + sdc@1e740000 { 84 + compatible = "aspeed,ast2500-sd-controller"; 85 + reg = <0x1e740000 0x100>; 86 + #address-cells = <1>; 87 + #size-cells = <1>; 88 + ranges = <0 0x1e740000 0x20000>; 89 + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 90 + 91 + sdhci0: sdhci@100 { 92 + compatible = "aspeed,ast2500-sdhci"; 93 + reg = <0x100 0x100>; 94 + interrupts = <26>; 95 + sdhci,auto-cmd12; 96 + clocks = <&syscon ASPEED_CLK_SDIO>; 97 + }; 98 + 99 + sdhci1: sdhci@200 { 100 + compatible = "aspeed,ast2500-sdhci"; 101 + reg = <0x200 0x100>; 102 + interrupts = <26>; 103 + sdhci,auto-cmd12; 104 + clocks = <&syscon ASPEED_CLK_SDIO>; 105 + }; 106 + };
+3 -1
Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
··· 6 6 Required properties: 7 7 - compatible : Should be one of the following 8 8 "brcm,bcm2835-sdhci" 9 + "brcm,bcm2711-emmc2" 9 10 "brcm,sdhci-iproc-cygnus" 10 11 "brcm,sdhci-iproc" 11 12 12 - Use brcm2835-sdhci for Rasperry PI. 13 + Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and 14 + bcm2711-emmc2 for the additional eMMC2 controller on BCM2711. 13 15 14 16 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers 15 17 restricted to 32bit host accesses to SDHCI registers.
+1
MAINTAINERS
··· 1462 1462 F: arch/arm/boot/dts/artpec6* 1463 1463 F: drivers/clk/axis 1464 1464 F: drivers/crypto/axis 1465 + F: drivers/mmc/host/usdhi6rol0.c 1465 1466 F: drivers/pinctrl/pinctrl-artpec* 1466 1467 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt 1467 1468
+1 -1
drivers/memstick/core/ms_block.c
··· 1087 1087 1088 1088 pos %= msb->free_block_count[zone]; 1089 1089 1090 - dbg_verbose("have %d choices for a free block, selected randomally: %d", 1090 + dbg_verbose("have %d choices for a free block, selected randomly: %d", 1091 1091 msb->free_block_count[zone], pos); 1092 1092 1093 1093 pba = find_next_zero_bit(msb->used_blocks_bitmap,
+2 -4
drivers/memstick/host/r592.c
··· 847 847 #ifdef CONFIG_PM_SLEEP 848 848 static int r592_suspend(struct device *core_dev) 849 849 { 850 - struct pci_dev *pdev = to_pci_dev(core_dev); 851 - struct r592_device *dev = pci_get_drvdata(pdev); 850 + struct r592_device *dev = dev_get_drvdata(core_dev); 852 851 853 852 r592_clear_interrupts(dev); 854 853 memstick_suspend_host(dev->host); ··· 857 858 858 859 static int r592_resume(struct device *core_dev) 859 860 { 860 - struct pci_dev *pdev = to_pci_dev(core_dev); 861 - struct r592_device *dev = pci_get_drvdata(pdev); 861 + struct r592_device *dev = dev_get_drvdata(core_dev); 862 862 863 863 r592_clear_interrupts(dev); 864 864 r592_enable_device(dev, false);
+3 -1
drivers/mmc/core/sdio.c
··· 951 951 */ 952 952 static int mmc_sdio_suspend(struct mmc_host *host) 953 953 { 954 + WARN_ON(host->sdio_irqs && !mmc_card_keep_power(host)); 955 + 954 956 /* Prevent processing of SDIO IRQs in suspended state. */ 955 957 mmc_card_set_suspended(host->card); 956 958 cancel_delayed_work_sync(&host->sdio_irq_work); ··· 1015 1013 if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) 1016 1014 wake_up_process(host->sdio_irq_thread); 1017 1015 else if (host->caps & MMC_CAP_SDIO_IRQ) 1018 - host->ops->enable_sdio_irq(host, 1); 1016 + queue_delayed_work(system_wq, &host->sdio_irq_work, 0); 1019 1017 } 1020 1018 1021 1019 out:
+40 -23
drivers/mmc/core/sdio_irq.c
··· 27 27 #include "core.h" 28 28 #include "card.h" 29 29 30 - static int process_sdio_pending_irqs(struct mmc_host *host) 30 + static int sdio_get_pending_irqs(struct mmc_host *host, u8 *pending) 31 31 { 32 32 struct mmc_card *card = host->card; 33 - int i, ret, count; 34 - unsigned char pending; 35 - struct sdio_func *func; 33 + int ret; 36 34 37 - /* Don't process SDIO IRQs if the card is suspended. */ 38 - if (mmc_card_suspended(card)) 39 - return 0; 35 + WARN_ON(!host->claimed); 40 36 41 - /* 42 - * Optimization, if there is only 1 function interrupt registered 43 - * and we know an IRQ was signaled then call irq handler directly. 44 - * Otherwise do the full probe. 45 - */ 46 - func = card->sdio_single_irq; 47 - if (func && host->sdio_irq_pending) { 48 - func->irq_handler(func); 49 - return 1; 50 - } 51 - 52 - ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending); 37 + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, pending); 53 38 if (ret) { 54 39 pr_debug("%s: error %d reading SDIO_CCCR_INTx\n", 55 40 mmc_card_id(card), ret); 56 41 return ret; 57 42 } 58 43 59 - if (pending && mmc_card_broken_irq_polling(card) && 44 + if (*pending && mmc_card_broken_irq_polling(card) && 60 45 !(host->caps & MMC_CAP_SDIO_IRQ)) { 61 46 unsigned char dummy; 62 47 ··· 51 66 */ 52 67 mmc_io_rw_direct(card, 0, 0, 0xff, 0, &dummy); 53 68 } 69 + 70 + return 0; 71 + } 72 + 73 + static int process_sdio_pending_irqs(struct mmc_host *host) 74 + { 75 + struct mmc_card *card = host->card; 76 + int i, ret, count; 77 + bool sdio_irq_pending = host->sdio_irq_pending; 78 + unsigned char pending; 79 + struct sdio_func *func; 80 + 81 + /* Don't process SDIO IRQs if the card is suspended. */ 82 + if (mmc_card_suspended(card)) 83 + return 0; 84 + 85 + /* Clear the flag to indicate that we have processed the IRQ. */ 86 + host->sdio_irq_pending = false; 87 + 88 + /* 89 + * Optimization, if there is only 1 function interrupt registered 90 + * and we know an IRQ was signaled then call irq handler directly. 91 + * Otherwise do the full probe. 92 + */ 93 + func = card->sdio_single_irq; 94 + if (func && sdio_irq_pending) { 95 + func->irq_handler(func); 96 + return 1; 97 + } 98 + 99 + ret = sdio_get_pending_irqs(host, &pending); 100 + if (ret) 101 + return ret; 54 102 55 103 count = 0; 56 104 for (i = 1; i <= 7; i++) { ··· 114 96 { 115 97 mmc_claim_host(host); 116 98 if (host->sdio_irqs) { 117 - host->sdio_irq_pending = true; 118 99 process_sdio_pending_irqs(host); 119 - if (host->ops->ack_sdio_irq) 100 + if (!host->sdio_irq_pending) 120 101 host->ops->ack_sdio_irq(host); 121 102 } 122 103 mmc_release_host(host); ··· 131 114 132 115 void sdio_signal_irq(struct mmc_host *host) 133 116 { 117 + host->sdio_irq_pending = true; 134 118 queue_delayed_work(system_wq, &host->sdio_irq_work, 0); 135 119 } 136 120 EXPORT_SYMBOL_GPL(sdio_signal_irq); ··· 177 159 if (ret) 178 160 break; 179 161 ret = process_sdio_pending_irqs(host); 180 - host->sdio_irq_pending = false; 181 162 mmc_release_host(host); 182 163 183 164 /*
+12
drivers/mmc/host/Kconfig
··· 154 154 155 155 If unsure, say N. 156 156 157 + config MMC_SDHCI_OF_ASPEED 158 + tristate "SDHCI OF support for the ASPEED SDHCI controller" 159 + depends on MMC_SDHCI_PLTFM 160 + depends on OF && OF_ADDRESS 161 + help 162 + This selects the ASPEED Secure Digital Host Controller Interface. 163 + 164 + If you have a controller with this interface, say Y or M here. You 165 + also need to enable an appropriate bus interface. 166 + 167 + If unsure, say N. 168 + 157 169 config MMC_SDHCI_OF_AT91 158 170 tristate "SDHCI OF support for the Atmel SDMMC controller" 159 171 depends on MMC_SDHCI_PLTFM
+1
drivers/mmc/host/Makefile
··· 84 84 obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o 85 85 obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o 86 86 obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o 87 + obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o 87 88 obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o 88 89 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o 89 90 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
+4
drivers/mmc/host/atmel-mci.c
··· 2413 2413 case 0x600: 2414 2414 case 0x500: 2415 2415 host->caps.has_odd_clk_div = 1; 2416 + /* Fall through */ 2416 2417 case 0x400: 2417 2418 case 0x300: 2418 2419 host->caps.has_dma_conf_reg = 1; ··· 2421 2420 host->caps.has_cfg_reg = 1; 2422 2421 host->caps.has_cstor_reg = 1; 2423 2422 host->caps.has_highspeed = 1; 2423 + /* Fall through */ 2424 2424 case 0x200: 2425 2425 host->caps.has_rwproof = 1; 2426 2426 host->caps.need_blksz_mul_4 = 0; 2427 2427 host->caps.need_notbusy_for_read_ops = 1; 2428 + /* Fall through */ 2428 2429 case 0x100: 2429 2430 host->caps.has_bad_data_ordering = 0; 2430 2431 host->caps.need_reset_after_xfer = 0; 2432 + /* Fall through */ 2431 2433 case 0x0: 2432 2434 break; 2433 2435 default:
+1 -2
drivers/mmc/host/bcm2835.c
··· 1314 1314 } 1315 1315 1316 1316 mmc->max_segs = 128; 1317 - mmc->max_req_size = 524288; 1317 + mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev)); 1318 1318 mmc->max_seg_size = mmc->max_req_size; 1319 1319 mmc->max_blk_size = 1024; 1320 1320 mmc->max_blk_count = 65535; ··· 1409 1409 1410 1410 host->irq = platform_get_irq(pdev, 0); 1411 1411 if (host->irq <= 0) { 1412 - dev_err(dev, "get IRQ failed\n"); 1413 1412 ret = -EINVAL; 1414 1413 goto err; 1415 1414 }
+1 -1
drivers/mmc/host/dw_mmc-hi3798cv200.c
··· 66 66 static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot, 67 67 u32 opcode) 68 68 { 69 - int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 }; 69 + static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 }; 70 70 struct dw_mci *host = slot->host; 71 71 struct hi3798cv200_priv *priv = host->priv; 72 72 int raise_point = -1, fall_point = -1;
+4
drivers/mmc/host/dw_mmc.c
··· 3460 3460 /* Force setup bus to guarantee available clock output */ 3461 3461 dw_mci_setup_bus(host->slot, true); 3462 3462 3463 + /* Re-enable SDIO interrupts. */ 3464 + if (sdio_irq_claimed(host->slot->mmc)) 3465 + __dw_mci_enable_sdio_irq(host->slot, 1); 3466 + 3463 3467 /* Now that slots are all setup, we can enable card detect */ 3464 3468 dw_mci_enable_cd(host); 3465 3469
+7 -12
drivers/mmc/host/jz4740_mmc.c
··· 25 25 26 26 #include <asm/cacheflush.h> 27 27 28 - #include <asm/mach-jz4740/dma.h> 29 - 30 28 #define JZ_REG_MMC_STRPCL 0x00 31 29 #define JZ_REG_MMC_STATUS 0x04 32 30 #define JZ_REG_MMC_CLKRT 0x08 ··· 184 186 uint32_t val) 185 187 { 186 188 if (host->version >= JZ_MMC_JZ4780) 187 - return writel(val, host->base + JZ_REG_MMC_IREG); 189 + writel(val, host->base + JZ_REG_MMC_IREG); 188 190 else 189 - return writew(val, host->base + JZ_REG_MMC_IREG); 191 + writew(val, host->base + JZ_REG_MMC_IREG); 190 192 } 191 193 192 194 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) ··· 290 292 if (data->flags & MMC_DATA_WRITE) { 291 293 conf.direction = DMA_MEM_TO_DEV; 292 294 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; 293 - conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT; 294 295 } else { 295 296 conf.direction = DMA_DEV_TO_MEM; 296 297 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; 297 - conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE; 298 298 } 299 299 300 300 sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED); ··· 816 820 del_timer(&host->timeout_timer); 817 821 818 822 if (status & JZ_MMC_STATUS_TIMEOUT_RES) { 819 - cmd->error = -ETIMEDOUT; 823 + cmd->error = -ETIMEDOUT; 820 824 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { 821 - cmd->error = -EIO; 825 + cmd->error = -EIO; 822 826 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 823 827 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 824 - if (cmd->data) 825 - cmd->data->error = -EIO; 826 - cmd->error = -EIO; 828 + if (cmd->data) 829 + cmd->data->error = -EIO; 830 + cmd->error = -EIO; 827 831 } 828 832 829 833 jz4740_mmc_set_irq_enabled(host, irq_reg, false); ··· 965 969 host->irq = platform_get_irq(pdev, 0); 966 970 if (host->irq < 0) { 967 971 ret = host->irq; 968 - dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); 969 972 goto err_free_host; 970 973 } 971 974
-1
drivers/mmc/host/meson-gx-mmc.c
··· 1091 1091 1092 1092 host->irq = platform_get_irq(pdev, 0); 1093 1093 if (host->irq <= 0) { 1094 - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1095 1094 ret = -EINVAL; 1096 1095 goto free_host; 1097 1096 }
+1 -1
drivers/mmc/host/mmc_spi.c
··· 891 891 /* Handle scatterlist segments one at a time, with synch for 892 892 * each 512-byte block 893 893 */ 894 - for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) { 894 + for_each_sg(data->sg, sg, data->sg_len, n_sg) { 895 895 int status = 0; 896 896 dma_addr_t dma_addr = 0; 897 897 void *kmap_addr;
+37 -32
drivers/mmc/host/mmci.c
··· 1219 1219 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1220 1220 return; 1221 1221 1222 - /* 1223 - * ST Micro variant: handle busy detection. 1224 - */ 1222 + /* Handle busy detection on DAT0 if the variant supports it. */ 1225 1223 if (busy_resp && host->variant->busy_detect) { 1226 1224 1227 - /* We are busy with a command, return */ 1228 - if (host->busy_status && 1229 - (status & host->variant->busy_detect_flag)) 1230 - return; 1231 - 1232 1225 /* 1233 - * We were not busy, but we now got a busy response on 1234 - * something that was not an error, and we double-check 1235 - * that the special busy status bit is still set before 1236 - * proceeding. 1226 + * Before unmasking for the busy end IRQ, confirm that the 1227 + * command was sent successfully. To keep track of having a 1228 + * command in-progress, waiting for busy signaling to end, 1229 + * store the status in host->busy_status. 1230 + * 1231 + * Note that, the card may need a couple of clock cycles before 1232 + * it starts signaling busy on DAT0, hence re-read the 1233 + * MMCISTATUS register here, to allow the busy bit to be set. 1234 + * Potentially we may even need to poll the register for a 1235 + * while, to allow it to be set, but tests indicates that it 1236 + * isn't needed. 1237 1237 */ 1238 1238 if (!host->busy_status && 1239 1239 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1240 1240 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1241 1241 1242 - /* Clear the busy start IRQ */ 1243 - writel(host->variant->busy_detect_mask, 1244 - host->base + MMCICLEAR); 1245 - 1246 - /* Unmask the busy end IRQ */ 1247 1242 writel(readl(base + MMCIMASK0) | 1248 1243 host->variant->busy_detect_mask, 1249 1244 base + MMCIMASK0); 1250 - /* 1251 - * Now cache the last response status code (until 1252 - * the busy bit goes low), and return. 1253 - */ 1245 + 1254 1246 host->busy_status = 1255 1247 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1256 1248 return; 1257 1249 } 1258 1250 1259 1251 /* 1260 - * At this point we are not busy with a command, we have 1261 - * not received a new busy request, clear and mask the busy 1262 - * end IRQ and fall through to process the IRQ. 1252 + * If there is a command in-progress that has been successfully 1253 + * sent, then bail out if busy status is set and wait for the 1254 + * busy end IRQ. 1255 + * 1256 + * Note that, the HW triggers an IRQ on both edges while 1257 + * monitoring DAT0 for busy completion, but there is only one 1258 + * status bit in MMCISTATUS for the busy state. Therefore 1259 + * both the start and the end interrupts needs to be cleared, 1260 + * one after the other. So, clear the busy start IRQ here. 1261 + */ 1262 + if (host->busy_status && 1263 + (status & host->variant->busy_detect_flag)) { 1264 + writel(host->variant->busy_detect_mask, 1265 + host->base + MMCICLEAR); 1266 + return; 1267 + } 1268 + 1269 + /* 1270 + * If there is a command in-progress that has been successfully 1271 + * sent and the busy bit isn't set, it means we have received 1272 + * the busy end IRQ. Clear and mask the IRQ, then continue to 1273 + * process the command. 1263 1274 */ 1264 1275 if (host->busy_status) { 1265 1276 ··· 1516 1505 } 1517 1506 1518 1507 /* 1519 - * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1520 - * enabled) in mmci_cmd_irq() function where ST Micro busy 1521 - * detection variant is handled. Considering the HW seems to be 1522 - * triggering the IRQ on both edges while monitoring DAT0 for 1523 - * busy completion and that same status bit is used to monitor 1524 - * start and end of busy detection, special care must be taken 1525 - * to make sure that both start and end interrupts are always 1526 - * cleared one after the other. 1508 + * Busy detection is managed by mmci_cmd_irq(), including to 1509 + * clear the corresponding IRQ. 1527 1510 */ 1528 1511 status &= readl(host->base + MMCIMASK0); 1529 1512 if (host->variant->busy_detect)
+23 -6
drivers/mmc/host/mtk-sd.c
··· 192 192 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 193 193 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 194 194 195 + #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 195 196 /* SDC_ADV_CFG0 mask */ 196 197 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 197 198 ··· 329 328 u32 ptr; 330 329 u32 bd_data_len; 331 330 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 331 + #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 332 332 }; 333 333 334 334 struct msdc_dma { ··· 643 641 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 644 642 << 28; 645 643 } 646 - bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 647 - bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 644 + 645 + if (host->dev_comp->support_64g) { 646 + bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 647 + bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 648 + } else { 649 + bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 650 + bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 651 + } 648 652 649 653 if (j == data->sg_count - 1) /* the last bd */ 650 654 bd[j].bd_info |= BDMA_DESC_EOL; ··· 1079 1071 } 1080 1072 1081 1073 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1082 - if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1083 - cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 1074 + if (events & MSDC_INT_CMDTMO || 1075 + (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1076 + cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1084 1077 /* 1085 1078 * should not clear fifo/interrupt as the tune data 1086 - * may have alreay come. 1079 + * may have alreay come when cmd19/cmd21 gets response 1080 + * CRC error. 1087 1081 */ 1088 1082 msdc_reset_hw(host); 1089 1083 if (events & MSDC_INT_RSPCRCERR) { ··· 1578 1568 1579 1569 /* Config SDIO device detect interrupt function */ 1580 1570 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1571 + sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1581 1572 1582 1573 /* Configure to default data timeout */ 1583 1574 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); ··· 2286 2275 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 2287 2276 /* MMC core transfer sizes tunable parameters */ 2288 2277 mmc->max_segs = MAX_BD_NUM; 2289 - mmc->max_seg_size = BDMA_DESC_BUFLEN; 2278 + if (host->dev_comp->support_64g) 2279 + mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2280 + else 2281 + mmc->max_seg_size = BDMA_DESC_BUFLEN; 2290 2282 mmc->max_blk_size = 2048; 2291 2283 mmc->max_req_size = 512 * 1024; 2292 2284 mmc->max_blk_count = mmc->max_req_size / 512; ··· 2435 2421 } else { 2436 2422 writel(host->save_para.pad_tune, host->base + tune_reg); 2437 2423 } 2424 + 2425 + if (sdio_irq_claimed(host->mmc)) 2426 + __msdc_enable_sdio_irq(host, 1); 2438 2427 } 2439 2428 2440 2429 static int msdc_runtime_suspend(struct device *dev)
+1 -3
drivers/mmc/host/mxcmmc.c
··· 1010 1010 1011 1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1012 1012 irq = platform_get_irq(pdev, 0); 1013 - if (irq < 0) { 1014 - dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); 1013 + if (irq < 0) 1015 1014 return irq; 1016 - } 1017 1015 1018 1016 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1019 1017 if (!mmc)
+1 -3
drivers/mmc/host/mxs-mmc.c
··· 571 571 struct device_node *np = pdev->dev.of_node; 572 572 struct mxs_mmc_host *host; 573 573 struct mmc_host *mmc; 574 - struct resource *iores; 575 574 int ret = 0, irq_err; 576 575 struct regulator *reg_vmmc; 577 576 struct mxs_ssp *ssp; ··· 586 587 host = mmc_priv(mmc); 587 588 ssp = &host->ssp; 588 589 ssp->dev = &pdev->dev; 589 - iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 590 - ssp->base = devm_ioremap_resource(&pdev->dev, iores); 590 + ssp->base = devm_platform_ioremap_resource(pdev, 0); 591 591 if (IS_ERR(ssp->base)) { 592 592 ret = PTR_ERR(ssp->base); 593 593 goto out_mmc_free;
+8 -5
drivers/mmc/host/renesas_sdhi_core.c
··· 124 124 { 125 125 struct renesas_sdhi *priv = host_to_priv(host); 126 126 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 127 - int i, ret; 127 + int i; 128 128 129 129 /* tested only on R-Car Gen2+ currently; may work for others */ 130 130 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) ··· 153 153 } 154 154 } 155 155 156 - ret = clk_set_rate(priv->clk, best_freq); 156 + clk_set_rate(priv->clk, best_freq); 157 157 158 - return ret == 0 ? best_freq : clk_get_rate(priv->clk); 158 + return clk_get_rate(priv->clk); 159 159 } 160 160 161 161 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, ··· 166 166 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 167 167 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 168 168 169 - if (new_clock == 0) 169 + if (new_clock == 0) { 170 + host->mmc->actual_clock = 0; 170 171 goto out; 172 + } 171 173 172 - clock = renesas_sdhi_clk_update(host, new_clock) / 512; 174 + host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 175 + clock = host->mmc->actual_clock / 512; 173 176 174 177 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 175 178 clock <<= 1;
-36
drivers/mmc/host/renesas_sdhi_sys_dmac.c
··· 68 68 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 69 69 }; 70 70 71 - /* Definitions for sampling clocks */ 72 - static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 73 - { 74 - .clk_rate = 0, 75 - .tap = 0x00000300, 76 - }, 77 - }; 78 - 79 - static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 80 - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 81 - TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 82 - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 83 - MMC_CAP_CMD23, 84 - .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 85 - .bus_shift = 2, 86 - .scc_offset = 0x1000, 87 - .taps = rcar_gen3_scc_taps, 88 - .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 89 - }; 90 - 91 71 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = { 92 72 { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, }, 93 73 { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, }, ··· 82 102 { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, }, 83 103 { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, }, 84 104 { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, 85 - { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, 86 - { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 87 105 { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, }, 88 106 { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, }, 89 - { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 90 107 { .compatible = "renesas,sdhi-shmobile" }, 91 108 {}, 92 109 }; ··· 447 470 .dataend = renesas_sdhi_sys_dmac_dataend_dma, 448 471 }; 449 472 450 - /* 451 - * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 452 - * implementation. Currently empty as all supported ES versions use 453 - * the internal DMAC. 454 - */ 455 - static const struct soc_device_attribute gen3_soc_whitelist[] = { 456 - { /* sentinel */ } 457 - }; 458 - 459 473 static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev) 460 474 { 461 - if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible && 462 - !soc_device_match(gen3_soc_whitelist)) 463 - return -ENODEV; 464 - 465 475 return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops); 466 476 } 467 477
-1
drivers/mmc/host/s3cmci.c
··· 1614 1614 1615 1615 host->irq = platform_get_irq(pdev, 0); 1616 1616 if (host->irq <= 0) { 1617 - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1618 1617 ret = -EINVAL; 1619 1618 goto probe_iounmap; 1620 1619 }
+4 -3
drivers/mmc/host/sdhci-cadence.c
··· 337 337 struct sdhci_pltfm_host *pltfm_host; 338 338 struct sdhci_cdns_priv *priv; 339 339 struct clk *clk; 340 - size_t priv_size; 341 340 unsigned int nr_phy_params; 342 341 int ret; 343 342 struct device *dev = &pdev->dev; 343 + static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT; 344 344 345 345 clk = devm_clk_get(dev, NULL); 346 346 if (IS_ERR(clk)) ··· 351 351 return ret; 352 352 353 353 nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); 354 - priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params; 355 - host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, priv_size); 354 + host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, 355 + struct_size(priv, phy_params, nr_phy_params)); 356 356 if (IS_ERR(host)) { 357 357 ret = PTR_ERR(host); 358 358 goto disable_clk; ··· 370 370 host->mmc_host_ops.hs400_enhanced_strobe = 371 371 sdhci_cdns_hs400_enhanced_strobe; 372 372 sdhci_enable_v4_mode(host); 373 + __sdhci_read_caps(host, &version, NULL, NULL); 373 374 374 375 sdhci_get_of_property(pdev); 375 376
+15 -19
drivers/mmc/host/sdhci-esdhc-imx.c
··· 1666 1666 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1667 1667 mmc_retune_needed(host->mmc); 1668 1668 1669 - if (!sdhci_sdio_irq_enabled(host)) { 1670 - imx_data->actual_clock = host->mmc->actual_clock; 1671 - esdhc_pltfm_set_clock(host, 0); 1672 - clk_disable_unprepare(imx_data->clk_per); 1673 - clk_disable_unprepare(imx_data->clk_ipg); 1674 - } 1669 + imx_data->actual_clock = host->mmc->actual_clock; 1670 + esdhc_pltfm_set_clock(host, 0); 1671 + clk_disable_unprepare(imx_data->clk_per); 1672 + clk_disable_unprepare(imx_data->clk_ipg); 1675 1673 clk_disable_unprepare(imx_data->clk_ahb); 1676 1674 1677 1675 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) ··· 1693 1695 if (err) 1694 1696 goto remove_pm_qos_request; 1695 1697 1696 - if (!sdhci_sdio_irq_enabled(host)) { 1697 - err = clk_prepare_enable(imx_data->clk_per); 1698 - if (err) 1699 - goto disable_ahb_clk; 1700 - err = clk_prepare_enable(imx_data->clk_ipg); 1701 - if (err) 1702 - goto disable_per_clk; 1703 - esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1704 - } 1698 + err = clk_prepare_enable(imx_data->clk_per); 1699 + if (err) 1700 + goto disable_ahb_clk; 1701 + 1702 + err = clk_prepare_enable(imx_data->clk_ipg); 1703 + if (err) 1704 + goto disable_per_clk; 1705 + 1706 + esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1705 1707 1706 1708 err = sdhci_runtime_resume_host(host, 0); 1707 1709 if (err) ··· 1713 1715 return err; 1714 1716 1715 1717 disable_ipg_clk: 1716 - if (!sdhci_sdio_irq_enabled(host)) 1717 - clk_disable_unprepare(imx_data->clk_ipg); 1718 + clk_disable_unprepare(imx_data->clk_ipg); 1718 1719 disable_per_clk: 1719 - if (!sdhci_sdio_irq_enabled(host)) 1720 - clk_disable_unprepare(imx_data->clk_per); 1720 + clk_disable_unprepare(imx_data->clk_per); 1721 1721 disable_ahb_clk: 1722 1722 clk_disable_unprepare(imx_data->clk_ahb); 1723 1723 remove_pm_qos_request:
+9
drivers/mmc/host/sdhci-iproc.c
··· 261 261 .mmc_caps = 0x00000000, 262 262 }; 263 263 264 + static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = { 265 + .ops = &sdhci_iproc_32only_ops, 266 + }; 267 + 268 + static const struct sdhci_iproc_data bcm2711_data = { 269 + .pdata = &sdhci_bcm2711_pltfm_data, 270 + }; 271 + 264 272 static const struct of_device_id sdhci_iproc_of_match[] = { 265 273 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data }, 274 + { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data }, 266 275 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data}, 267 276 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data }, 268 277 { }
-2
drivers/mmc/host/sdhci-msm.c
··· 1917 1917 /* Setup IRQ for handling power/voltage tasks with PMIC */ 1918 1918 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); 1919 1919 if (msm_host->pwr_irq < 0) { 1920 - dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", 1921 - msm_host->pwr_irq); 1922 1920 ret = msm_host->pwr_irq; 1923 1921 goto clk_disable; 1924 1922 }
+15
drivers/mmc/host/sdhci-of-arasan.c
··· 114 114 .hiword_update = true, 115 115 }; 116 116 117 + static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { 118 + .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, 119 + .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 120 + .hiword_update = false, 121 + }; 122 + 117 123 /** 118 124 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 119 125 * ··· 379 373 .pdata = &sdhci_arasan_cqe_pdata, 380 374 }; 381 375 376 + static struct sdhci_arasan_of_data intel_lgm_emmc_data = { 377 + .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, 378 + .pdata = &sdhci_arasan_cqe_pdata, 379 + }; 380 + 382 381 #ifdef CONFIG_PM_SLEEP 383 382 /** 384 383 * sdhci_arasan_suspend - Suspend method for the driver ··· 484 473 { 485 474 .compatible = "rockchip,rk3399-sdhci-5.1", 486 475 .data = &sdhci_arasan_rk3399_data, 476 + }, 477 + { 478 + .compatible = "intel,lgm-sdhci-5.1-emmc", 479 + .data = &intel_lgm_emmc_data, 487 480 }, 488 481 /* Generic compatible below here */ 489 482 {
+342
drivers/mmc/host/sdhci-of-aspeed.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* Copyright (C) 2019 ASPEED Technology Inc. */ 3 + /* Copyright (C) 2019 IBM Corp. */ 4 + 5 + #include <linux/clk.h> 6 + #include <linux/delay.h> 7 + #include <linux/device.h> 8 + #include <linux/io.h> 9 + #include <linux/mmc/host.h> 10 + #include <linux/module.h> 11 + #include <linux/of_address.h> 12 + #include <linux/of.h> 13 + #include <linux/of_platform.h> 14 + #include <linux/platform_device.h> 15 + #include <linux/spinlock.h> 16 + 17 + #include "sdhci-pltfm.h" 18 + 19 + #define ASPEED_SDC_INFO 0x00 20 + #define ASPEED_SDC_S1MMC8 BIT(25) 21 + #define ASPEED_SDC_S0MMC8 BIT(24) 22 + 23 + struct aspeed_sdc { 24 + struct clk *clk; 25 + struct resource *res; 26 + 27 + spinlock_t lock; 28 + void __iomem *regs; 29 + }; 30 + 31 + struct aspeed_sdhci { 32 + struct aspeed_sdc *parent; 33 + u32 width_mask; 34 + }; 35 + 36 + static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, 37 + struct aspeed_sdhci *sdhci, 38 + bool bus8) 39 + { 40 + u32 info; 41 + 42 + /* Set/clear 8 bit mode */ 43 + spin_lock(&sdc->lock); 44 + info = readl(sdc->regs + ASPEED_SDC_INFO); 45 + if (bus8) 46 + info |= sdhci->width_mask; 47 + else 48 + info &= ~sdhci->width_mask; 49 + writel(info, sdc->regs + ASPEED_SDC_INFO); 50 + spin_unlock(&sdc->lock); 51 + } 52 + 53 + static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 54 + { 55 + struct sdhci_pltfm_host *pltfm_host; 56 + unsigned long parent; 57 + int div; 58 + u16 clk; 59 + 60 + pltfm_host = sdhci_priv(host); 61 + parent = clk_get_rate(pltfm_host->clk); 62 + 63 + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 64 + 65 + if (clock == 0) 66 + return; 67 + 68 + if (WARN_ON(clock > host->max_clk)) 69 + clock = host->max_clk; 70 + 71 + for (div = 1; div < 256; div *= 2) { 72 + if ((parent / div) <= clock) 73 + break; 74 + } 75 + div >>= 1; 76 + 77 + clk = div << SDHCI_DIVIDER_SHIFT; 78 + 79 + sdhci_enable_clk(host, clk); 80 + } 81 + 82 + static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) 83 + { 84 + if (host->mmc->f_max) 85 + return host->mmc->f_max; 86 + 87 + return sdhci_pltfm_clk_get_max_clock(host); 88 + } 89 + 90 + static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) 91 + { 92 + struct sdhci_pltfm_host *pltfm_priv; 93 + struct aspeed_sdhci *aspeed_sdhci; 94 + struct aspeed_sdc *aspeed_sdc; 95 + u8 ctrl; 96 + 97 + pltfm_priv = sdhci_priv(host); 98 + aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); 99 + aspeed_sdc = aspeed_sdhci->parent; 100 + 101 + /* Set/clear 8-bit mode */ 102 + aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci, 103 + width == MMC_BUS_WIDTH_8); 104 + 105 + /* Set/clear 1 or 4 bit mode */ 106 + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 107 + if (width == MMC_BUS_WIDTH_4) 108 + ctrl |= SDHCI_CTRL_4BITBUS; 109 + else 110 + ctrl &= ~SDHCI_CTRL_4BITBUS; 111 + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 112 + } 113 + 114 + static const struct sdhci_ops aspeed_sdhci_ops = { 115 + .set_clock = aspeed_sdhci_set_clock, 116 + .get_max_clock = aspeed_sdhci_get_max_clock, 117 + .set_bus_width = aspeed_sdhci_set_bus_width, 118 + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 119 + .reset = sdhci_reset, 120 + .set_uhs_signaling = sdhci_set_uhs_signaling, 121 + }; 122 + 123 + static const struct sdhci_pltfm_data aspeed_sdhci_pdata = { 124 + .ops = &aspeed_sdhci_ops, 125 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 126 + }; 127 + 128 + static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, 129 + struct resource *res) 130 + { 131 + resource_size_t delta; 132 + 133 + if (!res || resource_type(res) != IORESOURCE_MEM) 134 + return -EINVAL; 135 + 136 + if (res->start < dev->parent->res->start) 137 + return -EINVAL; 138 + 139 + delta = res->start - dev->parent->res->start; 140 + if (delta & (0x100 - 1)) 141 + return -EINVAL; 142 + 143 + return (delta / 0x100) - 1; 144 + } 145 + 146 + static int aspeed_sdhci_probe(struct platform_device *pdev) 147 + { 148 + struct sdhci_pltfm_host *pltfm_host; 149 + struct aspeed_sdhci *dev; 150 + struct sdhci_host *host; 151 + struct resource *res; 152 + int slot; 153 + int ret; 154 + 155 + host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); 156 + if (IS_ERR(host)) 157 + return PTR_ERR(host); 158 + 159 + pltfm_host = sdhci_priv(host); 160 + dev = sdhci_pltfm_priv(pltfm_host); 161 + dev->parent = dev_get_drvdata(pdev->dev.parent); 162 + 163 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 164 + slot = aspeed_sdhci_calculate_slot(dev, res); 165 + 166 + if (slot < 0) 167 + return slot; 168 + else if (slot >= 2) 169 + return -EINVAL; 170 + 171 + dev_info(&pdev->dev, "Configuring for slot %d\n", slot); 172 + dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; 173 + 174 + sdhci_get_of_property(pdev); 175 + 176 + pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); 177 + if (IS_ERR(pltfm_host->clk)) 178 + return PTR_ERR(pltfm_host->clk); 179 + 180 + ret = clk_prepare_enable(pltfm_host->clk); 181 + if (ret) { 182 + dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); 183 + goto err_pltfm_free; 184 + } 185 + 186 + ret = mmc_of_parse(host->mmc); 187 + if (ret) 188 + goto err_sdhci_add; 189 + 190 + ret = sdhci_add_host(host); 191 + if (ret) 192 + goto err_sdhci_add; 193 + 194 + return 0; 195 + 196 + err_sdhci_add: 197 + clk_disable_unprepare(pltfm_host->clk); 198 + err_pltfm_free: 199 + sdhci_pltfm_free(pdev); 200 + return ret; 201 + } 202 + 203 + static int aspeed_sdhci_remove(struct platform_device *pdev) 204 + { 205 + struct sdhci_pltfm_host *pltfm_host; 206 + struct sdhci_host *host; 207 + int dead = 0; 208 + 209 + host = platform_get_drvdata(pdev); 210 + pltfm_host = sdhci_priv(host); 211 + 212 + sdhci_remove_host(host, dead); 213 + 214 + clk_disable_unprepare(pltfm_host->clk); 215 + 216 + sdhci_pltfm_free(pdev); 217 + 218 + return 0; 219 + } 220 + 221 + static const struct of_device_id aspeed_sdhci_of_match[] = { 222 + { .compatible = "aspeed,ast2400-sdhci", }, 223 + { .compatible = "aspeed,ast2500-sdhci", }, 224 + { .compatible = "aspeed,ast2600-sdhci", }, 225 + { } 226 + }; 227 + 228 + static struct platform_driver aspeed_sdhci_driver = { 229 + .driver = { 230 + .name = "sdhci-aspeed", 231 + .of_match_table = aspeed_sdhci_of_match, 232 + }, 233 + .probe = aspeed_sdhci_probe, 234 + .remove = aspeed_sdhci_remove, 235 + }; 236 + 237 + static int aspeed_sdc_probe(struct platform_device *pdev) 238 + 239 + { 240 + struct device_node *parent, *child; 241 + struct aspeed_sdc *sdc; 242 + int ret; 243 + 244 + sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); 245 + if (!sdc) 246 + return -ENOMEM; 247 + 248 + spin_lock_init(&sdc->lock); 249 + 250 + sdc->clk = devm_clk_get(&pdev->dev, NULL); 251 + if (IS_ERR(sdc->clk)) 252 + return PTR_ERR(sdc->clk); 253 + 254 + ret = clk_prepare_enable(sdc->clk); 255 + if (ret) { 256 + dev_err(&pdev->dev, "Unable to enable SDCLK\n"); 257 + return ret; 258 + } 259 + 260 + sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 261 + sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res); 262 + if (IS_ERR(sdc->regs)) { 263 + ret = PTR_ERR(sdc->regs); 264 + goto err_clk; 265 + } 266 + 267 + dev_set_drvdata(&pdev->dev, sdc); 268 + 269 + parent = pdev->dev.of_node; 270 + for_each_available_child_of_node(parent, child) { 271 + struct platform_device *cpdev; 272 + 273 + cpdev = of_platform_device_create(child, NULL, &pdev->dev); 274 + if (!cpdev) { 275 + of_node_put(child); 276 + ret = -ENODEV; 277 + goto err_clk; 278 + } 279 + } 280 + 281 + return 0; 282 + 283 + err_clk: 284 + clk_disable_unprepare(sdc->clk); 285 + return ret; 286 + } 287 + 288 + static int aspeed_sdc_remove(struct platform_device *pdev) 289 + { 290 + struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); 291 + 292 + clk_disable_unprepare(sdc->clk); 293 + 294 + return 0; 295 + } 296 + 297 + static const struct of_device_id aspeed_sdc_of_match[] = { 298 + { .compatible = "aspeed,ast2400-sd-controller", }, 299 + { .compatible = "aspeed,ast2500-sd-controller", }, 300 + { .compatible = "aspeed,ast2600-sd-controller", }, 301 + { } 302 + }; 303 + 304 + MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); 305 + 306 + static struct platform_driver aspeed_sdc_driver = { 307 + .driver = { 308 + .name = "sd-controller-aspeed", 309 + .pm = &sdhci_pltfm_pmops, 310 + .of_match_table = aspeed_sdc_of_match, 311 + }, 312 + .probe = aspeed_sdc_probe, 313 + .remove = aspeed_sdc_remove, 314 + }; 315 + 316 + static int __init aspeed_sdc_init(void) 317 + { 318 + int rc; 319 + 320 + rc = platform_driver_register(&aspeed_sdhci_driver); 321 + if (rc < 0) 322 + return rc; 323 + 324 + rc = platform_driver_register(&aspeed_sdc_driver); 325 + if (rc < 0) 326 + platform_driver_unregister(&aspeed_sdhci_driver); 327 + 328 + return rc; 329 + } 330 + module_init(aspeed_sdc_init); 331 + 332 + static void __exit aspeed_sdc_exit(void) 333 + { 334 + platform_driver_unregister(&aspeed_sdc_driver); 335 + platform_driver_unregister(&aspeed_sdhci_driver); 336 + } 337 + module_exit(aspeed_sdc_exit); 338 + 339 + MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); 340 + MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); 341 + MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); 342 + MODULE_LICENSE("GPL");
+1
drivers/mmc/host/sdhci-of-esdhc.c
··· 999 999 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1000 1000 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1001 1001 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1002 + { .family = "QorIQ LS1028A", .revision = "1.0", }, 1002 1003 { }, 1003 1004 }; 1004 1005
+5 -8
drivers/mmc/host/sdhci-pci-core.c
··· 1672 1672 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1673 1673 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1674 1674 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1675 + SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1675 1676 SDHCI_PCI_DEVICE(O2, 8120, o2), 1676 1677 SDHCI_PCI_DEVICE(O2, 8220, o2), 1677 1678 SDHCI_PCI_DEVICE(O2, 8221, o2), ··· 1760 1759 #ifdef CONFIG_PM_SLEEP 1761 1760 static int sdhci_pci_suspend(struct device *dev) 1762 1761 { 1763 - struct pci_dev *pdev = to_pci_dev(dev); 1764 - struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1762 + struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1765 1763 1766 1764 if (!chip) 1767 1765 return 0; ··· 1773 1773 1774 1774 static int sdhci_pci_resume(struct device *dev) 1775 1775 { 1776 - struct pci_dev *pdev = to_pci_dev(dev); 1777 - struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1776 + struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1778 1777 1779 1778 if (!chip) 1780 1779 return 0; ··· 1788 1789 #ifdef CONFIG_PM 1789 1790 static int sdhci_pci_runtime_suspend(struct device *dev) 1790 1791 { 1791 - struct pci_dev *pdev = to_pci_dev(dev); 1792 - struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1792 + struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1793 1793 1794 1794 if (!chip) 1795 1795 return 0; ··· 1801 1803 1802 1804 static int sdhci_pci_runtime_resume(struct device *dev) 1803 1805 { 1804 - struct pci_dev *pdev = to_pci_dev(dev); 1805 - struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 1806 + struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1806 1807 1807 1808 if (!chip) 1808 1809 return 0;
+216 -95
drivers/mmc/host/sdhci-pci-o2micro.c
··· 11 11 #include <linux/mmc/host.h> 12 12 #include <linux/mmc/mmc.h> 13 13 #include <linux/delay.h> 14 + #include <linux/iopoll.h> 14 15 15 16 #include "sdhci.h" 16 17 #include "sdhci-pci.h" ··· 52 51 #define O2_SD_VENDOR_SETTING2 0x1C8 53 52 #define O2_SD_HW_TUNING_DISABLE BIT(4) 54 53 55 - #define O2_PLL_WDT_CONTROL1 0x1CC 54 + #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 56 55 #define O2_PLL_FORCE_ACTIVE BIT(18) 57 56 #define O2_PLL_LOCK_STATUS BIT(14) 58 57 #define O2_PLL_SOFT_RESET BIT(12) 58 + #define O2_DLL_LOCK_STATUS BIT(11) 59 59 60 60 #define O2_SD_DETECT_SETTING 0x324 61 + 62 + static const u32 dmdn_table[] = {0x2B1C0000, 63 + 0x2C1A0000, 0x371B0000, 0x35100000}; 64 + #define DMDN_SZ ARRAY_SIZE(dmdn_table) 65 + 66 + struct o2_host { 67 + u8 dll_adjust_count; 68 + }; 69 + 70 + static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 71 + { 72 + ktime_t timeout; 73 + u32 scratch32; 74 + 75 + /* Wait max 50 ms */ 76 + timeout = ktime_add_ms(ktime_get(), 50); 77 + while (1) { 78 + bool timedout = ktime_after(ktime_get(), timeout); 79 + 80 + scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 81 + if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 82 + == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 83 + break; 84 + 85 + if (timedout) { 86 + pr_err("%s: Card Detect debounce never finished.\n", 87 + mmc_hostname(host->mmc)); 88 + sdhci_dumpregs(host); 89 + return; 90 + } 91 + udelay(10); 92 + } 93 + } 94 + 95 + static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 96 + { 97 + ktime_t timeout; 98 + u16 scratch; 99 + u32 scratch32; 100 + 101 + /* PLL software reset */ 102 + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 103 + scratch32 |= O2_PLL_SOFT_RESET; 104 + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 105 + udelay(1); 106 + scratch32 &= ~(O2_PLL_SOFT_RESET); 107 + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 108 + 109 + /* PLL force active */ 110 + scratch32 |= O2_PLL_FORCE_ACTIVE; 111 + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 112 + 113 + /* Wait max 20 ms */ 114 + timeout = ktime_add_ms(ktime_get(), 20); 115 + while (1) { 116 + bool timedout = ktime_after(ktime_get(), timeout); 117 + 118 + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 119 + if (scratch & O2_PLL_LOCK_STATUS) 120 + break; 121 + if (timedout) { 122 + pr_err("%s: Internal clock never stabilised.\n", 123 + mmc_hostname(host->mmc)); 124 + sdhci_dumpregs(host); 125 + goto out; 126 + } 127 + udelay(10); 128 + } 129 + 130 + /* Wait for card detect finish */ 131 + udelay(1); 132 + sdhci_o2_wait_card_detect_stable(host); 133 + 134 + out: 135 + /* Cancel PLL force active */ 136 + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 137 + scratch32 &= ~O2_PLL_FORCE_ACTIVE; 138 + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 139 + } 140 + 141 + static int sdhci_o2_get_cd(struct mmc_host *mmc) 142 + { 143 + struct sdhci_host *host = mmc_priv(mmc); 144 + 145 + if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 146 + sdhci_o2_enable_internal_clock(host); 147 + 148 + return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 149 + } 150 + 151 + static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 152 + { 153 + u32 scratch_32; 154 + 155 + pci_read_config_dword(chip->pdev, 156 + O2_SD_PLL_SETTING, &scratch_32); 157 + 158 + scratch_32 &= 0x0000FFFF; 159 + scratch_32 |= value; 160 + 161 + pci_write_config_dword(chip->pdev, 162 + O2_SD_PLL_SETTING, scratch_32); 163 + } 164 + 165 + static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 166 + { 167 + return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 168 + } 169 + 170 + /* 171 + * This function is used to detect dll lock status. 172 + * Since the dll lock status bit will toggle randomly 173 + * with very short interval which needs to be polled 174 + * as fast as possible. Set sleep_us as 1 microsecond. 175 + */ 176 + static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 177 + { 178 + u32 scratch32 = 0; 179 + 180 + return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 181 + scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 182 + } 61 183 62 184 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 63 185 { ··· 219 95 sdhci_reset_tuning(host); 220 96 } 221 97 98 + /* 99 + * This function is used to fix o2 dll shift issue. 100 + * It isn't necessary to detect card present before recovery. 101 + * Firstly, it is used by bht emmc card, which is embedded. 102 + * Second, before call recovery card present will be detected 103 + * outside of the execute tuning function. 104 + */ 105 + static int sdhci_o2_dll_recovery(struct sdhci_host *host) 106 + { 107 + int ret = 0; 108 + u8 scratch_8 = 0; 109 + u32 scratch_32 = 0; 110 + struct sdhci_pci_slot *slot = sdhci_priv(host); 111 + struct sdhci_pci_chip *chip = slot->chip; 112 + struct o2_host *o2_host = sdhci_pci_priv(slot); 113 + 114 + /* UnLock WP */ 115 + pci_read_config_byte(chip->pdev, 116 + O2_SD_LOCK_WP, &scratch_8); 117 + scratch_8 &= 0x7f; 118 + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 119 + while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 120 + /* Disable clock */ 121 + sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 122 + 123 + /* PLL software reset */ 124 + scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 125 + scratch_32 |= O2_PLL_SOFT_RESET; 126 + sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 127 + 128 + pci_read_config_dword(chip->pdev, 129 + O2_SD_FUNC_REG4, 130 + &scratch_32); 131 + /* Enable Base Clk setting change */ 132 + scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 133 + pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 134 + o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 135 + 136 + /* Enable internal clock */ 137 + scratch_8 = SDHCI_CLOCK_INT_EN; 138 + sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 139 + 140 + if (sdhci_o2_get_cd(host->mmc)) { 141 + /* 142 + * need wait at least 5ms for dll status stable, 143 + * after enable internal clock 144 + */ 145 + usleep_range(5000, 6000); 146 + if (sdhci_o2_wait_dll_detect_lock(host)) { 147 + scratch_8 |= SDHCI_CLOCK_CARD_EN; 148 + sdhci_writeb(host, scratch_8, 149 + SDHCI_CLOCK_CONTROL); 150 + ret = 1; 151 + } else { 152 + pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 153 + mmc_hostname(host->mmc), 154 + o2_host->dll_adjust_count); 155 + } 156 + } else { 157 + pr_err("%s: card present detect failed.\n", 158 + mmc_hostname(host->mmc)); 159 + break; 160 + } 161 + 162 + o2_host->dll_adjust_count++; 163 + } 164 + if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 165 + pr_err("%s: DLL adjust over max times\n", 166 + mmc_hostname(host->mmc)); 167 + /* Lock WP */ 168 + pci_read_config_byte(chip->pdev, 169 + O2_SD_LOCK_WP, &scratch_8); 170 + scratch_8 |= 0x80; 171 + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 172 + return ret; 173 + } 174 + 222 175 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 223 176 { 224 177 struct sdhci_host *host = mmc_priv(mmc); ··· 310 109 311 110 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) 312 111 return -EINVAL; 313 - 112 + /* 113 + * Judge the tuning reason, whether caused by dll shift 114 + * If cause by dll shift, should call sdhci_o2_dll_recovery 115 + */ 116 + if (!sdhci_o2_wait_dll_detect_lock(host)) 117 + if (!sdhci_o2_dll_recovery(host)) { 118 + pr_err("%s: o2 dll recovery failed\n", 119 + mmc_hostname(host->mmc)); 120 + return -EINVAL; 121 + } 314 122 /* 315 123 * o2 sdhci host didn't support 8bit emmc tuning 316 124 */ ··· 344 134 345 135 host->flags &= ~SDHCI_HS400_TUNING; 346 136 return 0; 347 - } 348 - 349 - static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 350 - { 351 - u32 scratch_32; 352 - pci_read_config_dword(chip->pdev, 353 - O2_SD_PLL_SETTING, &scratch_32); 354 - 355 - scratch_32 &= 0x0000FFFF; 356 - scratch_32 |= value; 357 - 358 - pci_write_config_dword(chip->pdev, 359 - O2_SD_PLL_SETTING, scratch_32); 360 137 } 361 138 362 139 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) ··· 481 284 host->irq = pci_irq_vector(chip->pdev, 0); 482 285 } 483 286 484 - static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 485 - { 486 - ktime_t timeout; 487 - u32 scratch32; 488 - 489 - /* Wait max 50 ms */ 490 - timeout = ktime_add_ms(ktime_get(), 50); 491 - while (1) { 492 - bool timedout = ktime_after(ktime_get(), timeout); 493 - 494 - scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 495 - if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 496 - == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 497 - break; 498 - 499 - if (timedout) { 500 - pr_err("%s: Card Detect debounce never finished.\n", 501 - mmc_hostname(host->mmc)); 502 - sdhci_dumpregs(host); 503 - return; 504 - } 505 - udelay(10); 506 - } 507 - } 508 - 509 - static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 510 - { 511 - ktime_t timeout; 512 - u16 scratch; 513 - u32 scratch32; 514 - 515 - /* PLL software reset */ 516 - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 517 - scratch32 |= O2_PLL_SOFT_RESET; 518 - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 519 - udelay(1); 520 - scratch32 &= ~(O2_PLL_SOFT_RESET); 521 - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 522 - 523 - /* PLL force active */ 524 - scratch32 |= O2_PLL_FORCE_ACTIVE; 525 - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 526 - 527 - /* Wait max 20 ms */ 528 - timeout = ktime_add_ms(ktime_get(), 20); 529 - while (1) { 530 - bool timedout = ktime_after(ktime_get(), timeout); 531 - 532 - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1); 533 - if (scratch & O2_PLL_LOCK_STATUS) 534 - break; 535 - if (timedout) { 536 - pr_err("%s: Internal clock never stabilised.\n", 537 - mmc_hostname(host->mmc)); 538 - sdhci_dumpregs(host); 539 - goto out; 540 - } 541 - udelay(10); 542 - } 543 - 544 - /* Wait for card detect finish */ 545 - udelay(1); 546 - sdhci_o2_wait_card_detect_stable(host); 547 - 548 - out: 549 - /* Cancel PLL force active */ 550 - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 551 - scratch32 &= ~O2_PLL_FORCE_ACTIVE; 552 - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 553 - } 554 - 555 - static int sdhci_o2_get_cd(struct mmc_host *mmc) 556 - { 557 - struct sdhci_host *host = mmc_priv(mmc); 558 - 559 - sdhci_o2_enable_internal_clock(host); 560 - 561 - return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 562 - } 563 - 564 287 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 565 288 { 566 289 /* Enable internal clock */ 567 290 clk |= SDHCI_CLOCK_INT_EN; 568 291 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 569 292 293 + sdhci_o2_enable_internal_clock(host); 570 294 if (sdhci_o2_get_cd(host->mmc)) { 571 295 clk |= SDHCI_CLOCK_CARD_EN; 572 296 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ··· 513 395 { 514 396 struct sdhci_pci_chip *chip; 515 397 struct sdhci_host *host; 398 + struct o2_host *o2_host = sdhci_pci_priv(slot); 516 399 u32 reg, caps; 517 400 int ret; 518 401 519 402 chip = slot->chip; 520 403 host = slot->host; 521 404 405 + o2_host->dll_adjust_count = 0; 522 406 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 523 407 524 408 /* ··· 807 687 .resume = sdhci_pci_o2_resume, 808 688 #endif 809 689 .ops = &sdhci_pci_o2_ops, 690 + .priv_size = sizeof(struct o2_host), 810 691 };
+1
drivers/mmc/host/sdhci-pci.h
··· 54 54 #define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48 55 55 #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4 56 56 #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5 57 + #define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5 57 58 58 59 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 59 60 #define PCI_DEVICE_ID_VIA_95D0 0x95d0
+1 -4
drivers/mmc/host/sdhci-pltfm.c
··· 118 118 size_t priv_size) 119 119 { 120 120 struct sdhci_host *host; 121 - struct resource *iomem; 122 121 void __iomem *ioaddr; 123 122 int irq, ret; 124 123 125 - iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 126 - ioaddr = devm_ioremap_resource(&pdev->dev, iomem); 124 + ioaddr = devm_platform_ioremap_resource(pdev, 0); 127 125 if (IS_ERR(ioaddr)) { 128 126 ret = PTR_ERR(ioaddr); 129 127 goto err; ··· 129 131 130 132 irq = platform_get_irq(pdev, 0); 131 133 if (irq < 0) { 132 - dev_err(&pdev->dev, "failed to get IRQ number\n"); 133 134 ret = irq; 134 135 goto err; 135 136 }
+2 -3
drivers/mmc/host/sdhci-s3c.c
··· 490 490 } 491 491 492 492 irq = platform_get_irq(pdev, 0); 493 - if (irq < 0) { 494 - dev_err(dev, "no irq specified\n"); 493 + if (irq < 0) 495 494 return irq; 496 - } 497 495 498 496 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 499 497 if (IS_ERR(host)) { ··· 609 611 switch (pdata->max_width) { 610 612 case 8: 611 613 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 614 + /* Fall through */ 612 615 case 4: 613 616 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 614 617 break;
+48 -28
drivers/mmc/host/sdhci.c
··· 668 668 /* 32-bit and 64-bit descriptors have these members in same position */ 669 669 dma_desc->cmd = cpu_to_le16(cmd); 670 670 dma_desc->len = cpu_to_le16(len); 671 - dma_desc->addr_lo = cpu_to_le32((u32)addr); 671 + dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr)); 672 672 673 673 if (host->flags & SDHCI_USE_64_BIT_DMA) 674 - dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 674 + dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr)); 675 675 676 676 *desc += host->desc_sz; 677 677 } ··· 816 816 } 817 817 } 818 818 819 + static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr) 820 + { 821 + sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS); 822 + if (host->flags & SDHCI_USE_64_BIT_DMA) 823 + sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); 824 + } 825 + 819 826 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) 820 827 { 821 828 if (host->bounce_buffer) ··· 833 826 834 827 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) 835 828 { 836 - if (host->v4_mode) { 837 - sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); 838 - if (host->flags & SDHCI_USE_64_BIT_DMA) 839 - sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); 840 - } else { 829 + if (host->v4_mode) 830 + sdhci_set_adma_addr(host, addr); 831 + else 841 832 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); 842 - } 843 833 } 844 834 845 835 static unsigned int sdhci_target_timeout(struct sdhci_host *host, ··· 1099 1095 host->flags &= ~SDHCI_REQ_USE_DMA; 1100 1096 } else if (host->flags & SDHCI_USE_ADMA) { 1101 1097 sdhci_adma_table_pre(host, data, sg_cnt); 1102 - 1103 - sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 1104 - if (host->flags & SDHCI_USE_64_BIT_DMA) 1105 - sdhci_writel(host, 1106 - (u64)host->adma_addr >> 32, 1107 - SDHCI_ADMA_ADDRESS_HI); 1098 + sdhci_set_adma_addr(host, host->adma_addr); 1108 1099 } else { 1109 1100 WARN_ON(sg_cnt != 1); 1110 1101 sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); ··· 1635 1636 clk |= SDHCI_CLOCK_INT_EN; 1636 1637 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1637 1638 1638 - /* Wait max 20 ms */ 1639 - timeout = ktime_add_ms(ktime_get(), 20); 1639 + /* Wait max 150 ms */ 1640 + timeout = ktime_add_ms(ktime_get(), 150); 1640 1641 while (1) { 1641 1642 bool timedout = ktime_after(ktime_get(), timeout); 1642 1643 ··· 1650 1651 return; 1651 1652 } 1652 1653 udelay(10); 1654 + } 1655 + 1656 + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { 1657 + clk |= SDHCI_CLOCK_PLL_EN; 1658 + clk &= ~SDHCI_CLOCK_INT_STABLE; 1659 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1660 + 1661 + /* Wait max 150 ms */ 1662 + timeout = ktime_add_ms(ktime_get(), 150); 1663 + while (1) { 1664 + bool timedout = ktime_after(ktime_get(), timeout); 1665 + 1666 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1667 + if (clk & SDHCI_CLOCK_INT_STABLE) 1668 + break; 1669 + if (timedout) { 1670 + pr_err("%s: PLL clock never stabilised.\n", 1671 + mmc_hostname(host->mmc)); 1672 + sdhci_dumpregs(host); 1673 + return; 1674 + } 1675 + udelay(10); 1676 + } 1653 1677 } 1654 1678 1655 1679 clk |= SDHCI_CLOCK_CARD_EN; ··· 1871 1849 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1872 1850 else if (timing == MMC_TIMING_UHS_SDR12) 1873 1851 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1874 - else if (timing == MMC_TIMING_UHS_SDR25) 1852 + else if (timing == MMC_TIMING_SD_HS || 1853 + timing == MMC_TIMING_MMC_HS || 1854 + timing == MMC_TIMING_UHS_SDR25) 1875 1855 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1876 1856 else if (timing == MMC_TIMING_UHS_SDR50) 1877 1857 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; ··· 2144 2120 pm_runtime_get_noresume(host->mmc->parent); 2145 2121 2146 2122 spin_lock_irqsave(&host->lock, flags); 2147 - if (enable) 2148 - host->flags |= SDHCI_SDIO_IRQ_ENABLED; 2149 - else 2150 - host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 2151 - 2152 2123 sdhci_enable_sdio_irq_nolock(host, enable); 2153 2124 spin_unlock_irqrestore(&host->lock, flags); 2154 2125 ··· 2158 2139 unsigned long flags; 2159 2140 2160 2141 spin_lock_irqsave(&host->lock, flags); 2161 - if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2162 - sdhci_enable_sdio_irq_nolock(host, true); 2142 + sdhci_enable_sdio_irq_nolock(host, true); 2163 2143 spin_unlock_irqrestore(&host->lock, flags); 2164 2144 } 2165 2145 ··· 2323 2305 } 2324 2306 EXPORT_SYMBOL_GPL(sdhci_reset_tuning); 2325 2307 2326 - static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) 2308 + void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) 2327 2309 { 2328 2310 sdhci_reset_tuning(host); 2329 2311 ··· 2334 2316 2335 2317 mmc_abort_tuning(host->mmc, opcode); 2336 2318 } 2319 + EXPORT_SYMBOL_GPL(sdhci_abort_tuning); 2337 2320 2338 2321 /* 2339 2322 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI ··· 3043 3024 3044 3025 spin_lock(&host->lock); 3045 3026 3046 - if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 3027 + if (host->runtime_suspended) { 3047 3028 spin_unlock(&host->lock); 3048 3029 return IRQ_NONE; 3049 3030 } ··· 3377 3358 host->runtime_suspended = false; 3378 3359 3379 3360 /* Enable SDIO IRQ */ 3380 - if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 3361 + if (sdio_irq_claimed(mmc)) 3381 3362 sdhci_enable_sdio_irq_nolock(host, true); 3382 3363 3383 3364 /* Enable Card Detection */ ··· 3584 3565 return ret; 3585 3566 } 3586 3567 3587 - void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 3568 + void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 3569 + const u32 *caps, const u32 *caps1) 3588 3570 { 3589 3571 u16 v; 3590 3572 u64 dt_caps_mask = 0;
+4 -8
drivers/mmc/host/sdhci.h
··· 114 114 #define SDHCI_DIV_HI_MASK 0x300 115 115 #define SDHCI_PROG_CLOCK_MODE 0x0020 116 116 #define SDHCI_CLOCK_CARD_EN 0x0004 117 + #define SDHCI_CLOCK_PLL_EN 0x0008 117 118 #define SDHCI_CLOCK_INT_STABLE 0x0002 118 119 #define SDHCI_CLOCK_INT_EN 0x0001 119 120 ··· 512 511 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 513 512 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 514 513 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 515 - #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 516 514 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 517 515 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 518 516 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ ··· 738 738 } 739 739 740 740 void sdhci_card_detect(struct sdhci_host *host); 741 - void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 742 - u32 *caps1); 741 + void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 742 + const u32 *caps, const u32 *caps1); 743 743 int sdhci_setup_host(struct sdhci_host *host); 744 744 void sdhci_cleanup_host(struct sdhci_host *host); 745 745 int __sdhci_add_host(struct sdhci_host *host); ··· 750 750 static inline void sdhci_read_caps(struct sdhci_host *host) 751 751 { 752 752 __sdhci_read_caps(host, NULL, NULL, NULL); 753 - } 754 - 755 - static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 756 - { 757 - return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 758 753 } 759 754 760 755 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, ··· 791 796 void sdhci_end_tuning(struct sdhci_host *host); 792 797 void sdhci_reset_tuning(struct sdhci_host *host); 793 798 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 799 + void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 794 800 795 801 #endif /* __SDHCI_HW_H */
+1 -3
drivers/mmc/host/sdhci_f_sdh30.c
··· 119 119 u32 reg = 0; 120 120 121 121 irq = platform_get_irq(pdev, 0); 122 - if (irq < 0) { 123 - dev_err(dev, "%s: no irq specified\n", __func__); 122 + if (irq < 0) 124 123 return irq; 125 - } 126 124 127 125 host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv)); 128 126 if (IS_ERR(host))
+1 -3
drivers/mmc/host/uniphier-sd.c
··· 557 557 int irq, ret; 558 558 559 559 irq = platform_get_irq(pdev, 0); 560 - if (irq < 0) { 561 - dev_err(dev, "failed to get IRQ number"); 560 + if (irq < 0) 562 561 return irq; 563 - } 564 562 565 563 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 566 564 if (!priv)
+10
include/linux/mmc/host.h
··· 128 128 int (*get_cd)(struct mmc_host *host); 129 129 130 130 void (*enable_sdio_irq)(struct mmc_host *host, int enable); 131 + /* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */ 131 132 void (*ack_sdio_irq)(struct mmc_host *host); 132 133 133 134 /* optional callback for HC quirks */ ··· 493 492 void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); 494 493 495 494 void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); 495 + 496 + /* 497 + * May be called from host driver's system/runtime suspend/resume callbacks, 498 + * to know if SDIO IRQs has been claimed. 499 + */ 500 + static inline bool sdio_irq_claimed(struct mmc_host *host) 501 + { 502 + return host->sdio_irqs > 0; 503 + } 496 504 497 505 static inline void mmc_signal_sdio_irq(struct mmc_host *host) 498 506 {
+2
include/linux/pci_ids.h
··· 2405 2405 #define PCI_DEVICE_ID_RDC_R6061 0x6061 2406 2406 #define PCI_DEVICE_ID_RDC_D1010 0x1010 2407 2407 2408 + #define PCI_VENDOR_ID_GLI 0x17a0 2409 + 2408 2410 #define PCI_VENDOR_ID_LENOVO 0x17aa 2409 2411 2410 2412 #define PCI_VENDOR_ID_QCOM 0x17cb