Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: fsl_micfil: Add i.MX943 platform support
On i.MX943, the FIFO data address is changed to 0x20~0x3c,
compared to previous version, there is a minus 4 offset,
so add a new regmap configuration for it.
And the bit width of CICOSR is changed to 5 bits, from bit
16th to 20th in REG_MICFIL_CTRL2 register, so update its
definition header file.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/20250114102720.3664667-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Shengjiu Wang
and committed by
Mark Brown
eab69050
9d499259
+78
-22
+77
-21
sound/soc/fsl/fsl_micfil.c
+77
-21
sound/soc/fsl/fsl_micfil.c
···
89
89
bool use_verid;
90
90
bool volume_sx;
91
91
u64 formats;
92
+
int fifo_offset;
92
93
};
93
94
94
95
static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
···
99
98
.dataline = 0xf,
100
99
.formats = SNDRV_PCM_FMTBIT_S16_LE,
101
100
.volume_sx = true,
101
+
.fifo_offset = 0,
102
102
};
103
103
104
104
static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
···
109
107
.dataline = 0xf,
110
108
.formats = SNDRV_PCM_FMTBIT_S32_LE,
111
109
.volume_sx = false,
110
+
.fifo_offset = 0,
112
111
};
113
112
114
113
static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
···
121
118
.use_edma = true,
122
119
.use_verid = true,
123
120
.volume_sx = false,
121
+
.fifo_offset = 0,
122
+
};
123
+
124
+
static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
125
+
.imx = true,
126
+
.fifos = 8,
127
+
.fifo_depth = 32,
128
+
.dataline = 0xf,
129
+
.formats = SNDRV_PCM_FMTBIT_S32_LE,
130
+
.use_edma = true,
131
+
.use_verid = true,
132
+
.volume_sx = false,
133
+
.fifo_offset = -4,
124
134
};
125
135
126
136
static const struct of_device_id fsl_micfil_dt_ids[] = {
127
137
{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
128
138
{ .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
129
139
{ .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
140
+
{ .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
130
141
{}
131
142
};
132
143
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
···
810
793
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
811
794
MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
812
795
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
813
-
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
796
+
FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
814
797
815
798
/* Configure CIC OSR in VADCICOSR */
816
799
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
···
949
932
{REG_MICFIL_VAD0_ZCD, 0x00000004},
950
933
};
951
934
935
+
static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
936
+
{REG_MICFIL_CTRL1, 0x00000000},
937
+
{REG_MICFIL_CTRL2, 0x00000000},
938
+
{REG_MICFIL_STAT, 0x00000000},
939
+
{REG_MICFIL_FIFO_CTRL, 0x0000001F},
940
+
{REG_MICFIL_FIFO_STAT, 0x00000000},
941
+
{REG_MICFIL_DATACH0 - 0x4, 0x00000000},
942
+
{REG_MICFIL_DATACH1 - 0x4, 0x00000000},
943
+
{REG_MICFIL_DATACH2 - 0x4, 0x00000000},
944
+
{REG_MICFIL_DATACH3 - 0x4, 0x00000000},
945
+
{REG_MICFIL_DATACH4 - 0x4, 0x00000000},
946
+
{REG_MICFIL_DATACH5 - 0x4, 0x00000000},
947
+
{REG_MICFIL_DATACH6 - 0x4, 0x00000000},
948
+
{REG_MICFIL_DATACH7 - 0x4, 0x00000000},
949
+
{REG_MICFIL_DC_CTRL, 0x00000000},
950
+
{REG_MICFIL_OUT_CTRL, 0x00000000},
951
+
{REG_MICFIL_OUT_STAT, 0x00000000},
952
+
{REG_MICFIL_VAD0_CTRL1, 0x00000000},
953
+
{REG_MICFIL_VAD0_CTRL2, 0x000A0000},
954
+
{REG_MICFIL_VAD0_STAT, 0x00000000},
955
+
{REG_MICFIL_VAD0_SCONFIG, 0x00000000},
956
+
{REG_MICFIL_VAD0_NCONFIG, 0x80000000},
957
+
{REG_MICFIL_VAD0_NDATA, 0x00000000},
958
+
{REG_MICFIL_VAD0_ZCD, 0x00000004},
959
+
};
960
+
952
961
static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
953
962
{
954
963
struct fsl_micfil *micfil = dev_get_drvdata(dev);
964
+
int ofs = micfil->soc->fifo_offset;
965
+
966
+
if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
967
+
return true;
955
968
956
969
switch (reg) {
957
970
case REG_MICFIL_CTRL1:
···
989
942
case REG_MICFIL_STAT:
990
943
case REG_MICFIL_FIFO_CTRL:
991
944
case REG_MICFIL_FIFO_STAT:
992
-
case REG_MICFIL_DATACH0:
993
-
case REG_MICFIL_DATACH1:
994
-
case REG_MICFIL_DATACH2:
995
-
case REG_MICFIL_DATACH3:
996
-
case REG_MICFIL_DATACH4:
997
-
case REG_MICFIL_DATACH5:
998
-
case REG_MICFIL_DATACH6:
999
-
case REG_MICFIL_DATACH7:
1000
945
case REG_MICFIL_DC_CTRL:
1001
946
case REG_MICFIL_OUT_CTRL:
1002
947
case REG_MICFIL_OUT_STAT:
···
1042
1003
1043
1004
static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1044
1005
{
1006
+
struct fsl_micfil *micfil = dev_get_drvdata(dev);
1007
+
int ofs = micfil->soc->fifo_offset;
1008
+
1009
+
if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1010
+
return true;
1011
+
1045
1012
switch (reg) {
1046
1013
case REG_MICFIL_STAT:
1047
1014
case REG_MICFIL_FIFO_STAT:
1048
-
case REG_MICFIL_DATACH0:
1049
-
case REG_MICFIL_DATACH1:
1050
-
case REG_MICFIL_DATACH2:
1051
-
case REG_MICFIL_DATACH3:
1052
-
case REG_MICFIL_DATACH4:
1053
-
case REG_MICFIL_DATACH5:
1054
-
case REG_MICFIL_DATACH6:
1055
-
case REG_MICFIL_DATACH7:
1056
1015
case REG_MICFIL_OUT_STAT:
1057
1016
case REG_MICFIL_VERID:
1058
1017
case REG_MICFIL_PARAM:
···
1070
1033
.max_register = REG_MICFIL_VAD0_ZCD,
1071
1034
.reg_defaults = fsl_micfil_reg_defaults,
1072
1035
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1036
+
.readable_reg = fsl_micfil_readable_reg,
1037
+
.volatile_reg = fsl_micfil_volatile_reg,
1038
+
.writeable_reg = fsl_micfil_writeable_reg,
1039
+
.cache_type = REGCACHE_MAPLE,
1040
+
};
1041
+
1042
+
static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1043
+
.reg_bits = 32,
1044
+
.reg_stride = 4,
1045
+
.val_bits = 32,
1046
+
1047
+
.max_register = REG_MICFIL_VAD0_ZCD,
1048
+
.reg_defaults = fsl_micfil_reg_defaults_v2,
1049
+
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1073
1050
.readable_reg = fsl_micfil_readable_reg,
1074
1051
.volatile_reg = fsl_micfil_volatile_reg,
1075
1052
.writeable_reg = fsl_micfil_writeable_reg,
···
1294
1243
if (IS_ERR(regs))
1295
1244
return PTR_ERR(regs);
1296
1245
1297
-
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1298
-
regs,
1299
-
&fsl_micfil_regmap_config);
1246
+
if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1247
+
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1248
+
regs,
1249
+
&fsl_micfil_regmap_config_v2);
1250
+
else
1251
+
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1252
+
regs,
1253
+
&fsl_micfil_regmap_config);
1300
1254
if (IS_ERR(micfil->regmap)) {
1301
1255
dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1302
1256
PTR_ERR(micfil->regmap));
···
1370
1314
}
1371
1315
1372
1316
micfil->dma_params_rx.chan_name = "rx";
1373
-
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
1317
+
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
1374
1318
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1375
1319
1376
1320
platform_set_drvdata(pdev, micfil);
+1
-1
sound/soc/fsl/fsl_micfil.h
+1
-1
sound/soc/fsl/fsl_micfil.h
···
62
62
#define MICFIL_QSEL_VLOW1_QUALITY 5
63
63
#define MICFIL_QSEL_VLOW2_QUALITY 4
64
64
65
-
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
65
+
#define MICFIL_CTRL2_CICOSR GENMASK(20, 16)
66
66
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
67
67
68
68
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */