Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Intel, nouveau, radeon and qxl.
Mostly for bugs introduced in the merge window, nothing too shocking"
[ And one cirrus fix added later and not mentioned in the pull request.. - Linus ]
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/cirrus: bind also to qemu-xen-traditional
qxl: don't create too large primary surface
drm/nouveau: fix regression on agp boards
drm/gt215/gr: fix initialisation on gddr5 boards
drm/radeon: reduce sparse false positive warnings
drm/radeon: fix vm page table block size calculation
drm/ttm: Don't evict BOs outside of the requested placement range
drm/ttm: Don't skip fpfn check if lpfn is 0 in ttm_bo_mem_compat
drm/radeon: use gart memory for DMA ring tests
drm/radeon: fix speaker allocation setup
drm/radeon: initialize sadb to NULL in the audio code
drm/i915: fix short vs. long hpd detection
drm/i915: Don't trust the DP_DETECT bit for eDP ports on CHV
Revert "drm/radeon/dpm: drop clk/voltage dependency filters for SI"
Revert "drm/radeon: drop btc_get_max_clock_from_voltage_dependency_table"
drm/i915: properly reenable gen8 pipe IRQs
drm/i915: Move DIV_ROUND_CLOSEST_ULL macro to header
drm/i915: intel_backlight scale() math WA
+176
-77
+2
drivers/gpu/drm/cirrus/cirrus_drv.c
+2
drivers/gpu/drm/cirrus/cirrus_drv.c
+10
-9
drivers/gpu/drm/i915/i915_irq.c
+10
-9
drivers/gpu/drm/i915/i915_irq.c
···
1711
1711
#define HPD_STORM_DETECT_PERIOD 1000
1712
1712
#define HPD_STORM_THRESHOLD 5
1713
1713
1714
-
static int ilk_port_to_hotplug_shift(enum port port)
1714
+
static int pch_port_to_hotplug_shift(enum port port)
1715
1715
{
1716
1716
switch (port) {
1717
1717
case PORT_A:
···
1727
1727
}
1728
1728
}
1729
1729
1730
-
static int g4x_port_to_hotplug_shift(enum port port)
1730
+
static int i915_port_to_hotplug_shift(enum port port)
1731
1731
{
1732
1732
switch (port) {
1733
1733
case PORT_A:
···
1785
1785
if (port && dev_priv->hpd_irq_port[port]) {
1786
1786
bool long_hpd;
1787
1787
1788
-
if (IS_G4X(dev)) {
1789
-
dig_shift = g4x_port_to_hotplug_shift(port);
1790
-
long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1791
-
} else {
1792
-
dig_shift = ilk_port_to_hotplug_shift(port);
1788
+
if (HAS_PCH_SPLIT(dev)) {
1789
+
dig_shift = pch_port_to_hotplug_shift(port);
1793
1790
long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1791
+
} else {
1792
+
dig_shift = i915_port_to_hotplug_shift(port);
1793
+
long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1794
1794
}
1795
1795
1796
1796
DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
···
3458
3458
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3459
3459
{
3460
3460
unsigned long irqflags;
3461
+
uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3461
3462
3462
3463
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3463
3464
GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3464
-
~dev_priv->de_irq_mask[PIPE_B]);
3465
+
~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3465
3466
GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3466
-
~dev_priv->de_irq_mask[PIPE_C]);
3467
+
~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3467
3468
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3468
3469
}
3469
3470
+21
-15
drivers/gpu/drm/i915/intel_display.c
+21
-15
drivers/gpu/drm/i915/intel_display.c
···
73
73
DRM_FORMAT_ARGB8888,
74
74
};
75
75
76
-
#define DIV_ROUND_CLOSEST_ULL(ll, d) \
77
-
({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
-
79
76
static void intel_increase_pllclock(struct drm_device *dev,
80
77
enum pipe pipe);
81
78
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
···
12354
12357
if (I915_READ(PCH_DP_D) & DP_DETECTED)
12355
12358
intel_dp_init(dev, PCH_DP_D, PORT_D);
12356
12359
} else if (IS_VALLEYVIEW(dev)) {
12357
-
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12360
+
/*
12361
+
* The DP_DETECTED bit is the latched state of the DDC
12362
+
* SDA pin at boot. However since eDP doesn't require DDC
12363
+
* (no way to plug in a DP->HDMI dongle) the DDC pins for
12364
+
* eDP ports may have been muxed to an alternate function.
12365
+
* Thus we can't rely on the DP_DETECTED bit alone to detect
12366
+
* eDP ports. Consult the VBT as well as DP_DETECTED to
12367
+
* detect eDP ports.
12368
+
*/
12369
+
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12358
12370
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12359
12371
PORT_B);
12360
-
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12361
-
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12362
-
}
12372
+
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12373
+
intel_dp_is_edp(dev, PORT_B))
12374
+
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12363
12375
12364
-
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12376
+
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12365
12377
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12366
12378
PORT_C);
12367
-
if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12368
-
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12369
-
}
12379
+
if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12380
+
intel_dp_is_edp(dev, PORT_C))
12381
+
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12370
12382
12371
12383
if (IS_CHERRYVIEW(dev)) {
12372
-
if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12384
+
if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12373
12385
intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12374
12386
PORT_D);
12375
-
if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12376
-
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12377
-
}
12387
+
/* eDP not supported on port D, so don't check VBT */
12388
+
if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12389
+
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12378
12390
}
12379
12391
12380
12392
intel_dsi_init(dev);
+3
drivers/gpu/drm/i915/intel_drv.h
+3
drivers/gpu/drm/i915/intel_drv.h
+2
-3
drivers/gpu/drm/i915/intel_panel.c
+2
-3
drivers/gpu/drm/i915/intel_panel.c
···
419
419
source_val = clamp(source_val, source_min, source_max);
420
420
421
421
/* avoid overflows */
422
-
target_val = (uint64_t)(source_val - source_min) *
423
-
(target_max - target_min);
424
-
do_div(target_val, source_max - source_min);
422
+
target_val = DIV_ROUND_CLOSEST_ULL((uint64_t)(source_val - source_min) *
423
+
(target_max - target_min), source_max - source_min);
425
424
target_val += target_min;
426
425
427
426
return target_val;
+8
-2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
+8
-2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
···
113
113
#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
114
114
#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
115
115
116
+
#include <subdev/fb.h>
117
+
116
118
/*
117
119
* This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
118
120
* the GPU itself that does context-switching, but it needs a special
···
571
569
gr_def(ctx, 0x407d08, 0x00010040);
572
570
else if (device->chipset < 0xa0)
573
571
gr_def(ctx, 0x407d08, 0x00390040);
574
-
else
575
-
gr_def(ctx, 0x407d08, 0x003d0040);
572
+
else {
573
+
if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
574
+
gr_def(ctx, 0x407d08, 0x003d0040);
575
+
else
576
+
gr_def(ctx, 0x407d08, 0x003c0040);
577
+
}
576
578
gr_def(ctx, 0x407d0c, 0x00000022);
577
579
}
578
580
+9
-3
drivers/gpu/drm/nouveau/nouveau_chan.c
+9
-3
drivers/gpu/drm/nouveau/nouveau_chan.c
···
400
400
struct nouveau_channel **pchan)
401
401
{
402
402
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
403
+
bool super;
403
404
int ret;
405
+
406
+
/* hack until fencenv50 is fixed, and agp access relaxed */
407
+
super = cli->base.super;
408
+
cli->base.super = true;
404
409
405
410
ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
406
411
if (ret) {
···
413
408
ret = nouveau_channel_dma(drm, device, handle, pchan);
414
409
if (ret) {
415
410
NV_PRINTK(debug, cli, "dma channel create, %d\n", ret);
416
-
return ret;
411
+
goto done;
417
412
}
418
413
}
419
414
···
421
416
if (ret) {
422
417
NV_PRINTK(error, cli, "channel failed to initialise, %d\n", ret);
423
418
nouveau_channel_del(pchan);
424
-
return ret;
425
419
}
426
420
427
-
return 0;
421
+
done:
422
+
cli->base.super = super;
423
+
return ret;
428
424
}
+8
-8
drivers/gpu/drm/qxl/qxl_display.c
+8
-8
drivers/gpu/drm/qxl/qxl_display.c
···
572
572
struct qxl_framebuffer *qfb;
573
573
struct qxl_bo *bo, *old_bo = NULL;
574
574
struct qxl_crtc *qcrtc = to_qxl_crtc(crtc);
575
-
uint32_t width, height, base_offset;
576
575
bool recreate_primary = false;
577
576
int ret;
578
577
int surf_id;
···
601
602
if (qcrtc->index == 0)
602
603
recreate_primary = true;
603
604
604
-
width = mode->hdisplay;
605
-
height = mode->vdisplay;
606
-
base_offset = 0;
605
+
if (bo->surf.stride * bo->surf.height > qdev->vram_size) {
606
+
DRM_ERROR("Mode doesn't fit in vram size (vgamem)");
607
+
return -EINVAL;
608
+
}
607
609
608
610
ret = qxl_bo_reserve(bo, false);
609
611
if (ret != 0)
···
618
618
if (recreate_primary) {
619
619
qxl_io_destroy_primary(qdev);
620
620
qxl_io_log(qdev,
621
-
"recreate primary: %dx%d (was %dx%d,%d,%d)\n",
622
-
width, height, bo->surf.width,
623
-
bo->surf.height, bo->surf.stride, bo->surf.format);
624
-
qxl_io_create_primary(qdev, base_offset, bo);
621
+
"recreate primary: %dx%d,%d,%d\n",
622
+
bo->surf.width, bo->surf.height,
623
+
bo->surf.stride, bo->surf.format);
624
+
qxl_io_create_primary(qdev, 0, bo);
625
625
bo->is_primary = true;
626
626
}
627
627
+18
drivers/gpu/drm/radeon/btc_dpm.c
+18
drivers/gpu/drm/radeon/btc_dpm.c
···
24
24
25
25
#include "drmP.h"
26
26
#include "radeon.h"
27
+
#include "radeon_asic.h"
27
28
#include "btcd.h"
28
29
#include "r600_dpm.h"
29
30
#include "cypress_dpm.h"
···
1170
1169
{ 20000, 30000, RADEON_SCLK_UP },
1171
1170
{ 25000, 30000, RADEON_SCLK_UP }
1172
1171
};
1172
+
1173
+
void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
1174
+
u32 *max_clock)
1175
+
{
1176
+
u32 i, clock = 0;
1177
+
1178
+
if ((table == NULL) || (table->count == 0)) {
1179
+
*max_clock = clock;
1180
+
return;
1181
+
}
1182
+
1183
+
for (i = 0; i < table->count; i++) {
1184
+
if (clock < table->entries[i].clk)
1185
+
clock = table->entries[i].clk;
1186
+
}
1187
+
*max_clock = clock;
1188
+
}
1173
1189
1174
1190
void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
1175
1191
u32 clock, u16 max_voltage, u16 *voltage)
+2
drivers/gpu/drm/radeon/btc_dpm.h
+2
drivers/gpu/drm/radeon/btc_dpm.h
···
46
46
struct rv7xx_pl *pl);
47
47
void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
48
48
u32 clock, u16 max_voltage, u16 *voltage);
49
+
void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
50
+
u32 *max_clock);
49
51
void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
50
52
u16 max_vddc, u16 max_vddci,
51
53
u16 *vddc, u16 *vddci);
+1
drivers/gpu/drm/radeon/ci_dpm.c
+1
drivers/gpu/drm/radeon/ci_dpm.c
+12
-9
drivers/gpu/drm/radeon/cik_sdma.c
+12
-9
drivers/gpu/drm/radeon/cik_sdma.c
···
611
611
{
612
612
unsigned i;
613
613
int r;
614
-
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
614
+
unsigned index;
615
615
u32 tmp;
616
+
u64 gpu_addr;
616
617
617
-
if (!ptr) {
618
-
DRM_ERROR("invalid vram scratch pointer\n");
619
-
return -EINVAL;
620
-
}
618
+
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
619
+
index = R600_WB_DMA_RING_TEST_OFFSET;
620
+
else
621
+
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
622
+
623
+
gpu_addr = rdev->wb.gpu_addr + index;
621
624
622
625
tmp = 0xCAFEDEAD;
623
-
writel(tmp, ptr);
626
+
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
624
627
625
628
r = radeon_ring_lock(rdev, ring, 5);
626
629
if (r) {
···
631
628
return r;
632
629
}
633
630
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
634
-
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
635
-
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
631
+
radeon_ring_write(ring, lower_32_bits(gpu_addr));
632
+
radeon_ring_write(ring, upper_32_bits(gpu_addr));
636
633
radeon_ring_write(ring, 1); /* number of DWs to follow */
637
634
radeon_ring_write(ring, 0xDEADBEEF);
638
635
radeon_ring_unlock_commit(rdev, ring, false);
639
636
640
637
for (i = 0; i < rdev->usec_timeout; i++) {
641
-
tmp = readl(ptr);
638
+
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
642
639
if (tmp == 0xDEADBEEF)
643
640
break;
644
641
DRM_UDELAY(1);
+1
drivers/gpu/drm/radeon/cypress_dpm.c
+1
drivers/gpu/drm/radeon/cypress_dpm.c
+3
-3
drivers/gpu/drm/radeon/dce3_1_afmt.c
+3
-3
drivers/gpu/drm/radeon/dce3_1_afmt.c
···
32
32
struct drm_connector *connector;
33
33
struct radeon_connector *radeon_connector = NULL;
34
34
u32 tmp;
35
-
u8 *sadb;
35
+
u8 *sadb = NULL;
36
36
int sad_count;
37
37
38
38
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
···
49
49
50
50
sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
51
51
if (sad_count < 0) {
52
-
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
53
-
return;
52
+
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
53
+
sad_count = 0;
54
54
}
55
55
56
56
/* program the speaker allocation */
+4
-4
drivers/gpu/drm/radeon/dce6_afmt.c
+4
-4
drivers/gpu/drm/radeon/dce6_afmt.c
···
155
155
struct drm_connector *connector;
156
156
struct radeon_connector *radeon_connector = NULL;
157
157
u32 offset, tmp;
158
-
u8 *sadb;
158
+
u8 *sadb = NULL;
159
159
int sad_count;
160
160
161
161
if (!dig || !dig->afmt || !dig->afmt->pin)
···
176
176
}
177
177
178
178
sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb);
179
-
if (sad_count <= 0) {
180
-
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
181
-
return;
179
+
if (sad_count < 0) {
180
+
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
181
+
sad_count = 0;
182
182
}
183
183
184
184
/* program the speaker allocation */
+4
-4
drivers/gpu/drm/radeon/evergreen_hdmi.c
+4
-4
drivers/gpu/drm/radeon/evergreen_hdmi.c
···
133
133
struct drm_connector *connector;
134
134
struct radeon_connector *radeon_connector = NULL;
135
135
u32 tmp;
136
-
u8 *sadb;
136
+
u8 *sadb = NULL;
137
137
int sad_count;
138
138
139
139
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
···
149
149
}
150
150
151
151
sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb);
152
-
if (sad_count <= 0) {
153
-
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
154
-
return;
152
+
if (sad_count < 0) {
153
+
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
154
+
sad_count = 0;
155
155
}
156
156
157
157
/* program the speaker allocation */
+1
drivers/gpu/drm/radeon/ni_dpm.c
+1
drivers/gpu/drm/radeon/ni_dpm.c
+12
-9
drivers/gpu/drm/radeon/r600_dma.c
+12
-9
drivers/gpu/drm/radeon/r600_dma.c
···
232
232
{
233
233
unsigned i;
234
234
int r;
235
-
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
235
+
unsigned index;
236
236
u32 tmp;
237
+
u64 gpu_addr;
237
238
238
-
if (!ptr) {
239
-
DRM_ERROR("invalid vram scratch pointer\n");
240
-
return -EINVAL;
241
-
}
239
+
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
240
+
index = R600_WB_DMA_RING_TEST_OFFSET;
241
+
else
242
+
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
243
+
244
+
gpu_addr = rdev->wb.gpu_addr + index;
242
245
243
246
tmp = 0xCAFEDEAD;
244
-
writel(tmp, ptr);
247
+
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
245
248
246
249
r = radeon_ring_lock(rdev, ring, 4);
247
250
if (r) {
···
252
249
return r;
253
250
}
254
251
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
255
-
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
256
-
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
252
+
radeon_ring_write(ring, lower_32_bits(gpu_addr));
253
+
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
257
254
radeon_ring_write(ring, 0xDEADBEEF);
258
255
radeon_ring_unlock_commit(rdev, ring, false);
259
256
260
257
for (i = 0; i < rdev->usec_timeout; i++) {
261
-
tmp = readl(ptr);
258
+
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
262
259
if (tmp == 0xDEADBEEF)
263
260
break;
264
261
DRM_UDELAY(1);
+1
drivers/gpu/drm/radeon/r600_dpm.c
+1
drivers/gpu/drm/radeon/r600_dpm.c
+2
drivers/gpu/drm/radeon/radeon.h
+2
drivers/gpu/drm/radeon/radeon.h
···
1133
1133
#define R600_WB_EVENT_OFFSET 3072
1134
1134
#define CIK_WB_CP1_WPTR_OFFSET 3328
1135
1135
#define CIK_WB_CP2_WPTR_OFFSET 3584
1136
+
#define R600_WB_DMA_RING_TEST_OFFSET 3588
1137
+
#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1136
1138
1137
1139
/**
1138
1140
* struct radeon_pm - power management datas
+1
-1
drivers/gpu/drm/radeon/radeon_device.c
+1
-1
drivers/gpu/drm/radeon/radeon_device.c
···
1130
1130
if (radeon_vm_block_size == -1) {
1131
1131
1132
1132
/* Total bits covered by PD + PTs */
1133
-
unsigned bits = ilog2(radeon_vm_size) + 17;
1133
+
unsigned bits = ilog2(radeon_vm_size) + 18;
1134
1134
1135
1135
/* Make sure the PD is 4K in size up to 8GB address space.
1136
1136
Above that split equal between PD and PTs */
+1
drivers/gpu/drm/radeon/rs780_dpm.c
+1
drivers/gpu/drm/radeon/rs780_dpm.c
+1
drivers/gpu/drm/radeon/rv6xx_dpm.c
+1
drivers/gpu/drm/radeon/rv6xx_dpm.c
+1
drivers/gpu/drm/radeon/rv770_dpm.c
+1
drivers/gpu/drm/radeon/rv770_dpm.c
+25
drivers/gpu/drm/radeon/si_dpm.c
+25
drivers/gpu/drm/radeon/si_dpm.c
···
23
23
24
24
#include "drmP.h"
25
25
#include "radeon.h"
26
+
#include "radeon_asic.h"
26
27
#include "sid.h"
27
28
#include "r600_dpm.h"
28
29
#include "si_dpm.h"
···
2917
2916
bool disable_sclk_switching = false;
2918
2917
u32 mclk, sclk;
2919
2918
u16 vddc, vddci;
2919
+
u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2920
2920
int i;
2921
2921
2922
2922
if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
···
2948
2946
ps->performance_levels[i].vddc = max_limits->vddc;
2949
2947
if (ps->performance_levels[i].vddci > max_limits->vddci)
2950
2948
ps->performance_levels[i].vddci = max_limits->vddci;
2949
+
}
2950
+
}
2951
+
2952
+
/* limit clocks to max supported clocks based on voltage dependency tables */
2953
+
btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2954
+
&max_sclk_vddc);
2955
+
btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2956
+
&max_mclk_vddci);
2957
+
btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2958
+
&max_mclk_vddc);
2959
+
2960
+
for (i = 0; i < ps->performance_level_count; i++) {
2961
+
if (max_sclk_vddc) {
2962
+
if (ps->performance_levels[i].sclk > max_sclk_vddc)
2963
+
ps->performance_levels[i].sclk = max_sclk_vddc;
2964
+
}
2965
+
if (max_mclk_vddci) {
2966
+
if (ps->performance_levels[i].mclk > max_mclk_vddci)
2967
+
ps->performance_levels[i].mclk = max_mclk_vddci;
2968
+
}
2969
+
if (max_mclk_vddc) {
2970
+
if (ps->performance_levels[i].mclk > max_mclk_vddc)
2971
+
ps->performance_levels[i].mclk = max_mclk_vddc;
2951
2972
}
2952
2973
}
2953
2974
+1
drivers/gpu/drm/radeon/sumo_dpm.c
+1
drivers/gpu/drm/radeon/sumo_dpm.c
+1
drivers/gpu/drm/radeon/trinity_dpm.c
+1
drivers/gpu/drm/radeon/trinity_dpm.c
+21
-7
drivers/gpu/drm/ttm/ttm_bo.c
+21
-7
drivers/gpu/drm/ttm/ttm_bo.c
···
709
709
710
710
static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
711
711
uint32_t mem_type,
712
+
const struct ttm_place *place,
712
713
bool interruptible,
713
714
bool no_wait_gpu)
714
715
{
···
721
720
spin_lock(&glob->lru_lock);
722
721
list_for_each_entry(bo, &man->lru, lru) {
723
722
ret = __ttm_bo_reserve(bo, false, true, false, NULL);
724
-
if (!ret)
723
+
if (!ret) {
724
+
if (place && (place->fpfn || place->lpfn)) {
725
+
/* Don't evict this BO if it's outside of the
726
+
* requested placement range
727
+
*/
728
+
if (place->fpfn >= (bo->mem.start + bo->mem.size) ||
729
+
(place->lpfn && place->lpfn <= bo->mem.start)) {
730
+
__ttm_bo_unreserve(bo);
731
+
ret = -EBUSY;
732
+
continue;
733
+
}
734
+
}
735
+
725
736
break;
737
+
}
726
738
}
727
739
728
740
if (ret) {
···
796
782
return ret;
797
783
if (mem->mm_node)
798
784
break;
799
-
ret = ttm_mem_evict_first(bdev, mem_type,
785
+
ret = ttm_mem_evict_first(bdev, mem_type, place,
800
786
interruptible, no_wait_gpu);
801
787
if (unlikely(ret != 0))
802
788
return ret;
···
1008
994
1009
995
for (i = 0; i < placement->num_placement; i++) {
1010
996
const struct ttm_place *heap = &placement->placement[i];
1011
-
if (mem->mm_node && heap->lpfn != 0 &&
997
+
if (mem->mm_node &&
1012
998
(mem->start < heap->fpfn ||
1013
-
mem->start + mem->num_pages > heap->lpfn))
999
+
(heap->lpfn != 0 && (mem->start + mem->num_pages) > heap->lpfn)))
1014
1000
continue;
1015
1001
1016
1002
*new_flags = heap->flags;
···
1021
1007
1022
1008
for (i = 0; i < placement->num_busy_placement; i++) {
1023
1009
const struct ttm_place *heap = &placement->busy_placement[i];
1024
-
if (mem->mm_node && heap->lpfn != 0 &&
1010
+
if (mem->mm_node &&
1025
1011
(mem->start < heap->fpfn ||
1026
-
mem->start + mem->num_pages > heap->lpfn))
1012
+
(heap->lpfn != 0 && (mem->start + mem->num_pages) > heap->lpfn)))
1027
1013
continue;
1028
1014
1029
1015
*new_flags = heap->flags;
···
1247
1233
spin_lock(&glob->lru_lock);
1248
1234
while (!list_empty(&man->lru)) {
1249
1235
spin_unlock(&glob->lru_lock);
1250
-
ret = ttm_mem_evict_first(bdev, mem_type, false, false);
1236
+
ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, false);
1251
1237
if (ret) {
1252
1238
if (allow_errors) {
1253
1239
return ret;