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clk: qcom: dispcc-sm8550: make struct clk_init_data const

The clk_init_data instances are not changed at runtime. Mark them as
constant data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-3-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson eb64ccac cb4c0069

+80 -80
+80 -80
drivers/clk/qcom/dispcc-sm8550.c
··· 95 95 .num_vco = ARRAY_SIZE(lucid_ole_vco), 96 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 97 97 .clkr = { 98 - .hw.init = &(struct clk_init_data) { 98 + .hw.init = &(const struct clk_init_data) { 99 99 .name = "disp_cc_pll0", 100 100 .parent_data = &(const struct clk_parent_data) { 101 101 .index = DT_BI_TCXO, ··· 126 126 .num_vco = ARRAY_SIZE(lucid_ole_vco), 127 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 128 128 .clkr = { 129 - .hw.init = &(struct clk_init_data) { 129 + .hw.init = &(const struct clk_init_data) { 130 130 .name = "disp_cc_pll1", 131 131 .parent_data = &(const struct clk_parent_data) { 132 132 .index = DT_BI_TCXO, ··· 286 286 .hid_width = 5, 287 287 .parent_map = disp_cc_parent_map_6, 288 288 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 289 - .clkr.hw.init = &(struct clk_init_data) { 289 + .clkr.hw.init = &(const struct clk_init_data) { 290 290 .name = "disp_cc_mdss_ahb_clk_src", 291 291 .parent_data = disp_cc_parent_data_6, 292 292 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), ··· 306 306 .hid_width = 5, 307 307 .parent_map = disp_cc_parent_map_2, 308 308 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 309 - .clkr.hw.init = &(struct clk_init_data) { 309 + .clkr.hw.init = &(const struct clk_init_data) { 310 310 .name = "disp_cc_mdss_byte0_clk_src", 311 311 .parent_data = disp_cc_parent_data_2, 312 312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 321 321 .hid_width = 5, 322 322 .parent_map = disp_cc_parent_map_2, 323 323 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 324 - .clkr.hw.init = &(struct clk_init_data) { 324 + .clkr.hw.init = &(const struct clk_init_data) { 325 325 .name = "disp_cc_mdss_byte1_clk_src", 326 326 .parent_data = disp_cc_parent_data_2, 327 327 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 336 336 .hid_width = 5, 337 337 .parent_map = disp_cc_parent_map_0, 338 338 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 339 - .clkr.hw.init = &(struct clk_init_data) { 339 + .clkr.hw.init = &(const struct clk_init_data) { 340 340 .name = "disp_cc_mdss_dptx0_aux_clk_src", 341 341 .parent_data = disp_cc_parent_data_0, 342 342 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 350 350 .mnd_width = 0, 351 351 .hid_width = 5, 352 352 .parent_map = disp_cc_parent_map_7, 353 - .clkr.hw.init = &(struct clk_init_data) { 353 + .clkr.hw.init = &(const struct clk_init_data) { 354 354 .name = "disp_cc_mdss_dptx0_link_clk_src", 355 355 .parent_data = disp_cc_parent_data_7, 356 356 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), ··· 365 365 .hid_width = 5, 366 366 .parent_map = disp_cc_parent_map_4, 367 367 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 368 - .clkr.hw.init = &(struct clk_init_data) { 368 + .clkr.hw.init = &(const struct clk_init_data) { 369 369 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 370 370 .parent_data = disp_cc_parent_data_4, 371 371 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), ··· 380 380 .hid_width = 5, 381 381 .parent_map = disp_cc_parent_map_4, 382 382 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 383 - .clkr.hw.init = &(struct clk_init_data) { 383 + .clkr.hw.init = &(const struct clk_init_data) { 384 384 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 385 385 .parent_data = disp_cc_parent_data_4, 386 386 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), ··· 395 395 .hid_width = 5, 396 396 .parent_map = disp_cc_parent_map_0, 397 397 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 398 - .clkr.hw.init = &(struct clk_init_data) { 398 + .clkr.hw.init = &(const struct clk_init_data) { 399 399 .name = "disp_cc_mdss_dptx1_aux_clk_src", 400 400 .parent_data = disp_cc_parent_data_0, 401 401 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 409 409 .mnd_width = 0, 410 410 .hid_width = 5, 411 411 .parent_map = disp_cc_parent_map_3, 412 - .clkr.hw.init = &(struct clk_init_data) { 412 + .clkr.hw.init = &(const struct clk_init_data) { 413 413 .name = "disp_cc_mdss_dptx1_link_clk_src", 414 414 .parent_data = disp_cc_parent_data_3, 415 415 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), ··· 424 424 .hid_width = 5, 425 425 .parent_map = disp_cc_parent_map_1, 426 426 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 427 - .clkr.hw.init = &(struct clk_init_data) { 427 + .clkr.hw.init = &(const struct clk_init_data) { 428 428 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 429 429 .parent_data = disp_cc_parent_data_1, 430 430 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 439 439 .hid_width = 5, 440 440 .parent_map = disp_cc_parent_map_1, 441 441 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 442 - .clkr.hw.init = &(struct clk_init_data) { 442 + .clkr.hw.init = &(const struct clk_init_data) { 443 443 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 444 444 .parent_data = disp_cc_parent_data_1, 445 445 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 454 454 .hid_width = 5, 455 455 .parent_map = disp_cc_parent_map_0, 456 456 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 457 - .clkr.hw.init = &(struct clk_init_data) { 457 + .clkr.hw.init = &(const struct clk_init_data) { 458 458 .name = "disp_cc_mdss_dptx2_aux_clk_src", 459 459 .parent_data = disp_cc_parent_data_0, 460 460 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 468 468 .mnd_width = 0, 469 469 .hid_width = 5, 470 470 .parent_map = disp_cc_parent_map_3, 471 - .clkr.hw.init = &(struct clk_init_data) { 471 + .clkr.hw.init = &(const struct clk_init_data) { 472 472 .name = "disp_cc_mdss_dptx2_link_clk_src", 473 473 .parent_data = disp_cc_parent_data_3, 474 474 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), ··· 483 483 .hid_width = 5, 484 484 .parent_map = disp_cc_parent_map_1, 485 485 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 486 - .clkr.hw.init = &(struct clk_init_data) { 486 + .clkr.hw.init = &(const struct clk_init_data) { 487 487 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 488 488 .parent_data = disp_cc_parent_data_1, 489 489 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 498 498 .hid_width = 5, 499 499 .parent_map = disp_cc_parent_map_1, 500 500 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 501 - .clkr.hw.init = &(struct clk_init_data) { 501 + .clkr.hw.init = &(const struct clk_init_data) { 502 502 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 503 503 .parent_data = disp_cc_parent_data_1, 504 504 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 513 513 .hid_width = 5, 514 514 .parent_map = disp_cc_parent_map_0, 515 515 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 516 - .clkr.hw.init = &(struct clk_init_data) { 516 + .clkr.hw.init = &(const struct clk_init_data) { 517 517 .name = "disp_cc_mdss_dptx3_aux_clk_src", 518 518 .parent_data = disp_cc_parent_data_0, 519 519 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 527 527 .mnd_width = 0, 528 528 .hid_width = 5, 529 529 .parent_map = disp_cc_parent_map_3, 530 - .clkr.hw.init = &(struct clk_init_data) { 530 + .clkr.hw.init = &(const struct clk_init_data) { 531 531 .name = "disp_cc_mdss_dptx3_link_clk_src", 532 532 .parent_data = disp_cc_parent_data_3, 533 533 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), ··· 542 542 .hid_width = 5, 543 543 .parent_map = disp_cc_parent_map_1, 544 544 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 545 - .clkr.hw.init = &(struct clk_init_data) { 545 + .clkr.hw.init = &(const struct clk_init_data) { 546 546 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 547 547 .parent_data = disp_cc_parent_data_1, 548 548 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), ··· 557 557 .hid_width = 5, 558 558 .parent_map = disp_cc_parent_map_5, 559 559 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 560 - .clkr.hw.init = &(struct clk_init_data) { 560 + .clkr.hw.init = &(const struct clk_init_data) { 561 561 .name = "disp_cc_mdss_esc0_clk_src", 562 562 .parent_data = disp_cc_parent_data_5, 563 563 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), ··· 572 572 .hid_width = 5, 573 573 .parent_map = disp_cc_parent_map_5, 574 574 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 575 - .clkr.hw.init = &(struct clk_init_data) { 575 + .clkr.hw.init = &(const struct clk_init_data) { 576 576 .name = "disp_cc_mdss_esc1_clk_src", 577 577 .parent_data = disp_cc_parent_data_5, 578 578 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), ··· 600 600 .hid_width = 5, 601 601 .parent_map = disp_cc_parent_map_8, 602 602 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 603 - .clkr.hw.init = &(struct clk_init_data) { 603 + .clkr.hw.init = &(const struct clk_init_data) { 604 604 .name = "disp_cc_mdss_mdp_clk_src", 605 605 .parent_data = disp_cc_parent_data_8, 606 606 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), ··· 615 615 .hid_width = 5, 616 616 .parent_map = disp_cc_parent_map_2, 617 617 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 618 - .clkr.hw.init = &(struct clk_init_data) { 618 + .clkr.hw.init = &(const struct clk_init_data) { 619 619 .name = "disp_cc_mdss_pclk0_clk_src", 620 620 .parent_data = disp_cc_parent_data_2, 621 621 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 630 630 .hid_width = 5, 631 631 .parent_map = disp_cc_parent_map_2, 632 632 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 633 - .clkr.hw.init = &(struct clk_init_data) { 633 + .clkr.hw.init = &(const struct clk_init_data) { 634 634 .name = "disp_cc_mdss_pclk1_clk_src", 635 635 .parent_data = disp_cc_parent_data_2, 636 636 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), ··· 645 645 .hid_width = 5, 646 646 .parent_map = disp_cc_parent_map_0, 647 647 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 648 - .clkr.hw.init = &(struct clk_init_data) { 648 + .clkr.hw.init = &(const struct clk_init_data) { 649 649 .name = "disp_cc_mdss_vsync_clk_src", 650 650 .parent_data = disp_cc_parent_data_0, 651 651 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), ··· 665 665 .hid_width = 5, 666 666 .parent_map = disp_cc_parent_map_9, 667 667 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 668 - .clkr.hw.init = &(struct clk_init_data) { 668 + .clkr.hw.init = &(const struct clk_init_data) { 669 669 .name = "disp_cc_sleep_clk_src", 670 670 .parent_data = disp_cc_parent_data_9, 671 671 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), ··· 680 680 .hid_width = 5, 681 681 .parent_map = disp_cc_parent_map_0, 682 682 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 683 - .clkr.hw.init = &(struct clk_init_data) { 683 + .clkr.hw.init = &(const struct clk_init_data) { 684 684 .name = "disp_cc_xo_clk_src", 685 685 .parent_data = disp_cc_parent_data_0_ao, 686 686 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), ··· 693 693 .reg = 0x8120, 694 694 .shift = 0, 695 695 .width = 4, 696 - .clkr.hw.init = &(struct clk_init_data) { 696 + .clkr.hw.init = &(const struct clk_init_data) { 697 697 .name = "disp_cc_mdss_byte0_div_clk_src", 698 698 .parent_hws = (const struct clk_hw*[]) { 699 699 &disp_cc_mdss_byte0_clk_src.clkr.hw, ··· 707 707 .reg = 0x813c, 708 708 .shift = 0, 709 709 .width = 4, 710 - .clkr.hw.init = &(struct clk_init_data) { 710 + .clkr.hw.init = &(const struct clk_init_data) { 711 711 .name = "disp_cc_mdss_byte1_div_clk_src", 712 712 .parent_hws = (const struct clk_hw*[]) { 713 713 &disp_cc_mdss_byte1_clk_src.clkr.hw, ··· 721 721 .reg = 0x8188, 722 722 .shift = 0, 723 723 .width = 4, 724 - .clkr.hw.init = &(struct clk_init_data) { 724 + .clkr.hw.init = &(const struct clk_init_data) { 725 725 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 726 726 .parent_hws = (const struct clk_hw*[]) { 727 727 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, ··· 736 736 .reg = 0x821c, 737 737 .shift = 0, 738 738 .width = 4, 739 - .clkr.hw.init = &(struct clk_init_data) { 739 + .clkr.hw.init = &(const struct clk_init_data) { 740 740 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 741 741 .parent_hws = (const struct clk_hw*[]) { 742 742 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, ··· 751 751 .reg = 0x8250, 752 752 .shift = 0, 753 753 .width = 4, 754 - .clkr.hw.init = &(struct clk_init_data) { 754 + .clkr.hw.init = &(const struct clk_init_data) { 755 755 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 756 756 .parent_hws = (const struct clk_hw*[]) { 757 757 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, ··· 766 766 .reg = 0x82cc, 767 767 .shift = 0, 768 768 .width = 4, 769 - .clkr.hw.init = &(struct clk_init_data) { 769 + .clkr.hw.init = &(const struct clk_init_data) { 770 770 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 771 771 .parent_hws = (const struct clk_hw*[]) { 772 772 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, ··· 783 783 .clkr = { 784 784 .enable_reg = 0xe058, 785 785 .enable_mask = BIT(0), 786 - .hw.init = &(struct clk_init_data){ 786 + .hw.init = &(const struct clk_init_data) { 787 787 .name = "disp_cc_mdss_accu_clk", 788 788 .parent_hws = (const struct clk_hw*[]) { 789 789 &disp_cc_xo_clk_src.clkr.hw, ··· 801 801 .clkr = { 802 802 .enable_reg = 0xa020, 803 803 .enable_mask = BIT(0), 804 - .hw.init = &(struct clk_init_data) { 804 + .hw.init = &(const struct clk_init_data) { 805 805 .name = "disp_cc_mdss_ahb1_clk", 806 806 .parent_hws = (const struct clk_hw*[]) { 807 807 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 819 819 .clkr = { 820 820 .enable_reg = 0x80a4, 821 821 .enable_mask = BIT(0), 822 - .hw.init = &(struct clk_init_data) { 822 + .hw.init = &(const struct clk_init_data) { 823 823 .name = "disp_cc_mdss_ahb_clk", 824 824 .parent_hws = (const struct clk_hw*[]) { 825 825 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 837 837 .clkr = { 838 838 .enable_reg = 0x8028, 839 839 .enable_mask = BIT(0), 840 - .hw.init = &(struct clk_init_data) { 840 + .hw.init = &(const struct clk_init_data) { 841 841 .name = "disp_cc_mdss_byte0_clk", 842 842 .parent_hws = (const struct clk_hw*[]) { 843 843 &disp_cc_mdss_byte0_clk_src.clkr.hw, ··· 855 855 .clkr = { 856 856 .enable_reg = 0x802c, 857 857 .enable_mask = BIT(0), 858 - .hw.init = &(struct clk_init_data) { 858 + .hw.init = &(const struct clk_init_data) { 859 859 .name = "disp_cc_mdss_byte0_intf_clk", 860 860 .parent_hws = (const struct clk_hw*[]) { 861 861 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, ··· 873 873 .clkr = { 874 874 .enable_reg = 0x8030, 875 875 .enable_mask = BIT(0), 876 - .hw.init = &(struct clk_init_data) { 876 + .hw.init = &(const struct clk_init_data) { 877 877 .name = "disp_cc_mdss_byte1_clk", 878 878 .parent_hws = (const struct clk_hw*[]) { 879 879 &disp_cc_mdss_byte1_clk_src.clkr.hw, ··· 891 891 .clkr = { 892 892 .enable_reg = 0x8034, 893 893 .enable_mask = BIT(0), 894 - .hw.init = &(struct clk_init_data) { 894 + .hw.init = &(const struct clk_init_data) { 895 895 .name = "disp_cc_mdss_byte1_intf_clk", 896 896 .parent_hws = (const struct clk_hw*[]) { 897 897 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, ··· 909 909 .clkr = { 910 910 .enable_reg = 0x8058, 911 911 .enable_mask = BIT(0), 912 - .hw.init = &(struct clk_init_data) { 912 + .hw.init = &(const struct clk_init_data) { 913 913 .name = "disp_cc_mdss_dptx0_aux_clk", 914 914 .parent_hws = (const struct clk_hw*[]) { 915 915 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, ··· 927 927 .clkr = { 928 928 .enable_reg = 0x804c, 929 929 .enable_mask = BIT(0), 930 - .hw.init = &(struct clk_init_data) { 930 + .hw.init = &(const struct clk_init_data) { 931 931 .name = "disp_cc_mdss_dptx0_crypto_clk", 932 932 .parent_hws = (const struct clk_hw*[]) { 933 933 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, ··· 945 945 .clkr = { 946 946 .enable_reg = 0x8040, 947 947 .enable_mask = BIT(0), 948 - .hw.init = &(struct clk_init_data) { 948 + .hw.init = &(const struct clk_init_data) { 949 949 .name = "disp_cc_mdss_dptx0_link_clk", 950 950 .parent_hws = (const struct clk_hw*[]) { 951 951 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, ··· 963 963 .clkr = { 964 964 .enable_reg = 0x8048, 965 965 .enable_mask = BIT(0), 966 - .hw.init = &(struct clk_init_data) { 966 + .hw.init = &(const struct clk_init_data) { 967 967 .name = "disp_cc_mdss_dptx0_link_intf_clk", 968 968 .parent_hws = (const struct clk_hw*[]) { 969 969 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, ··· 981 981 .clkr = { 982 982 .enable_reg = 0x8050, 983 983 .enable_mask = BIT(0), 984 - .hw.init = &(struct clk_init_data) { 984 + .hw.init = &(const struct clk_init_data) { 985 985 .name = "disp_cc_mdss_dptx0_pixel0_clk", 986 986 .parent_hws = (const struct clk_hw*[]) { 987 987 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, ··· 999 999 .clkr = { 1000 1000 .enable_reg = 0x8054, 1001 1001 .enable_mask = BIT(0), 1002 - .hw.init = &(struct clk_init_data) { 1002 + .hw.init = &(const struct clk_init_data) { 1003 1003 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1004 1004 .parent_hws = (const struct clk_hw*[]) { 1005 1005 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, ··· 1017 1017 .clkr = { 1018 1018 .enable_reg = 0x8044, 1019 1019 .enable_mask = BIT(0), 1020 - .hw.init = &(struct clk_init_data) { 1020 + .hw.init = &(const struct clk_init_data) { 1021 1021 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1022 1022 .parent_hws = (const struct clk_hw*[]) { 1023 1023 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, ··· 1035 1035 .clkr = { 1036 1036 .enable_reg = 0x8074, 1037 1037 .enable_mask = BIT(0), 1038 - .hw.init = &(struct clk_init_data) { 1038 + .hw.init = &(const struct clk_init_data) { 1039 1039 .name = "disp_cc_mdss_dptx1_aux_clk", 1040 1040 .parent_hws = (const struct clk_hw*[]) { 1041 1041 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, ··· 1053 1053 .clkr = { 1054 1054 .enable_reg = 0x8070, 1055 1055 .enable_mask = BIT(0), 1056 - .hw.init = &(struct clk_init_data) { 1056 + .hw.init = &(const struct clk_init_data) { 1057 1057 .name = "disp_cc_mdss_dptx1_crypto_clk", 1058 1058 .parent_hws = (const struct clk_hw*[]) { 1059 1059 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, ··· 1071 1071 .clkr = { 1072 1072 .enable_reg = 0x8064, 1073 1073 .enable_mask = BIT(0), 1074 - .hw.init = &(struct clk_init_data) { 1074 + .hw.init = &(const struct clk_init_data) { 1075 1075 .name = "disp_cc_mdss_dptx1_link_clk", 1076 1076 .parent_hws = (const struct clk_hw*[]) { 1077 1077 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, ··· 1089 1089 .clkr = { 1090 1090 .enable_reg = 0x806c, 1091 1091 .enable_mask = BIT(0), 1092 - .hw.init = &(struct clk_init_data) { 1092 + .hw.init = &(const struct clk_init_data) { 1093 1093 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1094 1094 .parent_hws = (const struct clk_hw*[]) { 1095 1095 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, ··· 1107 1107 .clkr = { 1108 1108 .enable_reg = 0x805c, 1109 1109 .enable_mask = BIT(0), 1110 - .hw.init = &(struct clk_init_data) { 1110 + .hw.init = &(const struct clk_init_data) { 1111 1111 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1112 1112 .parent_hws = (const struct clk_hw*[]) { 1113 1113 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, ··· 1125 1125 .clkr = { 1126 1126 .enable_reg = 0x8060, 1127 1127 .enable_mask = BIT(0), 1128 - .hw.init = &(struct clk_init_data) { 1128 + .hw.init = &(const struct clk_init_data) { 1129 1129 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1130 1130 .parent_hws = (const struct clk_hw*[]) { 1131 1131 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, ··· 1143 1143 .clkr = { 1144 1144 .enable_reg = 0x8068, 1145 1145 .enable_mask = BIT(0), 1146 - .hw.init = &(struct clk_init_data) { 1146 + .hw.init = &(const struct clk_init_data) { 1147 1147 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1148 1148 .parent_hws = (const struct clk_hw*[]) { 1149 1149 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, ··· 1161 1161 .clkr = { 1162 1162 .enable_reg = 0x808c, 1163 1163 .enable_mask = BIT(0), 1164 - .hw.init = &(struct clk_init_data) { 1164 + .hw.init = &(const struct clk_init_data) { 1165 1165 .name = "disp_cc_mdss_dptx2_aux_clk", 1166 1166 .parent_hws = (const struct clk_hw*[]) { 1167 1167 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, ··· 1179 1179 .clkr = { 1180 1180 .enable_reg = 0x8088, 1181 1181 .enable_mask = BIT(0), 1182 - .hw.init = &(struct clk_init_data) { 1182 + .hw.init = &(const struct clk_init_data) { 1183 1183 .name = "disp_cc_mdss_dptx2_crypto_clk", 1184 1184 .parent_hws = (const struct clk_hw*[]) { 1185 1185 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, ··· 1197 1197 .clkr = { 1198 1198 .enable_reg = 0x8080, 1199 1199 .enable_mask = BIT(0), 1200 - .hw.init = &(struct clk_init_data) { 1200 + .hw.init = &(const struct clk_init_data) { 1201 1201 .name = "disp_cc_mdss_dptx2_link_clk", 1202 1202 .parent_hws = (const struct clk_hw*[]) { 1203 1203 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, ··· 1215 1215 .clkr = { 1216 1216 .enable_reg = 0x8084, 1217 1217 .enable_mask = BIT(0), 1218 - .hw.init = &(struct clk_init_data) { 1218 + .hw.init = &(const struct clk_init_data) { 1219 1219 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1220 1220 .parent_hws = (const struct clk_hw*[]) { 1221 1221 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, ··· 1233 1233 .clkr = { 1234 1234 .enable_reg = 0x8078, 1235 1235 .enable_mask = BIT(0), 1236 - .hw.init = &(struct clk_init_data) { 1236 + .hw.init = &(const struct clk_init_data) { 1237 1237 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1238 1238 .parent_hws = (const struct clk_hw*[]) { 1239 1239 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, ··· 1251 1251 .clkr = { 1252 1252 .enable_reg = 0x807c, 1253 1253 .enable_mask = BIT(0), 1254 - .hw.init = &(struct clk_init_data) { 1254 + .hw.init = &(const struct clk_init_data) { 1255 1255 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1256 1256 .parent_hws = (const struct clk_hw*[]) { 1257 1257 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, ··· 1269 1269 .clkr = { 1270 1270 .enable_reg = 0x809c, 1271 1271 .enable_mask = BIT(0), 1272 - .hw.init = &(struct clk_init_data) { 1272 + .hw.init = &(const struct clk_init_data) { 1273 1273 .name = "disp_cc_mdss_dptx3_aux_clk", 1274 1274 .parent_hws = (const struct clk_hw*[]) { 1275 1275 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, ··· 1287 1287 .clkr = { 1288 1288 .enable_reg = 0x80a0, 1289 1289 .enable_mask = BIT(0), 1290 - .hw.init = &(struct clk_init_data) { 1290 + .hw.init = &(const struct clk_init_data) { 1291 1291 .name = "disp_cc_mdss_dptx3_crypto_clk", 1292 1292 .parent_hws = (const struct clk_hw*[]) { 1293 1293 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, ··· 1305 1305 .clkr = { 1306 1306 .enable_reg = 0x8094, 1307 1307 .enable_mask = BIT(0), 1308 - .hw.init = &(struct clk_init_data) { 1308 + .hw.init = &(const struct clk_init_data) { 1309 1309 .name = "disp_cc_mdss_dptx3_link_clk", 1310 1310 .parent_hws = (const struct clk_hw*[]) { 1311 1311 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, ··· 1323 1323 .clkr = { 1324 1324 .enable_reg = 0x8098, 1325 1325 .enable_mask = BIT(0), 1326 - .hw.init = &(struct clk_init_data) { 1326 + .hw.init = &(const struct clk_init_data) { 1327 1327 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1328 1328 .parent_hws = (const struct clk_hw*[]) { 1329 1329 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, ··· 1341 1341 .clkr = { 1342 1342 .enable_reg = 0x8090, 1343 1343 .enable_mask = BIT(0), 1344 - .hw.init = &(struct clk_init_data) { 1344 + .hw.init = &(const struct clk_init_data) { 1345 1345 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1346 1346 .parent_hws = (const struct clk_hw*[]) { 1347 1347 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, ··· 1359 1359 .clkr = { 1360 1360 .enable_reg = 0x8038, 1361 1361 .enable_mask = BIT(0), 1362 - .hw.init = &(struct clk_init_data) { 1362 + .hw.init = &(const struct clk_init_data) { 1363 1363 .name = "disp_cc_mdss_esc0_clk", 1364 1364 .parent_hws = (const struct clk_hw*[]) { 1365 1365 &disp_cc_mdss_esc0_clk_src.clkr.hw, ··· 1377 1377 .clkr = { 1378 1378 .enable_reg = 0x803c, 1379 1379 .enable_mask = BIT(0), 1380 - .hw.init = &(struct clk_init_data) { 1380 + .hw.init = &(const struct clk_init_data) { 1381 1381 .name = "disp_cc_mdss_esc1_clk", 1382 1382 .parent_hws = (const struct clk_hw*[]) { 1383 1383 &disp_cc_mdss_esc1_clk_src.clkr.hw, ··· 1395 1395 .clkr = { 1396 1396 .enable_reg = 0xa004, 1397 1397 .enable_mask = BIT(0), 1398 - .hw.init = &(struct clk_init_data) { 1398 + .hw.init = &(const struct clk_init_data) { 1399 1399 .name = "disp_cc_mdss_mdp1_clk", 1400 1400 .parent_hws = (const struct clk_hw*[]) { 1401 1401 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1413 1413 .clkr = { 1414 1414 .enable_reg = 0x800c, 1415 1415 .enable_mask = BIT(0), 1416 - .hw.init = &(struct clk_init_data) { 1416 + .hw.init = &(const struct clk_init_data) { 1417 1417 .name = "disp_cc_mdss_mdp_clk", 1418 1418 .parent_hws = (const struct clk_hw*[]) { 1419 1419 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1431 1431 .clkr = { 1432 1432 .enable_reg = 0xa010, 1433 1433 .enable_mask = BIT(0), 1434 - .hw.init = &(struct clk_init_data) { 1434 + .hw.init = &(const struct clk_init_data) { 1435 1435 .name = "disp_cc_mdss_mdp_lut1_clk", 1436 1436 .parent_hws = (const struct clk_hw*[]) { 1437 1437 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1449 1449 .clkr = { 1450 1450 .enable_reg = 0x8018, 1451 1451 .enable_mask = BIT(0), 1452 - .hw.init = &(struct clk_init_data) { 1452 + .hw.init = &(const struct clk_init_data) { 1453 1453 .name = "disp_cc_mdss_mdp_lut_clk", 1454 1454 .parent_hws = (const struct clk_hw*[]) { 1455 1455 &disp_cc_mdss_mdp_clk_src.clkr.hw, ··· 1467 1467 .clkr = { 1468 1468 .enable_reg = 0xc004, 1469 1469 .enable_mask = BIT(0), 1470 - .hw.init = &(struct clk_init_data) { 1470 + .hw.init = &(const struct clk_init_data) { 1471 1471 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1472 1472 .parent_hws = (const struct clk_hw*[]) { 1473 1473 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 1485 1485 .clkr = { 1486 1486 .enable_reg = 0x8004, 1487 1487 .enable_mask = BIT(0), 1488 - .hw.init = &(struct clk_init_data) { 1488 + .hw.init = &(const struct clk_init_data) { 1489 1489 .name = "disp_cc_mdss_pclk0_clk", 1490 1490 .parent_hws = (const struct clk_hw*[]) { 1491 1491 &disp_cc_mdss_pclk0_clk_src.clkr.hw, ··· 1503 1503 .clkr = { 1504 1504 .enable_reg = 0x8008, 1505 1505 .enable_mask = BIT(0), 1506 - .hw.init = &(struct clk_init_data) { 1506 + .hw.init = &(const struct clk_init_data) { 1507 1507 .name = "disp_cc_mdss_pclk1_clk", 1508 1508 .parent_hws = (const struct clk_hw*[]) { 1509 1509 &disp_cc_mdss_pclk1_clk_src.clkr.hw, ··· 1521 1521 .clkr = { 1522 1522 .enable_reg = 0xc00c, 1523 1523 .enable_mask = BIT(0), 1524 - .hw.init = &(struct clk_init_data) { 1524 + .hw.init = &(const struct clk_init_data) { 1525 1525 .name = "disp_cc_mdss_rscc_ahb_clk", 1526 1526 .parent_hws = (const struct clk_hw*[]) { 1527 1527 &disp_cc_mdss_ahb_clk_src.clkr.hw, ··· 1539 1539 .clkr = { 1540 1540 .enable_reg = 0xc008, 1541 1541 .enable_mask = BIT(0), 1542 - .hw.init = &(struct clk_init_data) { 1542 + .hw.init = &(const struct clk_init_data) { 1543 1543 .name = "disp_cc_mdss_rscc_vsync_clk", 1544 1544 .parent_hws = (const struct clk_hw*[]) { 1545 1545 &disp_cc_mdss_vsync_clk_src.clkr.hw, ··· 1557 1557 .clkr = { 1558 1558 .enable_reg = 0xa01c, 1559 1559 .enable_mask = BIT(0), 1560 - .hw.init = &(struct clk_init_data) { 1560 + .hw.init = &(const struct clk_init_data) { 1561 1561 .name = "disp_cc_mdss_vsync1_clk", 1562 1562 .parent_hws = (const struct clk_hw*[]) { 1563 1563 &disp_cc_mdss_vsync_clk_src.clkr.hw, ··· 1575 1575 .clkr = { 1576 1576 .enable_reg = 0x8024, 1577 1577 .enable_mask = BIT(0), 1578 - .hw.init = &(struct clk_init_data) { 1578 + .hw.init = &(const struct clk_init_data) { 1579 1579 .name = "disp_cc_mdss_vsync_clk", 1580 1580 .parent_hws = (const struct clk_hw*[]) { 1581 1581 &disp_cc_mdss_vsync_clk_src.clkr.hw, ··· 1593 1593 .clkr = { 1594 1594 .enable_reg = 0xe074, 1595 1595 .enable_mask = BIT(0), 1596 - .hw.init = &(struct clk_init_data) { 1596 + .hw.init = &(const struct clk_init_data) { 1597 1597 .name = "disp_cc_sleep_clk", 1598 1598 .parent_hws = (const struct clk_hw*[]) { 1599 1599 &disp_cc_sleep_clk_src.clkr.hw,