Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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os
linux
Merge tag 'intel-pinctrl-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.20-1
* Add Nova Lake to the list of supported platforms by platform driver
* Update Kconfig help text to clarify which drivers supports which platforms
* Convert more Intel pin control drivers to use intel_gpio_add_pin_ranges()
Signed-off-by: Linus Walleij <linusw@kernel.org>
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-6
drivers/pinctrl/intel/Kconfig
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-6
drivers/pinctrl/intel/Kconfig
···
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of Intel PCH pins and using them as GPIOs. Currently the following
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Intel SoCs / platforms require this to be functional:
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- Lunar Lake
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- Nova Lake
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- Panther Lake
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config PINCTRL_ALDERLAKE
···
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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-
of Intel Alder Lake PCH pins and using them as GPIOs.
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PCH pins of the following platforms and using them as GPIOs:
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- Alder Lake HX, N, and S
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- Raptor Lake HX, E, and S
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- Twin Lake
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config PINCTRL_BROXTON
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tristate "Intel Broxton pinctrl and GPIO driver"
···
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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-
of Intel Meteor Lake pins and using them as GPIOs.
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SoC pins of the following platforms and using them as GPIOs:
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- Arrow Lake (all variants)
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- Meteor Lake (all variants)
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config PINCTRL_METEORPOINT
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tristate "Intel Meteor Point pinctrl and GPIO driver"
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select PINCTRL_INTEL
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help
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Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
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provides an interface that allows configuring of PCH pins and
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using them as GPIOs.
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This pinctrl driver provides an interface that allows configuring
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PCH pins of the following platforms and using them as GPIOs:
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- Arrow Lake HX and S
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config PINCTRL_SUNRISEPOINT
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tristate "Intel Sunrisepoint pinctrl and GPIO driver"
···
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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-
of Intel Tiger Lake PCH pins and using them as GPIOs.
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PCH pins of the following platforms and using them as GPIOs:
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- Alder Lake H, P, PS, and U
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- Raptor Lake H, P, PS, PX, and U
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- Rocket Lake S
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- Tiger Lake (all variants)
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source "drivers/pinctrl/intel/Kconfig.tng"
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endmenu
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drivers/pinctrl/intel/pinctrl-baytrail.c
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drivers/pinctrl/intel/pinctrl-baytrail.c
···
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u32 val;
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};
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#define COMMUNITY(p, n, map) \
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#define BYT_COMMUNITY(p, n, g, map) \
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{ \
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.pin_base = (p), \
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.npins = (n), \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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.pad_map = (map),\
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}
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···
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FUNCTION("gpio", byt_score_gpio_groups),
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};
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static const struct intel_padgroup byt_score_gpps[] = {
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INTEL_GPP(0, 0, 31, 0),
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INTEL_GPP(1, 32, 63, 32),
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INTEL_GPP(2, 64, 95, 64),
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INTEL_GPP(3, 96, 101, 96),
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};
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static const struct intel_community byt_score_communities[] = {
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COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
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BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map),
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};
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static const struct intel_pinctrl_soc_data byt_score_soc_data = {
···
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FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
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};
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static const struct intel_padgroup byt_sus_gpps[] = {
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INTEL_GPP(0, 0, 31, 0),
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INTEL_GPP(1, 32, 43, 32),
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};
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static const struct intel_community byt_sus_communities[] = {
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COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
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BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map),
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};
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static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
···
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3, 6, 10, 13, 2, 5, 9, 7,
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};
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+
static const struct intel_padgroup byt_ncore_gpps[] = {
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INTEL_GPP(0, 0, 27, 0),
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+
};
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static const struct intel_community byt_ncore_communities[] = {
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COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
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BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map),
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};
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static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
···
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return 0;
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}
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static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct intel_pinctrl *vg = gpiochip_get_data(chip);
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struct device *dev = vg->dev;
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int ret;
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ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
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if (ret)
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return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
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return 0;
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}
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static int byt_gpio_probe(struct intel_pinctrl *vg)
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{
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struct platform_device *pdev = to_platform_device(vg->dev);
···
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gc->label = dev_name(vg->dev);
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gc->base = -1;
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gc->can_sleep = false;
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gc->add_pin_ranges = byt_gpio_add_pin_ranges;
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gc->add_pin_ranges = intel_gpio_add_pin_ranges;
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gc->parent = vg->dev;
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gc->ngpio = vg->soc->npins;
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drivers/pinctrl/intel/pinctrl-lynxpoint.c
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drivers/pinctrl/intel/pinctrl-lynxpoint.c
···
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#include "pinctrl-intel.h"
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#define COMMUNITY(p, n) \
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#define LPTLP_COMMUNITY(p, n, g) \
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{ \
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.pin_base = (p), \
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.npins = (n), \
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.gpps = (g), \
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.ngpps = ARRAY_SIZE(g), \
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}
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static const struct pinctrl_pin_desc lptlp_pins[] = {
···
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PINCTRL_PIN(94, "GP94_UART0_CTSB"),
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};
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static const struct intel_padgroup lptlp_gpps[] = {
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INTEL_GPP(0, 0, 31, 0),
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INTEL_GPP(1, 32, 63, 32),
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INTEL_GPP(2, 64, 94, 64),
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};
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static const struct intel_community lptlp_communities[] = {
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COMMUNITY(0, 95),
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LPTLP_COMMUNITY(0, 95, lptlp_gpps),
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};
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static const struct intel_pinctrl_soc_data lptlp_soc_data = {
···
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return 0;
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}
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static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct intel_pinctrl *lg = gpiochip_get_data(chip);
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struct device *dev = lg->dev;
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int ret;
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ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
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if (ret)
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return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
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return 0;
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}
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static int lp_gpio_probe(struct platform_device *pdev)
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{
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const struct intel_pinctrl_soc_data *soc;
···
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gc->base = -1;
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gc->ngpio = LP_NUM_GPIO;
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gc->can_sleep = false;
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gc->add_pin_ranges = lp_gpio_add_pin_ranges;
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+
gc->add_pin_ranges = intel_gpio_add_pin_ranges;
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gc->parent = dev;
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/* set up interrupts */