tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: add xcc index argument to gfx v9_4_3 functions

Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c.
For some active single-xcc emu models, the code path in
gfx_v9_0.c is better to keep reserved for a while.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Le Ma and committed by
Alex Deucher ec08571a 6f917fdc

+11 -11
+11 -11
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 1068 1068 } 1069 1069 } 1070 1070 1071 - void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev) 1071 + void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1072 1072 { 1073 1073 uint32_t data; 1074 1074 1075 - data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 1075 + data = RREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG); 1076 1076 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1077 - WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 1077 + WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data); 1078 1078 } 1079 1079 1080 1080 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) ··· 1177 1177 } 1178 1178 1179 1179 static void gfx_v9_4_3_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1180 - bool enable) 1180 + bool enable, int xcc_id) 1181 1181 { 1182 1182 u32 tmp; 1183 1183 1184 1184 /* These interrupts should be enabled to drive DS clock */ 1185 1185 1186 - tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1186 + tmp = RREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0); 1187 1187 1188 1188 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1189 1189 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1190 1190 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1191 1191 1192 - WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1192 + WREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0, tmp); 1193 1193 } 1194 1194 1195 1195 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) ··· 1198 1198 1199 1199 for (i = 0; i < adev->gfx.num_xcd; i++) { 1200 1200 WREG32_FIELD15_PREREG(GC, i, RLC_CNTL, RLC_ENABLE_F32, 0); 1201 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, false); 1201 + gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1202 1202 gfx_v9_4_3_wait_for_rlc_serdes(adev, i); 1203 1203 } 1204 1204 } ··· 1228 1228 1229 1229 /* carrizo do enable cp interrupt after cp inited */ 1230 1230 if (!(adev->flags & AMD_IS_APU)) { 1231 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, true); 1231 + gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1232 1232 udelay(50); 1233 1233 } 1234 1234 ··· 1865 1865 struct amdgpu_ring *ring; 1866 1866 1867 1867 for (i = 0; i < adev->gfx.num_xcd; i++) { 1868 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, false); 1868 + gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1869 1869 1870 1870 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1871 - gfx_v9_4_3_disable_gpa_mode(adev); 1871 + gfx_v9_4_3_disable_gpa_mode(adev, i); 1872 1872 1873 1873 r = gfx_v9_4_3_cp_compute_load_microcode(adev, i); 1874 1874 if (r) ··· 1888 1888 amdgpu_ring_test_helper(ring); 1889 1889 } 1890 1890 1891 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, true); 1891 + gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1892 1892 } 1893 1893 1894 1894 return 0;