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watchdog: rzg2l_wdt: Add rzv2m support

The WDT on RZ/V2M devices is basically the same as RZ/G2L, but without
the parity error registers. This means the driver has to reset the
hardware plus set the minimum timeout in order to do a restart and has
a single interrupt.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220823093233.8577-3-phil.edworthy@renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

authored by

Phil Edworthy and committed by
Wim Van Sebroeck ec122fd9 d59913b0

+33 -6
+33 -6
drivers/watchdog/rzg2l_wdt.c
··· 10 10 #include <linux/io.h> 11 11 #include <linux/kernel.h> 12 12 #include <linux/module.h> 13 - #include <linux/of.h> 13 + #include <linux/of_device.h> 14 14 #include <linux/platform_device.h> 15 15 #include <linux/pm_runtime.h> 16 16 #include <linux/reset.h> ··· 40 40 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 41 41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 42 42 43 + enum rz_wdt_type { 44 + WDT_RZG2L, 45 + WDT_RZV2M, 46 + }; 47 + 43 48 struct rzg2l_wdt_priv { 44 49 void __iomem *base; 45 50 struct watchdog_device wdev; ··· 53 48 unsigned long delay; 54 49 struct clk *pclk; 55 50 struct clk *osc_clk; 51 + enum rz_wdt_type devtype; 56 52 }; 57 53 58 54 static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) ··· 148 142 clk_prepare_enable(priv->pclk); 149 143 clk_prepare_enable(priv->osc_clk); 150 144 151 - /* Generate Reset (WDTRSTB) Signal on parity error */ 152 - rzg2l_wdt_write(priv, 0, PECR); 145 + if (priv->devtype == WDT_RZG2L) { 146 + /* Generate Reset (WDTRSTB) Signal on parity error */ 147 + rzg2l_wdt_write(priv, 0, PECR); 153 148 154 - /* Force parity error */ 155 - rzg2l_wdt_write(priv, PEEN_FORCE, PEEN); 149 + /* Force parity error */ 150 + rzg2l_wdt_write(priv, PEEN_FORCE, PEEN); 151 + } else { 152 + /* RZ/V2M doesn't have parity error registers */ 153 + 154 + wdev->timeout = 0; 155 + 156 + /* Initialize time out */ 157 + rzg2l_wdt_init_timeout(wdev); 158 + 159 + /* Initialize watchdog counter register */ 160 + rzg2l_wdt_write(priv, 0, WDTTIM); 161 + 162 + /* Enable watchdog timer*/ 163 + rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT); 164 + 165 + /* Wait 2 consecutive overflow cycles for reset */ 166 + mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate)); 167 + } 156 168 157 169 return 0; 158 170 } ··· 251 227 if (ret) 252 228 return dev_err_probe(dev, ret, "failed to deassert"); 253 229 230 + priv->devtype = (uintptr_t)of_device_get_match_data(dev); 231 + 254 232 pm_runtime_enable(&pdev->dev); 255 233 256 234 priv->wdev.info = &rzg2l_wdt_ident; ··· 281 255 } 282 256 283 257 static const struct of_device_id rzg2l_wdt_ids[] = { 284 - { .compatible = "renesas,rzg2l-wdt", }, 258 + { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L }, 259 + { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M }, 285 260 { /* sentinel */ } 286 261 }; 287 262 MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);