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Merge tag 'iommu-fixes-v5.4-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull iommu fixes from Joerg Roedel:

- Fix for Intel IOMMU to correct invalidation commands when in SVA
mode.

- Update MAINTAINERS entry for Intel IOMMU

* tag 'iommu-fixes-v5.4-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/vt-d: Fix QI_DEV_IOTLB_PFSID and QI_DEV_EIOTLB_PFSID macros
MAINTAINERS: Update for INTEL IOMMU (VT-d) entry

+9 -4
+5 -2
MAINTAINERS
··· 8298 8298 8299 8299 INTEL IOMMU (VT-d) 8300 8300 M: David Woodhouse <dwmw2@infradead.org> 8301 + M: Lu Baolu <baolu.lu@linux.intel.com> 8301 8302 L: iommu@lists.linux-foundation.org 8302 - T: git git://git.infradead.org/iommu-2.6.git 8303 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git 8303 8304 S: Supported 8304 - F: drivers/iommu/intel-iommu.c 8305 + F: drivers/iommu/dmar.c 8306 + F: drivers/iommu/intel*.[ch] 8305 8307 F: include/linux/intel-iommu.h 8308 + F: include/linux/intel-svm.h 8306 8309 8307 8310 INTEL IOP-ADMA DMA DRIVER 8308 8311 R: Dan Williams <dan.j.williams@intel.com>
+4 -2
include/linux/intel-iommu.h
··· 336 336 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) 337 337 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) 338 338 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 339 - #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52)) 339 + #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 340 + ((u64)((pfsid >> 4) & 0xfff) << 52)) 340 341 #define QI_DEV_IOTLB_SIZE 1 341 342 #define QI_DEV_IOTLB_MAX_INVS 32 342 343 ··· 361 360 #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) 362 361 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) 363 362 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) 364 - #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52)) 363 + #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ 364 + ((u64)((pfsid >> 4) & 0xfff) << 52)) 365 365 #define QI_DEV_EIOTLB_MAX_INVS 32 366 366 367 367 /* Page group response descriptor QW0 */