Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: amd: ps: remove the register read and write wrappers.
Instead of acp63_readl() and acp63_writel() wrappers
readl and writel functions can be used directly.
Remove acp63_readl() and acp63_writel() wrappers.
Signed-off-by: Syed Saba Kareem <Syed.SabaKareem@amd.com
Reviewed-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com
Link: https://lore.kernel.org/r/20230426122219.3745586-1-Syed.SabaKareem@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
authored by
Syed Saba Kareem
and committed by
Mark Brown
ec54f810
9abcd240
+46
-60
-10
sound/soc/amd/ps/acp63.h
-10
sound/soc/amd/ps/acp63.h
···
92
92
struct snd_pcm_substream *capture_stream;
93
93
};
94
94
95
-
static inline u32 acp63_readl(void __iomem *base_addr)
96
-
{
97
-
return readl(base_addr);
98
-
}
99
-
100
-
static inline void acp63_writel(u32 val, void __iomem *base_addr)
101
-
{
102
-
writel(val, base_addr);
103
-
}
104
-
105
95
struct acp63_dev_data {
106
96
void __iomem *acp63_base;
107
97
struct resource *res;
+16
-17
sound/soc/amd/ps/pci-ps.c
+16
-17
sound/soc/amd/ps/pci-ps.c
···
22
22
u32 val;
23
23
int timeout;
24
24
25
-
val = acp63_readl(acp_base + ACP_PGFSM_STATUS);
25
+
val = readl(acp_base + ACP_PGFSM_STATUS);
26
26
27
27
if (!val)
28
28
return val;
29
29
30
30
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
31
-
acp63_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
31
+
writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
32
32
timeout = 0;
33
33
while (++timeout < 500) {
34
-
val = acp63_readl(acp_base + ACP_PGFSM_STATUS);
34
+
val = readl(acp_base + ACP_PGFSM_STATUS);
35
35
if (!val)
36
36
return 0;
37
37
udelay(1);
···
44
44
u32 val;
45
45
int timeout;
46
46
47
-
acp63_writel(1, acp_base + ACP_SOFT_RESET);
47
+
writel(1, acp_base + ACP_SOFT_RESET);
48
48
timeout = 0;
49
49
while (++timeout < 500) {
50
-
val = acp63_readl(acp_base + ACP_SOFT_RESET);
50
+
val = readl(acp_base + ACP_SOFT_RESET);
51
51
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
52
52
break;
53
53
cpu_relax();
54
54
}
55
-
acp63_writel(0, acp_base + ACP_SOFT_RESET);
55
+
writel(0, acp_base + ACP_SOFT_RESET);
56
56
timeout = 0;
57
57
while (++timeout < 500) {
58
-
val = acp63_readl(acp_base + ACP_SOFT_RESET);
58
+
val = readl(acp_base + ACP_SOFT_RESET);
59
59
if (!val)
60
60
return 0;
61
61
cpu_relax();
···
65
65
66
66
static void acp63_enable_interrupts(void __iomem *acp_base)
67
67
{
68
-
acp63_writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
68
+
writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
69
69
}
70
70
71
71
static void acp63_disable_interrupts(void __iomem *acp_base)
72
72
{
73
-
acp63_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
74
-
ACP_EXTERNAL_INTR_STAT);
75
-
acp63_writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
76
-
acp63_writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
73
+
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT);
74
+
writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
75
+
writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
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76
}
78
77
79
78
static int acp63_init(void __iomem *acp_base, struct device *dev)
···
84
85
dev_err(dev, "ACP power on failed\n");
85
86
return ret;
86
87
}
87
-
acp63_writel(0x01, acp_base + ACP_CONTROL);
88
+
writel(0x01, acp_base + ACP_CONTROL);
88
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ret = acp63_reset(acp_base);
89
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if (ret) {
90
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dev_err(dev, "ACP reset failed\n");
···
104
105
dev_err(dev, "ACP reset failed\n");
105
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return ret;
106
107
}
107
-
acp63_writel(0, acp_base + ACP_CONTROL);
108
+
writel(0, acp_base + ACP_CONTROL);
108
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return 0;
109
110
}
110
111
···
119
120
if (!adata)
120
121
return IRQ_NONE;
121
122
122
-
val = acp63_readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
123
+
val = readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
123
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if (val & BIT(PDM_DMA_STAT)) {
124
125
pdev_index = adata->pdm_dev_index;
125
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ps_pdm_data = dev_get_drvdata(&adata->pdev[pdev_index]->dev);
126
-
acp63_writel(BIT(PDM_DMA_STAT), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
127
+
writel(BIT(PDM_DMA_STAT), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
127
128
if (ps_pdm_data->capture_stream)
128
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snd_pcm_period_elapsed(ps_pdm_data->capture_stream);
129
130
return IRQ_HANDLED;
···
301
302
dev_err(&pci->dev, "ACP PCI IRQ request failed\n");
302
303
goto de_init;
303
304
}
304
-
val = acp63_readl(adata->acp63_base + ACP_PIN_CONFIG);
305
+
val = readl(adata->acp63_base + ACP_PIN_CONFIG);
305
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get_acp63_device_config(val, pci, adata);
306
307
ret = create_acp63_platform_devs(pci, adata, addr);
307
308
if (ret < 0) {
+30
-33
sound/soc/amd/ps/ps-pdm-dma.c
+30
-33
sound/soc/amd/ps/ps-pdm-dma.c
···
45
45
static void acp63_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size,
46
46
u32 watermark_size, void __iomem *acp_base)
47
47
{
48
-
acp63_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
49
-
acp63_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
50
-
acp63_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
51
-
acp63_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
48
+
writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
49
+
writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
50
+
writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
51
+
writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
52
52
}
53
53
54
54
static void acp63_enable_pdm_clock(void __iomem *acp_base)
···
58
58
pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
59
59
pdm_ctrl = 0x00;
60
60
61
-
acp63_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
62
-
pdm_ctrl = acp63_readl(acp_base + ACP_WOV_MISC_CTRL);
61
+
writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
62
+
pdm_ctrl = readl(acp_base + ACP_WOV_MISC_CTRL);
63
63
pdm_ctrl &= ~ACP_WOV_GAIN_CONTROL;
64
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pdm_ctrl |= FIELD_PREP(ACP_WOV_GAIN_CONTROL, clamp(pdm_gain, 0, 3));
65
-
acp63_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
65
+
writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
66
66
}
67
67
68
68
static void acp63_enable_pdm_interrupts(struct pdm_dev_data *adata)
···
70
70
u32 ext_int_ctrl;
71
71
72
72
mutex_lock(adata->acp_lock);
73
-
ext_int_ctrl = acp63_readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
73
+
ext_int_ctrl = readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
74
74
ext_int_ctrl |= PDM_DMA_INTR_MASK;
75
-
acp63_writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
75
+
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
76
76
mutex_unlock(adata->acp_lock);
77
77
}
78
78
···
81
81
u32 ext_int_ctrl;
82
82
83
83
mutex_lock(adata->acp_lock);
84
-
ext_int_ctrl = acp63_readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
84
+
ext_int_ctrl = readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
85
85
ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
86
-
acp63_writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
86
+
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
87
87
mutex_unlock(adata->acp_lock);
88
88
}
89
89
···
93
93
u32 pdm_enable, pdm_dma_enable;
94
94
95
95
pdm_dma_status = false;
96
-
pdm_enable = acp63_readl(acp_base + ACP_WOV_PDM_ENABLE);
97
-
pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
96
+
pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE);
97
+
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
98
98
if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable & ACP_PDM_DMA_EN_STATUS))
99
99
pdm_dma_status = true;
100
100
···
111
111
pdm_dma_enable = 0x01;
112
112
113
113
acp63_enable_pdm_clock(acp_base);
114
-
acp63_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
115
-
acp63_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
114
+
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
115
+
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
116
116
timeout = 0;
117
117
while (++timeout < ACP_COUNTER) {
118
-
pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
118
+
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
119
119
if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
120
120
return 0;
121
121
udelay(DELAY_US);
···
131
131
pdm_enable = 0x00;
132
132
pdm_dma_enable = 0x00;
133
133
134
-
pdm_enable = acp63_readl(acp_base + ACP_WOV_PDM_ENABLE);
135
-
pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
134
+
pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE);
135
+
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
136
136
if (pdm_dma_enable & 0x01) {
137
137
pdm_dma_enable = 0x02;
138
-
acp63_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
138
+
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
139
139
timeout = 0;
140
140
while (++timeout < ACP_COUNTER) {
141
-
pdm_dma_enable = acp63_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
141
+
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
142
142
if ((pdm_dma_enable & 0x02) == 0x00)
143
143
break;
144
144
udelay(DELAY_US);
···
148
148
}
149
149
if (pdm_enable == ACP_PDM_ENABLE) {
150
150
pdm_enable = ACP_PDM_DISABLE;
151
-
acp63_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
151
+
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
152
152
}
153
-
acp63_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
153
+
writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
154
154
return 0;
155
155
}
156
156
···
164
164
val = PDM_PTE_OFFSET;
165
165
166
166
/* Group Enable */
167
-
acp63_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp63_base +
168
-
ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
169
-
acp63_writel(PAGE_SIZE_4K_ENABLE, rtd->acp63_base +
170
-
ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
167
+
writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp63_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
168
+
writel(PAGE_SIZE_4K_ENABLE, rtd->acp63_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
171
169
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
172
170
/* Load the low address of page int ACP SRAM through SRBM */
173
171
low = lower_32_bits(addr);
174
172
high = upper_32_bits(addr);
175
173
176
-
acp63_writel(low, rtd->acp63_base + ACP_SCRATCH_REG_0 + val);
174
+
writel(low, rtd->acp63_base + ACP_SCRATCH_REG_0 + val);
177
175
high |= BIT(31);
178
-
acp63_writel(high, rtd->acp63_base + ACP_SCRATCH_REG_0 + val + 4);
176
+
writel(high, rtd->acp63_base + ACP_SCRATCH_REG_0 + val + 4);
179
177
val += 8;
180
178
addr += PAGE_SIZE;
181
179
}
···
240
242
u32 high, low;
241
243
u64 byte_count;
242
244
243
-
high = acp63_readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
245
+
high = readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
244
246
byte_count = high;
245
-
low = acp63_readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
247
+
low = readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
246
248
byte_count = (byte_count << 32) | low;
247
249
return byte_count;
248
250
}
···
307
309
case SNDRV_PCM_TRIGGER_START:
308
310
case SNDRV_PCM_TRIGGER_RESUME:
309
311
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
310
-
acp63_writel(ch_mask, rtd->acp63_base + ACP_WOV_PDM_NO_OF_CHANNELS);
311
-
acp63_writel(PDM_DECIMATION_FACTOR, rtd->acp63_base +
312
-
ACP_WOV_PDM_DECIMATION_FACTOR);
312
+
writel(ch_mask, rtd->acp63_base + ACP_WOV_PDM_NO_OF_CHANNELS);
313
+
writel(PDM_DECIMATION_FACTOR, rtd->acp63_base + ACP_WOV_PDM_DECIMATION_FACTOR);
313
314
rtd->bytescount = acp63_pdm_get_byte_count(rtd, substream->stream);
314
315
pdm_status = acp63_check_pdm_dma_status(rtd->acp63_base);
315
316
if (!pdm_status)