+1 -1

drivers/gpu/drm/amd/amdkfd/kfd_device.c

reviewed

··· 1039 1039 1040 1040 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1041 1041 { 1042 1042 - int ret, i; 1042 1042 + int ret = 0, i; 1043 1043 1044 1044 if (!kfd->init_complete) 1045 1045 return 0;

+4 -11

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

reviewed

··· 857 857 int retval; 858 858 struct mqd_manager *mqd_mgr; 859 859 860 860 - mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 861 861 - q->properties.type)]; 860 860 + mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 862 861 863 862 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 864 863 deallocate_hqd(dqm, q); ··· 1443 1444 static int unregister_process(struct device_queue_manager *dqm, 1444 1445 struct qcm_process_device *qpd) 1445 1446 { 1446 1446 - int retval; 1447 1447 + int retval = 0; 1447 1448 struct device_process_node *cur, *next; 1448 1449 1449 1450 pr_debug("qpd->queues_list is %s\n", 1450 1451 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1451 1452 1452 1452 - retval = 0; 1453 1453 dqm_lock(dqm); 1454 1454 1455 1455 list_for_each_entry_safe(cur, next, &dqm->queues, list) { ··· 1478 1480 unsigned int vmid) 1479 1481 { 1480 1482 uint32_t xcc_mask = dqm->dev->xcc_mask; 1481 1481 - int xcc_id, ret; 1483 1483 + int xcc_id, ret = 0; 1482 1484 1483 1485 for_each_inst(xcc_id, xcc_mask) { 1484 1486 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( ··· 1829 1831 { 1830 1832 struct device *dev = dqm->dev->adev->dev; 1831 1833 int retval, num_hw_queue_slots; 1832 1832 - 1833 1833 - retval = 0; 1834 1834 1835 1835 dqm_lock(dqm); 1836 1836 ··· 2781 2785 static int process_termination_cpsch(struct device_queue_manager *dqm, 2782 2786 struct qcm_process_device *qpd) 2783 2787 { 2784 2784 - int retval; 2788 2788 + int retval = 0; 2785 2789 struct queue *q; 2786 2790 struct device *dev = dqm->dev->adev->dev; 2787 2791 struct kernel_queue *kq, *kq_next; ··· 2790 2794 enum kfd_unmap_queues_filter filter = 2791 2795 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 2792 2796 bool found = false; 2793 2793 - 2794 2794 - retval = 0; 2795 2797 2796 2798 dqm_lock(dqm); 2797 2799 ··· 3459 3465 else 3460 3466 per_device_suspended++; 3461 3467 } else if (err != -EBUSY) { 3462 3462 - r = err; 3463 3468 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3464 3469 break; 3465 3470 }

+4 -4

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

reviewed

··· 596 596 struct queue_properties *p, struct mm_struct *mms) 597 597 { 598 598 uint32_t xcc_mask = mm->dev->xcc_mask; 599 599 - int xcc_id, err, inst = 0; 599 599 + int xcc_id, err = 0, inst = 0; 600 600 void *xcc_mqd; 601 601 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 602 602 ··· 620 620 uint32_t pipe_id, uint32_t queue_id) 621 621 { 622 622 uint32_t xcc_mask = mm->dev->xcc_mask; 623 623 - int xcc_id, err, inst = 0; 623 623 + int xcc_id, err = 0, inst = 0; 624 624 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 625 625 struct v9_mqd *m; 626 626 u32 doorbell_off; ··· 818 818 uint32_t pipe_id, uint32_t queue_id) 819 819 { 820 820 uint32_t xcc_mask = mm->dev->xcc_mask; 821 821 - int xcc_id, err, inst = 0; 821 821 + int xcc_id, err = 0, inst = 0; 822 822 void *xcc_mqd; 823 823 struct v9_mqd *m; 824 824 uint64_t mqd_offset; ··· 848 848 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 849 849 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 850 850 uint32_t xcc_mask = mm->dev->xcc_mask; 851 851 - int xcc_id, err, inst = 0; 851 851 + int xcc_id, err = 0, inst = 0; 852 852 void *xcc_mqd; 853 853 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 854 854

-1

drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c

reviewed

··· 174 174 case KFD_QUEUE_TYPE_SDMA_XGMI: 175 175 packet->bitfields2.engine_sel = q->properties.sdma_engine_id + 176 176 engine_sel__mes_map_queues__sdma0_vi; 177 177 - use_static = false; /* no static queues under SDMA */ 178 177 break; 179 178 default: 180 179 WARN(1, "queue type %d", q->properties.type);