Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next
* clk-bindings:
dt-bindings: clock: mediatek: Add power-domains property
dt-bindings: clock: silabs,si5341: Add missing properties
dt-bindings: clock: adi,axi-clkgen: add clock-output-names property
dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding
dt-bindings: clock: Convert silabs,si570 to DT schema
dt-bindings: clock: Convert silabs,si5341 to DT schema
dt-bindings: clock: Convert silabs,si514/544 to DT schema
* clk-cleanup:
clk: tegra: do not overallocate memory for bpmp clocks
clk: ep93xx: Use int type to store negative error codes
dt-bindings: clock: st: flexgen: remove deprecated compatibles
clk: st: flexgen: remove unused compatible
clk: clk-axi-clkgen: remove unneeded semicolon
clk: tegra: Remove redundant semicolons
clk: npcm: select CONFIG_AUXILIARY_BUS
clk: remove unneeded 'fast_io' parameter in regmap_config
* clk-renesas: (27 commits)
clk: renesas: r9a09g05[67]: Reduce differences
clk: renesas: r9a09g047: Add USB3.0 clocks/resets
clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
clk: renesas: r9a09g056: Add clock and reset entries for I3C
clk: renesas: r9a09g057: Add clock and reset entries for I3C
dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
clk: renesas: rzv2h: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
clk: renesas: r9a09g047: Add GPT clocks and resets
clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
clk: renesas: rzg2l: convert from round_rate() to determine_rate()
clk: renesas: r9a07g04[34]: Use tabs instead of spaces
clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL
clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
clk: renesas: r9a08g045: Add MSTOP for GPIO
...
* clk-thead:
clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
clk: thead: support changing DPU pixel clock rate
clk: thead: add support for enabling/disabling PLLs
clk: thead: Correct parent for DPU pixel clocks
clk: thead: th1520-ap: fix parent of padctrl0 clock
clk: thead: th1520-ap: describe gate clocks with clk_gate
* clk-spacemit:
clk: spacemit: fix i2s clock
clk: spacemit: introduce pre-div for ddn clock
dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock
clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
clk: spacemit: fix sspax_clk
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
+929
-547
-3
Documentation/devicetree/bindings/clock/st/st,flexgen.txt
-3
Documentation/devicetree/bindings/clock/st/st,flexgen.txt
···
64
64
audio use case)
65
65
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
66
66
and activate synchronous mode)
67
-
"st,flexgen-stih407-a0"
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67
"st,flexgen-stih410-a0"
69
-
"st,flexgen-stih407-c0"
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68
"st,flexgen-stih410-c0"
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69
"st,flexgen-stih418-c0"
72
-
"st,flexgen-stih407-d0"
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70
"st,flexgen-stih410-d0"
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71
"st,flexgen-stih407-d2"
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72
"st,flexgen-stih418-d2"
+172
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+172
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+
%YAML 1.2
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+
---
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+
$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
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+
$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
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+
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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+
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description:
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+
The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
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Pin multiplexing and GPIO configuration are performed on a per-pin basis.
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+
Each port supports up to 8 pins, each configurable for either GPIO (port mode)
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+
or alternate function mode. Each pin supports function mode values ranging from
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0x0 to 0x2A, allowing selection from up to 43 different functions.
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+
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properties:
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compatible:
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enum:
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- renesas,r9a09g077-pinctrl # RZ/T2H
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- renesas,r9a09g087-pinctrl # RZ/N2H
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+
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reg:
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+
minItems: 1
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items:
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- description: Non-safety I/O Port base
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- description: Safety I/O Port safety region base
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+
- description: Safety I/O Port Non-safety region base
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+
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reg-names:
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+
minItems: 1
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items:
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- const: nsr
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- const: srs
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- const: srn
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+
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gpio-controller: true
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+
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'#gpio-cells':
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const: 2
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description:
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The first cell contains the global GPIO port index, constructed using the
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RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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(e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
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flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
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+
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gpio-ranges:
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maxItems: 1
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+
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clocks:
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maxItems: 1
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+
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power-domains:
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maxItems: 1
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+
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definitions:
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renesas-rzt2h-n2h-pins-node:
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type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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properties:
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pinmux:
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description:
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Values are constructed from I/O port number, pin number, and
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alternate function configuration number using the RZT2H_PORT_PINMUX()
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helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
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pins: true
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phandle: true
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input: true
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input-enable: true
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output-enable: true
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oneOf:
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- required: [pinmux]
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- required: [pins]
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additionalProperties: false
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+
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patternProperties:
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# Grouping nodes: allow multiple "-pins" subnodes within a "-group"
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'.*-group$':
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type: object
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description:
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Pin controller client devices can organize pin configuration entries into
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grouping nodes ending in "-group". These group nodes may contain multiple
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child nodes each ending in "-pins" to configure distinct sets of pins.
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additionalProperties: false
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patternProperties:
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'-pins$':
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$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
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+
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# Standalone "-pins" nodes under client devices or groups
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'-pins$':
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$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
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+
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'-hog$':
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type: object
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description: GPIO hog node
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properties:
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gpio-hog: true
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gpios: true
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input: true
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output-high: true
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output-low: true
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line-name: true
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required:
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- gpio-hog
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- gpios
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additionalProperties: false
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+
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allOf:
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+
- $ref: pinctrl.yaml#
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+
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required:
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+
- compatible
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+
- reg
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+
- reg-names
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+
- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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+
- clocks
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- power-domains
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+
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unevaluatedProperties: false
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+
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+
examples:
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+
- |
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+
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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+
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pinctrl@802c0000 {
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compatible = "renesas,r9a09g077-pinctrl";
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reg = <0x802c0000 0x2000>,
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<0x812c0000 0x2000>,
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<0x802b0000 0x2000>;
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reg-names = "nsr", "srs", "srn";
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+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
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+
gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 288>;
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power-domains = <&cpg>;
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+
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serial0-pins {
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pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
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+
<RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
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};
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+
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+
sd1-pwr-en-hog {
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gpio-hog;
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gpios = <RZT2H_GPIO(39, 2) 0>;
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+
output-high;
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line-name = "sd1_pwr_en";
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+
};
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+
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i2c0-pins {
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+
pins = "RIIC0_SDA", "RIIC0_SCL";
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input-enable;
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+
};
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+
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sd0-sd-group {
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+
ctrl-pins {
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+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
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+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
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+
};
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+
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+
data-pins {
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+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
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+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
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+
};
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+
};
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+
};
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
364
364
config COMMON_CLK_NPCM8XX
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tristate "Clock driver for the NPCM8XX SoC Family"
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depends on ARCH_NPCM || COMPILE_TEST
367
+
select AUXILIARY_BUS
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help
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This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family,
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all the clocks are initialized by the bootloader, so this driver
-1
drivers/clk/actions/owl-common.c
-1
drivers/clk/actions/owl-common.c
+1
-1
drivers/clk/clk-axi-clkgen.c
+1
-1
drivers/clk/clk-axi-clkgen.c
-1
drivers/clk/clk-axm5516.c
-1
drivers/clk/clk-axm5516.c
+2
-1
drivers/clk/clk-ep93xx.c
+2
-1
drivers/clk/clk-ep93xx.c
···
486
486
static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv)
487
487
{
488
488
struct clk_parent_data parent_data = { };
489
-
unsigned int i, idx, ret, clk_uart_div;
489
+
unsigned int i, idx, clk_uart_div;
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struct ep93xx_clk *clk;
491
491
u32 val;
492
+
int ret;
492
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493
494
regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
494
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if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD)
-1
drivers/clk/nxp/clk-lpc32xx.c
-1
drivers/clk/nxp/clk-lpc32xx.c
-1
drivers/clk/qcom/a53-pll.c
-1
drivers/clk/qcom/a53-pll.c
-1
drivers/clk/qcom/a7-pll.c
-1
drivers/clk/qcom/a7-pll.c
-1
drivers/clk/qcom/apss-ipq-pll.c
-1
drivers/clk/qcom/apss-ipq-pll.c
-1
drivers/clk/qcom/clk-cbf-8996.c
-1
drivers/clk/qcom/clk-cbf-8996.c
-1
drivers/clk/qcom/clk-cpu-8996.c
-1
drivers/clk/qcom/clk-cpu-8996.c
-1
drivers/clk/qcom/hfpll.c
-1
drivers/clk/qcom/hfpll.c
-1
drivers/clk/qcom/ipq-cmn-pll.c
-1
drivers/clk/qcom/ipq-cmn-pll.c
+19
-1
drivers/clk/renesas/clk-mstp.c
+19
-1
drivers/clk/renesas/clk-mstp.c
···
303
303
pm_clk_destroy(dev);
304
304
}
305
305
306
+
static struct device_node *cpg_mstp_pd_np __initdata = NULL;
307
+
static struct generic_pm_domain *cpg_mstp_pd_genpd __initdata = NULL;
308
+
306
309
void __init cpg_mstp_add_clk_domain(struct device_node *np)
307
310
{
308
311
struct generic_pm_domain *pd;
···
327
324
pd->detach_dev = cpg_mstp_detach_dev;
328
325
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
329
326
330
-
of_genpd_add_provider_simple(np, pd);
327
+
cpg_mstp_pd_np = of_node_get(np);
328
+
cpg_mstp_pd_genpd = pd;
331
329
}
330
+
331
+
static int __init cpg_mstp_pd_init_provider(void)
332
+
{
333
+
int error;
334
+
335
+
if (!cpg_mstp_pd_np)
336
+
return -ENODEV;
337
+
338
+
error = of_genpd_add_provider_simple(cpg_mstp_pd_np, cpg_mstp_pd_genpd);
339
+
340
+
of_node_put(cpg_mstp_pd_np);
341
+
return error;
342
+
}
343
+
postcore_initcall(cpg_mstp_pd_init_provider);
+70
-70
drivers/clk/renesas/r9a07g043-cpg.c
+70
-70
drivers/clk/renesas/r9a07g043-cpg.c
···
164
164
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
165
165
#ifdef CONFIG_ARM64
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166
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
167
-
0x514, 0, 0),
167
+
0x514, 0, MSTOP(BUS_REG1, BIT(7))),
168
168
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
169
-
0x518, 0, 0),
169
+
0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
170
170
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
171
-
0x518, 1, 0),
171
+
0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
172
172
#endif
173
173
#ifdef CONFIG_RISCV
174
174
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
175
-
0x518, 0, 0),
175
+
0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
176
176
DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
177
-
0x518, 1, 0),
177
+
0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
178
178
#endif
179
179
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
180
-
0x52c, 0, 0),
180
+
0x52c, 0, MSTOP(BUS_REG1, BIT(2))),
181
181
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
182
-
0x52c, 1, 0),
182
+
0x52c, 1, MSTOP(BUS_REG1, BIT(3))),
183
183
DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
184
-
0x534, 0, 0),
184
+
0x534, 0, MSTOP(BUS_REG0, BIT(4))),
185
185
DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
186
-
0x534, 1, 0),
186
+
0x534, 1, MSTOP(BUS_REG0, BIT(5))),
187
187
DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
188
-
0x534, 2, 0),
188
+
0x534, 2, MSTOP(BUS_REG0, BIT(6))),
189
189
DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
190
-
0x538, 0, 0),
190
+
0x538, 0, MSTOP(BUS_MCPU1, BIT(2))),
191
191
DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
192
-
0x548, 0, 0),
192
+
0x548, 0, MSTOP(BUS_REG0, BIT(2))),
193
193
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
194
-
0x548, 1, 0),
194
+
0x548, 1, MSTOP(BUS_REG0, BIT(2))),
195
195
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
196
-
0x550, 0, 0),
196
+
0x550, 0, MSTOP(BUS_MCPU1, BIT(1))),
197
197
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
198
-
0x550, 1, 0),
198
+
0x550, 1, MSTOP(BUS_MCPU1, BIT(1))),
199
199
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
200
-
0x554, 0, 0),
200
+
0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))),
201
201
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
202
-
0x554, 1, 0),
202
+
0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))),
203
203
DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
204
-
0x554, 2, 0),
204
+
0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))),
205
205
DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
206
-
0x554, 3, 0),
206
+
0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))),
207
207
DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
208
-
0x554, 4, 0),
208
+
0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))),
209
209
DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
210
-
0x554, 5, 0),
210
+
0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))),
211
211
DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
212
-
0x554, 6, 0),
212
+
0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))),
213
213
DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
214
-
0x554, 7, 0),
214
+
0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
215
215
#ifdef CONFIG_ARM64
216
-
DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
217
-
0x564, 0, 0),
218
-
DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
219
-
0x564, 1, 0),
220
-
DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
221
-
0x564, 2, 0),
222
-
DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
223
-
0x564, 3, 0),
216
+
DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
217
+
0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
218
+
DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
219
+
0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
220
+
DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
221
+
0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
222
+
DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
223
+
0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
224
224
DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,
225
-
0x56c, 0, 0),
225
+
0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
226
226
DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT,
227
-
0x56c, 0, 0),
227
+
0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
228
228
DEF_MOD("lcdc_clk_d", R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3,
229
-
0x56c, 1, 0),
229
+
0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))),
230
230
#endif
231
231
DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
232
-
0x570, 0, 0),
232
+
0x570, 0, MSTOP(BUS_MCPU1, BIT(10))),
233
233
DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
234
-
0x570, 1, 0),
234
+
0x570, 1, MSTOP(BUS_MCPU1, BIT(10))),
235
235
DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
236
-
0x570, 2, 0),
236
+
0x570, 2, MSTOP(BUS_MCPU1, BIT(11))),
237
237
DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
238
-
0x570, 3, 0),
238
+
0x570, 3, MSTOP(BUS_MCPU1, BIT(11))),
239
239
DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
240
-
0x570, 4, 0),
240
+
0x570, 4, MSTOP(BUS_MCPU1, BIT(12))),
241
241
DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
242
-
0x570, 5, 0),
242
+
0x570, 5, MSTOP(BUS_MCPU1, BIT(12))),
243
243
DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
244
-
0x570, 6, 0),
244
+
0x570, 6, MSTOP(BUS_MCPU1, BIT(13))),
245
245
DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
246
-
0x570, 7, 0),
246
+
0x570, 7, MSTOP(BUS_MCPU1, BIT(13))),
247
247
DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
248
-
0x578, 0, 0),
248
+
0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))),
249
249
DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
250
-
0x578, 1, 0),
250
+
0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))),
251
251
DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
252
-
0x578, 2, 0),
252
+
0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))),
253
253
DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
254
-
0x578, 3, 0),
254
+
0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))),
255
255
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
256
-
0x57c, 0, 0),
256
+
0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
257
257
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
258
-
0x57c, 0, 0),
258
+
0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
259
259
DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
260
-
0x57c, 1, 0),
260
+
0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
261
261
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
262
-
0x57c, 1, 0),
262
+
0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
263
263
DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
264
-
0x580, 0, 0),
264
+
0x580, 0, MSTOP(BUS_MCPU2, BIT(10))),
265
265
DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
266
-
0x580, 1, 0),
266
+
0x580, 1, MSTOP(BUS_MCPU2, BIT(11))),
267
267
DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
268
-
0x580, 2, 0),
268
+
0x580, 2, MSTOP(BUS_MCPU2, BIT(12))),
269
269
DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
270
-
0x580, 3, 0),
270
+
0x580, 3, MSTOP(BUS_MCPU2, BIT(13))),
271
271
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
272
-
0x584, 0, 0),
272
+
0x584, 0, MSTOP(BUS_MCPU2, BIT(1))),
273
273
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
274
-
0x584, 1, 0),
274
+
0x584, 1, MSTOP(BUS_MCPU2, BIT(2))),
275
275
DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
276
-
0x584, 2, 0),
276
+
0x584, 2, MSTOP(BUS_MCPU2, BIT(3))),
277
277
DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
278
-
0x584, 3, 0),
278
+
0x584, 3, MSTOP(BUS_MCPU2, BIT(4))),
279
279
DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
280
-
0x584, 4, 0),
280
+
0x584, 4, MSTOP(BUS_MCPU2, BIT(5))),
281
281
DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
282
-
0x588, 0, 0),
282
+
0x588, 0, MSTOP(BUS_MCPU2, BIT(7))),
283
283
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
284
-
0x588, 1, 0),
284
+
0x588, 1, MSTOP(BUS_MCPU2, BIT(8))),
285
285
DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
286
-
0x590, 0, 0),
286
+
0x590, 0, MSTOP(BUS_MCPU1, BIT(14))),
287
287
DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
288
-
0x590, 1, 0),
288
+
0x590, 1, MSTOP(BUS_MCPU1, BIT(15))),
289
289
DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
290
-
0x590, 2, 0),
290
+
0x590, 2, MSTOP(BUS_MCPU2, BIT(0))),
291
291
DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
292
-
0x594, 0, 0),
292
+
0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
293
293
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
294
-
0x598, 0, 0),
294
+
0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))),
295
295
DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
296
-
0x5a8, 0, 0),
296
+
0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
297
297
DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
298
-
0x5a8, 1, 0),
298
+
0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))),
299
299
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
300
-
0x5ac, 0, 0),
300
+
0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))),
301
301
#ifdef CONFIG_RISCV
302
302
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
303
-
0x608, 0, 0),
303
+
0x608, 0, MSTOP(BUS_REG1, BIT(7))),
304
304
#endif
305
305
};
306
306
+81
-81
drivers/clk/renesas/r9a07g044-cpg.c
+81
-81
drivers/clk/renesas/r9a07g044-cpg.c
···
242
242
} mod_clks = {
243
243
.common = {
244
244
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
245
-
0x514, 0, 0),
245
+
0x514, 0, MSTOP(BUS_REG1, BIT(7))),
246
246
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
247
-
0x518, 0, 0),
247
+
0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
248
248
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
249
-
0x518, 1, 0),
249
+
0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
250
250
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
251
-
0x52c, 0, 0),
251
+
0x52c, 0, MSTOP(BUS_REG1, BIT(2))),
252
252
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
253
-
0x52c, 1, 0),
253
+
0x52c, 1, MSTOP(BUS_REG1, BIT(3))),
254
254
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
255
-
0x534, 0, 0),
255
+
0x534, 0, MSTOP(BUS_REG0, BIT(4))),
256
256
DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
257
-
0x534, 1, 0),
257
+
0x534, 1, MSTOP(BUS_REG0, BIT(5))),
258
258
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
259
-
0x534, 2, 0),
259
+
0x534, 2, MSTOP(BUS_REG0, BIT(6))),
260
260
DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
261
-
0x538, 0, 0),
261
+
0x538, 0, MSTOP(BUS_MCPU1, BIT(2))),
262
262
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
263
-
0x540, 0, 0),
263
+
0x540, 0, MSTOP(BUS_MCPU1, BIT(4))),
264
264
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
265
-
0x544, 0, 0),
265
+
0x544, 0, MSTOP(BUS_MCPU1, BIT(5))),
266
266
DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
267
-
0x544, 1, 0),
267
+
0x544, 1, MSTOP(BUS_MCPU1, BIT(6))),
268
268
DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
269
-
0x544, 2, 0),
269
+
0x544, 2, MSTOP(BUS_MCPU1, BIT(7))),
270
270
DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
271
-
0x544, 3, 0),
271
+
0x544, 3, MSTOP(BUS_MCPU1, BIT(8))),
272
272
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
273
-
0x548, 0, 0),
273
+
0x548, 0, MSTOP(BUS_REG0, BIT(2))),
274
274
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
275
-
0x548, 1, 0),
275
+
0x548, 1, MSTOP(BUS_REG0, BIT(2))),
276
276
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
277
-
0x548, 2, 0),
277
+
0x548, 2, MSTOP(BUS_REG0, BIT(3))),
278
278
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
279
-
0x548, 3, 0),
279
+
0x548, 3, MSTOP(BUS_REG0, BIT(3))),
280
280
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
281
-
0x550, 0, 0),
281
+
0x550, 0, MSTOP(BUS_MCPU1, BIT(1))),
282
282
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
283
-
0x550, 1, 0),
283
+
0x550, 1, MSTOP(BUS_MCPU1, BIT(1))),
284
284
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
285
-
0x554, 0, 0),
285
+
0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))),
286
286
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
287
-
0x554, 1, 0),
287
+
0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))),
288
288
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
289
-
0x554, 2, 0),
289
+
0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))),
290
290
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
291
-
0x554, 3, 0),
291
+
0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))),
292
292
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
293
-
0x554, 4, 0),
293
+
0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))),
294
294
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
295
-
0x554, 5, 0),
295
+
0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))),
296
296
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
297
-
0x554, 6, 0),
297
+
0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))),
298
298
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
299
-
0x554, 7, 0),
299
+
0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
300
300
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
301
-
0x558, 0, 0),
301
+
0x558, 0, MSTOP(BUS_REG1, BIT(4))),
302
302
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
303
303
0x558, 1, 0),
304
304
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
305
305
0x558, 2, 0),
306
-
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
307
-
0x564, 0, 0),
308
-
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
309
-
0x564, 1, 0),
310
-
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
311
-
0x564, 2, 0),
312
-
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
313
-
0x564, 3, 0),
306
+
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
307
+
0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
308
+
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
309
+
0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
310
+
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
311
+
0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
312
+
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
313
+
0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
314
314
DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
315
-
0x568, 0, 0),
315
+
0x568, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
316
316
DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
317
-
0x568, 1, 0),
317
+
0x568, 1, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
318
318
DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
319
-
0x568, 2, 0),
319
+
0x568, 2, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
320
320
DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
321
-
0x568, 3, 0),
321
+
0x568, 3, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
322
322
DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
323
-
0x568, 4, 0),
323
+
0x568, 4, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
324
324
DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
325
-
0x568, 5, 0),
325
+
0x568, 5, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
326
326
DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
327
-
0x56c, 0, 0),
327
+
0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
328
328
DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
329
-
0x56c, 0, 0),
329
+
0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
330
330
DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
331
-
0x56c, 1, 0),
331
+
0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))),
332
332
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
333
-
0x570, 0, 0),
333
+
0x570, 0, MSTOP(BUS_MCPU1, BIT(10))),
334
334
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
335
-
0x570, 1, 0),
335
+
0x570, 1, MSTOP(BUS_MCPU1, BIT(10))),
336
336
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
337
-
0x570, 2, 0),
337
+
0x570, 2, MSTOP(BUS_MCPU1, BIT(11))),
338
338
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
339
-
0x570, 3, 0),
339
+
0x570, 3, MSTOP(BUS_MCPU1, BIT(11))),
340
340
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
341
-
0x570, 4, 0),
341
+
0x570, 4, MSTOP(BUS_MCPU1, BIT(12))),
342
342
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
343
-
0x570, 5, 0),
343
+
0x570, 5, MSTOP(BUS_MCPU1, BIT(12))),
344
344
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
345
-
0x570, 6, 0),
345
+
0x570, 6, MSTOP(BUS_MCPU1, BIT(13))),
346
346
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
347
-
0x570, 7, 0),
347
+
0x570, 7, MSTOP(BUS_MCPU1, BIT(13))),
348
348
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
349
-
0x578, 0, 0),
349
+
0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))),
350
350
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
351
-
0x578, 1, 0),
351
+
0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))),
352
352
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
353
-
0x578, 2, 0),
353
+
0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))),
354
354
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
355
-
0x578, 3, 0),
355
+
0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))),
356
356
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
357
-
0x57c, 0, 0),
357
+
0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
358
358
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
359
-
0x57c, 0, 0),
359
+
0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
360
360
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
361
-
0x57c, 1, 0),
361
+
0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
362
362
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
363
-
0x57c, 1, 0),
363
+
0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
364
364
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
365
-
0x580, 0, 0),
365
+
0x580, 0, MSTOP(BUS_MCPU2, BIT(10))),
366
366
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
367
-
0x580, 1, 0),
367
+
0x580, 1, MSTOP(BUS_MCPU2, BIT(11))),
368
368
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
369
-
0x580, 2, 0),
369
+
0x580, 2, MSTOP(BUS_MCPU2, BIT(12))),
370
370
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
371
-
0x580, 3, 0),
371
+
0x580, 3, MSTOP(BUS_MCPU2, BIT(13))),
372
372
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
373
-
0x584, 0, 0),
373
+
0x584, 0, MSTOP(BUS_MCPU2, BIT(1))),
374
374
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
375
-
0x584, 1, 0),
375
+
0x584, 1, MSTOP(BUS_MCPU2, BIT(2))),
376
376
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
377
-
0x584, 2, 0),
377
+
0x584, 2, MSTOP(BUS_MCPU2, BIT(3))),
378
378
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
379
-
0x584, 3, 0),
379
+
0x584, 3, MSTOP(BUS_MCPU2, BIT(4))),
380
380
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
381
-
0x584, 4, 0),
381
+
0x584, 4, MSTOP(BUS_MCPU2, BIT(5))),
382
382
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
383
-
0x588, 0, 0),
383
+
0x588, 0, MSTOP(BUS_MCPU2, BIT(7))),
384
384
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
385
-
0x588, 1, 0),
385
+
0x588, 1, MSTOP(BUS_MCPU2, BIT(8))),
386
386
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
387
-
0x590, 0, 0),
387
+
0x590, 0, MSTOP(BUS_MCPU1, BIT(14))),
388
388
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
389
-
0x590, 1, 0),
389
+
0x590, 1, MSTOP(BUS_MCPU1, BIT(15))),
390
390
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
391
-
0x590, 2, 0),
391
+
0x590, 2, MSTOP(BUS_MCPU2, BIT(0))),
392
392
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
393
-
0x594, 0, 0),
393
+
0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
394
394
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
395
-
0x598, 0, 0),
395
+
0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))),
396
396
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
397
-
0x5a8, 0, 0),
397
+
0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
398
398
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
399
-
0x5a8, 1, 0),
399
+
0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))),
400
400
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
401
-
0x5ac, 0, 0),
401
+
0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))),
402
402
},
403
403
#ifdef CONFIG_CLK_R9A07G054
404
404
.drp = {
+28
-1
drivers/clk/renesas/r9a08g045-cpg.c
+28
-1
drivers/clk/renesas/r9a08g045-cpg.c
···
183
183
DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
184
184
dtable_1_32, 0, 0, 0, NULL),
185
185
DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
186
+
DEF_FIXED("P5", R9A08G045_CLK_P5, CLK_PLL2_DIV2, 1, 4),
186
187
DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),
187
188
DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
188
189
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
···
285
284
MSTOP(BUS_MCPU2, BIT(5))),
286
285
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,
287
286
MSTOP(BUS_MCPU3, BIT(4))),
288
-
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),
287
+
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0,
288
+
MSTOP(BUS_PERI_CPU, BIT(6))),
289
289
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,
290
290
MSTOP(BUS_MCPU2, BIT(14))),
291
291
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,
292
292
MSTOP(BUS_MCPU2, BIT(14))),
293
293
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
294
294
MSTOP(BUS_MCPU2, BIT(15))),
295
+
DEF_MOD("pci_aclk", R9A08G045_PCI_ACLK, R9A08G045_CLK_M0, 0x608, 0,
296
+
MSTOP(BUS_PERI_COM, BIT(10))),
297
+
DEF_MOD("pci_clkl1pm", R9A08G045_PCI_CLKL1PM, R9A08G045_CLK_ZT, 0x608, 1,
298
+
MSTOP(BUS_PERI_COM, BIT(10))),
299
+
DEF_MOD("i3c_pclk", R9A08G045_I3C_PCLK, R9A08G045_CLK_TSU, 0x610, 0,
300
+
MSTOP(BUS_MCPU3, BIT(10))),
301
+
DEF_MOD("i3c_tclk", R9A08G045_I3C_TCLK, R9A08G045_CLK_P5, 0x610, 1,
302
+
MSTOP(BUS_MCPU3, BIT(10))),
295
303
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,
296
304
MSTOP(BUS_MCPU3, GENMASK(8, 7))),
297
305
};
···
341
331
DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
342
332
DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
343
333
DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
334
+
DEF_RST(R9A08G045_PCI_ARESETN, 0x908, 0),
335
+
DEF_RST(R9A08G045_PCI_RST_B, 0x908, 1),
336
+
DEF_RST(R9A08G045_PCI_RST_GP_B, 0x908, 2),
337
+
DEF_RST(R9A08G045_PCI_RST_PS_B, 0x908, 3),
338
+
DEF_RST(R9A08G045_PCI_RST_RSM_B, 0x908, 4),
339
+
DEF_RST(R9A08G045_PCI_RST_CFG_B, 0x908, 5),
340
+
DEF_RST(R9A08G045_PCI_RST_LOAD_B, 0x908, 6),
341
+
DEF_RST(R9A08G045_I3C_TRESETN, 0x910, 0),
342
+
DEF_RST(R9A08G045_I3C_PRESETN, 0x910, 1),
344
343
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
345
344
};
346
345
···
359
340
MOD_CLK_BASE + R9A08G045_IA55_CLK,
360
341
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
361
342
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
343
+
};
344
+
345
+
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
346
+
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
362
347
};
363
348
364
349
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
···
380
357
.mod_clks = r9a08g045_mod_clks,
381
358
.num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
382
359
.num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
360
+
361
+
/* No PM modules Clocks */
362
+
.no_pm_mod_clks = r9a08g045_no_pm_mod_clks,
363
+
.num_no_pm_mod_clks = ARRAY_SIZE(r9a08g045_no_pm_mod_clks),
383
364
384
365
/* Resets */
385
366
.resets = r9a08g045_resets,
+35
-1
drivers/clk/renesas/r9a09g047-cpg.c
+35
-1
drivers/clk/renesas/r9a09g047-cpg.c
···
16
16
17
17
enum clk_ids {
18
18
/* Core Clock Outputs exported to DT */
19
-
LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
19
+
LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
20
20
21
21
/* External Input Clocks */
22
22
CLK_AUDIO_EXTAL,
···
48
48
CLK_PLLDTY_ACPU_DIV2,
49
49
CLK_PLLDTY_ACPU_DIV4,
50
50
CLK_PLLDTY_DIV8,
51
+
CLK_PLLDTY_RCPU,
52
+
CLK_PLLDTY_RCPU_DIV4,
51
53
CLK_PLLETH_DIV_250_FIX,
52
54
CLK_PLLETH_DIV_125_FIX,
53
55
CLK_CSDIV_PLLETH_GBE0,
···
159
157
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
160
158
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
161
159
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
160
+
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
161
+
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
162
162
163
163
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
164
164
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
···
181
177
CLK_PLLETH_DIV_125_FIX, 1, 1),
182
178
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
183
179
CLK_PLLETH_DIV_125_FIX, 1, 1),
180
+
DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
181
+
DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
184
182
};
185
183
186
184
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
185
+
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
186
+
BUS_MSTOP(5, BIT(9))),
187
+
DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
188
+
BUS_MSTOP(3, BIT(2))),
189
+
DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
190
+
BUS_MSTOP(3, BIT(3))),
191
+
DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
192
+
BUS_MSTOP(10, BIT(11))),
193
+
DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
194
+
BUS_MSTOP(10, BIT(12))),
187
195
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
188
196
BUS_MSTOP_NONE),
189
197
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
190
198
BUS_MSTOP(3, BIT(5))),
199
+
DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
200
+
BUS_MSTOP(6, BIT(11))),
201
+
DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
202
+
BUS_MSTOP(6, BIT(12))),
191
203
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
192
204
BUS_MSTOP(1, BIT(0))),
193
205
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
···
278
258
BUS_MSTOP(8, BIT(4))),
279
259
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
280
260
BUS_MSTOP(8, BIT(4))),
261
+
DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
262
+
BUS_MSTOP(7, BIT(12))),
263
+
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
264
+
BUS_MSTOP(7, BIT(14))),
281
265
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
282
266
BUS_MSTOP(8, BIT(5)), 1),
283
267
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
···
324
300
325
301
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
326
302
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
303
+
DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
304
+
DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
305
+
DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
306
+
DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
307
+
DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
327
308
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
328
309
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
329
310
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
311
+
DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
312
+
DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
313
+
DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */
314
+
DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */
330
315
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
331
316
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
332
317
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
···
358
325
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
359
326
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
360
327
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
328
+
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
361
329
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
362
330
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
363
331
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
+12
-4
drivers/clk/renesas/r9a09g056-cpg.c
+12
-4
drivers/clk/renesas/r9a09g056-cpg.c
···
36
36
CLK_PLLCM33_DIV4,
37
37
CLK_PLLCM33_DIV5,
38
38
CLK_PLLCM33_DIV16,
39
+
CLK_PLLCM33_GEAR,
39
40
CLK_SMUX2_XSPI_CLK0,
40
41
CLK_SMUX2_XSPI_CLK1,
41
42
CLK_PLLCM33_XSPI,
42
-
CLK_PLLCM33_GEAR,
43
43
CLK_PLLCLN_DIV2,
44
44
CLK_PLLCLN_DIV8,
45
45
CLK_PLLCLN_DIV16,
···
120
120
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
121
121
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
122
122
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
123
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
123
124
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
124
125
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
125
126
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
126
127
dtable_2_16),
127
-
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
128
128
129
129
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
130
130
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
···
205
205
BUS_MSTOP(5, BIT(13))),
206
206
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
207
207
BUS_MSTOP(3, BIT(14))),
208
+
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
209
+
BUS_MSTOP(10, BIT(15))),
210
+
DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
211
+
BUS_MSTOP(10, BIT(15))),
212
+
DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
213
+
BUS_MSTOP(10, BIT(15))),
208
214
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
209
215
BUS_MSTOP(3, BIT(13))),
210
216
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
···
314
308
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
315
309
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
316
310
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
311
+
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
312
+
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
317
313
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
318
314
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
319
315
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
···
325
317
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
326
318
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
327
319
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
328
-
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
329
-
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
320
+
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
321
+
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
330
322
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
331
323
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
332
324
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+9
-2
drivers/clk/renesas/r9a09g057-cpg.c
+9
-2
drivers/clk/renesas/r9a09g057-cpg.c
···
134
134
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
135
135
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
136
136
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
137
-
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR,
138
-
CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
139
137
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
138
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
140
139
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
141
140
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
142
141
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
···
259
260
BUS_MSTOP(11, BIT(2))),
260
261
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
261
262
BUS_MSTOP(3, BIT(14))),
263
+
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
264
+
BUS_MSTOP(10, BIT(15))),
265
+
DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
266
+
BUS_MSTOP(10, BIT(15))),
267
+
DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
268
+
BUS_MSTOP(10, BIT(15))),
262
269
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
263
270
BUS_MSTOP(3, BIT(13))),
264
271
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
···
408
403
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
409
404
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
410
405
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
406
+
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
407
+
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
411
408
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
412
409
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
413
410
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
+40
-1
drivers/clk/renesas/r9a09g077-cpg.c
+40
-1
drivers/clk/renesas/r9a09g077-cpg.c
···
46
46
#define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1)
47
47
#define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1)
48
48
#define DIVCA55S CONF_PACK(SCKCR2, 12, 1)
49
+
#define DIVSCI5ASYNC CONF_PACK(SCKCR2, 18, 2)
49
50
50
51
#define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2)
52
+
#define DIVSCI1ASYNC CONF_PACK(SCKCR3, 8, 2)
53
+
#define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2)
54
+
#define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
55
+
#define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
51
56
52
57
#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
53
58
···
72
67
73
68
enum clk_ids {
74
69
/* Core Clock Outputs exported to DT */
75
-
LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS,
70
+
LAST_DT_CORE_CLK = R9A09G077_ETCLKE,
76
71
77
72
/* External Input Clocks */
78
73
CLK_EXTAL,
···
89
84
CLK_SEL_CLK_PLL4,
90
85
CLK_PLL4D1,
91
86
CLK_SCI0ASYNC,
87
+
CLK_SCI1ASYNC,
88
+
CLK_SCI2ASYNC,
89
+
CLK_SCI3ASYNC,
90
+
CLK_SCI4ASYNC,
91
+
CLK_SCI5ASYNC,
92
92
93
93
/* Module Clocks */
94
94
MOD_CLK_BASE,
···
143
133
DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
144
134
DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
145
135
dtable_24_25_30_32),
136
+
DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
137
+
dtable_24_25_30_32),
138
+
DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
139
+
dtable_24_25_30_32),
140
+
DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
141
+
dtable_24_25_30_32),
142
+
DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
143
+
dtable_24_25_30_32),
144
+
DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
145
+
dtable_24_25_30_32),
146
146
147
147
/* Core output clk */
148
148
DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
···
166
146
DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
167
147
dtable_1_2),
168
148
DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
149
+
DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
169
150
DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
170
151
DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
152
+
DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
171
153
DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
172
154
DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
155
+
DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
156
+
DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
157
+
DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
158
+
DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
159
+
DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
160
+
DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
173
161
};
174
162
175
163
static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
176
164
DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
165
+
DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC),
166
+
DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC),
167
+
DEF_MOD("sci3fck", 11, CLK_SCI3ASYNC),
168
+
DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
177
169
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
178
170
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
171
+
DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
172
+
DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
173
+
DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),
174
+
DEF_MOD("usb", 408, R9A09G077_CLK_PCLKAM),
175
+
DEF_MOD("gmac1", 416, R9A09G077_CLK_PCLKAM),
176
+
DEF_MOD("gmac2", 417, R9A09G077_CLK_PCLKAM),
177
+
DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
179
178
DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
180
179
DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
181
180
DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
+5
-2
drivers/clk/renesas/renesas-cpg-mssr.c
+5
-2
drivers/clk/renesas/renesas-cpg-mssr.c
···
1082
1082
1083
1083
of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) {
1084
1084
int idx;
1085
+
unsigned int *new_ids;
1085
1086
1086
1087
if (it.node != priv->np)
1087
1088
continue;
···
1093
1092
if (args[0] != CPG_MOD)
1094
1093
continue;
1095
1094
1096
-
ids = krealloc_array(ids, (num + 1), sizeof(*ids), GFP_KERNEL);
1097
-
if (!ids) {
1095
+
new_ids = krealloc_array(ids, (num + 1), sizeof(*ids), GFP_KERNEL);
1096
+
if (!new_ids) {
1098
1097
of_node_put(it.node);
1098
+
kfree(ids);
1099
1099
return -ENOMEM;
1100
1100
}
1101
+
ids = new_ids;
1101
1102
1102
1103
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1103
1104
idx = MOD_CLK_PACK_10(args[1]); /* for DEF_MOD_STB() */
+26
-35
drivers/clk/renesas/rzg2l-cpg.c
+26
-35
drivers/clk/renesas/rzg2l-cpg.c
···
824
824
return pll5_rate;
825
825
}
826
826
827
-
static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
828
-
unsigned long rate,
829
-
unsigned long *parent_rate)
827
+
static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
828
+
struct clk_rate_request *req)
830
829
{
831
-
return rate;
830
+
return 0;
832
831
}
833
832
834
833
static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
···
901
902
902
903
static const struct clk_ops rzg2l_cpg_sipll5_ops = {
903
904
.recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
904
-
.round_rate = rzg2l_cpg_sipll5_round_rate,
905
+
.determine_rate = rzg2l_cpg_sipll5_determine_rate,
905
906
.set_rate = rzg2l_cpg_sipll5_set_rate,
906
907
};
907
908
···
1638
1639
1639
1640
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
1640
1641
1641
-
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
1642
-
unsigned long id)
1642
+
static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
1643
+
unsigned long id, bool assert)
1643
1644
{
1644
1645
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1645
1646
const struct rzg2l_cpg_info *info = priv->info;
···
1647
1648
u32 mask = BIT(info->resets[id].bit);
1648
1649
s8 monbit = info->resets[id].monbit;
1649
1650
u32 value = mask << 16;
1651
+
int ret;
1650
1652
1651
-
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
1653
+
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
1654
+
assert ? "assert" : "deassert", id, CLK_RST_R(reg));
1652
1655
1656
+
if (!assert)
1657
+
value |= mask;
1653
1658
writel(value, priv->base + CLK_RST_R(reg));
1654
1659
1655
1660
if (info->has_clk_mon_regs) {
···
1667
1664
return 0;
1668
1665
}
1669
1666
1670
-
return readl_poll_timeout_atomic(priv->base + reg, value,
1671
-
value & mask, 10, 200);
1667
+
ret = readl_poll_timeout_atomic(priv->base + reg, value,
1668
+
assert == !!(value & mask), 10, 200);
1669
+
if (ret && !assert) {
1670
+
value = mask << 16;
1671
+
writel(value, priv->base + CLK_RST_R(info->resets[id].off));
1672
+
}
1673
+
1674
+
return ret;
1675
+
}
1676
+
1677
+
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
1678
+
unsigned long id)
1679
+
{
1680
+
return __rzg2l_cpg_assert(rcdev, id, true);
1672
1681
}
1673
1682
1674
1683
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
1675
1684
unsigned long id)
1676
1685
{
1677
-
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1678
-
const struct rzg2l_cpg_info *info = priv->info;
1679
-
unsigned int reg = info->resets[id].off;
1680
-
u32 mask = BIT(info->resets[id].bit);
1681
-
s8 monbit = info->resets[id].monbit;
1682
-
u32 value = (mask << 16) | mask;
1683
-
1684
-
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
1685
-
CLK_RST_R(reg));
1686
-
1687
-
writel(value, priv->base + CLK_RST_R(reg));
1688
-
1689
-
if (info->has_clk_mon_regs) {
1690
-
reg = CLK_MRST_R(reg);
1691
-
} else if (monbit >= 0) {
1692
-
reg = CPG_RST_MON;
1693
-
mask = BIT(monbit);
1694
-
} else {
1695
-
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1696
-
udelay(35);
1697
-
return 0;
1698
-
}
1699
-
1700
-
return readl_poll_timeout_atomic(priv->base + reg, value,
1701
-
!(value & mask), 10, 200);
1686
+
return __rzg2l_cpg_assert(rcdev, id, false);
1702
1687
}
1703
1688
1704
1689
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
+1
drivers/clk/renesas/rzg2l-cpg.h
+1
drivers/clk/renesas/rzg2l-cpg.h
···
34
34
#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
35
35
#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
36
36
#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
37
+
#define CPG_BUS_PERI_VIDEO_MSTOP (0xB78)
37
38
#define CPG_BUS_REG0_MSTOP (0xB7C)
38
39
#define CPG_BUS_REG1_MSTOP (0xB80)
39
40
#define CPG_BUS_TZCDDR_MSTOP (0xB84)
+9
-13
drivers/clk/renesas/rzv2h-cpg.c
+9
-13
drivers/clk/renesas/rzv2h-cpg.c
···
294
294
divider->flags, divider->width);
295
295
}
296
296
297
-
static long rzv2h_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
298
-
unsigned long *prate)
299
-
{
300
-
struct clk_divider *divider = to_clk_divider(hw);
301
-
302
-
return divider_round_rate(hw, rate, prate, divider->table,
303
-
divider->width, divider->flags);
304
-
}
305
-
306
297
static int rzv2h_ddiv_determine_rate(struct clk_hw *hw,
307
298
struct clk_rate_request *req)
308
299
{
···
350
359
351
360
static const struct clk_ops rzv2h_ddiv_clk_divider_ops = {
352
361
.recalc_rate = rzv2h_ddiv_recalc_rate,
353
-
.round_rate = rzv2h_ddiv_round_rate,
354
362
.determine_rate = rzv2h_ddiv_determine_rate,
355
363
.set_rate = rzv2h_ddiv_set_rate,
356
364
};
···
854
864
u32 mask = BIT(priv->resets[id].reset_bit);
855
865
u8 monbit = priv->resets[id].mon_bit;
856
866
u32 value = mask << 16;
867
+
int ret;
857
868
858
869
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
859
870
assert ? "assert" : "deassert", id, reg);
···
866
875
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
867
876
mask = BIT(monbit);
868
877
869
-
return readl_poll_timeout_atomic(priv->base + reg, value,
870
-
assert ? (value & mask) : !(value & mask),
871
-
10, 200);
878
+
ret = readl_poll_timeout_atomic(priv->base + reg, value,
879
+
assert == !!(value & mask), 10, 200);
880
+
if (ret && !assert) {
881
+
value = mask << 16;
882
+
writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));
883
+
}
884
+
885
+
return ret;
872
886
}
873
887
874
888
static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
+53
-8
drivers/clk/spacemit/ccu-k1.c
+53
-8
drivers/clk/spacemit/ccu-k1.c
···
136
136
CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0);
137
137
138
138
CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
139
-
CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 0);
140
-
CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 0);
139
+
CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0);
140
+
CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0);
141
141
142
142
CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0);
143
143
144
-
CCU_FACTOR_GATE_DEFINE(i2s_sysclk, CCU_PARENT_HW(pll1_d16_153p6), MPMU_ISCCR, BIT(31), 50, 1);
145
-
CCU_FACTOR_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_sysclk), MPMU_ISCCR, BIT(29), 1, 1);
144
+
CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1);
145
+
146
+
static const struct clk_parent_data i2s_153p6_base_parents[] = {
147
+
CCU_PARENT_HW(i2s_153p6),
148
+
CCU_PARENT_HW(pll1_d8_307p2),
149
+
};
150
+
CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0);
151
+
152
+
static const struct clk_parent_data i2s_sysclk_src_parents[] = {
153
+
CCU_PARENT_HW(pll1_d96_25p6),
154
+
CCU_PARENT_HW(i2s_153p6_base)
155
+
};
156
+
CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0);
157
+
158
+
CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0);
159
+
160
+
CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1);
161
+
/*
162
+
* Divider of i2s_bclk always implies a 1/2 factor, which is
163
+
* described by i2s_bclk_factor.
164
+
*/
165
+
CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, 27, 2, BIT(29), 0);
146
166
147
167
static const struct clk_parent_data apb_parents[] = {
148
168
CCU_PARENT_HW(pll1_d96_25p6),
···
267
247
268
248
CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
269
249
270
-
static const struct clk_parent_data sspa_parents[] = {
250
+
/*
251
+
* When i2s_bclk is selected as the parent clock of sspa,
252
+
* the hardware requires bit3 to be set
253
+
*/
254
+
CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0);
255
+
CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0);
256
+
257
+
static const struct clk_parent_data sspa0_parents[] = {
271
258
CCU_PARENT_HW(pll1_d384_6p4),
272
259
CCU_PARENT_HW(pll1_d192_12p8),
273
260
CCU_PARENT_HW(pll1_d96_25p6),
···
282
255
CCU_PARENT_HW(pll1_d768_3p2),
283
256
CCU_PARENT_HW(pll1_d1536_1p6),
284
257
CCU_PARENT_HW(pll1_d3072_0p8),
285
-
CCU_PARENT_HW(i2s_bclk),
258
+
CCU_PARENT_HW(sspa0_i2s_bclk),
286
259
};
287
-
CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
288
-
CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
260
+
CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
261
+
262
+
static const struct clk_parent_data sspa1_parents[] = {
263
+
CCU_PARENT_HW(pll1_d384_6p4),
264
+
CCU_PARENT_HW(pll1_d192_12p8),
265
+
CCU_PARENT_HW(pll1_d96_25p6),
266
+
CCU_PARENT_HW(pll1_d48_51p2),
267
+
CCU_PARENT_HW(pll1_d768_3p2),
268
+
CCU_PARENT_HW(pll1_d1536_1p6),
269
+
CCU_PARENT_HW(pll1_d3072_0p8),
270
+
CCU_PARENT_HW(sspa1_i2s_bclk),
271
+
};
272
+
CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
273
+
289
274
CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
290
275
CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0);
291
276
CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
···
795
756
[CLK_I2S_BCLK] = &i2s_bclk.common.hw,
796
757
[CLK_APB] = &apb_clk.common.hw,
797
758
[CLK_WDT_BUS] = &wdt_bus_clk.common.hw,
759
+
[CLK_I2S_153P6] = &i2s_153p6.common.hw,
760
+
[CLK_I2S_153P6_BASE] = &i2s_153p6_base.common.hw,
761
+
[CLK_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw,
762
+
[CLK_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw,
798
763
};
799
764
800
765
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
···
908
865
[CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw,
909
866
[CLK_TSEN_BUS] = &tsen_bus_clk.common.hw,
910
867
[CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw,
868
+
[CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw,
869
+
[CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw,
911
870
};
912
871
913
872
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
+13
-10
drivers/clk/spacemit/ccu_ddn.c
+13
-10
drivers/clk/spacemit/ccu_ddn.c
···
22
22
23
23
#include "ccu_ddn.h"
24
24
25
-
static unsigned long ccu_ddn_calc_rate(unsigned long prate,
26
-
unsigned long num, unsigned long den)
25
+
static unsigned long ccu_ddn_calc_rate(unsigned long prate, unsigned long num,
26
+
unsigned long den, unsigned int pre_div)
27
27
{
28
-
return prate * den / 2 / num;
28
+
return prate * den / pre_div / num;
29
29
}
30
30
31
31
static unsigned long ccu_ddn_calc_best_rate(struct ccu_ddn *ddn,
32
32
unsigned long rate, unsigned long prate,
33
33
unsigned long *num, unsigned long *den)
34
34
{
35
-
rational_best_approximation(rate, prate / 2,
35
+
rational_best_approximation(rate, prate / ddn->pre_div,
36
36
ddn->den_mask >> ddn->den_shift,
37
37
ddn->num_mask >> ddn->num_shift,
38
38
den, num);
39
-
return ccu_ddn_calc_rate(prate, *num, *den);
39
+
return ccu_ddn_calc_rate(prate, *num, *den, ddn->pre_div);
40
40
}
41
41
42
-
static long ccu_ddn_round_rate(struct clk_hw *hw, unsigned long rate,
43
-
unsigned long *prate)
42
+
static int ccu_ddn_determine_rate(struct clk_hw *hw,
43
+
struct clk_rate_request *req)
44
44
{
45
45
struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
46
46
unsigned long num, den;
47
47
48
-
return ccu_ddn_calc_best_rate(ddn, rate, *prate, &num, &den);
48
+
req->rate = ccu_ddn_calc_best_rate(ddn, req->rate,
49
+
req->best_parent_rate, &num, &den);
50
+
51
+
return 0;
49
52
}
50
53
51
54
static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate)
···
61
58
num = (val & ddn->num_mask) >> ddn->num_shift;
62
59
den = (val & ddn->den_mask) >> ddn->den_shift;
63
60
64
-
return ccu_ddn_calc_rate(prate, num, den);
61
+
return ccu_ddn_calc_rate(prate, num, den, ddn->pre_div);
65
62
}
66
63
67
64
static int ccu_ddn_set_rate(struct clk_hw *hw, unsigned long rate,
···
81
78
82
79
const struct clk_ops spacemit_ccu_ddn_ops = {
83
80
.recalc_rate = ccu_ddn_recalc_rate,
84
-
.round_rate = ccu_ddn_round_rate,
81
+
.determine_rate = ccu_ddn_determine_rate,
85
82
.set_rate = ccu_ddn_set_rate,
86
83
};
+4
-2
drivers/clk/spacemit/ccu_ddn.h
+4
-2
drivers/clk/spacemit/ccu_ddn.h
···
18
18
unsigned int num_shift;
19
19
unsigned int den_mask;
20
20
unsigned int den_shift;
21
+
unsigned int pre_div;
21
22
};
22
23
23
24
#define CCU_DDN_INIT(_name, _parent, _flags) \
24
25
CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
25
26
26
27
#define CCU_DDN_DEFINE(_name, _parent, _reg_ctrl, _num_shift, _num_width, \
27
-
_den_shift, _den_width, _flags) \
28
+
_den_shift, _den_width, _pre_div, _flags) \
28
29
static struct ccu_ddn _name = { \
29
30
.common = { \
30
31
.reg_ctrl = _reg_ctrl, \
···
34
33
.num_mask = GENMASK(_num_shift + _num_width - 1, _num_shift), \
35
34
.num_shift = _num_shift, \
36
35
.den_mask = GENMASK(_den_shift + _den_width - 1, _den_shift), \
37
-
.den_shift = _den_shift, \
36
+
.den_shift = _den_shift, \
37
+
.pre_div = _pre_div, \
38
38
}
39
39
40
40
static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
+7
-5
drivers/clk/spacemit/ccu_mix.c
+7
-5
drivers/clk/spacemit/ccu_mix.c
···
80
80
MIX_FC_TIMEOUT_US);
81
81
}
82
82
83
-
static long ccu_factor_round_rate(struct clk_hw *hw, unsigned long rate,
84
-
unsigned long *prate)
83
+
static int ccu_factor_determine_rate(struct clk_hw *hw,
84
+
struct clk_rate_request *req)
85
85
{
86
-
return ccu_factor_recalc_rate(hw, *prate);
86
+
req->rate = ccu_factor_recalc_rate(hw, req->best_parent_rate);
87
+
88
+
return 0;
87
89
}
88
90
89
91
static int ccu_factor_set_rate(struct clk_hw *hw, unsigned long rate,
···
200
198
};
201
199
202
200
const struct clk_ops spacemit_ccu_factor_ops = {
203
-
.round_rate = ccu_factor_round_rate,
201
+
.determine_rate = ccu_factor_determine_rate,
204
202
.recalc_rate = ccu_factor_recalc_rate,
205
203
.set_rate = ccu_factor_set_rate,
206
204
};
···
222
220
.enable = ccu_gate_enable,
223
221
.is_enabled = ccu_gate_is_enabled,
224
222
225
-
.round_rate = ccu_factor_round_rate,
223
+
.determine_rate = ccu_factor_determine_rate,
226
224
.recalc_rate = ccu_factor_recalc_rate,
227
225
.set_rate = ccu_factor_set_rate,
228
226
};
+6
-4
drivers/clk/spacemit/ccu_pll.c
+6
-4
drivers/clk/spacemit/ccu_pll.c
···
125
125
return entry ? entry->rate : 0;
126
126
}
127
127
128
-
static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
129
-
unsigned long *prate)
128
+
static int ccu_pll_determine_rate(struct clk_hw *hw,
129
+
struct clk_rate_request *req)
130
130
{
131
131
struct ccu_pll *pll = hw_to_ccu_pll(hw);
132
132
133
-
return ccu_pll_lookup_best_rate(pll, rate)->rate;
133
+
req->rate = ccu_pll_lookup_best_rate(pll, req->rate)->rate;
134
+
135
+
return 0;
134
136
}
135
137
136
138
static int ccu_pll_init(struct clk_hw *hw)
···
154
152
.disable = ccu_pll_disable,
155
153
.set_rate = ccu_pll_set_rate,
156
154
.recalc_rate = ccu_pll_recalc_rate,
157
-
.round_rate = ccu_pll_round_rate,
155
+
.determine_rate = ccu_pll_determine_rate,
158
156
.is_enabled = ccu_pll_is_enabled,
159
157
};
-80
drivers/clk/st/clk-flexgen.c
-80
drivers/clk/st/clk-flexgen.c
···
303
303
.mode = 1,
304
304
};
305
305
306
-
static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
307
-
/* This clk needs to be on so that memory interface is accessible */
308
-
{ .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
309
-
};
310
-
311
-
static const struct clkgen_data clkgen_stih407_a0 = {
312
-
.outputs = clkgen_stih407_a0_clk_out,
313
-
.outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
314
-
};
315
-
316
306
static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
317
307
/* Those clks need to be on so that memory interface is accessible */
318
308
{ .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
···
312
322
static const struct clkgen_data clkgen_stih410_a0 = {
313
323
.outputs = clkgen_stih410_a0_clk_out,
314
324
.outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
315
-
};
316
-
317
-
static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
318
-
{ .name = "clk-icn-gpu", },
319
-
{ .name = "clk-fdma", },
320
-
{ .name = "clk-nand", },
321
-
{ .name = "clk-hva", },
322
-
{ .name = "clk-proc-stfe", },
323
-
{ .name = "clk-proc-tp", },
324
-
{ .name = "clk-rx-icn-dmu", },
325
-
{ .name = "clk-rx-icn-hva", },
326
-
/* This clk needs to be on to keep bus interconnect alive */
327
-
{ .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
328
-
/* This clk needs to be on to keep bus interconnect alive */
329
-
{ .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
330
-
{ .name = "clk-mmc-0", },
331
-
{ .name = "clk-mmc-1", },
332
-
{ .name = "clk-jpegdec", },
333
-
/* This clk needs to be on to keep A9 running */
334
-
{ .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
335
-
{ .name = "clk-ic-bdisp-0", },
336
-
{ .name = "clk-ic-bdisp-1", },
337
-
{ .name = "clk-pp-dmu", },
338
-
{ .name = "clk-vid-dmu", },
339
-
{ .name = "clk-dss-lpc", },
340
-
{ .name = "clk-st231-aud-0", },
341
-
{ .name = "clk-st231-gp-1", },
342
-
{ .name = "clk-st231-dmu", },
343
-
/* This clk needs to be on to keep bus interconnect alive */
344
-
{ .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
345
-
{ .name = "clk-tx-icn-disp-1", },
346
-
/* This clk needs to be on to keep bus interconnect alive */
347
-
{ .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
348
-
{ .name = "clk-stfe-frc2", },
349
-
{ .name = "clk-eth-phy", },
350
-
{ .name = "clk-eth-ref-phyclk", },
351
-
{ .name = "clk-flash-promip", },
352
-
{ .name = "clk-main-disp", },
353
-
{ .name = "clk-aux-disp", },
354
-
{ .name = "clk-compo-dvp", },
355
-
};
356
-
357
-
static const struct clkgen_data clkgen_stih407_c0 = {
358
-
.outputs = clkgen_stih407_c0_clk_out,
359
-
.outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
360
325
};
361
326
362
327
static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
···
427
482
.outputs_nb = ARRAY_SIZE(clkgen_stih418_c0_clk_out),
428
483
};
429
484
430
-
static const struct clkgen_clk_out clkgen_stih407_d0_clk_out[] = {
431
-
{ .name = "clk-pcm-0", },
432
-
{ .name = "clk-pcm-1", },
433
-
{ .name = "clk-pcm-2", },
434
-
{ .name = "clk-spdiff", },
435
-
};
436
-
437
-
static const struct clkgen_data clkgen_stih407_d0 = {
438
-
.flags = CLK_SET_RATE_PARENT,
439
-
.outputs = clkgen_stih407_d0_clk_out,
440
-
.outputs_nb = ARRAY_SIZE(clkgen_stih407_d0_clk_out),
441
-
};
442
-
443
485
static const struct clkgen_clk_out clkgen_stih410_d0_clk_out[] = {
444
486
{ .name = "clk-pcm-0", },
445
487
{ .name = "clk-pcm-1", },
···
529
597
.data = &clkgen_video,
530
598
},
531
599
{
532
-
.compatible = "st,flexgen-stih407-a0",
533
-
.data = &clkgen_stih407_a0,
534
-
},
535
-
{
536
600
.compatible = "st,flexgen-stih410-a0",
537
601
.data = &clkgen_stih410_a0,
538
-
},
539
-
{
540
-
.compatible = "st,flexgen-stih407-c0",
541
-
.data = &clkgen_stih407_c0,
542
602
},
543
603
{
544
604
.compatible = "st,flexgen-stih410-c0",
···
539
615
{
540
616
.compatible = "st,flexgen-stih418-c0",
541
617
.data = &clkgen_stih418_c0,
542
-
},
543
-
{
544
-
.compatible = "st,flexgen-stih407-d0",
545
-
.data = &clkgen_stih407_d0,
546
618
},
547
619
{
548
620
.compatible = "st,flexgen-stih410-d0",
+1
-1
drivers/clk/tegra/clk-bpmp.c
+1
-1
drivers/clk/tegra/clk-bpmp.c
+1
-1
drivers/clk/tegra/clk-dfll.c
+1
-1
drivers/clk/tegra/clk-dfll.c
+290
-210
drivers/clk/thead/clk-th1520-ap.c
+290
-210
drivers/clk/thead/clk-th1520-ap.c
···
18
18
#define TH1520_PLL_FBDIV GENMASK(19, 8)
19
19
#define TH1520_PLL_REFDIV GENMASK(5, 0)
20
20
#define TH1520_PLL_BYPASS BIT(30)
21
+
#define TH1520_PLL_VCO_RST BIT(29)
21
22
#define TH1520_PLL_DSMPD BIT(24)
22
23
#define TH1520_PLL_FRAC GENMASK(23, 0)
23
24
#define TH1520_PLL_FRAC_BITS 24
···
49
48
};
50
49
51
50
struct ccu_gate {
52
-
u32 enable;
53
-
struct ccu_common common;
51
+
int clkid;
52
+
u32 reg;
53
+
struct clk_gate gate;
54
54
};
55
55
56
56
struct ccu_div {
57
57
u32 enable;
58
+
u32 div_en;
58
59
struct ccu_div_internal div;
59
60
struct ccu_internal mux;
60
61
struct ccu_common common;
···
90
87
0), \
91
88
}
92
89
93
-
#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \
90
+
#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \
94
91
struct ccu_gate _struct = { \
95
-
.enable = _gate, \
96
-
.common = { \
97
-
.clkid = _clkid, \
98
-
.cfg0 = _reg, \
92
+
.clkid = _clkid, \
93
+
.reg = _reg, \
94
+
.gate = { \
95
+
.bit_idx = _bit, \
99
96
.hw.init = CLK_HW_INIT_PARENTS_DATA( \
100
97
_name, \
101
98
_parent, \
···
121
118
struct ccu_common *common = hw_to_ccu_common(hw);
122
119
123
120
return container_of(common, struct ccu_div, common);
124
-
}
125
-
126
-
static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
127
-
{
128
-
struct ccu_common *common = hw_to_ccu_common(hw);
129
-
130
-
return container_of(common, struct ccu_gate, common);
131
121
}
132
122
133
123
static u8 ccu_get_parent_helper(struct ccu_common *common,
···
193
197
return rate;
194
198
}
195
199
200
+
static int ccu_div_determine_rate(struct clk_hw *hw,
201
+
struct clk_rate_request *req)
202
+
{
203
+
struct ccu_div *cd = hw_to_ccu_div(hw);
204
+
unsigned int val;
205
+
206
+
if (cd->div_en)
207
+
return divider_determine_rate(hw, req, NULL,
208
+
cd->div.width, cd->div.flags);
209
+
210
+
regmap_read(cd->common.map, cd->common.cfg0, &val);
211
+
val = val >> cd->div.shift;
212
+
val &= GENMASK(cd->div.width - 1, 0);
213
+
return divider_ro_determine_rate(hw, req, NULL, cd->div.width,
214
+
cd->div.flags, val);
215
+
}
216
+
217
+
static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
218
+
unsigned long parent_rate)
219
+
{
220
+
struct ccu_div *cd = hw_to_ccu_div(hw);
221
+
int val = divider_get_val(rate, parent_rate, NULL,
222
+
cd->div.width, cd->div.flags);
223
+
unsigned int curr_val, reg_val;
224
+
225
+
if (val < 0)
226
+
return val;
227
+
228
+
regmap_read(cd->common.map, cd->common.cfg0, ®_val);
229
+
curr_val = reg_val >> cd->div.shift;
230
+
curr_val &= GENMASK(cd->div.width - 1, 0);
231
+
232
+
if (!cd->div_en && curr_val != val)
233
+
return -EINVAL;
234
+
235
+
reg_val &= ~cd->div_en;
236
+
regmap_write(cd->common.map, cd->common.cfg0, reg_val);
237
+
udelay(1);
238
+
239
+
reg_val &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
240
+
reg_val |= val << cd->div.shift;
241
+
regmap_write(cd->common.map, cd->common.cfg0, reg_val);
242
+
243
+
reg_val |= cd->div_en;
244
+
regmap_write(cd->common.map, cd->common.cfg0, reg_val);
245
+
246
+
return 0;
247
+
}
248
+
196
249
static u8 ccu_div_get_parent(struct clk_hw *hw)
197
250
{
198
251
struct ccu_div *cd = hw_to_ccu_div(hw);
···
284
239
.get_parent = ccu_div_get_parent,
285
240
.set_parent = ccu_div_set_parent,
286
241
.recalc_rate = ccu_div_recalc_rate,
287
-
.determine_rate = clk_hw_determine_rate_no_reparent,
242
+
.set_rate = ccu_div_set_rate,
243
+
.determine_rate = ccu_div_determine_rate,
288
244
};
245
+
246
+
static void ccu_pll_disable(struct clk_hw *hw)
247
+
{
248
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
249
+
250
+
regmap_set_bits(pll->common.map, pll->common.cfg1,
251
+
TH1520_PLL_VCO_RST);
252
+
}
253
+
254
+
static int ccu_pll_enable(struct clk_hw *hw)
255
+
{
256
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
257
+
258
+
return regmap_clear_bits(pll->common.map, pll->common.cfg1,
259
+
TH1520_PLL_VCO_RST);
260
+
}
261
+
262
+
static int ccu_pll_is_enabled(struct clk_hw *hw)
263
+
{
264
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
265
+
266
+
return !regmap_test_bits(pll->common.map, pll->common.cfg1,
267
+
TH1520_PLL_VCO_RST);
268
+
}
289
269
290
270
static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw,
291
271
unsigned long parent_rate)
···
369
299
}
370
300
371
301
static const struct clk_ops clk_pll_ops = {
302
+
.disable = ccu_pll_disable,
303
+
.enable = ccu_pll_enable,
304
+
.is_enabled = ccu_pll_is_enabled,
372
305
.recalc_rate = ccu_pll_recalc_rate,
373
306
};
374
307
···
387
314
.hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll0",
388
315
osc_24m_clk,
389
316
&clk_pll_ops,
390
-
0),
317
+
CLK_IS_CRITICAL),
391
318
},
392
319
};
393
320
···
399
326
.hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll1",
400
327
osc_24m_clk,
401
328
&clk_pll_ops,
402
-
0),
329
+
CLK_IS_CRITICAL),
403
330
},
404
331
};
405
332
···
411
338
.hw.init = CLK_HW_INIT_PARENTS_DATA("gmac-pll",
412
339
osc_24m_clk,
413
340
&clk_pll_ops,
414
-
0),
341
+
CLK_IS_CRITICAL),
415
342
},
416
343
};
417
344
···
431
358
.hw.init = CLK_HW_INIT_PARENTS_DATA("video-pll",
432
359
osc_24m_clk,
433
360
&clk_pll_ops,
434
-
0),
361
+
CLK_IS_CRITICAL),
435
362
},
436
363
};
437
364
···
483
410
.hw.init = CLK_HW_INIT_PARENTS_DATA("tee-pll",
484
411
osc_24m_clk,
485
412
&clk_pll_ops,
486
-
0),
413
+
CLK_IS_CRITICAL),
487
414
},
488
415
};
489
416
···
559
486
.hw.init = CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk",
560
487
gmac_pll_clk_parent,
561
488
&ccu_div_ops,
562
-
0),
489
+
CLK_IS_CRITICAL),
563
490
},
564
491
};
565
492
···
581
508
.hw.init = CLK_HW_INIT_PARENTS_DATA("axi-aclk",
582
509
axi_parents,
583
510
&ccu_div_ops,
584
-
0),
511
+
CLK_IS_CRITICAL),
585
512
},
586
513
};
587
514
···
730
657
.hw.init = CLK_HW_INIT_PARENTS_DATA("apb-pclk",
731
658
apb_parents,
732
659
&ccu_div_ops,
733
-
CLK_IGNORE_UNUSED),
660
+
CLK_IS_CRITICAL),
734
661
},
735
662
};
736
663
···
761
688
.hw.init = CLK_HW_INIT_PARENTS_HW("vi",
762
689
video_pll_clk_parent,
763
690
&ccu_div_ops,
764
-
0),
691
+
CLK_IS_CRITICAL),
765
692
},
766
693
};
767
694
···
786
713
.hw.init = CLK_HW_INIT_PARENTS_HW("vo-axi",
787
714
video_pll_clk_parent,
788
715
&ccu_div_ops,
789
-
0),
716
+
CLK_IS_CRITICAL),
790
717
},
791
718
};
792
719
···
811
738
.hw.init = CLK_HW_INIT_PARENTS_HW("vp-axi",
812
739
video_pll_clk_parent,
813
740
&ccu_div_ops,
814
-
CLK_IGNORE_UNUSED),
741
+
CLK_IS_CRITICAL),
815
742
},
816
743
};
817
744
···
829
756
};
830
757
831
758
static struct ccu_div dpu0_clk = {
759
+
.div_en = BIT(8),
832
760
.div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
833
761
.common = {
834
762
.clkid = CLK_DPU0,
···
837
763
.hw.init = CLK_HW_INIT_PARENTS_HW("dpu0",
838
764
dpu0_pll_clk_parent,
839
765
&ccu_div_ops,
840
-
0),
766
+
CLK_SET_RATE_UNGATE),
841
767
},
842
768
};
843
769
770
+
static const struct clk_parent_data dpu0_clk_pd[] = {
771
+
{ .hw = &dpu0_clk.common.hw }
772
+
};
773
+
844
774
static struct ccu_div dpu1_clk = {
775
+
.div_en = BIT(8),
845
776
.div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
846
777
.common = {
847
778
.clkid = CLK_DPU1,
···
854
775
.hw.init = CLK_HW_INIT_PARENTS_HW("dpu1",
855
776
dpu1_pll_clk_parent,
856
777
&ccu_div_ops,
857
-
0),
778
+
CLK_SET_RATE_UNGATE),
858
779
},
780
+
};
781
+
782
+
static const struct clk_parent_data dpu1_clk_pd[] = {
783
+
{ .hw = &dpu1_clk.common.hw }
859
784
};
860
785
861
786
static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref",
···
869
786
{ .hw = &emmc_sdio_ref_clk.hw },
870
787
};
871
788
872
-
static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, BIT(4), 0);
873
-
static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, BIT(5), 0);
789
+
static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, 4, 0);
790
+
static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, 5, 0);
874
791
static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_aclk_pd,
875
-
0x134, BIT(8), 0);
792
+
0x134, 8, CLK_IS_CRITICAL);
876
793
static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
877
-
0x134, BIT(7), 0);
794
+
0x134, 7, CLK_IS_CRITICAL);
878
795
static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd,
879
-
0x138, BIT(8), CLK_IGNORE_UNUSED);
796
+
0x138, 8, CLK_IS_CRITICAL);
880
797
static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
881
-
0x140, BIT(9), CLK_IGNORE_UNUSED);
798
+
0x140, 9, CLK_IS_CRITICAL);
882
799
static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
883
-
0x150, BIT(9), CLK_IGNORE_UNUSED);
800
+
0x150, 9, CLK_IS_CRITICAL);
884
801
static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", perisys_ahb_hclk_pd,
885
-
0x150, BIT(10), CLK_IGNORE_UNUSED);
802
+
0x150, 10, CLK_IS_CRITICAL);
886
803
static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_pd,
887
-
0x150, BIT(11), CLK_IGNORE_UNUSED);
804
+
0x150, 11, CLK_IS_CRITICAL);
888
805
static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hclk", perisys_ahb_hclk_pd,
889
-
0x150, BIT(12), 0);
890
-
static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, BIT(5), 0);
891
-
static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(13), 0);
892
-
static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", emmc_sdio_ref_clk_pd, 0x204, BIT(30), 0);
893
-
static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, BIT(26), 0);
894
-
static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_pd, 0x204, BIT(24), 0);
895
-
static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x204, BIT(23), 0);
896
-
static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb_pclk_pd, 0x204, BIT(22), 0);
897
-
static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_pd, 0x204, BIT(21), 0);
898
-
static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0x204, BIT(20), 0);
899
-
static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, BIT(19), 0);
900
-
static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, BIT(18), 0);
901
-
static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", video_pll_clk_pd, 0x204, BIT(17), 0);
902
-
static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", video_pll_clk_pd, 0x204, BIT(16), 0);
903
-
static CCU_GATE(CLK_SPI, spi_clk, "spi", video_pll_clk_pd, 0x204, BIT(15), 0);
904
-
static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk_pd, 0x204, BIT(14), 0);
905
-
static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk_pd, 0x204, BIT(13), 0);
906
-
static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk_pd, 0x204, BIT(12), 0);
907
-
static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk_pd, 0x204, BIT(11), 0);
908
-
static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk_pd, 0x204, BIT(10), 0);
909
-
static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk_pd, 0x204, BIT(9), 0);
910
-
static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x204, BIT(8), 0);
911
-
static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x204, BIT(7), 0);
912
-
static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0x204, BIT(6), 0);
913
-
static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, BIT(5), 0);
914
-
static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, BIT(4), 0);
915
-
static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", perisys_apb_pclk_pd, 0x204, BIT(3), 0);
916
-
static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", perisys_apb_pclk_pd, 0x204, BIT(2), 0);
917
-
static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", perisys_apb_pclk_pd, 0x204, BIT(1), 0);
918
-
static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", perisys_apb_pclk_pd, 0x204, BIT(0), 0);
919
-
static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", ahb2_cpusys_hclk_pd, 0x208, BIT(10), 0);
920
-
static CCU_GATE(CLK_DMA, dma_clk, "dma", axi4_cpusys2_aclk_pd, 0x208, BIT(8), 0);
921
-
static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208, BIT(7), 0);
922
-
static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", apb3_cpusys_pclk_pd, 0x208, BIT(6), 0);
923
-
static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", apb3_cpusys_pclk_pd, 0x208, BIT(5), 0);
924
-
static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", apb3_cpusys_pclk_pd, 0x208, BIT(4), 0);
925
-
static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", apb3_cpusys_pclk_pd, 0x208, BIT(3), 0);
926
-
static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", apb3_cpusys_pclk_pd, 0x208, BIT(2), 0);
927
-
static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x208, BIT(1), 0);
928
-
static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x208, BIT(0), 0);
929
-
static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", axi_aclk_pd, 0x20c, BIT(4), 0);
930
-
static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0);
931
-
static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0);
932
-
static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0);
806
+
0x150, 12, 0);
807
+
static const struct clk_parent_data perisys_apb4_hclk_pd[] = {
808
+
{ .hw = &perisys_apb4_hclk.gate.hw },
809
+
};
810
+
811
+
static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, 5, CLK_IS_CRITICAL);
812
+
static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, 13, CLK_IS_CRITICAL);
813
+
static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", emmc_sdio_ref_clk_pd, 0x204, 30, 0);
814
+
static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, 26, 0);
815
+
static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_pd, 0x204, 24, 0);
816
+
static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x204, 23, 0);
817
+
static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb4_hclk_pd, 0x204, 22, 0);
818
+
static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_pd, 0x204, 21, 0);
819
+
static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0x204, 20, 0);
820
+
static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, 19, 0);
821
+
static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, 18, 0);
822
+
static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", video_pll_clk_pd, 0x204, 17, 0);
823
+
static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", video_pll_clk_pd, 0x204, 16, 0);
824
+
static CCU_GATE(CLK_SPI, spi_clk, "spi", video_pll_clk_pd, 0x204, 15, 0);
825
+
static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk_pd, 0x204, 14, 0);
826
+
static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk_pd, 0x204, 13, 0);
827
+
static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk_pd, 0x204, 12, 0);
828
+
static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk_pd, 0x204, 11, 0);
829
+
static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk_pd, 0x204, 10, 0);
830
+
static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk_pd, 0x204, 9, 0);
831
+
static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x204, 8, 0);
832
+
static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x204, 7, 0);
833
+
static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0x204, 6, 0);
834
+
static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, 5, 0);
835
+
static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, 4, 0);
836
+
static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", perisys_apb_pclk_pd, 0x204, 3, 0);
837
+
static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", perisys_apb_pclk_pd, 0x204, 2, 0);
838
+
static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", perisys_apb_pclk_pd, 0x204, 1, 0);
839
+
static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", perisys_apb_pclk_pd, 0x204, 0, 0);
840
+
static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", ahb2_cpusys_hclk_pd, 0x208, 10, 0);
841
+
static CCU_GATE(CLK_DMA, dma_clk, "dma", axi4_cpusys2_aclk_pd, 0x208, 8, 0);
842
+
static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208, 7, 0);
843
+
static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", apb3_cpusys_pclk_pd, 0x208, 6, 0);
844
+
static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", apb3_cpusys_pclk_pd, 0x208, 5, 0);
845
+
static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", apb3_cpusys_pclk_pd, 0x208, 4, 0);
846
+
static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", apb3_cpusys_pclk_pd, 0x208, 3, 0);
847
+
static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", apb3_cpusys_pclk_pd, 0x208, 2, 0);
848
+
static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x208, 1, 0);
849
+
static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x208, 0, 0);
850
+
static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", axi_aclk_pd, 0x20c, 4, 0);
851
+
static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, 3, 0);
852
+
static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, 2, 0);
853
+
static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, 1, 0);
933
854
934
855
static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk",
935
-
video_pll_clk_pd, 0x0, BIT(0), 0);
856
+
video_pll_clk_pd, 0x0, 0, CLK_IS_CRITICAL);
936
857
static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd,
937
-
0x0, BIT(3), 0);
858
+
0x0, 3, 0);
938
859
static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",
939
-
video_pll_clk_pd, 0x0, BIT(4), 0);
860
+
video_pll_clk_pd, 0x0, 4, CLK_IS_CRITICAL);
940
861
static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",
941
-
video_pll_clk_pd, 0x0, BIT(5), 0);
862
+
dpu0_clk_pd, 0x0, 5, CLK_SET_RATE_PARENT);
942
863
static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",
943
-
video_pll_clk_pd, 0x0, BIT(6), 0);
864
+
dpu1_clk_pd, 0x0, 6, CLK_SET_RATE_PARENT);
944
865
static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0,
945
-
BIT(7), 0);
866
+
7, 0);
946
867
static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0,
947
-
BIT(8), 0);
868
+
8, 0);
948
869
static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0,
949
-
BIT(9), 0);
870
+
9, 0);
950
871
static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd,
951
-
0x0, BIT(10), 0);
872
+
0x0, 10, 0);
952
873
static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0,
953
-
BIT(11), 0);
874
+
11, 0);
954
875
static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd,
955
-
0x0, BIT(12), 0);
876
+
0x0, 12, 0);
956
877
static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk",
957
-
video_pll_clk_pd, 0x0, BIT(13), 0);
878
+
video_pll_clk_pd, 0x0, 13, 0);
958
879
static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk",
959
-
video_pll_clk_pd, 0x0, BIT(14), 0);
880
+
video_pll_clk_pd, 0x0, 14, 0);
960
881
static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk",
961
-
video_pll_clk_pd, 0x0, BIT(15), 0);
882
+
video_pll_clk_pd, 0x0, 15, 0);
962
883
static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk",
963
-
video_pll_clk_pd, 0x0, BIT(16), 0);
884
+
video_pll_clk_pd, 0x0, 16, 0);
964
885
static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk",
965
-
video_pll_clk_pd, 0x0, BIT(17), 0);
886
+
video_pll_clk_pd, 0x0, 17, 0);
966
887
static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk",
967
-
video_pll_clk_pd, 0x0, BIT(18), 0);
888
+
video_pll_clk_pd, 0x0, 18, 0);
968
889
static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_pd,
969
-
0x0, BIT(19), 0);
890
+
0x0, 19, 0);
970
891
static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk",
971
-
video_pll_clk_pd, 0x0, BIT(20), 0);
892
+
video_pll_clk_pd, 0x0, 20, CLK_IS_CRITICAL);
972
893
static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk",
973
-
video_pll_clk_pd, 0x0, BIT(21), 0);
894
+
video_pll_clk_pd, 0x0, 21, CLK_IS_CRITICAL);
974
895
static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk",
975
-
video_pll_clk_pd, 0x0, BIT(22), 0);
896
+
video_pll_clk_pd, 0x0, 22, 0);
976
897
static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk,
977
-
"iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0);
898
+
"iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, 23, 0);
978
899
static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk,
979
-
"iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0);
900
+
"iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, 24, 0);
980
901
static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk,
981
-
"iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0);
902
+
"iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, 25, 0);
982
903
static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk",
983
-
video_pll_clk_pd, 0x0, BIT(27), 0);
904
+
video_pll_clk_pd, 0x0, 27, CLK_IS_CRITICAL);
984
905
static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk",
985
-
video_pll_clk_pd, 0x0, BIT(28), 0);
906
+
video_pll_clk_pd, 0x0, 28, CLK_IS_CRITICAL);
986
907
static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk",
987
-
video_pll_clk_pd, 0x0, BIT(29), 0);
908
+
video_pll_clk_pd, 0x0, 29, CLK_IS_CRITICAL);
988
909
static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk",
989
-
video_pll_clk_pd, 0x0, BIT(30), 0);
910
+
video_pll_clk_pd, 0x0, 30, 0);
990
911
static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk",
991
-
video_pll_clk_pd, 0x0, BIT(31), 0);
912
+
video_pll_clk_pd, 0x0, 31, 0);
992
913
static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd,
993
-
0x4, BIT(0), 0);
914
+
0x4, 0, 0);
994
915
995
916
static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m",
996
917
&gmac_pll_clk.common.hw, 10, 1, 0);
···
1050
963
&uart_sclk,
1051
964
};
1052
965
1053
-
static struct ccu_common *th1520_gate_clks[] = {
1054
-
&emmc_sdio_clk.common,
1055
-
&aon2cpu_a2x_clk.common,
1056
-
&x2x_cpusys_clk.common,
1057
-
&brom_clk.common,
1058
-
&bmu_clk.common,
1059
-
&cpu2aon_x2h_clk.common,
1060
-
&cpu2peri_x2h_clk.common,
1061
-
&cpu2vp_clk.common,
1062
-
&perisys_apb1_hclk.common,
1063
-
&perisys_apb2_hclk.common,
1064
-
&perisys_apb3_hclk.common,
1065
-
&perisys_apb4_hclk.common,
1066
-
&npu_axi_clk.common,
1067
-
&gmac1_clk.common,
1068
-
&padctrl1_clk.common,
1069
-
&dsmart_clk.common,
1070
-
&padctrl0_clk.common,
1071
-
&gmac_axi_clk.common,
1072
-
&gpio3_clk.common,
1073
-
&gmac0_clk.common,
1074
-
&pwm_clk.common,
1075
-
&qspi0_clk.common,
1076
-
&qspi1_clk.common,
1077
-
&spi_clk.common,
1078
-
&uart0_pclk.common,
1079
-
&uart1_pclk.common,
1080
-
&uart2_pclk.common,
1081
-
&uart3_pclk.common,
1082
-
&uart4_pclk.common,
1083
-
&uart5_pclk.common,
1084
-
&gpio0_clk.common,
1085
-
&gpio1_clk.common,
1086
-
&gpio2_clk.common,
1087
-
&i2c0_clk.common,
1088
-
&i2c1_clk.common,
1089
-
&i2c2_clk.common,
1090
-
&i2c3_clk.common,
1091
-
&i2c4_clk.common,
1092
-
&i2c5_clk.common,
1093
-
&spinlock_clk.common,
1094
-
&dma_clk.common,
1095
-
&mbox0_clk.common,
1096
-
&mbox1_clk.common,
1097
-
&mbox2_clk.common,
1098
-
&mbox3_clk.common,
1099
-
&wdt0_clk.common,
1100
-
&wdt1_clk.common,
1101
-
&timer0_clk.common,
1102
-
&timer1_clk.common,
1103
-
&sram0_clk.common,
1104
-
&sram1_clk.common,
1105
-
&sram2_clk.common,
1106
-
&sram3_clk.common,
966
+
static struct ccu_gate *th1520_gate_clks[] = {
967
+
&emmc_sdio_clk,
968
+
&aon2cpu_a2x_clk,
969
+
&x2x_cpusys_clk,
970
+
&brom_clk,
971
+
&bmu_clk,
972
+
&cpu2aon_x2h_clk,
973
+
&cpu2peri_x2h_clk,
974
+
&cpu2vp_clk,
975
+
&perisys_apb1_hclk,
976
+
&perisys_apb2_hclk,
977
+
&perisys_apb3_hclk,
978
+
&perisys_apb4_hclk,
979
+
&npu_axi_clk,
980
+
&gmac1_clk,
981
+
&padctrl1_clk,
982
+
&dsmart_clk,
983
+
&padctrl0_clk,
984
+
&gmac_axi_clk,
985
+
&gpio3_clk,
986
+
&gmac0_clk,
987
+
&pwm_clk,
988
+
&qspi0_clk,
989
+
&qspi1_clk,
990
+
&spi_clk,
991
+
&uart0_pclk,
992
+
&uart1_pclk,
993
+
&uart2_pclk,
994
+
&uart3_pclk,
995
+
&uart4_pclk,
996
+
&uart5_pclk,
997
+
&gpio0_clk,
998
+
&gpio1_clk,
999
+
&gpio2_clk,
1000
+
&i2c0_clk,
1001
+
&i2c1_clk,
1002
+
&i2c2_clk,
1003
+
&i2c3_clk,
1004
+
&i2c4_clk,
1005
+
&i2c5_clk,
1006
+
&spinlock_clk,
1007
+
&dma_clk,
1008
+
&mbox0_clk,
1009
+
&mbox1_clk,
1010
+
&mbox2_clk,
1011
+
&mbox3_clk,
1012
+
&wdt0_clk,
1013
+
&wdt1_clk,
1014
+
&timer0_clk,
1015
+
&timer1_clk,
1016
+
&sram0_clk,
1017
+
&sram1_clk,
1018
+
&sram2_clk,
1019
+
&sram3_clk,
1107
1020
};
1108
1021
1109
-
static struct ccu_common *th1520_vo_gate_clks[] = {
1110
-
&axi4_vo_aclk.common,
1111
-
&gpu_core_clk.common,
1112
-
&gpu_cfg_aclk.common,
1113
-
&dpu0_pixelclk.common,
1114
-
&dpu1_pixelclk.common,
1115
-
&dpu_hclk.common,
1116
-
&dpu_aclk.common,
1117
-
&dpu_cclk.common,
1118
-
&hdmi_sfr_clk.common,
1119
-
&hdmi_pclk.common,
1120
-
&hdmi_cec_clk.common,
1121
-
&mipi_dsi0_pclk.common,
1122
-
&mipi_dsi1_pclk.common,
1123
-
&mipi_dsi0_cfg_clk.common,
1124
-
&mipi_dsi1_cfg_clk.common,
1125
-
&mipi_dsi0_refclk.common,
1126
-
&mipi_dsi1_refclk.common,
1127
-
&hdmi_i2s_clk.common,
1128
-
&x2h_dpu1_aclk.common,
1129
-
&x2h_dpu_aclk.common,
1130
-
&axi4_vo_pclk.common,
1131
-
&iopmp_vosys_dpu_pclk.common,
1132
-
&iopmp_vosys_dpu1_pclk.common,
1133
-
&iopmp_vosys_gpu_pclk.common,
1134
-
&iopmp_dpu1_aclk.common,
1135
-
&iopmp_dpu_aclk.common,
1136
-
&iopmp_gpu_aclk.common,
1137
-
&mipi_dsi0_pixclk.common,
1138
-
&mipi_dsi1_pixclk.common,
1139
-
&hdmi_pixclk.common
1022
+
static struct ccu_gate *th1520_vo_gate_clks[] = {
1023
+
&axi4_vo_aclk,
1024
+
&gpu_core_clk,
1025
+
&gpu_cfg_aclk,
1026
+
&dpu0_pixelclk,
1027
+
&dpu1_pixelclk,
1028
+
&dpu_hclk,
1029
+
&dpu_aclk,
1030
+
&dpu_cclk,
1031
+
&hdmi_sfr_clk,
1032
+
&hdmi_pclk,
1033
+
&hdmi_cec_clk,
1034
+
&mipi_dsi0_pclk,
1035
+
&mipi_dsi1_pclk,
1036
+
&mipi_dsi0_cfg_clk,
1037
+
&mipi_dsi1_cfg_clk,
1038
+
&mipi_dsi0_refclk,
1039
+
&mipi_dsi1_refclk,
1040
+
&hdmi_i2s_clk,
1041
+
&x2h_dpu1_aclk,
1042
+
&x2h_dpu_aclk,
1043
+
&axi4_vo_pclk,
1044
+
&iopmp_vosys_dpu_pclk,
1045
+
&iopmp_vosys_dpu1_pclk,
1046
+
&iopmp_vosys_gpu_pclk,
1047
+
&iopmp_dpu1_aclk,
1048
+
&iopmp_dpu_aclk,
1049
+
&iopmp_gpu_aclk,
1050
+
&mipi_dsi0_pixclk,
1051
+
&mipi_dsi1_pixclk,
1052
+
&hdmi_pixclk
1140
1053
};
1141
1054
1142
1055
static const struct regmap_config th1520_clk_regmap_config = {
1143
1056
.reg_bits = 32,
1144
1057
.val_bits = 32,
1145
1058
.reg_stride = 4,
1146
-
.fast_io = true,
1147
1059
};
1148
1060
1149
1061
struct th1520_plat_data {
1150
1062
struct ccu_common **th1520_pll_clks;
1151
1063
struct ccu_common **th1520_div_clks;
1152
1064
struct ccu_mux **th1520_mux_clks;
1153
-
struct ccu_common **th1520_gate_clks;
1065
+
struct ccu_gate **th1520_gate_clks;
1154
1066
1155
1067
int nr_clks;
1156
1068
int nr_pll_clks;
···
1188
1102
1189
1103
struct regmap *map;
1190
1104
void __iomem *base;
1191
-
struct clk_hw *hw;
1192
1105
int ret, i;
1193
1106
1194
1107
plat_data = device_get_match_data(&pdev->dev);
···
1246
1161
}
1247
1162
1248
1163
for (i = 0; i < plat_data->nr_gate_clks; i++) {
1249
-
struct ccu_gate *cg = hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->hw);
1164
+
struct ccu_gate *cg = plat_data->th1520_gate_clks[i];
1250
1165
1251
-
plat_data->th1520_gate_clks[i]->map = map;
1166
+
cg->gate.reg = base + cg->reg;
1252
1167
1253
-
hw = devm_clk_hw_register_gate_parent_data(dev,
1254
-
cg->common.hw.init->name,
1255
-
cg->common.hw.init->parent_data,
1256
-
cg->common.hw.init->flags,
1257
-
base + cg->common.cfg0,
1258
-
ffs(cg->enable) - 1, 0, NULL);
1259
-
if (IS_ERR(hw))
1260
-
return PTR_ERR(hw);
1168
+
ret = devm_clk_hw_register(dev, &cg->gate.hw);
1169
+
if (ret)
1170
+
return ret;
1261
1171
1262
-
priv->hws[cg->common.clkid] = hw;
1172
+
priv->hws[cg->clkid] = &cg->gate.hw;
1263
1173
}
1264
1174
1265
1175
if (plat_data == &th1520_ap_platdata) {
+2
include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+2
include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+6
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+6
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
···
25
25
#define R9A09G077_CLK_PCLKM 13
26
26
#define R9A09G077_CLK_PCLKL 14
27
27
#define R9A09G077_SDHI_CLKHS 15
28
+
#define R9A09G077_USB_CLK 16
29
+
#define R9A09G077_ETCLKA 17
30
+
#define R9A09G077_ETCLKB 18
31
+
#define R9A09G077_ETCLKC 19
32
+
#define R9A09G077_ETCLKD 20
33
+
#define R9A09G077_ETCLKE 21
28
34
29
35
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
+6
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+6
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
···
25
25
#define R9A09G087_CLK_PCLKM 13
26
26
#define R9A09G087_CLK_PCLKL 14
27
27
#define R9A09G087_SDHI_CLKHS 15
28
+
#define R9A09G087_USB_CLK 16
29
+
#define R9A09G087_ETCLKA 17
30
+
#define R9A09G087_ETCLKB 18
31
+
#define R9A09G087_ETCLKC 19
32
+
#define R9A09G087_ETCLKD 20
33
+
#define R9A09G087_ETCLKE 21
28
34
29
35
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
+6
include/dt-bindings/clock/spacemit,k1-syscon.h
+6
include/dt-bindings/clock/spacemit,k1-syscon.h
···
77
77
#define CLK_I2S_BCLK 30
78
78
#define CLK_APB 31
79
79
#define CLK_WDT_BUS 32
80
+
#define CLK_I2S_153P6 33
81
+
#define CLK_I2S_153P6_BASE 34
82
+
#define CLK_I2S_SYSCLK_SRC 35
83
+
#define CLK_I2S_BCLK_FACTOR 36
80
84
81
85
/* MPMU resets */
82
86
#define RESET_WDT 0
···
186
182
#define CLK_SSPA1_BUS 97
187
183
#define CLK_TSEN_BUS 98
188
184
#define CLK_IPC_AP2AUD_BUS 99
185
+
#define CLK_SSPA0_I2S_BCLK 100
186
+
#define CLK_SSPA1_I2S_BCLK 101
189
187
190
188
/* APBC resets */
191
189
#define RESET_UART0 0
+22
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
+22
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* This header provides constants for Renesas RZ/T2H family pinctrl bindings.
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
9
+
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
10
+
11
+
#define RZT2H_PINS_PER_PORT 8
12
+
13
+
/*
14
+
* Create the pin index from its bank and position numbers and store in
15
+
* the upper 16 bits the alternate function identifier
16
+
*/
17
+
#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
18
+
19
+
/* Convert a port and pin label to its global pin index */
20
+
#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin))
21
+
22
+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */