tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"Nothing earth-shattering, really - some CPU errata workarounds (one
day they'll get it right, ha!) and a fix for a boot failure with very
large kernel images where the alternative patching gets confused when
patching relative branches using veneers.

- Fix alternative patching for very large kernel images and modules

- Hook up existing CPU errata workarounds for Qualcomm Kryo CPUs"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
arm64: Add MIDR value for KRYO4XX gold CPU cores
arm64/alternatives: use subsections for replacement sequences

Linus Torvalds ec84c3f6 35e884f8

+35 -17
+8
Documentation/arm64/silicon-errata.rst
··· 147 147 +----------------+-----------------+-----------------+-----------------------------+ 148 148 | Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 | 149 149 +----------------+-----------------+-----------------+-----------------------------+ 150 + | Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1463225 | 151 + +----------------+-----------------+-----------------+-----------------------------+ 152 + | Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1418040 | 153 + +----------------+-----------------+-----------------+-----------------------------+ 154 + | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1530923 | 155 + +----------------+-----------------+-----------------+-----------------------------+ 156 + | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 | 157 + +----------------+-----------------+-----------------+-----------------------------+ 150 158 +----------------+-----------------+-----------------+-----------------------------+ 151 159 | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | 152 160 +----------------+-----------------+-----------------+-----------------------------+
+8 -8
arch/arm64/include/asm/alternative.h
··· 73 73 ".pushsection .altinstructions,\"a\"\n" \ 74 74 ALTINSTR_ENTRY(feature) \ 75 75 ".popsection\n" \ 76 - ".pushsection .altinstr_replacement, \"a\"\n" \ 76 + ".subsection 1\n" \ 77 77 "663:\n\t" \ 78 78 newinstr "\n" \ 79 79 "664:\n\t" \ 80 - ".popsection\n\t" \ 80 + ".previous\n\t" \ 81 81 ".org . - (664b-663b) + (662b-661b)\n\t" \ 82 82 ".org . - (662b-661b) + (664b-663b)\n" \ 83 83 ".endif\n" ··· 117 117 662: .pushsection .altinstructions, "a" 118 118 altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f 119 119 .popsection 120 - .pushsection .altinstr_replacement, "ax" 120 + .subsection 1 121 121 663: \insn2 122 - 664: .popsection 122 + 664: .previous 123 123 .org . - (664b-663b) + (662b-661b) 124 124 .org . - (662b-661b) + (664b-663b) 125 125 .endif ··· 160 160 .pushsection .altinstructions, "a" 161 161 altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f 162 162 .popsection 163 - .pushsection .altinstr_replacement, "ax" 163 + .subsection 1 164 164 .align 2 /* So GAS knows label 661 is suitably aligned */ 165 165 661: 166 166 .endm ··· 179 179 .macro alternative_else 180 180 662: 181 181 .if .Lasm_alt_mode==0 182 - .pushsection .altinstr_replacement, "ax" 182 + .subsection 1 183 183 .else 184 - .popsection 184 + .previous 185 185 .endif 186 186 663: 187 187 .endm ··· 192 192 .macro alternative_endif 193 193 664: 194 194 .if .Lasm_alt_mode==0 195 - .popsection 195 + .previous 196 196 .endif 197 197 .org . - (664b-663b) + (662b-661b) 198 198 .org . - (662b-661b) + (664b-663b)
+2
arch/arm64/include/asm/cputype.h
··· 86 86 #define QCOM_CPU_PART_FALKOR 0xC00 87 87 #define QCOM_CPU_PART_KRYO 0x200 88 88 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 89 + #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 89 90 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 90 91 91 92 #define NVIDIA_CPU_PART_DENVER 0x003 ··· 115 114 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) 116 115 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) 117 116 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) 117 + #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) 118 118 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) 119 119 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) 120 120 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
+15 -6
arch/arm64/kernel/cpu_errata.c
··· 472 472 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 473 473 int scope) 474 474 { 475 - u32 midr = read_cpuid_id(); 476 - /* Cortex-A76 r0p0 - r3p1 */ 477 - struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1); 478 - 479 - WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 480 - return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode(); 475 + return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 481 476 } 482 477 #endif 483 478 ··· 723 728 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 724 729 /* Neoverse-N1 r0p0 to r3p1 */ 725 730 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 731 + /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 732 + MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 726 733 {}, 727 734 }; 728 735 #endif ··· 769 772 #ifdef CONFIG_ARM64_ERRATUM_1530923 770 773 /* Cortex A55 r0p0 to r2p0 */ 771 774 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 775 + /* Kryo4xx Silver (rdpe => r1p0) */ 776 + MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 772 777 #endif 773 778 {}, 779 + }; 780 + #endif 781 + 782 + #ifdef CONFIG_ARM64_ERRATUM_1463225 783 + static const struct midr_range erratum_1463225[] = { 784 + /* Cortex-A76 r0p0 - r3p1 */ 785 + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 786 + /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 787 + MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 774 788 }; 775 789 #endif 776 790 ··· 924 916 .capability = ARM64_WORKAROUND_1463225, 925 917 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 926 918 .matches = has_cortex_a76_erratum_1463225, 919 + .midr_range_list = erratum_1463225, 927 920 }, 928 921 #endif 929 922 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
+2
arch/arm64/kernel/cpufeature.c
··· 1408 1408 static const struct midr_range cpus[] = { 1409 1409 #ifdef CONFIG_ARM64_ERRATUM_1024718 1410 1410 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1411 + /* Kryo4xx Silver (rdpe => r1p0) */ 1412 + MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1411 1413 #endif 1412 1414 {}, 1413 1415 };
-3
arch/arm64/kernel/vmlinux.lds.S
··· 165 165 *(.altinstructions) 166 166 __alt_instructions_end = .; 167 167 } 168 - .altinstr_replacement : { 169 - *(.altinstr_replacement) 170 - } 171 168 172 169 . = ALIGN(SEGMENT_ALIGN); 173 170 __inittext_end = .;