Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'ib-mfd-dt-soc-6.11' into ibs-for-mfd-merged
+203
-8
-8
Documentation/devicetree/bindings/mfd/syscon.yaml
-8
Documentation/devicetree/bindings/mfd/syscon.yaml
···
57
57
- hisilicon,pcie-sas-subctrl
58
58
- hisilicon,peri-subctrl
59
59
- hpe,gxp-sysreg
60
-
- intel,lgm-syscon
61
60
- loongson,ls1b-syscon
62
61
- loongson,ls1c-syscon
63
62
- marvell,armada-3700-cpu-misc
···
70
71
- mediatek,mt8173-pctl-a-syscfg
71
72
- mediatek,mt8365-syscfg
72
73
- microchip,lan966x-cpu-syscon
73
-
- microchip,sparx5-cpu-syscon
74
74
- mstar,msc313-pmsleep
75
75
- nuvoton,ma35d1-sys
76
76
- nuvoton,wpcm450-shm
···
88
90
- ti,am62-usb-phy-ctrl
89
91
- ti,am62p-cpsw-mac-efuse
90
92
- ti,am654-dss-oldi-io-ctrl
91
-
- ti,am654-serdes-ctrl
92
93
- ti,j784s4-pcie-ctrl
93
94
94
95
- const: syscon
···
108
111
109
112
resets:
110
113
maxItems: 1
111
-
112
-
hwlocks:
113
-
maxItems: 1
114
-
description:
115
-
Reference to a phandle of a hardware spinlock provider node.
116
114
117
115
required:
118
116
- compatible
+57
Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml
+57
Documentation/devicetree/bindings/soc/intel/intel,lgm-syscon.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Intel Lightning Mountain(LGM) Syscon
8
+
9
+
maintainers:
10
+
- Chuanhua Lei <lchuanhua@maxlinear.com>
11
+
- Rahul Tanwar <rtanwar@maxlinear.com>
12
+
13
+
properties:
14
+
compatible:
15
+
items:
16
+
- const: intel,lgm-syscon
17
+
- const: syscon
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
ranges: true
23
+
24
+
"#address-cells":
25
+
const: 1
26
+
27
+
"#size-cells":
28
+
const: 1
29
+
30
+
patternProperties:
31
+
"^emmc-phy@[0-9a-f]+$":
32
+
$ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- "#address-cells"
38
+
- "#size-cells"
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
chiptop@e0200000 {
45
+
compatible = "intel,lgm-syscon", "syscon";
46
+
reg = <0xe0200000 0x100>;
47
+
ranges = <0x0 0xe0200000 0x100>;
48
+
#address-cells = <1>;
49
+
#size-cells = <1>;
50
+
51
+
emmc-phy@a8 {
52
+
compatible = "intel,lgm-emmc-phy";
53
+
reg = <0x00a8 0x10>;
54
+
clocks = <&emmc>;
55
+
#phy-cells = <0>;
56
+
};
57
+
};
+49
Documentation/devicetree/bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml
+49
Documentation/devicetree/bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Microchip Sparx5 CPU Syscon
8
+
9
+
maintainers:
10
+
- Lars Povlsen <lars.povlsen@microchip.com>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- const: microchip,sparx5-cpu-syscon
16
+
- const: syscon
17
+
- const: simple-mfd
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
mux-controller:
23
+
$ref: /schemas/mux/reg-mux.yaml#
24
+
25
+
required:
26
+
- compatible
27
+
- reg
28
+
- mux-controller
29
+
30
+
additionalProperties: false
31
+
32
+
examples:
33
+
- |
34
+
soc {
35
+
#address-cells = <2>;
36
+
#size-cells = <1>;
37
+
38
+
syscon@600000000 {
39
+
compatible = "microchip,sparx5-cpu-syscon", "syscon",
40
+
"simple-mfd";
41
+
reg = <0x6 0x00000000 0xd0>;
42
+
43
+
mux: mux-controller {
44
+
compatible = "mmio-mux";
45
+
#mux-control-cells = <1>;
46
+
mux-reg-masks = <0x88 0xf0>;
47
+
};
48
+
};
49
+
};
+55
Documentation/devicetree/bindings/soc/sprd/sprd,sc9863a-glbregs.yaml
+55
Documentation/devicetree/bindings/soc/sprd/sprd,sc9863a-glbregs.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/sprd/sprd,sc9863a-glbregs.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SC9863A Syscon
8
+
9
+
maintainers:
10
+
- Orson Zhai <orsonzhai@gmail.com>
11
+
- Baolin Wang <baolin.wang7@gmail.com>
12
+
- Chunyan Zhang <zhang.lyra@gmail.com>
13
+
14
+
properties:
15
+
compatible:
16
+
items:
17
+
- const: sprd,sc9863a-glbregs
18
+
- const: syscon
19
+
- const: simple-mfd
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
ranges: true
25
+
26
+
"#address-cells":
27
+
const: 1
28
+
29
+
"#size-cells":
30
+
const: 1
31
+
32
+
patternProperties:
33
+
"@[0-9a-f]+$":
34
+
$ref: /schemas/clock/sprd,sc9863a-clk.yaml
35
+
description: Clock controllers
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
syscon@20e00000 {
42
+
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
43
+
reg = <0x20e00000 0x4000>;
44
+
ranges = <0 0x20e00000 0x4000>;
45
+
#address-cells = <1>;
46
+
#size-cells = <1>;
47
+
48
+
apahb_gate: apahb-gate@0 {
49
+
compatible = "sprd,sc9863a-apahb-gate";
50
+
reg = <0x0 0x1020>;
51
+
#clock-cells = <1>;
52
+
};
53
+
};
54
+
55
+
...
+42
Documentation/devicetree/bindings/soc/ti/ti,am654-serdes-ctrl.yaml
+42
Documentation/devicetree/bindings/soc/ti/ti,am654-serdes-ctrl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments AM654 Serdes Control Syscon
8
+
9
+
maintainers:
10
+
- Nishanth Menon <nm@ti.com>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- const: ti,am654-serdes-ctrl
16
+
- const: syscon
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
mux-controller:
22
+
$ref: /schemas/mux/reg-mux.yaml#
23
+
24
+
required:
25
+
- compatible
26
+
- reg
27
+
- mux-controller
28
+
29
+
additionalProperties: false
30
+
31
+
examples:
32
+
- |
33
+
clock@4080 {
34
+
compatible = "ti,am654-serdes-ctrl", "syscon";
35
+
reg = <0x4080 0x4>;
36
+
37
+
mux-controller {
38
+
compatible = "mmio-mux";
39
+
#mux-control-cells = <1>;
40
+
mux-reg-masks = <0x0 0x3>; /* lane select */
41
+
};
42
+
};