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dt-bindings: soc: fsl: cpm_qe: convert to yaml format

Convert binding doc qe.txt to yaml format. Split it to
fsl,qe-firmware.yaml, fsl,qe-ic.yaml, fsl,qe-muram.yaml, fsl,qe-si.yaml
fsl,qe-siram.yaml, fsl,qe.yaml.

Additional Changes:
- Fix error in example.
- Change to low case for hex value.
- Remove fsl,qe-num-riscs and fsl,qe-snums from required list.
- Add #address-cell and #size-cell.
- Add interrupts description for qe-ic.
- Add compatible string fsl,ls1043-qe-si for fsl,qe-si.yaml
- Add compatible string fsl,ls1043-qe-siram for fsl,qe-siram.yaml
- Add child node for fsl,qe.yaml

Fix below warning:
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: /soc/uqe@2400000/muram@10000: failed to match any schema with compatible: ['fsl,qe-muram', 'fsl,cpm-muram']
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: /soc/uqe@2400000/muram@10000: failed to match any schema with compatible: ['fsl,qe-muram', 'fsl,cpm-muram']
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: /soc/uqe@2400000/muram@10000/data-only@0: failed to match any schema with compatible: ['fsl,qe-muram-data', 'fsl,cpm-muram-data']
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: /soc/uqe@2400000: failed to match any schema with compatible: ['fsl,qe', 'simple-bus']
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: /soc/uqe@2400000/muram@10000/data-only@0: failed to match any schema with compatible: ['fsl,qe-muram-data', 'fsl,cpm-muram-data']
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: /soc/uqe@2400000/qeic@80: failed to match any schema with compatible: ['fsl,qe-ic']

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240703-ls_qe_warning-v1-1-7fe4af5b0bb0@nxp.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

authored by

Frank Li and committed by
Rob Herring (Arm)
ecbfc6ff 1a73912f

+393 -178
+48
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine module Firmware Node 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: | 13 + This node defines a firmware binary that is embedded in the device tree, for 14 + the purpose of passing the firmware from bootloader to the kernel, or from 15 + the hypervisor to the guest. 16 + 17 + The firmware node itself contains the firmware binary contents, a compatible 18 + property, and any firmware-specific properties. The node should be placed 19 + inside a QE node that needs it. Doing so eliminates the need for a 20 + fsl,firmware-phandle property. Other QE nodes that need the same firmware 21 + should define an fsl,firmware-phandle property that points to the firmware node 22 + in the first QE node. 23 + 24 + The fsl,firmware property can be specified in the DTS (possibly using incbin) 25 + or can be inserted by the boot loader at boot time. 26 + 27 + properties: 28 + compatible: 29 + enum: 30 + - fsl,qe-firmware 31 + 32 + fsl,firmware: 33 + $ref: /schemas/types.yaml#/definitions/uint8-array 34 + description: 35 + A standard property. This property contains the firmware binary "blob". 36 + 37 + required: 38 + - compatible 39 + - fsl,firmware 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + qe-firmware { 46 + compatible = "fsl,qe-firmware"; 47 + fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>; 48 + };
+47
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine module Interrupt Controller (IC) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + const: fsl,qe-ic 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + interrupts: 20 + items: 21 + - description: QE interrupt 22 + - description: QE critical 23 + - description: QE error 24 + minItems: 1 25 + 26 + interrupt-controller: true 27 + 28 + "#interrupt-cells": 29 + const: 1 30 + 31 + required: 32 + - compatible 33 + - reg 34 + - interrupt-controller 35 + - "#interrupt-cells" 36 + 37 + additionalProperties: false 38 + 39 + examples: 40 + - | 41 + interrupt-controller@80 { 42 + compatible = "fsl,qe-ic"; 43 + reg = <0x80 0x80>; 44 + #interrupt-cells = <1>; 45 + interrupt-controller; 46 + interrupts = <95 2 0 0 94 2 0 0>; 47 + };
+71
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine Multi-User RAM (MURAM) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: Multi-User RAM (MURAM) 13 + 14 + properties: 15 + compatible: 16 + items: 17 + - const: fsl,qe-muram 18 + - const: fsl,cpm-muram 19 + 20 + ranges: 21 + maxItems: 1 22 + 23 + "#address-cells": 24 + const: 1 25 + 26 + "#size-cells": 27 + const: 1 28 + 29 + mode: 30 + $ref: /schemas/types.yaml#/definitions/string 31 + enum: [host, slave] 32 + 33 + 34 + patternProperties: 35 + '^data\-only@[a-f0-9]+$': 36 + type: object 37 + properties: 38 + compatible: 39 + items: 40 + - const: fsl,qe-muram-data 41 + - const: fsl,cpm-muram-data 42 + 43 + reg: 44 + maxItems: 1 45 + 46 + required: 47 + - compatible 48 + - reg 49 + 50 + additionalProperties: false 51 + 52 + required: 53 + - compatible 54 + - ranges 55 + 56 + additionalProperties: false 57 + 58 + examples: 59 + - | 60 + muram@10000 { 61 + compatible = "fsl,qe-muram", "fsl,cpm-muram"; 62 + ranges = <0 0x00010000 0x0000c000>; 63 + #address-cells = <1>; 64 + #size-cells = <1>; 65 + 66 + data-only@0{ 67 + compatible = "fsl,qe-muram-data", 68 + "fsl,cpm-muram-data"; 69 + reg = <0 0xc000>; 70 + }; 71 + };
+40
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine module Serial Interface Block (SI) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: 13 + The SI manages the routing of eight TDM lines to the QE block serial drivers, 14 + the MCC and the UCCs, for receive and transmit. 15 + 16 + properties: 17 + compatible: 18 + oneOf: 19 + - items: 20 + - enum: 21 + - fsl,ls1043-qe-si 22 + - const: fsl,t1040-qe-si 23 + - enum: 24 + - fsl,t1040-qe-si 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + required: 30 + - compatible 31 + - reg 32 + 33 + additionalProperties: false 34 + 35 + examples: 36 + - | 37 + si@700 { 38 + compatible = "fsl,t1040-qe-si"; 39 + reg = <0x700 0x80>; 40 + };
+39
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: 13 + store the routing entries of SI 14 + 15 + properties: 16 + compatible: 17 + oneOf: 18 + - items: 19 + - enum: 20 + - fsl,ls1043-qe-siram 21 + - const: fsl,t1040-qe-siram 22 + - const: fsl,t1040-qe-siram 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + required: 28 + - compatible 29 + - reg 30 + 31 + additionalProperties: false 32 + 33 + examples: 34 + - | 35 + siram@1000 { 36 + compatible = "fsl,t1040-qe-siram"; 37 + reg = <0x1000 0x800>; 38 + }; 39 +
+148
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale QUICC Engine module (QE) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: | 13 + This represents qe module that is installed on PowerQUICC II Pro. 14 + 15 + NOTE: This is an interim binding; it should be updated to fit 16 + in with the CPM binding later in this document. 17 + 18 + Basically, it is a bus of devices, that could act more or less 19 + as a complete entity (UCC, USB etc ). All of them should be siblings on 20 + the "root" qe node, using the common properties from there. 21 + The description below applies to the qe of MPC8360 and 22 + more nodes and properties would be extended in the future. 23 + 24 + properties: 25 + compatible: 26 + items: 27 + - const: fsl,qe 28 + - const: simple-bus 29 + 30 + reg: 31 + maxItems: 1 32 + 33 + ranges: 34 + maxItems: 1 35 + 36 + model: 37 + $ref: /schemas/types.yaml#/definitions/string 38 + enum: [QE, CPM, CPM2] 39 + 40 + bus-frequency: 41 + $ref: /schemas/types.yaml#/definitions/uint32 42 + description: the clock frequency for QUICC Engine. 43 + 44 + fsl,qe-num-riscs: 45 + $ref: /schemas/types.yaml#/definitions/uint32 46 + description: define how many RISC engines the QE has. 47 + 48 + fsl,qe-snums: 49 + $ref: /schemas/types.yaml#/definitions/uint8-array 50 + maxItems: 28 51 + description: 52 + defining the array of serial number (SNUM) values for the virtual 53 + threads. 54 + 55 + fsl,firmware-phandle: 56 + $ref: /schemas/types.yaml#/definitions/phandle 57 + description: | 58 + required only if there is no fsl,qe-firmware child node 59 + 60 + Points to a firmware node (see "QE Firmware Node" below) 61 + that contains the firmware that should be uploaded for this QE. 62 + The compatible property for the firmware node should say, 63 + "fsl,qe-firmware". 64 + 65 + brg-frequency: 66 + $ref: /schemas/types.yaml#/definitions/uint32 67 + description: 68 + the internal clock source frequency for baud-rate 69 + generators in Hz. 70 + 71 + fsl,qe-num-snums: 72 + $ref: /schemas/types.yaml#/definitions/uint32 73 + deprecated: true 74 + description: | 75 + define how many serial number(SNUM) the QE can use 76 + for the threads. Use fsl,qe-snums instead to not only specify the 77 + number of snums, but also their values. 78 + 79 + patternProperties: 80 + '^muram@[a-f0-9]+$': 81 + $ref: fsl,qe-muram.yaml 82 + 83 + '^interrupt-controller@[a-f0-9]+$': 84 + $ref: fsl,qe-ic.yaml 85 + 86 + '^si@[a-f0-9]+$': 87 + $ref: fsl,qe-si.yaml 88 + 89 + '^siram@[a-f0-9]+$': 90 + $ref: fsl,qe-siram.yaml 91 + 92 + required: 93 + - compatible 94 + - reg 95 + - bus-frequency 96 + 97 + allOf: 98 + - $ref: /schemas/simple-bus.yaml# 99 + 100 + unevaluatedProperties: false 101 + 102 + examples: 103 + - | 104 + qe-bus@e0100000 { 105 + compatible = "fsl,qe", "simple-bus"; 106 + reg = <0xe0100000 0x480>; 107 + ranges = <0 0xe0100000 0x00100000>; 108 + #address-cells = <1>; 109 + #size-cells = <1>; 110 + brg-frequency = <0>; 111 + bus-frequency = <0x179a7b00>; 112 + fsl,qe-snums = /bits/ 8 < 113 + 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d 114 + 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 115 + 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 116 + 0xd8 0xd9 0xe8 0xe9>; 117 + 118 + interrupt-controller@80 { 119 + compatible = "fsl,qe-ic"; 120 + reg = <0x80 0x80>; 121 + #interrupt-cells = <1>; 122 + interrupt-controller; 123 + interrupts = <95 2 0 0 94 2 0 0>; 124 + }; 125 + 126 + si@700 { 127 + compatible = "fsl,t1040-qe-si"; 128 + reg = <0x700 0x80>; 129 + }; 130 + 131 + siram@1000 { 132 + compatible = "fsl,t1040-qe-siram"; 133 + reg = <0x1000 0x800>; 134 + }; 135 + 136 + muram@10000 { 137 + compatible = "fsl,qe-muram", "fsl,cpm-muram"; 138 + ranges = <0 0x00010000 0x0000c000>; 139 + #address-cells = <1>; 140 + #size-cells = <1>; 141 + 142 + data-only@0{ 143 + compatible = "fsl,qe-muram-data", 144 + "fsl,cpm-muram-data"; 145 + reg = <0 0xc000>; 146 + }; 147 + }; 148 + };
-178
Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
··· 1 - * Freescale QUICC Engine module (QE) 2 - This represents qe module that is installed on PowerQUICC II Pro. 3 - 4 - NOTE: This is an interim binding; it should be updated to fit 5 - in with the CPM binding later in this document. 6 - 7 - Basically, it is a bus of devices, that could act more or less 8 - as a complete entity (UCC, USB etc ). All of them should be siblings on 9 - the "root" qe node, using the common properties from there. 10 - The description below applies to the qe of MPC8360 and 11 - more nodes and properties would be extended in the future. 12 - 13 - i) Root QE device 14 - 15 - Required properties: 16 - - compatible : should be "fsl,qe"; 17 - - model : precise model of the QE, Can be "QE", "CPM", or "CPM2" 18 - - reg : offset and length of the device registers. 19 - - bus-frequency : the clock frequency for QUICC Engine. 20 - - fsl,qe-num-riscs: define how many RISC engines the QE has. 21 - - fsl,qe-snums: This property has to be specified as '/bits/ 8' value, 22 - defining the array of serial number (SNUM) values for the virtual 23 - threads. 24 - 25 - Optional properties: 26 - - fsl,firmware-phandle: 27 - Usage: required only if there is no fsl,qe-firmware child node 28 - Value type: <phandle> 29 - Definition: Points to a firmware node (see "QE Firmware Node" below) 30 - that contains the firmware that should be uploaded for this QE. 31 - The compatible property for the firmware node should say, 32 - "fsl,qe-firmware". 33 - 34 - Recommended properties 35 - - brg-frequency : the internal clock source frequency for baud-rate 36 - generators in Hz. 37 - 38 - Deprecated properties 39 - - fsl,qe-num-snums: define how many serial number(SNUM) the QE can use 40 - for the threads. Use fsl,qe-snums instead to not only specify the 41 - number of snums, but also their values. 42 - 43 - Example: 44 - qe@e0100000 { 45 - #address-cells = <1>; 46 - #size-cells = <1>; 47 - #interrupt-cells = <2>; 48 - compatible = "fsl,qe"; 49 - ranges = <0 e0100000 00100000>; 50 - reg = <e0100000 480>; 51 - brg-frequency = <0>; 52 - bus-frequency = <179A7B00>; 53 - fsl,qe-snums = /bits/ 8 < 54 - 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D 55 - 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89 56 - 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9 57 - 0xD8 0xD9 0xE8 0xE9>; 58 - } 59 - 60 - * Multi-User RAM (MURAM) 61 - 62 - Required properties: 63 - - compatible : should be "fsl,qe-muram", "fsl,cpm-muram". 64 - - mode : the could be "host" or "slave". 65 - - ranges : Should be defined as specified in 1) to describe the 66 - translation of MURAM addresses. 67 - - data-only : sub-node which defines the address area under MURAM 68 - bus that can be allocated as data/parameter 69 - 70 - Example: 71 - 72 - muram@10000 { 73 - compatible = "fsl,qe-muram", "fsl,cpm-muram"; 74 - ranges = <0 00010000 0000c000>; 75 - 76 - data-only@0{ 77 - compatible = "fsl,qe-muram-data", 78 - "fsl,cpm-muram-data"; 79 - reg = <0 c000>; 80 - }; 81 - }; 82 - 83 - * Interrupt Controller (IC) 84 - 85 - Required properties: 86 - - compatible : should be "fsl,qe-ic". 87 - - reg : Address range of IC register set. 88 - - interrupts : interrupts generated by the device. 89 - - interrupt-controller : this device is a interrupt controller. 90 - 91 - Example: 92 - 93 - qeic: interrupt-controller@80 { 94 - interrupt-controller; 95 - compatible = "fsl,qe-ic"; 96 - #address-cells = <0>; 97 - #interrupt-cells = <1>; 98 - reg = <0x80 0x80>; 99 - interrupts = <95 2 0 0 94 2 0 0>; 100 - }; 101 - 102 - * Serial Interface Block (SI) 103 - 104 - The SI manages the routing of eight TDM lines to the QE block serial drivers 105 - , the MCC and the UCCs, for receive and transmit. 106 - 107 - Required properties: 108 - - compatible : must be "fsl,<chip>-qe-si". For t1040, must contain 109 - "fsl,t1040-qe-si". 110 - - reg : Address range of SI register set. 111 - 112 - Example: 113 - 114 - si1: si@700 { 115 - compatible = "fsl,t1040-qe-si"; 116 - reg = <0x700 0x80>; 117 - }; 118 - 119 - * Serial Interface Block RAM(SIRAM) 120 - 121 - store the routing entries of SI 122 - 123 - Required properties: 124 - - compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain 125 - "fsl,t1040-qe-siram". 126 - - reg : Address range of SI RAM. 127 - 128 - Example: 129 - 130 - siram1: siram@1000 { 131 - compatible = "fsl,t1040-qe-siram"; 132 - reg = <0x1000 0x800>; 133 - }; 134 - 135 - * QE Firmware Node 136 - 137 - This node defines a firmware binary that is embedded in the device tree, for 138 - the purpose of passing the firmware from bootloader to the kernel, or from 139 - the hypervisor to the guest. 140 - 141 - The firmware node itself contains the firmware binary contents, a compatible 142 - property, and any firmware-specific properties. The node should be placed 143 - inside a QE node that needs it. Doing so eliminates the need for a 144 - fsl,firmware-phandle property. Other QE nodes that need the same firmware 145 - should define an fsl,firmware-phandle property that points to the firmware node 146 - in the first QE node. 147 - 148 - The fsl,firmware property can be specified in the DTS (possibly using incbin) 149 - or can be inserted by the boot loader at boot time. 150 - 151 - Required properties: 152 - - compatible 153 - Usage: required 154 - Value type: <string> 155 - Definition: A standard property. Specify a string that indicates what 156 - kind of firmware it is. For QE, this should be "fsl,qe-firmware". 157 - 158 - - fsl,firmware 159 - Usage: required 160 - Value type: <prop-encoded-array>, encoded as an array of bytes 161 - Definition: A standard property. This property contains the firmware 162 - binary "blob". 163 - 164 - Example: 165 - qe1@e0080000 { 166 - compatible = "fsl,qe"; 167 - qe_firmware:qe-firmware { 168 - compatible = "fsl,qe-firmware"; 169 - fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; 170 - }; 171 - ... 172 - }; 173 - 174 - qe2@e0090000 { 175 - compatible = "fsl,qe"; 176 - fsl,firmware-phandle = <&qe_firmware>; 177 - ... 178 - };