tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qcom-qmp: pcs-pcie: Add v8 register offsets

Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new
PCS PCIE specific offsets in a dedicated header file.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-3-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Qiang Yu and committed by
Vinod Koul ecc12453 5359da47

+34
+34
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_PCIE_V8_H_ 7 + #define QCOM_PHY_QMP_PCS_PCIE_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - PCIE PCS registers */ 10 + 11 + #define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2 0x00c 12 + #define QPHY_PCIE_V8_PCS_TX_RX_CONFIG 0x018 13 + #define QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE 0x01c 14 + #define QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS 0x090 15 + #define QPHY_PCIE_V8_PCS_EQ_CONFIG1 0x0a0 16 + #define QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME 0x0f0 17 + #define QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME 0x0f4 18 + #define QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5 0x108 19 + #define QPHY_PCIE_V8_PCS_G4_PRE_GAIN 0x15c 20 + #define QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB 0x170 21 + #define QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN 0x178 22 + #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1 0x17c 23 + #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3 0x184 24 + #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5 0x18c 25 + #define QPHY_PCIE_V8_PCS_RX_SIGDET_LVL 0x190 26 + #define QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5 0x1ac 27 + #define QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL 0x1b8 28 + #define QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5 0x1c0 29 + #define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6 0x1d0 30 + #define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1 0x1dc 31 + #define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2 0x1e0 32 + #define QPHY_PCIE_V8_PCS_EQ_CONFIG4 0x1f8 33 + #define QPHY_PCIE_V8_PCS_EQ_CONFIG5 0x1fc 34 + #endif