Merge branch 'for-linus' of git://git.kernel.dk/linux-block

+4 -2

block/badblocks.c

··· 354 354 * current range. Earlier ranges could also overlap, 355 355 * but only this one can overlap the end of the range. 356 356 */ 357 - if (BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > target) { 357 + if ((BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > target) && 358 + (BB_OFFSET(p[lo]) < target)) { 358 359 /* Partial overlap, leave the tail of this range */ 359 360 int ack = BB_ACK(p[lo]); 360 361 sector_t a = BB_OFFSET(p[lo]); ··· 378 377 lo--; 379 378 } 380 379 while (lo >= 0 && 381 - BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) { 380 + (BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) && 381 + (BB_OFFSET(p[lo]) < target)) { 382 382 /* This range does overlap */ 383 383 if (BB_OFFSET(p[lo]) < s) { 384 384 /* Keep the early parts of this range. */

+8 -6

drivers/nvme/host/core.c

··· 554 554 555 555 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 556 556 c.identify.opcode = nvme_admin_identify; 557 - c.identify.cns = cpu_to_le32(1); 557 + c.identify.cns = cpu_to_le32(NVME_ID_CNS_CTRL); 558 558 559 559 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); 560 560 if (!*id) ··· 572 572 struct nvme_command c = { }; 573 573 574 574 c.identify.opcode = nvme_admin_identify; 575 - c.identify.cns = cpu_to_le32(2); 575 + c.identify.cns = cpu_to_le32(NVME_ID_CNS_NS_ACTIVE_LIST); 576 576 c.identify.nsid = cpu_to_le32(nsid); 577 577 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000); 578 578 } ··· 900 900 return -ENODEV; 901 901 } 902 902 903 - if (ns->ctrl->vs >= NVME_VS(1, 1)) 903 + if (ns->ctrl->vs >= NVME_VS(1, 1, 0)) 904 904 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui)); 905 - if (ns->ctrl->vs >= NVME_VS(1, 2)) 905 + if (ns->ctrl->vs >= NVME_VS(1, 2, 0)) 906 906 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid)); 907 907 908 908 return 0; ··· 1086 1086 int ret; 1087 1087 1088 1088 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) { 1089 + if (csts == ~0) 1090 + return -ENODEV; 1089 1091 if ((csts & NVME_CSTS_RDY) == bit) 1090 1092 break; 1091 1093 ··· 1242 1240 } 1243 1241 page_shift = NVME_CAP_MPSMIN(cap) + 12; 1244 1242 1245 - if (ctrl->vs >= NVME_VS(1, 1)) 1243 + if (ctrl->vs >= NVME_VS(1, 1, 0)) 1246 1244 ctrl->subsystem = NVME_CAP_NSSRC(cap); 1247 1245 1248 1246 ret = nvme_identify_ctrl(ctrl, &id); ··· 1842 1840 return; 1843 1841 1844 1842 nn = le32_to_cpu(id->nn); 1845 - if (ctrl->vs >= NVME_VS(1, 1) && 1843 + if (ctrl->vs >= NVME_VS(1, 1, 0) && 1846 1844 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) { 1847 1845 if (!nvme_scan_ns_list(ctrl, nn)) 1848 1846 goto done;

+54 -23

drivers/nvme/host/pci.c

··· 99 99 dma_addr_t cmb_dma_addr; 100 100 u64 cmb_size; 101 101 u32 cmbsz; 102 + u32 cmbloc; 102 103 struct nvme_ctrl ctrl; 103 104 struct completion ioq_wait; 104 105 }; ··· 894 893 "I/O %d QID %d timeout, reset controller\n", 895 894 req->tag, nvmeq->qid); 896 895 nvme_dev_disable(dev, false); 897 - queue_work(nvme_workq, &dev->reset_work); 896 + nvme_reset(dev); 898 897 899 898 /* 900 899 * Mark the request as handled, since the inline shutdown ··· 1215 1214 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1216 1215 struct nvme_queue *nvmeq; 1217 1216 1218 - dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? 1217 + dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1219 1218 NVME_CAP_NSSRC(cap) : 0; 1220 1219 1221 1220 if (dev->subsystem && ··· 1292 1291 1293 1292 /* Skip controllers under certain specific conditions. */ 1294 1293 if (nvme_should_reset(dev, csts)) { 1295 - if (queue_work(nvme_workq, &dev->reset_work)) 1294 + if (!nvme_reset(dev)) 1296 1295 dev_warn(dev->dev, 1297 1296 "Failed status: 0x%x, reset controller.\n", 1298 1297 csts); ··· 1332 1331 return ret >= 0 ? 0 : ret; 1333 1332 } 1334 1333 1334 + static ssize_t nvme_cmb_show(struct device *dev, 1335 + struct device_attribute *attr, 1336 + char *buf) 1337 + { 1338 + struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1339 + 1340 + return snprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1341 + ndev->cmbloc, ndev->cmbsz); 1342 + } 1343 + static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1344 + 1335 1345 static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1336 1346 { 1337 1347 u64 szu, size, offset; 1338 - u32 cmbloc; 1339 1348 resource_size_t bar_size; 1340 1349 struct pci_dev *pdev = to_pci_dev(dev->dev); 1341 1350 void __iomem *cmb; 1342 1351 dma_addr_t dma_addr; 1343 1352 1344 - if (!use_cmb_sqes) 1345 - return NULL; 1346 - 1347 1353 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1348 1354 if (!(NVME_CMB_SZ(dev->cmbsz))) 1349 1355 return NULL; 1356 + dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1350 1357 1351 - cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1358 + if (!use_cmb_sqes) 1359 + return NULL; 1352 1360 1353 1361 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1354 1362 size = szu * NVME_CMB_SZ(dev->cmbsz); 1355 - offset = szu * NVME_CMB_OFST(cmbloc); 1356 - bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); 1363 + offset = szu * NVME_CMB_OFST(dev->cmbloc); 1364 + bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 1357 1365 1358 1366 if (offset > bar_size) 1359 1367 return NULL; ··· 1375 1365 if (size > bar_size - offset) 1376 1366 size = bar_size - offset; 1377 1367 1378 - dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; 1368 + dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 1379 1369 cmb = ioremap_wc(dma_addr, size); 1380 1370 if (!cmb) 1381 1371 return NULL; ··· 1521 1511 return 0; 1522 1512 } 1523 1513 1524 - static void nvme_disable_io_queues(struct nvme_dev *dev) 1514 + static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1525 1515 { 1526 - int pass, queues = dev->online_queues - 1; 1516 + int pass; 1527 1517 unsigned long timeout; 1528 1518 u8 opcode = nvme_admin_delete_sq; 1529 1519 ··· 1626 1616 dev->q_depth); 1627 1617 } 1628 1618 1629 - if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) 1619 + /* 1620 + * CMBs can currently only exist on >=1.2 PCIe devices. We only 1621 + * populate sysfs if a CMB is implemented. Note that we add the 1622 + * CMB attribute to the nvme_ctrl kobj which removes the need to remove 1623 + * it on exit. Since nvme_dev_attrs_group has no name we can pass 1624 + * NULL as final argument to sysfs_add_file_to_group. 1625 + */ 1626 + 1627 + if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 1630 1628 dev->cmb = nvme_map_cmb(dev); 1629 + 1630 + if (dev->cmbsz) { 1631 + if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1632 + &dev_attr_cmb.attr, NULL)) 1633 + dev_warn(dev->dev, 1634 + "failed to add sysfs attribute for CMB\n"); 1635 + } 1636 + } 1631 1637 1632 1638 pci_enable_pcie_error_reporting(pdev); 1633 1639 pci_save_state(pdev); ··· 1675 1649 1676 1650 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 1677 1651 { 1678 - int i; 1652 + int i, queues; 1679 1653 u32 csts = -1; 1680 1654 1681 1655 del_timer_sync(&dev->watchdog_timer); ··· 1686 1660 csts = readl(dev->bar + NVME_REG_CSTS); 1687 1661 } 1688 1662 1663 + queues = dev->online_queues - 1; 1689 1664 for (i = dev->queue_count - 1; i > 0; i--) 1690 1665 nvme_suspend_queue(dev->queues[i]); 1691 1666 ··· 1698 1671 if (dev->queue_count) 1699 1672 nvme_suspend_queue(dev->queues[0]); 1700 1673 } else { 1701 - nvme_disable_io_queues(dev); 1674 + nvme_disable_io_queues(dev, queues); 1702 1675 nvme_disable_admin_queue(dev, shutdown); 1703 1676 } 1704 1677 nvme_pci_disable(dev); ··· 1845 1818 { 1846 1819 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 1847 1820 return -ENODEV; 1848 - 1821 + if (work_busy(&dev->reset_work)) 1822 + return -ENODEV; 1849 1823 if (!queue_work(nvme_workq, &dev->reset_work)) 1850 1824 return -EBUSY; 1851 - 1852 - flush_work(&dev->reset_work); 1853 1825 return 0; 1854 1826 } 1855 1827 ··· 1872 1846 1873 1847 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 1874 1848 { 1875 - return nvme_reset(to_nvme_dev(ctrl)); 1849 + struct nvme_dev *dev = to_nvme_dev(ctrl); 1850 + int ret = nvme_reset(dev); 1851 + 1852 + if (!ret) 1853 + flush_work(&dev->reset_work); 1854 + return ret; 1876 1855 } 1877 1856 1878 1857 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { ··· 1971 1940 if (prepare) 1972 1941 nvme_dev_disable(dev, false); 1973 1942 else 1974 - queue_work(nvme_workq, &dev->reset_work); 1943 + nvme_reset(dev); 1975 1944 } 1976 1945 1977 1946 static void nvme_shutdown(struct pci_dev *pdev) ··· 2040 2009 struct pci_dev *pdev = to_pci_dev(dev); 2041 2010 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2042 2011 2043 - queue_work(nvme_workq, &ndev->reset_work); 2012 + nvme_reset(ndev); 2044 2013 return 0; 2045 2014 } 2046 2015 #endif ··· 2079 2048 2080 2049 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2081 2050 pci_restore_state(pdev); 2082 - queue_work(nvme_workq, &dev->reset_work); 2051 + nvme_reset(dev); 2083 2052 return PCI_ERS_RESULT_RECOVERED; 2084 2053 } 2085 2054

+2 -2

drivers/nvme/host/scsi.c

··· 606 606 eui = id_ns->eui64; 607 607 len = sizeof(id_ns->eui64); 608 608 609 - if (ns->ctrl->vs >= NVME_VS(1, 2)) { 609 + if (ns->ctrl->vs >= NVME_VS(1, 2, 0)) { 610 610 if (bitmap_empty(eui, len * 8)) { 611 611 eui = id_ns->nguid; 612 612 len = sizeof(id_ns->nguid); ··· 679 679 { 680 680 int res; 681 681 682 - if (ns->ctrl->vs >= NVME_VS(1, 1)) { 682 + if (ns->ctrl->vs >= NVME_VS(1, 1, 0)) { 683 683 res = nvme_fill_device_id_eui64(ns, hdr, resp, alloc_len); 684 684 if (res != -EOPNOTSUPP) 685 685 return res;

+4 -4

drivers/nvme/target/admin-cmd.c

··· 199 199 */ 200 200 201 201 /* we support multiple ports and multiples hosts: */ 202 - id->mic = (1 << 0) | (1 << 1); 202 + id->cmic = (1 << 0) | (1 << 1); 203 203 204 204 /* no limit on data transfer sizes for now */ 205 205 id->mdts = 0; ··· 511 511 case nvme_admin_identify: 512 512 req->data_len = 4096; 513 513 switch (le32_to_cpu(cmd->identify.cns)) { 514 - case 0x00: 514 + case NVME_ID_CNS_NS: 515 515 req->execute = nvmet_execute_identify_ns; 516 516 return 0; 517 - case 0x01: 517 + case NVME_ID_CNS_CTRL: 518 518 req->execute = nvmet_execute_identify_ctrl; 519 519 return 0; 520 - case 0x02: 520 + case NVME_ID_CNS_NS_ACTIVE_LIST: 521 521 req->execute = nvmet_execute_identify_nslist; 522 522 return 0; 523 523 }

+1 -1

drivers/nvme/target/core.c

··· 882 882 if (!subsys) 883 883 return NULL; 884 884 885 - subsys->ver = (1 << 16) | (2 << 8) | 1; /* NVMe 1.2.1 */ 885 + subsys->ver = NVME_VS(1, 2, 1); /* NVMe 1.2.1 */ 886 886 887 887 switch (type) { 888 888 case NVME_NQN_NVME:

+2 -2

drivers/nvme/target/discovery.c

··· 54 54 /* we support only dynamic controllers */ 55 55 e->cntlid = cpu_to_le16(NVME_CNTLID_DYNAMIC); 56 56 e->asqsz = cpu_to_le16(NVMF_AQ_DEPTH); 57 - e->nqntype = type; 57 + e->subtype = type; 58 58 memcpy(e->trsvcid, port->disc_addr.trsvcid, NVMF_TRSVCID_SIZE); 59 59 memcpy(e->traddr, port->disc_addr.traddr, NVMF_TRADDR_SIZE); 60 60 memcpy(e->tsas.common, port->disc_addr.tsas.common, NVMF_TSAS_SIZE); ··· 187 187 case nvme_admin_identify: 188 188 req->data_len = 4096; 189 189 switch (le32_to_cpu(cmd->identify.cns)) { 190 - case 0x01: 190 + case NVME_ID_CNS_CTRL: 191 191 req->execute = 192 192 nvmet_execute_identify_disc_ctrl; 193 193 return 0;

+40 -9

include/linux/nvme.h

··· 16 16 #define _LINUX_NVME_H 17 17 18 18 #include <linux/types.h> 19 - #include <linux/uuid.h> 20 19 21 20 /* NQN names in commands fields specified one size */ 22 21 #define NVMF_NQN_FIELD_LEN 256 ··· 181 182 char fr[8]; 182 183 __u8 rab; 183 184 __u8 ieee[3]; 184 - __u8 mic; 185 + __u8 cmic; 185 186 __u8 mdts; 186 187 __le16 cntlid; 187 188 __le32 ver; ··· 201 202 __u8 apsta; 202 203 __le16 wctemp; 203 204 __le16 cctemp; 204 - __u8 rsvd270[50]; 205 + __le16 mtfa; 206 + __le32 hmpre; 207 + __le32 hmmin; 208 + __u8 tnvmcap[16]; 209 + __u8 unvmcap[16]; 210 + __le32 rpmbs; 211 + __u8 rsvd316[4]; 205 212 __le16 kas; 206 213 __u8 rsvd322[190]; 207 214 __u8 sqes; ··· 272 267 __le16 nabo; 273 268 __le16 nabspf; 274 269 __u16 rsvd46; 275 - __le64 nvmcap[2]; 270 + __u8 nvmcap[16]; 276 271 __u8 rsvd64[40]; 277 272 __u8 nguid[16]; 278 273 __u8 eui64[8]; 279 274 struct nvme_lbaf lbaf[16]; 280 275 __u8 rsvd192[192]; 281 276 __u8 vs[3712]; 277 + }; 278 + 279 + enum { 280 + NVME_ID_CNS_NS = 0x00, 281 + NVME_ID_CNS_CTRL = 0x01, 282 + NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 283 + NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 284 + NVME_ID_CNS_NS_PRESENT = 0x11, 285 + NVME_ID_CNS_CTRL_NS_LIST = 0x12, 286 + NVME_ID_CNS_CTRL_LIST = 0x13, 282 287 }; 283 288 284 289 enum { ··· 571 556 nvme_admin_set_features = 0x09, 572 557 nvme_admin_get_features = 0x0a, 573 558 nvme_admin_async_event = 0x0c, 559 + nvme_admin_ns_mgmt = 0x0d, 574 560 nvme_admin_activate_fw = 0x10, 575 561 nvme_admin_download_fw = 0x11, 562 + nvme_admin_ns_attach = 0x15, 576 563 nvme_admin_keep_alive = 0x18, 577 564 nvme_admin_format_nvm = 0x80, 578 565 nvme_admin_security_send = 0x81, ··· 600 583 NVME_FEAT_WRITE_ATOMIC = 0x0a, 601 584 NVME_FEAT_ASYNC_EVENT = 0x0b, 602 585 NVME_FEAT_AUTO_PST = 0x0c, 586 + NVME_FEAT_HOST_MEM_BUF = 0x0d, 603 587 NVME_FEAT_KATO = 0x0f, 604 588 NVME_FEAT_SW_PROGRESS = 0x80, 605 589 NVME_FEAT_HOST_ID = 0x81, ··· 763 745 struct nvmf_disc_rsp_page_entry { 764 746 __u8 trtype; 765 747 __u8 adrfam; 766 - __u8 nqntype; 748 + __u8 subtype; 767 749 __u8 treq; 768 750 __le16 portid; 769 751 __le16 cntlid; ··· 812 794 }; 813 795 814 796 struct nvmf_connect_data { 815 - uuid_be hostid; 797 + __u8 hostid[16]; 816 798 __le16 cntlid; 817 799 char resv4[238]; 818 800 char subsysnqn[NVMF_NQN_FIELD_LEN]; ··· 923 905 NVME_SC_INVALID_VECTOR = 0x108, 924 906 NVME_SC_INVALID_LOG_PAGE = 0x109, 925 907 NVME_SC_INVALID_FORMAT = 0x10a, 926 - NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 908 + NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 927 909 NVME_SC_INVALID_QUEUE = 0x10c, 928 910 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 929 911 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 930 912 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 931 - NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 913 + NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 914 + NVME_SC_FW_NEEDS_RESET = 0x111, 915 + NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 916 + NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, 917 + NVME_SC_OVERLAPPING_RANGE = 0x114, 918 + NVME_SC_NS_INSUFFICENT_CAP = 0x115, 919 + NVME_SC_NS_ID_UNAVAILABLE = 0x116, 920 + NVME_SC_NS_ALREADY_ATTACHED = 0x118, 921 + NVME_SC_NS_IS_PRIVATE = 0x119, 922 + NVME_SC_NS_NOT_ATTACHED = 0x11a, 923 + NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 924 + NVME_SC_CTRL_LIST_INVALID = 0x11c, 932 925 933 926 /* 934 927 * I/O Command Set Specific - NVM commands: ··· 970 941 NVME_SC_REFTAG_CHECK = 0x284, 971 942 NVME_SC_COMPARE_FAILED = 0x285, 972 943 NVME_SC_ACCESS_DENIED = 0x286, 944 + NVME_SC_UNWRITTEN_BLOCK = 0x287, 973 945 974 946 NVME_SC_DNR = 0x4000, 975 947 }; ··· 990 960 __le16 status; /* did the command fail, and if so, why? */ 991 961 }; 992 962 993 - #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 963 + #define NVME_VS(major, minor, tertiary) \ 964 + (((major) << 16) | ((minor) << 8) | (tertiary)) 994 965 995 966 #endif /* _LINUX_NVME_H */

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