Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.18-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"Another batch of fixes for ARC, this time mainly DMA API rework
wreckage:
- Fix software managed DMA wreckage after rework in 4.17 [Euginey]
* missing cache flush
* SMP_CACHE_BYTES vs cache_line_size
- Fix allmodconfig build errors [Randy]
- Maintainer update for Mellanox (EZChip) NPS platform"
* tag 'arc-4.18-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
arc: fix type warnings in arc/mm/cache.c
arc: fix build errors in arc/include/asm/delay.h
arc: [plat-eznps] fix printk warning in arc/plat-eznps/mtm.c
arc: [plat-eznps] fix data type errors in platform headers
ARC: [plat-eznps] Add missing struct nps_host_reg_aux_dpc
ARC: add SMP_CACHE_BYTES value validate
ARC: dma [non-IOC] setup SMP_CACHE_BYTES and cache_line_size
ARC: dma [non IOC]: fix arc_dma_sync_single_for_(device|cpu)
ARC: Add Ofer Levi as plat-eznps maintainer
+85
-8
+1
MAINTAINERS
+1
MAINTAINERS
+3
arch/arc/Kconfig
+3
arch/arc/Kconfig
+3
-1
arch/arc/include/asm/cache.h
+3
-1
arch/arc/include/asm/cache.h
···
48
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})
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50
50
/* Largest line length for either L1 or L2 is 128 bytes */
51
-
#define ARCH_DMA_MINALIGN 128
51
+
#define SMP_CACHE_BYTES 128
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+
#define cache_line_size() SMP_CACHE_BYTES
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+
#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
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extern void arc_cache_init(void);
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extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
+3
arch/arc/include/asm/delay.h
+3
arch/arc/include/asm/delay.h
+14
-3
arch/arc/mm/cache.c
+14
-3
arch/arc/mm/cache.c
···
1038
1038
void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
1039
1039
unsigned long pfn)
1040
1040
{
1041
-
unsigned int paddr = pfn << PAGE_SHIFT;
1041
+
phys_addr_t paddr = pfn << PAGE_SHIFT;
1042
1042
1043
1043
u_vaddr &= PAGE_MASK;
1044
1044
···
1058
1058
unsigned long u_vaddr)
1059
1059
{
1060
1060
/* TBD: do we really need to clear the kernel mapping */
1061
-
__flush_dcache_page(page_address(page), u_vaddr);
1062
-
__flush_dcache_page(page_address(page), page_address(page));
1061
+
__flush_dcache_page((phys_addr_t)page_address(page), u_vaddr);
1062
+
__flush_dcache_page((phys_addr_t)page_address(page),
1063
+
(phys_addr_t)page_address(page));
1063
1064
1064
1065
}
1065
1066
···
1246
1245
}
1247
1246
}
1248
1247
}
1248
+
1249
+
/*
1250
+
* Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
1251
+
* or equal to any cache line length.
1252
+
*/
1253
+
BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,
1254
+
"SMP_CACHE_BYTES must be >= any cache line length");
1255
+
if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES))
1256
+
panic("L2 Cache line [%d] > kernel Config [%d]\n",
1257
+
l2_line_sz, SMP_CACHE_BYTES);
1249
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1259
/* Note that SLC disable not formally supported till HS 3.0 */
1251
1260
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
+47
-2
arch/arc/mm/dma.c
+47
-2
arch/arc/mm/dma.c
···
129
129
return ret;
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}
131
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+
/*
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+
* Cache operations depending on function and direction argument, inspired by
134
+
* https://lkml.org/lkml/2018/5/18/979
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+
* "dma_sync_*_for_cpu and direction=TO_DEVICE (was Re: [PATCH 02/20]
136
+
* dma-mapping: provide a generic dma-noncoherent implementation)"
137
+
*
138
+
* | map == for_device | unmap == for_cpu
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+
* |----------------------------------------------------------------
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+
* TO_DEV | writeback writeback | none none
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+
* FROM_DEV | invalidate invalidate | invalidate* invalidate*
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+
* BIDIR | writeback+inv writeback+inv | invalidate invalidate
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+
*
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+
* [*] needed for CPU speculative prefetches
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+
*
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+
* NOTE: we don't check the validity of direction argument as it is done in
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* upper layer functions (in include/linux/dma-mapping.h)
148
+
*/
149
+
132
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
133
151
size_t size, enum dma_data_direction dir)
134
152
{
135
-
dma_cache_wback(paddr, size);
153
+
switch (dir) {
154
+
case DMA_TO_DEVICE:
155
+
dma_cache_wback(paddr, size);
156
+
break;
157
+
158
+
case DMA_FROM_DEVICE:
159
+
dma_cache_inv(paddr, size);
160
+
break;
161
+
162
+
case DMA_BIDIRECTIONAL:
163
+
dma_cache_wback_inv(paddr, size);
164
+
break;
165
+
166
+
default:
167
+
break;
168
+
}
136
169
}
137
170
138
171
void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
139
172
size_t size, enum dma_data_direction dir)
140
173
{
141
-
dma_cache_inv(paddr, size);
174
+
switch (dir) {
175
+
case DMA_TO_DEVICE:
176
+
break;
177
+
178
+
/* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
179
+
case DMA_FROM_DEVICE:
180
+
case DMA_BIDIRECTIONAL:
181
+
dma_cache_inv(paddr, size);
182
+
break;
183
+
184
+
default:
185
+
break;
186
+
}
142
187
}
+10
arch/arc/plat-eznps/include/plat/ctop.h
+10
arch/arc/plat-eznps/include/plat/ctop.h
···
21
21
#error "Incorrect ctop.h include"
22
22
#endif
23
23
24
+
#include <linux/types.h>
24
25
#include <soc/nps/common.h>
25
26
26
27
/* core auxiliary registers */
···
144
143
};
145
144
146
145
/* AUX registers definition */
146
+
struct nps_host_reg_aux_dpc {
147
+
union {
148
+
struct {
149
+
u32 ien:1, men:1, hen:1, reserved:29;
150
+
};
151
+
u32 value;
152
+
};
153
+
};
154
+
147
155
struct nps_host_reg_aux_udmc {
148
156
union {
149
157
struct {
+4
-2
arch/arc/plat-eznps/mtm.c
+4
-2
arch/arc/plat-eznps/mtm.c
···
15
15
*/
16
16
17
17
#include <linux/smp.h>
18
+
#include <linux/init.h>
19
+
#include <linux/kernel.h>
18
20
#include <linux/io.h>
19
21
#include <linux/log2.h>
20
22
#include <asm/arcregs.h>
···
159
157
/* Verify and set the value of the mtm hs counter */
160
158
static int __init set_mtm_hs_ctr(char *ctr_str)
161
159
{
162
-
long hs_ctr;
160
+
int hs_ctr;
163
161
int ret;
164
162
165
-
ret = kstrtol(ctr_str, 0, &hs_ctr);
163
+
ret = kstrtoint(ctr_str, 0, &hs_ctr);
166
164
167
165
if (ret || hs_ctr > MT_HS_CNT_MAX || hs_ctr < MT_HS_CNT_MIN) {
168
166
pr_err("** Invalid @nps_mtm_hs_ctr [%d] needs to be [%d:%d] (incl)\n",