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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dp: Enable support for eDP v1.4+ link rates table
The MSM DRM driver currently does not support panels which report their
supported link rates via the SUPPORTED_LINK_RATES table.
For panels which do not offer the optional eDP v1.3 fallback via
MAX_LINK_RATE, this will cause a panel probe failure (e.g. Samsung
ATNA30DW01-1 as found in Microsoft Surface Pro 11).
Detect eDP v1.4 panels and parse the SUPPORTED_LINK_RATES table when
present.
Additionally, set the rate using LINK_RATE_SET instead of LINK_BW_SET,
but only if LINK_BW_SET hasn't already been written to.
Signed-off-by: Dale Whinham <daleyo@gmail.com>
Tested-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Tested-by: Steev Klimaszewski <threeway@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/695064/
Link: https://lore.kernel.org/r/20251218-drm-msm-edp14-v2-1-2e56c2338ab1@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Dale Whinham
and committed by
Dmitry Baryshkov
ed100aa2
794b0e68
+120
-32
+35
-21
drivers/gpu/drm/msm/dp/dp_ctrl.c
+35
-21
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
175
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static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
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struct msm_dp_link_info *link)
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{
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-
u8 values[2];
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+
u8 lane_count, bw_code;
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int err;
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-
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
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-
values[1] = link->num_lanes;
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+
lane_count = link->num_lanes;
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if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
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-
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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-
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
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+
err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count);
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if (err < 0)
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return err;
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-
return 0;
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+
if (link->use_rate_set) {
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DRM_DEBUG_DP("using LINK_RATE_SET: 0x%02x", link->rate_set);
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+
err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set);
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} else {
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bw_code = drm_dp_link_rate_to_bw_code(link->rate);
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DRM_DEBUG_DP("using LINK_BW_SET: 0x%02x", bw_code);
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err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code);
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}
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+
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return err;
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}
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/*
···
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static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl)
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{
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int ret = 0;
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+
struct msm_dp_link_info *link_params = &ctrl->link->link_params;
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-
switch (ctrl->link->link_params.rate) {
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-
case 810000:
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ctrl->link->link_params.rate = 540000;
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-
break;
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-
case 540000:
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-
ctrl->link->link_params.rate = 270000;
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-
break;
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-
case 270000:
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ctrl->link->link_params.rate = 162000;
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-
break;
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-
case 162000:
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-
default:
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-
ret = -EINVAL;
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-
break;
1479
+
if (link_params->rate_set) {
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+
--link_params->rate_set;
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link_params->rate = link_params->supported_rates[link_params->rate_set];
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+
} else {
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switch (link_params->rate) {
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case 810000:
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link_params->rate = 540000;
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+
break;
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+
case 540000:
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link_params->rate = 270000;
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break;
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+
case 270000:
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link_params->rate = 162000;
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+
break;
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+
case 162000:
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+
default:
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+
ret = -EINVAL;
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+
break;
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+
}
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}
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if (!ret) {
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drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
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-
ctrl->link->link_params.rate);
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+
link_params->rate);
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}
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1507
1505
return ret;
+3
drivers/gpu/drm/msm/dp/dp_link.h
+3
drivers/gpu/drm/msm/dp/dp_link.h
+82
-11
drivers/gpu/drm/msm/dp/dp_panel.c
+82
-11
drivers/gpu/drm/msm/dp/dp_panel.c
···
13
13
#include <drm/drm_print.h>
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#include <linux/io.h>
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+
#include <linux/types.h>
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#include <asm/byteorder.h>
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#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4)
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···
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drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
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link->max_dp_lanes, link->max_dp_link_rate);
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-
link_info->rate = drm_dp_max_link_rate(dpcd);
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+
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(link->lttpr_common_caps);
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+
max_lttpr_rate = drm_dp_lttpr_max_link_rate(link->lttpr_common_caps);
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+
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+
/* eDP sink */
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+
if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
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+
u8 edp_rev;
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+
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rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev);
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+
if (rc)
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return rc;
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+
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drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev);
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+
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/* For eDP v1.4+, parse the SUPPORTED_LINK_RATES table */
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+
if (edp_rev >= DP_EDP_14) {
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+
__le16 rates[DP_MAX_SUPPORTED_RATES];
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u8 bw_set;
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+
int i;
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+
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rc = drm_dp_dpcd_read_data(panel->aux, DP_SUPPORTED_LINK_RATES,
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rates, sizeof(rates));
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if (rc)
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return rc;
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+
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rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set);
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+
if (rc)
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+
return rc;
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+
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/* Find index of max supported link rate that does not exceed dtsi limits */
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for (i = 0; i < ARRAY_SIZE(rates); i++) {
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+
/*
141
+
* The value from the DPCD multiplied by 200 gives
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+
* the link rate in kHz. Divide by 10 to convert to
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+
* symbol rate, accounting for 8b/10b encoding.
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+
*/
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u32 rate = (le16_to_cpu(rates[i]) * 200) / 10;
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+
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+
if (!rate)
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+
break;
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+
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+
drm_dbg_dp(panel->drm_dev,
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"SUPPORTED_LINK_RATES[%d]: %d\n", i, rate);
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+
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+
/*
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* Limit link rate from link-frequencies of endpoint
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* property of dtsi
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+
*/
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if (rate > link->max_dp_link_rate)
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+
break;
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+
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+
/* Limit link rate from LTTPR capabilities, if any */
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+
if (max_lttpr_rate && rate > max_lttpr_rate)
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+
break;
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+
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+
link_info->rate = rate;
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+
link_info->supported_rates[i] = rate;
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+
link_info->rate_set = i;
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+
}
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+
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+
/* Only use LINK_RATE_SET if LINK_BW_SET hasn't already been written to */
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+
if (!bw_set && link_info->rate)
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+
link_info->use_rate_set = true;
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+
}
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+
}
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+
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+
/* Fall back on MAX_LINK_RATE/LINK_BW_SET (DP, eDP <= v1.3) */
176
+
if (!link_info->rate) {
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+
link_info->rate = drm_dp_max_link_rate(dpcd);
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+
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+
/* Limit link rate from link-frequencies of endpoint property of dtsi */
180
+
if (link_info->rate > link->max_dp_link_rate)
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+
link_info->rate = link->max_dp_link_rate;
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+
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+
/* Limit link rate from LTTPR capabilities, if any */
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+
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
185
+
link_info->rate = max_lttpr_rate;
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+
}
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+
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link_info->num_lanes = drm_dp_max_lane_count(dpcd);
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189
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/* Limit data lanes from data-lanes of endpoint property of dtsi */
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if (link_info->num_lanes > link->max_dp_lanes)
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link_info->num_lanes = link->max_dp_lanes;
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193
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-
/* Limit link rate from link-frequencies of endpoint property of dtsi */
120
-
if (link_info->rate > link->max_dp_link_rate)
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-
link_info->rate = link->max_dp_link_rate;
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-
123
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/* Limit data lanes from LTTPR capabilities, if any */
124
-
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
125
195
if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes)
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196
link_info->num_lanes = max_lttpr_lanes;
127
197
128
-
/* Limit link rate from LTTPR capabilities, if any */
129
-
max_lttpr_rate = drm_dp_lttpr_max_link_rate(panel->link->lttpr_common_caps);
130
-
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
131
-
link_info->rate = max_lttpr_rate;
132
-
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198
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
134
199
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
200
+
drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set);
201
+
drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set);
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202
drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);
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203
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if (drm_dp_enhanced_frame_cap(dpcd))