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drm/i915/display: Acomodate format check in intel_plane_can_async_flip()

The function intel_plane_can_async_flip() checks for async supported
modifier, add format support check also in the same function.

Note: on ADL the surface base addr is required to be 16k aligned and if
not might generate DMAR and GGTT faults leading to glitches. This patch
changes the 16k alignment to 4k for planar formats.

v11: Move filtering Indexed 8bit to a separate patch (Ville)
v12: correct the commit msg and remove unwanted debug print (Ville)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250407-asyn-v13-3-b93ef83076c5@intel.com

authored by

Arun R Murthy and committed by
Suraj Kandpal ed1d563c 0d6dcd74

+14 -15
+2 -2
drivers/gpu/drm/i915/display/i9xx_plane.c
··· 828 828 { 829 829 struct intel_display *display = to_intel_display(plane); 830 830 831 - if (intel_plane_can_async_flip(plane, fb->modifier)) 831 + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 832 832 return 256 * 1024; 833 833 834 834 /* FIXME undocumented so not sure what's actually needed */ ··· 852 852 { 853 853 struct intel_display *display = to_intel_display(plane); 854 854 855 - if (intel_plane_can_async_flip(plane, fb->modifier)) 855 + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 856 856 return 256 * 1024; 857 857 858 858 if (intel_scanout_needs_vtd_wa(display))
+5 -1
drivers/gpu/drm/i915/display/intel_atomic_plane.c
··· 174 174 DISPLAY_INFO(display)->cursor_needs_physical; 175 175 } 176 176 177 - bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) 177 + bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, 178 + u64 modifier) 178 179 { 180 + if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier)) 181 + return false; 182 + 179 183 return plane->can_async_flip && plane->can_async_flip(modifier); 180 184 } 181 185
+2 -1
drivers/gpu/drm/i915/display/intel_atomic_plane.h
··· 21 21 22 22 struct intel_plane * 23 23 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); 24 - bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); 24 + bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, 25 + u64 modifier); 25 26 unsigned int intel_adjusted_rate(const struct drm_rect *src, 26 27 const struct drm_rect *dst, 27 28 unsigned int rate);
+4 -10
drivers/gpu/drm/i915/display/intel_display.c
··· 6021 6021 if (!plane->async_flip) 6022 6022 continue; 6023 6023 6024 - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { 6024 + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, 6025 + new_plane_state->hw.fb->modifier)) { 6025 6026 drm_dbg_kms(display->drm, 6026 - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", 6027 + "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", 6027 6028 plane->base.base.id, plane->base.name, 6029 + &new_plane_state->hw.fb->format->format, 6028 6030 new_plane_state->hw.fb->modifier); 6029 - return -EINVAL; 6030 - } 6031 - 6032 - if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, 6033 - new_plane_state->hw.fb->modifier)) { 6034 - drm_dbg_kms(display->drm, 6035 - "[PLANE:%d:%s] Planar formats do not support async flips\n", 6036 - plane->base.base.id, plane->base.name); 6037 6031 return -EINVAL; 6038 6032 } 6039 6033
+1 -1
drivers/gpu/drm/i915/display/skl_universal_plane.c
··· 601 601 * Figure out what's going on here... 602 602 */ 603 603 if (display->platform.alderlake_p && 604 - intel_plane_can_async_flip(plane, fb->modifier)) 604 + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 605 605 return mult * 16 * 1024; 606 606 607 607 switch (fb->modifier) {