Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm radeon/nouveau/core fixes from Dave Airlie:
"Mostly radeon fixes, with some nouveau bios parser, ttm fix and a fix
for AST driver"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (42 commits)
drm/fb-helper: don't sleep for screen unblank when an oops is in progress
drm, ttm Fix uninitialized warning
drm/ttm: fix the tt_populated check in ttm_tt_destroy()
drm/nouveau/ttm: prevent double-free in nouveau_sgdma_create_ttm() failure path
drm/nouveau/bios/init: fix thinko in INIT_CONFIGURE_MEM
drm/nouveau/kms: enable for non-vga pci classes
drm/nouveau/bios/init: stub opcode 0xaa
drm/radeon: avoid UVD corruptions on AGP cards
drm/radeon: fix panel scaling with eDP and LVDS bridges
drm/radeon/dpm: rework auto performance level enable
drm/radeon: Fix hmdi typo
drm/radeon/dpm/rs780: fix force_performance state for same sclks
drm/radeon/dpm/rs780: don't enable sclk scaling if not required
drm/radeon/dpm/rs780: add some sanity checking to sclk scaling
drm/radeon/dpm/rs780: use drm_mode_vrefresh()
drm/udl: rip out set_need_resched
drm/ast: fix the ast open key function
drm/radeon/dpm: add bapm callback for kb/kv
drm/radeon/dpm: add bapm callback for trinity
drm/radeon/dpm: add infrastructure to properly handle bapm
...
+837
-261
+1
-1
drivers/gpu/drm/ast/ast_drv.h
+1
-1
drivers/gpu/drm/ast/ast_drv.h
+8
drivers/gpu/drm/drm_fb_helper.c
+8
drivers/gpu/drm/drm_fb_helper.c
···
416
416
return;
417
417
418
418
/*
419
+
* fbdev->blank can be called from irq context in case of a panic.
420
+
* Since we already have our own special panic handler which will
421
+
* restore the fbdev console mode completely, just bail out early.
422
+
*/
423
+
if (oops_in_progress)
424
+
return;
425
+
426
+
/*
419
427
* For each CRTC in this fb, turn the connectors on/off.
420
428
*/
421
429
drm_modeset_lock_all(dev);
+18
-3
drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+18
-3
drivers/gpu/drm/nouveau/core/subdev/bios/init.c
···
579
579
init_reserved(struct nvbios_init *init)
580
580
{
581
581
u8 opcode = nv_ro08(init->bios, init->offset);
582
-
trace("RESERVED\t0x%02x\n", opcode);
583
-
init->offset += 1;
582
+
u8 length, i;
583
+
584
+
switch (opcode) {
585
+
case 0xaa:
586
+
length = 4;
587
+
break;
588
+
default:
589
+
length = 1;
590
+
break;
591
+
}
592
+
593
+
trace("RESERVED 0x%02x\t", opcode);
594
+
for (i = 1; i < length; i++)
595
+
cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
596
+
cont("\n");
597
+
init->offset += length;
584
598
}
585
599
586
600
/**
···
1451
1437
data = init_rdvgai(init, 0x03c4, 0x01);
1452
1438
init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1453
1439
1454
-
while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1440
+
for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1455
1441
switch (addr) {
1456
1442
case 0x10021c: /* CKE_NORMAL */
1457
1443
case 0x1002d0: /* CMD_REFRESH */
···
2149
2135
[0x99] = { init_zm_auxch },
2150
2136
[0x9a] = { init_i2c_long_if },
2151
2137
[0xa9] = { init_gpio_ne },
2138
+
[0xaa] = { init_reserved },
2152
2139
};
2153
2140
2154
2141
#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
+17
-22
drivers/gpu/drm/nouveau/nouveau_display.c
+17
-22
drivers/gpu/drm/nouveau/nouveau_display.c
···
278
278
{
279
279
struct nouveau_drm *drm = nouveau_drm(dev);
280
280
struct nouveau_display *disp;
281
-
u32 pclass = dev->pdev->class >> 8;
282
281
int ret, gen;
283
282
284
283
disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL);
···
339
340
drm_kms_helper_poll_init(dev);
340
341
drm_kms_helper_poll_disable(dev);
341
342
342
-
if (nouveau_modeset == 1 ||
343
-
(nouveau_modeset < 0 && pclass == PCI_CLASS_DISPLAY_VGA)) {
344
-
if (drm->vbios.dcb.entries) {
345
-
if (nv_device(drm->device)->card_type < NV_50)
346
-
ret = nv04_display_create(dev);
347
-
else
348
-
ret = nv50_display_create(dev);
349
-
} else {
350
-
ret = 0;
351
-
}
352
-
353
-
if (ret)
354
-
goto disp_create_err;
355
-
356
-
if (dev->mode_config.num_crtc) {
357
-
ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
358
-
if (ret)
359
-
goto vblank_err;
360
-
}
361
-
362
-
nouveau_backlight_init(dev);
343
+
if (drm->vbios.dcb.entries) {
344
+
if (nv_device(drm->device)->card_type < NV_50)
345
+
ret = nv04_display_create(dev);
346
+
else
347
+
ret = nv50_display_create(dev);
348
+
} else {
349
+
ret = 0;
363
350
}
364
351
352
+
if (ret)
353
+
goto disp_create_err;
354
+
355
+
if (dev->mode_config.num_crtc) {
356
+
ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
357
+
if (ret)
358
+
goto vblank_err;
359
+
}
360
+
361
+
nouveau_backlight_init(dev);
365
362
return 0;
366
363
367
364
vblank_err:
+2
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
+2
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
+1
-3
drivers/gpu/drm/nouveau/nouveau_sgdma.c
+1
-3
drivers/gpu/drm/nouveau/nouveau_sgdma.c
···
104
104
else
105
105
nvbe->ttm.ttm.func = &nv50_sgdma_backend;
106
106
107
-
if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page)) {
108
-
kfree(nvbe);
107
+
if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page))
109
108
return NULL;
110
-
}
111
109
return &nvbe->ttm.ttm;
112
110
}
+15
-8
drivers/gpu/drm/radeon/atombios_encoders.c
+15
-8
drivers/gpu/drm/radeon/atombios_encoders.c
···
707
707
switch (connector->connector_type) {
708
708
case DRM_MODE_CONNECTOR_DVII:
709
709
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
710
-
if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
711
-
radeon_audio)
710
+
if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
711
+
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
712
+
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
712
713
return ATOM_ENCODER_MODE_HDMI;
713
714
else if (radeon_connector->use_digital)
714
715
return ATOM_ENCODER_MODE_DVI;
···
719
718
case DRM_MODE_CONNECTOR_DVID:
720
719
case DRM_MODE_CONNECTOR_HDMIA:
721
720
default:
722
-
if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
723
-
radeon_audio)
721
+
if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
722
+
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
723
+
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
724
724
return ATOM_ENCODER_MODE_HDMI;
725
725
else
726
726
return ATOM_ENCODER_MODE_DVI;
···
734
732
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
735
733
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
736
734
return ATOM_ENCODER_MODE_DP;
737
-
else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
738
-
radeon_audio)
735
+
else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
736
+
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
737
+
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
739
738
return ATOM_ENCODER_MODE_HDMI;
740
739
else
741
740
return ATOM_ENCODER_MODE_DVI;
···
1650
1647
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1651
1648
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1652
1649
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1653
-
/* some early dce3.2 boards have a bug in their transmitter control table */
1654
-
if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1650
+
/* some dce3.x boards have a bug in their transmitter control table.
1651
+
* ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1652
+
* does the same thing and more.
1653
+
*/
1654
+
if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1655
+
(rdev->family != CHIP_RS880))
1655
1656
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1656
1657
}
1657
1658
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
-6
drivers/gpu/drm/radeon/btc_dpm.c
-6
drivers/gpu/drm/radeon/btc_dpm.c
-6
drivers/gpu/drm/radeon/ci_dpm.c
-6
drivers/gpu/drm/radeon/ci_dpm.c
···
4748
4748
if (pi->pcie_performance_request)
4749
4749
ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4750
4750
4751
-
ret = ci_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
4752
-
if (ret) {
4753
-
DRM_ERROR("ci_dpm_force_performance_level failed\n");
4754
-
return ret;
4755
-
}
4756
-
4757
4751
cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4758
4752
RADEON_CG_BLOCK_MC |
4759
4753
RADEON_CG_BLOCK_SDMA |
+26
-13
drivers/gpu/drm/radeon/ci_smc.c
+26
-13
drivers/gpu/drm/radeon/ci_smc.c
···
47
47
u32 smc_start_address,
48
48
const u8 *src, u32 byte_count, u32 limit)
49
49
{
50
+
unsigned long flags;
50
51
u32 data, original_data;
51
52
u32 addr;
52
53
u32 extra_shift;
53
-
int ret;
54
+
int ret = 0;
54
55
55
56
if (smc_start_address & 3)
56
57
return -EINVAL;
···
60
59
61
60
addr = smc_start_address;
62
61
62
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
63
63
while (byte_count >= 4) {
64
64
/* SMC address space is BE */
65
65
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
66
66
67
67
ret = ci_set_smc_sram_address(rdev, addr, limit);
68
68
if (ret)
69
-
return ret;
69
+
goto done;
70
70
71
71
WREG32(SMC_IND_DATA_0, data);
72
72
···
82
80
83
81
ret = ci_set_smc_sram_address(rdev, addr, limit);
84
82
if (ret)
85
-
return ret;
83
+
goto done;
86
84
87
85
original_data = RREG32(SMC_IND_DATA_0);
88
86
···
99
97
100
98
ret = ci_set_smc_sram_address(rdev, addr, limit);
101
99
if (ret)
102
-
return ret;
100
+
goto done;
103
101
104
102
WREG32(SMC_IND_DATA_0, data);
105
103
}
106
-
return 0;
104
+
105
+
done:
106
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
107
+
108
+
return ret;
107
109
}
108
110
109
111
void ci_start_smc(struct radeon_device *rdev)
···
203
197
204
198
int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
205
199
{
200
+
unsigned long flags;
206
201
u32 ucode_start_address;
207
202
u32 ucode_size;
208
203
const u8 *src;
···
226
219
return -EINVAL;
227
220
228
221
src = (const u8 *)rdev->smc_fw->data;
222
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
229
223
WREG32(SMC_IND_INDEX_0, ucode_start_address);
230
224
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
231
225
while (ucode_size >= 4) {
···
239
231
ucode_size -= 4;
240
232
}
241
233
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
234
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
242
235
243
236
return 0;
244
237
}
···
247
238
int ci_read_smc_sram_dword(struct radeon_device *rdev,
248
239
u32 smc_address, u32 *value, u32 limit)
249
240
{
241
+
unsigned long flags;
250
242
int ret;
251
243
244
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
252
245
ret = ci_set_smc_sram_address(rdev, smc_address, limit);
253
-
if (ret)
254
-
return ret;
246
+
if (ret == 0)
247
+
*value = RREG32(SMC_IND_DATA_0);
248
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
255
249
256
-
*value = RREG32(SMC_IND_DATA_0);
257
-
return 0;
250
+
return ret;
258
251
}
259
252
260
253
int ci_write_smc_sram_dword(struct radeon_device *rdev,
261
254
u32 smc_address, u32 value, u32 limit)
262
255
{
256
+
unsigned long flags;
263
257
int ret;
264
258
259
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
265
260
ret = ci_set_smc_sram_address(rdev, smc_address, limit);
266
-
if (ret)
267
-
return ret;
261
+
if (ret == 0)
262
+
WREG32(SMC_IND_DATA_0, value);
263
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
268
264
269
-
WREG32(SMC_IND_DATA_0, value);
270
-
return 0;
265
+
return ret;
271
266
}
+29
-7
drivers/gpu/drm/radeon/cik.c
+29
-7
drivers/gpu/drm/radeon/cik.c
···
77
77
static void cik_program_aspm(struct radeon_device *rdev);
78
78
static void cik_init_pg(struct radeon_device *rdev);
79
79
static void cik_init_cg(struct radeon_device *rdev);
80
+
static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
81
+
bool enable);
80
82
81
83
/* get temperature in millidegrees */
82
84
int ci_get_temp(struct radeon_device *rdev)
···
122
120
*/
123
121
u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
124
122
{
123
+
unsigned long flags;
125
124
u32 r;
126
125
126
+
spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
127
127
WREG32(PCIE_INDEX, reg);
128
128
(void)RREG32(PCIE_INDEX);
129
129
r = RREG32(PCIE_DATA);
130
+
spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
130
131
return r;
131
132
}
132
133
133
134
void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
134
135
{
136
+
unsigned long flags;
137
+
138
+
spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
135
139
WREG32(PCIE_INDEX, reg);
136
140
(void)RREG32(PCIE_INDEX);
137
141
WREG32(PCIE_DATA, v);
138
142
(void)RREG32(PCIE_DATA);
143
+
spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
139
144
}
140
145
141
146
static const u32 spectre_rlc_save_restore_register_list[] =
···
2731
2722
} else if ((rdev->pdev->device == 0x1309) ||
2732
2723
(rdev->pdev->device == 0x130A) ||
2733
2724
(rdev->pdev->device == 0x130D) ||
2734
-
(rdev->pdev->device == 0x1313)) {
2725
+
(rdev->pdev->device == 0x1313) ||
2726
+
(rdev->pdev->device == 0x131D)) {
2735
2727
rdev->config.cik.max_cu_per_sh = 6;
2736
2728
rdev->config.cik.max_backends_per_se = 2;
2737
2729
} else if ((rdev->pdev->device == 0x1306) ||
···
4023
4013
{
4024
4014
int r;
4025
4015
4016
+
cik_enable_gui_idle_interrupt(rdev, false);
4017
+
4026
4018
r = cik_cp_load_microcode(rdev);
4027
4019
if (r)
4028
4020
return r;
···
4035
4023
r = cik_cp_compute_resume(rdev);
4036
4024
if (r)
4037
4025
return r;
4026
+
4027
+
cik_enable_gui_idle_interrupt(rdev, true);
4038
4028
4039
4029
return 0;
4040
4030
}
···
5390
5376
void cik_update_cg(struct radeon_device *rdev,
5391
5377
u32 block, bool enable)
5392
5378
{
5379
+
5393
5380
if (block & RADEON_CG_BLOCK_GFX) {
5381
+
cik_enable_gui_idle_interrupt(rdev, false);
5394
5382
/* order matters! */
5395
5383
if (enable) {
5396
5384
cik_enable_mgcg(rdev, true);
···
5401
5385
cik_enable_cgcg(rdev, false);
5402
5386
cik_enable_mgcg(rdev, false);
5403
5387
}
5388
+
cik_enable_gui_idle_interrupt(rdev, true);
5404
5389
}
5405
5390
5406
5391
if (block & RADEON_CG_BLOCK_MC) {
···
5558
5541
{
5559
5542
u32 data, orig;
5560
5543
5561
-
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
5544
+
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5562
5545
orig = data = RREG32(RLC_PG_CNTL);
5563
5546
data |= GFX_PG_ENABLE;
5564
5547
if (orig != data)
···
5822
5805
if (rdev->pg_flags) {
5823
5806
cik_enable_sck_slowdown_on_pu(rdev, true);
5824
5807
cik_enable_sck_slowdown_on_pd(rdev, true);
5825
-
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
5808
+
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5826
5809
cik_init_gfx_cgpg(rdev);
5827
5810
cik_enable_cp_pg(rdev, true);
5828
5811
cik_enable_gds_pg(rdev, true);
···
5836
5819
{
5837
5820
if (rdev->pg_flags) {
5838
5821
cik_update_gfx_pg(rdev, false);
5839
-
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
5822
+
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5840
5823
cik_enable_cp_pg(rdev, false);
5841
5824
cik_enable_gds_pg(rdev, false);
5842
5825
}
···
5912
5895
u32 tmp;
5913
5896
5914
5897
/* gfx ring */
5915
-
WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5898
+
tmp = RREG32(CP_INT_CNTL_RING0) &
5899
+
(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5900
+
WREG32(CP_INT_CNTL_RING0, tmp);
5916
5901
/* sdma */
5917
5902
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5918
5903
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
···
6055
6036
*/
6056
6037
int cik_irq_set(struct radeon_device *rdev)
6057
6038
{
6058
-
u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE |
6059
-
PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
6039
+
u32 cp_int_cntl;
6060
6040
u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
6061
6041
u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
6062
6042
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
···
6075
6057
cik_disable_interrupt_state(rdev);
6076
6058
return 0;
6077
6059
}
6060
+
6061
+
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6062
+
(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6063
+
cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
6078
6064
6079
6065
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
6080
6066
hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
-6
drivers/gpu/drm/radeon/cypress_dpm.c
-6
drivers/gpu/drm/radeon/cypress_dpm.c
···
2014
2014
if (eg_pi->pcie_performance_request)
2015
2015
cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2016
2016
2017
-
ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
2018
-
if (ret) {
2019
-
DRM_ERROR("rv770_dpm_force_performance_level failed\n");
2020
-
return ret;
2021
-
}
2022
-
2023
2017
return 0;
2024
2018
}
2025
2019
+10
-2
drivers/gpu/drm/radeon/dce6_afmt.c
+10
-2
drivers/gpu/drm/radeon/dce6_afmt.c
···
28
28
static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
29
29
u32 block_offset, u32 reg)
30
30
{
31
+
unsigned long flags;
31
32
u32 r;
32
33
34
+
spin_lock_irqsave(&rdev->end_idx_lock, flags);
33
35
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
34
36
r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
37
+
spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
38
+
35
39
return r;
36
40
}
37
41
38
42
static void dce6_endpoint_wreg(struct radeon_device *rdev,
39
43
u32 block_offset, u32 reg, u32 v)
40
44
{
45
+
unsigned long flags;
46
+
47
+
spin_lock_irqsave(&rdev->end_idx_lock, flags);
41
48
if (ASIC_IS_DCE8(rdev))
42
49
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
43
50
else
44
51
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
45
52
AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
46
53
WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
54
+
spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
47
55
}
48
56
49
57
#define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
···
94
86
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
95
87
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
96
88
u32 offset = dig->afmt->offset;
97
-
u32 id = dig->afmt->pin->id;
98
89
99
90
if (!dig->afmt->pin)
100
91
return;
101
92
102
-
WREG32(AFMT_AUDIO_SRC_CONTROL + offset, AFMT_AUDIO_SRC_SELECT(id));
93
+
WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
94
+
AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
103
95
}
104
96
105
97
void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
+129
-35
drivers/gpu/drm/radeon/kv_dpm.c
+129
-35
drivers/gpu/drm/radeon/kv_dpm.c
···
40
40
static void kv_enable_new_levels(struct radeon_device *rdev);
41
41
static void kv_program_nbps_index_settings(struct radeon_device *rdev,
42
42
struct radeon_ps *new_rps);
43
+
static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
43
44
static int kv_set_enabled_levels(struct radeon_device *rdev);
44
45
static int kv_force_dpm_highest(struct radeon_device *rdev);
45
46
static int kv_force_dpm_lowest(struct radeon_device *rdev);
···
520
519
521
520
static void kv_program_vc(struct radeon_device *rdev)
522
521
{
523
-
WREG32_SMC(CG_FTV_0, 0x3FFFC000);
522
+
WREG32_SMC(CG_FTV_0, 0x3FFFC100);
524
523
}
525
524
526
525
static void kv_clear_vc(struct radeon_device *rdev)
···
639
638
640
639
static int kv_unforce_levels(struct radeon_device *rdev)
641
640
{
642
-
return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
641
+
if (rdev->family == CHIP_KABINI)
642
+
return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
643
+
else
644
+
return kv_set_enabled_levels(rdev);
643
645
}
644
646
645
647
static int kv_update_sclk_t(struct radeon_device *rdev)
···
671
667
&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
672
668
673
669
if (table && table->count) {
674
-
for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
675
-
if ((table->entries[i].clk == pi->boot_pl.sclk) ||
676
-
(i == 0))
670
+
for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
671
+
if (table->entries[i].clk == pi->boot_pl.sclk)
677
672
break;
678
673
}
679
674
···
685
682
if (table->num_max_dpm_entries == 0)
686
683
return -EINVAL;
687
684
688
-
for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
689
-
if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) ||
690
-
(i == 0))
685
+
for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
686
+
if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
691
687
break;
692
688
}
693
689
···
1080
1078
PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1081
1079
}
1082
1080
1081
+
static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1082
+
{
1083
+
struct kv_power_info *pi = kv_get_pi(rdev);
1084
+
1085
+
pi->acp_boot_level = 0xff;
1086
+
}
1087
+
1083
1088
static void kv_update_current_ps(struct radeon_device *rdev,
1084
1089
struct radeon_ps *rps)
1085
1090
{
···
1107
1098
pi->requested_rps = *rps;
1108
1099
pi->requested_ps = *new_ps;
1109
1100
pi->requested_rps.ps_priv = &pi->requested_ps;
1101
+
}
1102
+
1103
+
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1104
+
{
1105
+
struct kv_power_info *pi = kv_get_pi(rdev);
1106
+
int ret;
1107
+
1108
+
if (pi->bapm_enable) {
1109
+
ret = kv_smc_bapm_enable(rdev, enable);
1110
+
if (ret)
1111
+
DRM_ERROR("kv_smc_bapm_enable failed\n");
1112
+
}
1110
1113
}
1111
1114
1112
1115
int kv_dpm_enable(struct radeon_device *rdev)
···
1213
1192
return ret;
1214
1193
}
1215
1194
1195
+
kv_reset_acp_boot_level(rdev);
1196
+
1216
1197
if (rdev->irq.installed &&
1217
1198
r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1218
1199
ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
···
1224
1201
}
1225
1202
rdev->irq.dpm_thermal = true;
1226
1203
radeon_irq_set(rdev);
1204
+
}
1205
+
1206
+
ret = kv_smc_bapm_enable(rdev, false);
1207
+
if (ret) {
1208
+
DRM_ERROR("kv_smc_bapm_enable failed\n");
1209
+
return ret;
1227
1210
}
1228
1211
1229
1212
/* powerdown unused blocks for now */
···
1254
1225
RADEON_CG_BLOCK_SDMA |
1255
1226
RADEON_CG_BLOCK_BIF |
1256
1227
RADEON_CG_BLOCK_HDP), false);
1228
+
1229
+
kv_smc_bapm_enable(rdev, false);
1257
1230
1258
1231
/* powerup blocks */
1259
1232
kv_dpm_powergate_acp(rdev, false);
···
1481
1450
return kv_enable_samu_dpm(rdev, !gate);
1482
1451
}
1483
1452
1453
+
static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1454
+
{
1455
+
u8 i;
1456
+
struct radeon_clock_voltage_dependency_table *table =
1457
+
&rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1458
+
1459
+
for (i = 0; i < table->count; i++) {
1460
+
if (table->entries[i].clk >= 0) /* XXX */
1461
+
break;
1462
+
}
1463
+
1464
+
if (i >= table->count)
1465
+
i = table->count - 1;
1466
+
1467
+
return i;
1468
+
}
1469
+
1470
+
static void kv_update_acp_boot_level(struct radeon_device *rdev)
1471
+
{
1472
+
struct kv_power_info *pi = kv_get_pi(rdev);
1473
+
u8 acp_boot_level;
1474
+
1475
+
if (!pi->caps_stable_p_state) {
1476
+
acp_boot_level = kv_get_acp_boot_level(rdev);
1477
+
if (acp_boot_level != pi->acp_boot_level) {
1478
+
pi->acp_boot_level = acp_boot_level;
1479
+
kv_send_msg_to_smc_with_parameter(rdev,
1480
+
PPSMC_MSG_ACPDPM_SetEnabledMask,
1481
+
(1 << pi->acp_boot_level));
1482
+
}
1483
+
}
1484
+
}
1485
+
1484
1486
static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1485
1487
{
1486
1488
struct kv_power_info *pi = kv_get_pi(rdev);
···
1525
1461
if (pi->caps_stable_p_state)
1526
1462
pi->acp_boot_level = table->count - 1;
1527
1463
else
1528
-
pi->acp_boot_level = 0;
1464
+
pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1529
1465
1530
1466
ret = kv_copy_bytes_to_smc(rdev,
1531
1467
pi->dpm_table_start +
···
1652
1588
}
1653
1589
}
1654
1590
1655
-
for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1656
-
if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) ||
1657
-
(i == 0)) {
1658
-
pi->highest_valid = i;
1591
+
for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1592
+
if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1659
1593
break;
1660
-
}
1661
1594
}
1595
+
pi->highest_valid = i;
1662
1596
1663
1597
if (pi->lowest_valid > pi->highest_valid) {
1664
1598
if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
···
1677
1615
}
1678
1616
}
1679
1617
1680
-
for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1618
+
for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1681
1619
if (table->entries[i].sclk_frequency <=
1682
-
new_ps->levels[new_ps->num_levels - 1].sclk ||
1683
-
i == 0) {
1684
-
pi->highest_valid = i;
1620
+
new_ps->levels[new_ps->num_levels - 1].sclk)
1685
1621
break;
1686
-
}
1687
1622
}
1623
+
pi->highest_valid = i;
1688
1624
1689
1625
if (pi->lowest_valid > pi->highest_valid) {
1690
1626
if ((new_ps->levels[0].sclk -
···
1784
1724
RADEON_CG_BLOCK_BIF |
1785
1725
RADEON_CG_BLOCK_HDP), false);
1786
1726
1727
+
if (pi->bapm_enable) {
1728
+
ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1729
+
if (ret) {
1730
+
DRM_ERROR("kv_smc_bapm_enable failed\n");
1731
+
return ret;
1732
+
}
1733
+
}
1734
+
1787
1735
if (rdev->family == CHIP_KABINI) {
1788
1736
if (pi->enable_dpm) {
1789
1737
kv_set_valid_clock_range(rdev, new_ps);
···
1843
1775
return ret;
1844
1776
}
1845
1777
#endif
1778
+
kv_update_acp_boot_level(rdev);
1846
1779
kv_update_sclk_t(rdev);
1847
1780
kv_enable_nb_dpm(rdev);
1848
1781
}
···
1854
1785
RADEON_CG_BLOCK_BIF |
1855
1786
RADEON_CG_BLOCK_HDP), true);
1856
1787
1857
-
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1858
1788
return 0;
1859
1789
}
1860
1790
···
1874
1806
1875
1807
void kv_dpm_reset_asic(struct radeon_device *rdev)
1876
1808
{
1877
-
kv_force_lowest_valid(rdev);
1878
-
kv_init_graphics_levels(rdev);
1879
-
kv_program_bootup_state(rdev);
1880
-
kv_upload_dpm_settings(rdev);
1881
-
kv_force_lowest_valid(rdev);
1882
-
kv_unforce_levels(rdev);
1809
+
struct kv_power_info *pi = kv_get_pi(rdev);
1810
+
1811
+
if (rdev->family == CHIP_KABINI) {
1812
+
kv_force_lowest_valid(rdev);
1813
+
kv_init_graphics_levels(rdev);
1814
+
kv_program_bootup_state(rdev);
1815
+
kv_upload_dpm_settings(rdev);
1816
+
kv_force_lowest_valid(rdev);
1817
+
kv_unforce_levels(rdev);
1818
+
} else {
1819
+
kv_init_graphics_levels(rdev);
1820
+
kv_program_bootup_state(rdev);
1821
+
kv_freeze_sclk_dpm(rdev, true);
1822
+
kv_upload_dpm_settings(rdev);
1823
+
kv_freeze_sclk_dpm(rdev, false);
1824
+
kv_set_enabled_level(rdev, pi->graphics_boot_level);
1825
+
}
1883
1826
}
1884
1827
1885
1828
//XXX use sumo_dpm_display_configuration_changed
···
1950
1871
if (ret)
1951
1872
return ret;
1952
1873
1953
-
for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {
1874
+
for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
1954
1875
if (enable_mask & (1 << i))
1955
1876
break;
1956
1877
}
1957
1878
1958
-
return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1879
+
if (rdev->family == CHIP_KABINI)
1880
+
return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1881
+
else
1882
+
return kv_set_enabled_level(rdev, i);
1959
1883
}
1960
1884
1961
1885
static int kv_force_dpm_lowest(struct radeon_device *rdev)
···
1975
1893
break;
1976
1894
}
1977
1895
1978
-
return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1896
+
if (rdev->family == CHIP_KABINI)
1897
+
return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1898
+
else
1899
+
return kv_set_enabled_level(rdev, i);
1979
1900
}
1980
1901
1981
1902
static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
···
1996
1911
if (!pi->caps_sclk_ds)
1997
1912
return 0;
1998
1913
1999
-
for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {
1914
+
for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2000
1915
temp = sclk / sumo_get_sleep_divider_from_id(i);
2001
-
if ((temp >= min) || (i == 0))
1916
+
if (temp >= min)
2002
1917
break;
2003
1918
}
2004
1919
···
2124
2039
ps->dpmx_nb_ps_lo = 0x1;
2125
2040
ps->dpmx_nb_ps_hi = 0x0;
2126
2041
} else {
2127
-
ps->dpm0_pg_nb_ps_lo = 0x1;
2042
+
ps->dpm0_pg_nb_ps_lo = 0x3;
2128
2043
ps->dpm0_pg_nb_ps_hi = 0x0;
2129
-
ps->dpmx_nb_ps_lo = 0x2;
2130
-
ps->dpmx_nb_ps_hi = 0x1;
2044
+
ps->dpmx_nb_ps_lo = 0x3;
2045
+
ps->dpmx_nb_ps_hi = 0x0;
2131
2046
2132
-
if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2047
+
if (pi->sys_info.nb_dpm_enable) {
2133
2048
force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2134
2049
pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2135
2050
pi->disable_nb_ps3_in_battery;
···
2293
2208
if (i >= pi->lowest_valid && i <= pi->highest_valid)
2294
2209
kv_dpm_power_level_enable(rdev, i, true);
2295
2210
}
2211
+
}
2212
+
2213
+
static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2214
+
{
2215
+
u32 new_mask = (1 << level);
2216
+
2217
+
return kv_send_msg_to_smc_with_parameter(rdev,
2218
+
PPSMC_MSG_SCLKDPM_SetEnabledMask,
2219
+
new_mask);
2296
2220
}
2297
2221
2298
2222
static int kv_set_enabled_levels(struct radeon_device *rdev)
+1
drivers/gpu/drm/radeon/kv_dpm.h
+1
drivers/gpu/drm/radeon/kv_dpm.h
···
192
192
int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
193
193
u32 *value, u32 limit);
194
194
int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
195
+
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
195
196
int kv_copy_bytes_to_smc(struct radeon_device *rdev,
196
197
u32 smc_start_address,
197
198
const u8 *src, u32 byte_count, u32 limit);
+8
drivers/gpu/drm/radeon/kv_smc.c
+8
drivers/gpu/drm/radeon/kv_smc.c
···
107
107
return kv_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Disable);
108
108
}
109
109
110
+
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)
111
+
{
112
+
if (enable)
113
+
return kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableBAPM);
114
+
else
115
+
return kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableBAPM);
116
+
}
117
+
110
118
int kv_copy_bytes_to_smc(struct radeon_device *rdev,
111
119
u32 smc_start_address,
112
120
const u8 *src, u32 byte_count, u32 limit)
-6
drivers/gpu/drm/radeon/ni_dpm.c
-6
drivers/gpu/drm/radeon/ni_dpm.c
+2
drivers/gpu/drm/radeon/ppsmc.h
+2
drivers/gpu/drm/radeon/ppsmc.h
···
163
163
#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)
164
164
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
165
165
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
166
+
#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)
167
+
#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121)
166
168
#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)
167
169
168
170
+7
drivers/gpu/drm/radeon/r100.c
+7
drivers/gpu/drm/radeon/r100.c
···
2853
2853
2854
2854
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2855
2855
{
2856
+
unsigned long flags;
2856
2857
uint32_t data;
2857
2858
2859
+
spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2858
2860
WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2859
2861
r100_pll_errata_after_index(rdev);
2860
2862
data = RREG32(RADEON_CLOCK_CNTL_DATA);
2861
2863
r100_pll_errata_after_data(rdev);
2864
+
spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2862
2865
return data;
2863
2866
}
2864
2867
2865
2868
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2866
2869
{
2870
+
unsigned long flags;
2871
+
2872
+
spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2867
2873
WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2868
2874
r100_pll_errata_after_index(rdev);
2869
2875
WREG32(RADEON_CLOCK_CNTL_DATA, v);
2870
2876
r100_pll_errata_after_data(rdev);
2877
+
spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2871
2878
}
2872
2879
2873
2880
static void r100_set_safe_registers(struct radeon_device *rdev)
+7
drivers/gpu/drm/radeon/r420.c
+7
drivers/gpu/drm/radeon/r420.c
···
160
160
161
161
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
162
162
{
163
+
unsigned long flags;
163
164
u32 r;
164
165
166
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
165
167
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
166
168
r = RREG32(R_0001FC_MC_IND_DATA);
169
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
167
170
return r;
168
171
}
169
172
170
173
void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
171
174
{
175
+
unsigned long flags;
176
+
177
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
172
178
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
173
179
S_0001F8_MC_IND_WR_EN(1));
174
180
WREG32(R_0001FC_MC_IND_DATA, v);
181
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
175
182
}
176
183
177
184
static void r420_debugfs(struct radeon_device *rdev)
+19
drivers/gpu/drm/radeon/r600.c
+19
drivers/gpu/drm/radeon/r600.c
···
119
119
return rdev->clock.spll.reference_freq;
120
120
}
121
121
122
+
int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
123
+
{
124
+
return 0;
125
+
}
126
+
122
127
/* get temperature in millidegrees */
123
128
int rv6xx_get_temp(struct radeon_device *rdev)
124
129
{
···
1050
1045
1051
1046
uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1052
1047
{
1048
+
unsigned long flags;
1053
1049
uint32_t r;
1054
1050
1051
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1055
1052
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1056
1053
r = RREG32(R_0028FC_MC_DATA);
1057
1054
WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1055
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1058
1056
return r;
1059
1057
}
1060
1058
1061
1059
void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1062
1060
{
1061
+
unsigned long flags;
1062
+
1063
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1063
1064
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1064
1065
S_0028F8_MC_IND_WR_EN(1));
1065
1066
WREG32(R_0028FC_MC_DATA, v);
1066
1067
WREG32(R_0028F8_MC_INDEX, 0x7F);
1068
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1067
1069
}
1068
1070
1069
1071
static void r600_mc_program(struct radeon_device *rdev)
···
2104
2092
*/
2105
2093
u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2106
2094
{
2095
+
unsigned long flags;
2107
2096
u32 r;
2108
2097
2098
+
spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2109
2099
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2110
2100
(void)RREG32(PCIE_PORT_INDEX);
2111
2101
r = RREG32(PCIE_PORT_DATA);
2102
+
spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2112
2103
return r;
2113
2104
}
2114
2105
2115
2106
void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2116
2107
{
2108
+
unsigned long flags;
2109
+
2110
+
spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2117
2111
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2118
2112
(void)RREG32(PCIE_PORT_INDEX);
2119
2113
WREG32(PCIE_PORT_DATA, (v));
2120
2114
(void)RREG32(PCIE_PORT_DATA);
2115
+
spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2121
2116
}
2122
2117
2123
2118
/*
+14
-24
drivers/gpu/drm/radeon/r600_dpm.c
+14
-24
drivers/gpu/drm/radeon/r600_dpm.c
···
1219
1219
1220
1220
void r600_free_extended_power_table(struct radeon_device *rdev)
1221
1221
{
1222
-
if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries)
1223
-
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1224
-
if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries)
1225
-
kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1226
-
if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries)
1227
-
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
1228
-
if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries)
1229
-
kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
1230
-
if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)
1231
-
kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
1232
-
if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
1233
-
kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);
1234
-
if (rdev->pm.dpm.dyn_state.ppm_table)
1235
-
kfree(rdev->pm.dpm.dyn_state.ppm_table);
1236
-
if (rdev->pm.dpm.dyn_state.cac_tdp_table)
1237
-
kfree(rdev->pm.dpm.dyn_state.cac_tdp_table);
1238
-
if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
1239
-
kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
1240
-
if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
1241
-
kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries);
1242
-
if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)
1243
-
kfree(rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries);
1244
-
if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)
1245
-
kfree(rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries);
1222
+
struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state;
1223
+
1224
+
kfree(dyn_state->vddc_dependency_on_sclk.entries);
1225
+
kfree(dyn_state->vddci_dependency_on_mclk.entries);
1226
+
kfree(dyn_state->vddc_dependency_on_mclk.entries);
1227
+
kfree(dyn_state->mvdd_dependency_on_mclk.entries);
1228
+
kfree(dyn_state->cac_leakage_table.entries);
1229
+
kfree(dyn_state->phase_shedding_limits_table.entries);
1230
+
kfree(dyn_state->ppm_table);
1231
+
kfree(dyn_state->cac_tdp_table);
1232
+
kfree(dyn_state->vce_clock_voltage_dependency_table.entries);
1233
+
kfree(dyn_state->uvd_clock_voltage_dependency_table.entries);
1234
+
kfree(dyn_state->samu_clock_voltage_dependency_table.entries);
1235
+
kfree(dyn_state->acp_clock_voltage_dependency_table.entries);
1246
1236
}
1247
1237
1248
1238
enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
+1
-1
drivers/gpu/drm/radeon/r600d.h
+1
-1
drivers/gpu/drm/radeon/r600d.h
···
1040
1040
# define HDMI0_AVI_INFO_CONT (1 << 1)
1041
1041
# define HDMI0_AUDIO_INFO_SEND (1 << 4)
1042
1042
# define HDMI0_AUDIO_INFO_CONT (1 << 5)
1043
-
# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
1043
+
# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
1044
1044
# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
1045
1045
# define HDMI0_MPEG_INFO_SEND (1 << 8)
1046
1046
# define HDMI0_MPEG_INFO_CONT (1 << 9)
+81
-1
drivers/gpu/drm/radeon/radeon.h
+81
-1
drivers/gpu/drm/radeon/radeon.h
···
181
181
#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
182
182
183
183
/* PG flags */
184
-
#define RADEON_PG_SUPPORT_GFX_CG (1 << 0)
184
+
#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
185
185
#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
186
186
#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
187
187
#define RADEON_PG_SUPPORT_UVD (1 << 3)
···
1778
1778
int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1779
1779
bool (*vblank_too_short)(struct radeon_device *rdev);
1780
1780
void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1781
+
void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1781
1782
} dpm;
1782
1783
/* pageflipping */
1783
1784
struct {
···
2111
2110
resource_size_t rmmio_size;
2112
2111
/* protects concurrent MM_INDEX/DATA based register access */
2113
2112
spinlock_t mmio_idx_lock;
2113
+
/* protects concurrent SMC based register access */
2114
+
spinlock_t smc_idx_lock;
2115
+
/* protects concurrent PLL register access */
2116
+
spinlock_t pll_idx_lock;
2117
+
/* protects concurrent MC register access */
2118
+
spinlock_t mc_idx_lock;
2119
+
/* protects concurrent PCIE register access */
2120
+
spinlock_t pcie_idx_lock;
2121
+
/* protects concurrent PCIE_PORT register access */
2122
+
spinlock_t pciep_idx_lock;
2123
+
/* protects concurrent PIF register access */
2124
+
spinlock_t pif_idx_lock;
2125
+
/* protects concurrent CG register access */
2126
+
spinlock_t cg_idx_lock;
2127
+
/* protects concurrent UVD register access */
2128
+
spinlock_t uvd_idx_lock;
2129
+
/* protects concurrent RCU register access */
2130
+
spinlock_t rcu_idx_lock;
2131
+
/* protects concurrent DIDT register access */
2132
+
spinlock_t didt_idx_lock;
2133
+
/* protects concurrent ENDPOINT (audio) register access */
2134
+
spinlock_t end_idx_lock;
2114
2135
void __iomem *rmmio;
2115
2136
radeon_rreg_t mc_rreg;
2116
2137
radeon_wreg_t mc_wreg;
···
2300
2277
*/
2301
2278
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2302
2279
{
2280
+
unsigned long flags;
2303
2281
uint32_t r;
2304
2282
2283
+
spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2305
2284
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2306
2285
r = RREG32(RADEON_PCIE_DATA);
2286
+
spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2307
2287
return r;
2308
2288
}
2309
2289
2310
2290
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2311
2291
{
2292
+
unsigned long flags;
2293
+
2294
+
spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2312
2295
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2313
2296
WREG32(RADEON_PCIE_DATA, (v));
2297
+
spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2314
2298
}
2315
2299
2316
2300
static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2317
2301
{
2302
+
unsigned long flags;
2318
2303
u32 r;
2319
2304
2305
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2320
2306
WREG32(TN_SMC_IND_INDEX_0, (reg));
2321
2307
r = RREG32(TN_SMC_IND_DATA_0);
2308
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2322
2309
return r;
2323
2310
}
2324
2311
2325
2312
static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2326
2313
{
2314
+
unsigned long flags;
2315
+
2316
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2327
2317
WREG32(TN_SMC_IND_INDEX_0, (reg));
2328
2318
WREG32(TN_SMC_IND_DATA_0, (v));
2319
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2329
2320
}
2330
2321
2331
2322
static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2332
2323
{
2324
+
unsigned long flags;
2333
2325
u32 r;
2334
2326
2327
+
spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2335
2328
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2336
2329
r = RREG32(R600_RCU_DATA);
2330
+
spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2337
2331
return r;
2338
2332
}
2339
2333
2340
2334
static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2341
2335
{
2336
+
unsigned long flags;
2337
+
2338
+
spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2342
2339
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2343
2340
WREG32(R600_RCU_DATA, (v));
2341
+
spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2344
2342
}
2345
2343
2346
2344
static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2347
2345
{
2346
+
unsigned long flags;
2348
2347
u32 r;
2349
2348
2349
+
spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2350
2350
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2351
2351
r = RREG32(EVERGREEN_CG_IND_DATA);
2352
+
spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2352
2353
return r;
2353
2354
}
2354
2355
2355
2356
static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2356
2357
{
2358
+
unsigned long flags;
2359
+
2360
+
spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2357
2361
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2358
2362
WREG32(EVERGREEN_CG_IND_DATA, (v));
2363
+
spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2359
2364
}
2360
2365
2361
2366
static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2362
2367
{
2368
+
unsigned long flags;
2363
2369
u32 r;
2364
2370
2371
+
spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2365
2372
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2366
2373
r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2374
+
spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2367
2375
return r;
2368
2376
}
2369
2377
2370
2378
static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2371
2379
{
2380
+
unsigned long flags;
2381
+
2382
+
spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2372
2383
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2373
2384
WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2385
+
spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2374
2386
}
2375
2387
2376
2388
static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2377
2389
{
2390
+
unsigned long flags;
2378
2391
u32 r;
2379
2392
2393
+
spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2380
2394
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2381
2395
r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2396
+
spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2382
2397
return r;
2383
2398
}
2384
2399
2385
2400
static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2386
2401
{
2402
+
unsigned long flags;
2403
+
2404
+
spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2387
2405
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2388
2406
WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2407
+
spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2389
2408
}
2390
2409
2391
2410
static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2392
2411
{
2412
+
unsigned long flags;
2393
2413
u32 r;
2394
2414
2415
+
spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2395
2416
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2396
2417
r = RREG32(R600_UVD_CTX_DATA);
2418
+
spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2397
2419
return r;
2398
2420
}
2399
2421
2400
2422
static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2401
2423
{
2424
+
unsigned long flags;
2425
+
2426
+
spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2402
2427
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2403
2428
WREG32(R600_UVD_CTX_DATA, (v));
2429
+
spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2404
2430
}
2405
2431
2406
2432
2407
2433
static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2408
2434
{
2435
+
unsigned long flags;
2409
2436
u32 r;
2410
2437
2438
+
spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2411
2439
WREG32(CIK_DIDT_IND_INDEX, (reg));
2412
2440
r = RREG32(CIK_DIDT_IND_DATA);
2441
+
spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2413
2442
return r;
2414
2443
}
2415
2444
2416
2445
static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2417
2446
{
2447
+
unsigned long flags;
2448
+
2449
+
spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2418
2450
WREG32(CIK_DIDT_IND_INDEX, (reg));
2419
2451
WREG32(CIK_DIDT_IND_DATA, (v));
2452
+
spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2420
2453
}
2421
2454
2422
2455
void r100_pll_errata_after_index(struct radeon_device *rdev);
···
2648
2569
#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2649
2570
#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2650
2571
#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2572
+
#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2651
2573
2652
2574
/* Common functions */
2653
2575
/* AGP */
+8
-3
drivers/gpu/drm/radeon/radeon_asic.c
+8
-3
drivers/gpu/drm/radeon/radeon_asic.c
···
1037
1037
.set_pcie_lanes = &r600_set_pcie_lanes,
1038
1038
.set_clock_gating = NULL,
1039
1039
.get_temperature = &rv6xx_get_temp,
1040
+
.set_uvd_clocks = &r600_set_uvd_clocks,
1040
1041
},
1041
1042
.dpm = {
1042
1043
.init = &rv6xx_dpm_init,
···
1127
1126
.set_pcie_lanes = NULL,
1128
1127
.set_clock_gating = NULL,
1129
1128
.get_temperature = &rv6xx_get_temp,
1129
+
.set_uvd_clocks = &r600_set_uvd_clocks,
1130
1130
},
1131
1131
.dpm = {
1132
1132
.init = &rs780_dpm_init,
···
1143
1141
.get_mclk = &rs780_dpm_get_mclk,
1144
1142
.print_power_state = &rs780_dpm_print_power_state,
1145
1143
.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1144
+
.force_performance_level = &rs780_dpm_force_performance_level,
1146
1145
},
1147
1146
.pflip = {
1148
1147
.pre_page_flip = &rs600_pre_page_flip,
···
1794
1791
.print_power_state = &trinity_dpm_print_power_state,
1795
1792
.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1796
1793
.force_performance_level = &trinity_dpm_force_performance_level,
1794
+
.enable_bapm = &trinity_dpm_enable_bapm,
1797
1795
},
1798
1796
.pflip = {
1799
1797
.pre_page_flip = &evergreen_pre_page_flip,
···
2170
2166
.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2171
2167
.force_performance_level = &kv_dpm_force_performance_level,
2172
2168
.powergate_uvd = &kv_dpm_powergate_uvd,
2169
+
.enable_bapm = &kv_dpm_enable_bapm,
2173
2170
},
2174
2171
.pflip = {
2175
2172
.pre_page_flip = &evergreen_pre_page_flip,
···
2395
2390
RADEON_CG_SUPPORT_HDP_LS |
2396
2391
RADEON_CG_SUPPORT_HDP_MGCG;
2397
2392
rdev->pg_flags = 0 |
2398
-
/*RADEON_PG_SUPPORT_GFX_CG | */
2393
+
/*RADEON_PG_SUPPORT_GFX_PG | */
2399
2394
RADEON_PG_SUPPORT_SDMA;
2400
2395
break;
2401
2396
case CHIP_OLAND:
···
2484
2479
RADEON_CG_SUPPORT_HDP_LS |
2485
2480
RADEON_CG_SUPPORT_HDP_MGCG;
2486
2481
rdev->pg_flags = 0;
2487
-
/*RADEON_PG_SUPPORT_GFX_CG |
2482
+
/*RADEON_PG_SUPPORT_GFX_PG |
2488
2483
RADEON_PG_SUPPORT_GFX_SMG |
2489
2484
RADEON_PG_SUPPORT_GFX_DMG |
2490
2485
RADEON_PG_SUPPORT_UVD |
···
2512
2507
RADEON_CG_SUPPORT_HDP_LS |
2513
2508
RADEON_CG_SUPPORT_HDP_MGCG;
2514
2509
rdev->pg_flags = 0;
2515
-
/*RADEON_PG_SUPPORT_GFX_CG |
2510
+
/*RADEON_PG_SUPPORT_GFX_PG |
2516
2511
RADEON_PG_SUPPORT_GFX_SMG |
2517
2512
RADEON_PG_SUPPORT_UVD |
2518
2513
RADEON_PG_SUPPORT_VCE |
+5
drivers/gpu/drm/radeon/radeon_asic.h
+5
drivers/gpu/drm/radeon/radeon_asic.h
···
389
389
u32 r600_get_xclk(struct radeon_device *rdev);
390
390
uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
391
391
int rv6xx_get_temp(struct radeon_device *rdev);
392
+
int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
392
393
int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
393
394
void r600_dpm_post_set_power_state(struct radeon_device *rdev);
394
395
/* r600 dma */
···
429
428
struct radeon_ps *ps);
430
429
void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
431
430
struct seq_file *m);
431
+
int rs780_dpm_force_performance_level(struct radeon_device *rdev,
432
+
enum radeon_dpm_forced_level level);
432
433
433
434
/*
434
435
* rv770,rv730,rv710,rv740
···
628
625
struct seq_file *m);
629
626
int trinity_dpm_force_performance_level(struct radeon_device *rdev,
630
627
enum radeon_dpm_forced_level level);
628
+
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
631
629
632
630
/* DCE6 - SI */
633
631
void dce6_bandwidth_update(struct radeon_device *rdev);
···
785
781
int kv_dpm_force_performance_level(struct radeon_device *rdev,
786
782
enum radeon_dpm_forced_level level);
787
783
void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
784
+
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
788
785
789
786
/* uvd v1.0 */
790
787
uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
+65
-4
drivers/gpu/drm/radeon/radeon_connectors.c
+65
-4
drivers/gpu/drm/radeon/radeon_connectors.c
···
396
396
}
397
397
}
398
398
399
+
if (property == rdev->mode_info.audio_property) {
400
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
401
+
/* need to find digital encoder on connector */
402
+
encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
403
+
if (!encoder)
404
+
return 0;
405
+
406
+
radeon_encoder = to_radeon_encoder(encoder);
407
+
408
+
if (radeon_connector->audio != val) {
409
+
radeon_connector->audio = val;
410
+
radeon_property_change_mode(&radeon_encoder->base);
411
+
}
412
+
}
413
+
399
414
if (property == rdev->mode_info.underscan_property) {
400
415
/* need to find digital encoder on connector */
401
416
encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
···
1435
1420
if (radeon_dp_getdpcd(radeon_connector))
1436
1421
ret = connector_status_connected;
1437
1422
} else {
1438
-
/* try non-aux ddc (DP to DVI/HMDI/etc. adapter) */
1423
+
/* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1439
1424
if (radeon_ddc_probe(radeon_connector, false))
1440
1425
ret = connector_status_connected;
1441
1426
}
···
1500
1485
.detect = radeon_dp_detect,
1501
1486
.fill_modes = drm_helper_probe_single_connector_modes,
1502
1487
.set_property = radeon_connector_set_property,
1488
+
.destroy = radeon_dp_connector_destroy,
1489
+
.force = radeon_dvi_force,
1490
+
};
1491
+
1492
+
static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1493
+
.dpms = drm_helper_connector_dpms,
1494
+
.detect = radeon_dp_detect,
1495
+
.fill_modes = drm_helper_probe_single_connector_modes,
1496
+
.set_property = radeon_lvds_set_property,
1497
+
.destroy = radeon_dp_connector_destroy,
1498
+
.force = radeon_dvi_force,
1499
+
};
1500
+
1501
+
static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1502
+
.dpms = drm_helper_connector_dpms,
1503
+
.detect = radeon_dp_detect,
1504
+
.fill_modes = drm_helper_probe_single_connector_modes,
1505
+
.set_property = radeon_lvds_set_property,
1503
1506
.destroy = radeon_dp_connector_destroy,
1504
1507
.force = radeon_dvi_force,
1505
1508
};
···
1613
1580
goto failed;
1614
1581
radeon_dig_connector->igp_lane_info = igp_lane_info;
1615
1582
radeon_connector->con_priv = radeon_dig_connector;
1616
-
drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1617
-
drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1618
1583
if (i2c_bus->valid) {
1619
1584
/* add DP i2c bus */
1620
1585
if (connector_type == DRM_MODE_CONNECTOR_eDP)
···
1629
1598
case DRM_MODE_CONNECTOR_VGA:
1630
1599
case DRM_MODE_CONNECTOR_DVIA:
1631
1600
default:
1601
+
drm_connector_init(dev, &radeon_connector->base,
1602
+
&radeon_dp_connector_funcs, connector_type);
1603
+
drm_connector_helper_add(&radeon_connector->base,
1604
+
&radeon_dp_connector_helper_funcs);
1632
1605
connector->interlace_allowed = true;
1633
1606
connector->doublescan_allowed = true;
1634
1607
radeon_connector->dac_load_detect = true;
···
1645
1610
case DRM_MODE_CONNECTOR_HDMIA:
1646
1611
case DRM_MODE_CONNECTOR_HDMIB:
1647
1612
case DRM_MODE_CONNECTOR_DisplayPort:
1613
+
drm_connector_init(dev, &radeon_connector->base,
1614
+
&radeon_dp_connector_funcs, connector_type);
1615
+
drm_connector_helper_add(&radeon_connector->base,
1616
+
&radeon_dp_connector_helper_funcs);
1648
1617
drm_object_attach_property(&radeon_connector->base.base,
1649
1618
rdev->mode_info.underscan_property,
1650
1619
UNDERSCAN_OFF);
···
1658
1619
drm_object_attach_property(&radeon_connector->base.base,
1659
1620
rdev->mode_info.underscan_vborder_property,
1660
1621
0);
1622
+
drm_object_attach_property(&radeon_connector->base.base,
1623
+
rdev->mode_info.audio_property,
1624
+
RADEON_AUDIO_DISABLE);
1661
1625
subpixel_order = SubPixelHorizontalRGB;
1662
1626
connector->interlace_allowed = true;
1663
1627
if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
···
1676
1634
break;
1677
1635
case DRM_MODE_CONNECTOR_LVDS:
1678
1636
case DRM_MODE_CONNECTOR_eDP:
1637
+
drm_connector_init(dev, &radeon_connector->base,
1638
+
&radeon_lvds_bridge_connector_funcs, connector_type);
1639
+
drm_connector_helper_add(&radeon_connector->base,
1640
+
&radeon_dp_connector_helper_funcs);
1679
1641
drm_object_attach_property(&radeon_connector->base.base,
1680
1642
dev->mode_config.scaling_mode_property,
1681
1643
DRM_MODE_SCALE_FULLSCREEN);
···
1754
1708
rdev->mode_info.underscan_vborder_property,
1755
1709
0);
1756
1710
}
1711
+
if (ASIC_IS_DCE2(rdev)) {
1712
+
drm_object_attach_property(&radeon_connector->base.base,
1713
+
rdev->mode_info.audio_property,
1714
+
RADEON_AUDIO_DISABLE);
1715
+
}
1757
1716
if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1758
1717
radeon_connector->dac_load_detect = true;
1759
1718
drm_object_attach_property(&radeon_connector->base.base,
···
1799
1748
rdev->mode_info.underscan_vborder_property,
1800
1749
0);
1801
1750
}
1751
+
if (ASIC_IS_DCE2(rdev)) {
1752
+
drm_object_attach_property(&radeon_connector->base.base,
1753
+
rdev->mode_info.audio_property,
1754
+
RADEON_AUDIO_DISABLE);
1755
+
}
1802
1756
subpixel_order = SubPixelHorizontalRGB;
1803
1757
connector->interlace_allowed = true;
1804
1758
if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
···
1843
1787
rdev->mode_info.underscan_vborder_property,
1844
1788
0);
1845
1789
}
1790
+
if (ASIC_IS_DCE2(rdev)) {
1791
+
drm_object_attach_property(&radeon_connector->base.base,
1792
+
rdev->mode_info.audio_property,
1793
+
RADEON_AUDIO_DISABLE);
1794
+
}
1846
1795
connector->interlace_allowed = true;
1847
1796
/* in theory with a DP to VGA converter... */
1848
1797
connector->doublescan_allowed = false;
···
1858
1797
goto failed;
1859
1798
radeon_dig_connector->igp_lane_info = igp_lane_info;
1860
1799
radeon_connector->con_priv = radeon_dig_connector;
1861
-
drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1800
+
drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type);
1862
1801
drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1863
1802
if (i2c_bus->valid) {
1864
1803
/* add DP i2c bus */
+8
-3
drivers/gpu/drm/radeon/radeon_cs.c
+8
-3
drivers/gpu/drm/radeon/radeon_cs.c
···
28
28
#include <drm/radeon_drm.h>
29
29
#include "radeon_reg.h"
30
30
#include "radeon.h"
31
+
#include "radeon_trace.h"
31
32
32
33
static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
33
34
{
···
81
80
p->relocs[i].lobj.bo = p->relocs[i].robj;
82
81
p->relocs[i].lobj.written = !!r->write_domain;
83
82
84
-
/* the first reloc of an UVD job is the
85
-
msg and that must be in VRAM */
86
-
if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
83
+
/* the first reloc of an UVD job is the msg and that must be in
84
+
VRAM, also but everything into VRAM on AGP cards to avoid
85
+
image corruptions */
86
+
if (p->ring == R600_RING_TYPE_UVD_INDEX &&
87
+
(i == 0 || p->rdev->flags & RADEON_IS_AGP)) {
87
88
/* TODO: is this still needed for NI+ ? */
88
89
p->relocs[i].lobj.domain =
89
90
RADEON_GEM_DOMAIN_VRAM;
···
561
558
r = radeon_cs_handle_lockup(rdev, r);
562
559
return r;
563
560
}
561
+
562
+
trace_radeon_cs(&parser);
564
563
565
564
r = radeon_cs_ib_chunk(rdev, &parser);
566
565
if (r) {
+11
drivers/gpu/drm/radeon/radeon_device.c
+11
drivers/gpu/drm/radeon/radeon_device.c
···
1249
1249
/* Registers mapping */
1250
1250
/* TODO: block userspace mapping of io register */
1251
1251
spin_lock_init(&rdev->mmio_idx_lock);
1252
+
spin_lock_init(&rdev->smc_idx_lock);
1253
+
spin_lock_init(&rdev->pll_idx_lock);
1254
+
spin_lock_init(&rdev->mc_idx_lock);
1255
+
spin_lock_init(&rdev->pcie_idx_lock);
1256
+
spin_lock_init(&rdev->pciep_idx_lock);
1257
+
spin_lock_init(&rdev->pif_idx_lock);
1258
+
spin_lock_init(&rdev->cg_idx_lock);
1259
+
spin_lock_init(&rdev->uvd_idx_lock);
1260
+
spin_lock_init(&rdev->rcu_idx_lock);
1261
+
spin_lock_init(&rdev->didt_idx_lock);
1262
+
spin_lock_init(&rdev->end_idx_lock);
1252
1263
if (rdev->family >= CHIP_BONAIRE) {
1253
1264
rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1254
1265
rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
+12
drivers/gpu/drm/radeon/radeon_display.c
+12
drivers/gpu/drm/radeon/radeon_display.c
···
1172
1172
{ UNDERSCAN_AUTO, "auto" },
1173
1173
};
1174
1174
1175
+
static struct drm_prop_enum_list radeon_audio_enum_list[] =
1176
+
{ { RADEON_AUDIO_DISABLE, "off" },
1177
+
{ RADEON_AUDIO_ENABLE, "on" },
1178
+
{ RADEON_AUDIO_AUTO, "auto" },
1179
+
};
1180
+
1175
1181
static int radeon_modeset_create_props(struct radeon_device *rdev)
1176
1182
{
1177
1183
int sz;
···
1227
1221
"underscan vborder", 0, 128);
1228
1222
if (!rdev->mode_info.underscan_vborder_property)
1229
1223
return -ENOMEM;
1224
+
1225
+
sz = ARRAY_SIZE(radeon_audio_enum_list);
1226
+
rdev->mode_info.audio_property =
1227
+
drm_property_create_enum(rdev->ddev, 0,
1228
+
"audio",
1229
+
radeon_audio_enum_list, sz);
1230
1230
1231
1231
return 0;
1232
1232
}
+1
-1
drivers/gpu/drm/radeon/radeon_drv.c
+1
-1
drivers/gpu/drm/radeon/radeon_drv.c
+9
drivers/gpu/drm/radeon/radeon_mode.h
+9
drivers/gpu/drm/radeon/radeon_mode.h
···
247
247
struct drm_property *underscan_property;
248
248
struct drm_property *underscan_hborder_property;
249
249
struct drm_property *underscan_vborder_property;
250
+
/* audio */
251
+
struct drm_property *audio_property;
250
252
/* hardcoded DFP edid from BIOS */
251
253
struct edid *bios_hardcoded_edid;
252
254
int bios_hardcoded_edid_size;
···
473
471
u8 cd_mux_state;
474
472
};
475
473
474
+
enum radeon_connector_audio {
475
+
RADEON_AUDIO_DISABLE = 0,
476
+
RADEON_AUDIO_ENABLE = 1,
477
+
RADEON_AUDIO_AUTO = 2
478
+
};
479
+
476
480
struct radeon_connector {
477
481
struct drm_connector base;
478
482
uint32_t connector_id;
···
497
489
struct radeon_hpd hpd;
498
490
struct radeon_router router;
499
491
struct radeon_i2c_chan *router_bus;
492
+
enum radeon_connector_audio audio;
500
493
};
501
494
502
495
struct radeon_framebuffer {
+66
-15
drivers/gpu/drm/radeon/radeon_pm.c
+66
-15
drivers/gpu/drm/radeon/radeon_pm.c
···
67
67
68
68
void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69
69
{
70
-
if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70
+
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71
+
mutex_lock(&rdev->pm.mutex);
72
+
if (power_supply_is_system_supplied() > 0)
73
+
rdev->pm.dpm.ac_power = true;
74
+
else
75
+
rdev->pm.dpm.ac_power = false;
76
+
if (rdev->asic->dpm.enable_bapm)
77
+
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78
+
mutex_unlock(&rdev->pm.mutex);
79
+
} else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71
80
if (rdev->pm.profile == PM_PROFILE_AUTO) {
72
81
mutex_lock(&rdev->pm.mutex);
73
82
radeon_pm_update_profile(rdev);
···
342
333
struct device_attribute *attr,
343
334
char *buf)
344
335
{
345
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
336
+
struct drm_device *ddev = dev_get_drvdata(dev);
346
337
struct radeon_device *rdev = ddev->dev_private;
347
338
int cp = rdev->pm.profile;
348
339
···
358
349
const char *buf,
359
350
size_t count)
360
351
{
361
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
352
+
struct drm_device *ddev = dev_get_drvdata(dev);
362
353
struct radeon_device *rdev = ddev->dev_private;
363
354
364
355
mutex_lock(&rdev->pm.mutex);
···
392
383
struct device_attribute *attr,
393
384
char *buf)
394
385
{
395
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
386
+
struct drm_device *ddev = dev_get_drvdata(dev);
396
387
struct radeon_device *rdev = ddev->dev_private;
397
388
int pm = rdev->pm.pm_method;
398
389
···
406
397
const char *buf,
407
398
size_t count)
408
399
{
409
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
400
+
struct drm_device *ddev = dev_get_drvdata(dev);
410
401
struct radeon_device *rdev = ddev->dev_private;
411
402
412
403
/* we don't support the legacy modes with dpm */
···
442
433
struct device_attribute *attr,
443
434
char *buf)
444
435
{
445
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
436
+
struct drm_device *ddev = dev_get_drvdata(dev);
446
437
struct radeon_device *rdev = ddev->dev_private;
447
438
enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
448
439
···
456
447
const char *buf,
457
448
size_t count)
458
449
{
459
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
450
+
struct drm_device *ddev = dev_get_drvdata(dev);
460
451
struct radeon_device *rdev = ddev->dev_private;
461
452
462
453
mutex_lock(&rdev->pm.mutex);
···
481
472
struct device_attribute *attr,
482
473
char *buf)
483
474
{
484
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
475
+
struct drm_device *ddev = dev_get_drvdata(dev);
485
476
struct radeon_device *rdev = ddev->dev_private;
486
477
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
487
478
···
495
486
const char *buf,
496
487
size_t count)
497
488
{
498
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
489
+
struct drm_device *ddev = dev_get_drvdata(dev);
499
490
struct radeon_device *rdev = ddev->dev_private;
500
491
enum radeon_dpm_forced_level level;
501
492
int ret = 0;
···
533
524
struct device_attribute *attr,
534
525
char *buf)
535
526
{
536
-
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
527
+
struct drm_device *ddev = dev_get_drvdata(dev);
537
528
struct radeon_device *rdev = ddev->dev_private;
538
529
int temp;
539
530
···
541
532
temp = radeon_get_temperature(rdev);
542
533
else
543
534
temp = 0;
535
+
536
+
return snprintf(buf, PAGE_SIZE, "%d\n", temp);
537
+
}
538
+
539
+
static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
540
+
struct device_attribute *attr,
541
+
char *buf)
542
+
{
543
+
struct drm_device *ddev = dev_get_drvdata(dev);
544
+
struct radeon_device *rdev = ddev->dev_private;
545
+
int hyst = to_sensor_dev_attr(attr)->index;
546
+
int temp;
547
+
548
+
if (hyst)
549
+
temp = rdev->pm.dpm.thermal.min_temp;
550
+
else
551
+
temp = rdev->pm.dpm.thermal.max_temp;
544
552
545
553
return snprintf(buf, PAGE_SIZE, "%d\n", temp);
546
554
}
···
570
544
}
571
545
572
546
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
547
+
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
548
+
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
573
549
static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
574
550
575
551
static struct attribute *hwmon_attributes[] = {
576
552
&sensor_dev_attr_temp1_input.dev_attr.attr,
553
+
&sensor_dev_attr_temp1_crit.dev_attr.attr,
554
+
&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
577
555
&sensor_dev_attr_name.dev_attr.attr,
578
556
NULL
579
557
};
580
558
559
+
static umode_t hwmon_attributes_visible(struct kobject *kobj,
560
+
struct attribute *attr, int index)
561
+
{
562
+
struct device *dev = container_of(kobj, struct device, kobj);
563
+
struct drm_device *ddev = dev_get_drvdata(dev);
564
+
struct radeon_device *rdev = ddev->dev_private;
565
+
566
+
/* Skip limit attributes if DPM is not enabled */
567
+
if (rdev->pm.pm_method != PM_METHOD_DPM &&
568
+
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
569
+
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
570
+
return 0;
571
+
572
+
return attr->mode;
573
+
}
574
+
581
575
static const struct attribute_group hwmon_attrgroup = {
582
576
.attrs = hwmon_attributes,
577
+
.is_visible = hwmon_attributes_visible,
583
578
};
584
579
585
580
static int radeon_hwmon_init(struct radeon_device *rdev)
···
917
870
918
871
radeon_dpm_post_set_power_state(rdev);
919
872
920
-
/* force low perf level for thermal */
921
-
if (rdev->pm.dpm.thermal_active &&
922
-
rdev->asic->dpm.force_performance_level) {
923
-
radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
873
+
if (rdev->asic->dpm.force_performance_level) {
874
+
if (rdev->pm.dpm.thermal_active)
875
+
/* force low perf level for thermal */
876
+
radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
877
+
else
878
+
/* otherwise, enable auto */
879
+
radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
924
880
}
925
881
926
882
done:
···
1152
1102
{
1153
1103
int ret;
1154
1104
1155
-
/* default to performance state */
1105
+
/* default to balanced state */
1156
1106
rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1157
1107
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1108
+
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1158
1109
rdev->pm.default_sclk = rdev->clock.default_sclk;
1159
1110
rdev->pm.default_mclk = rdev->clock.default_mclk;
1160
1111
rdev->pm.current_sclk = rdev->clock.default_sclk;
+20
-7
drivers/gpu/drm/radeon/radeon_trace.h
+20
-7
drivers/gpu/drm/radeon/radeon_trace.h
···
27
27
TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages)
28
28
);
29
29
30
+
TRACE_EVENT(radeon_cs,
31
+
TP_PROTO(struct radeon_cs_parser *p),
32
+
TP_ARGS(p),
33
+
TP_STRUCT__entry(
34
+
__field(u32, ring)
35
+
__field(u32, dw)
36
+
__field(u32, fences)
37
+
),
38
+
39
+
TP_fast_assign(
40
+
__entry->ring = p->ring;
41
+
__entry->dw = p->chunks[p->chunk_ib_idx].length_dw;
42
+
__entry->fences = radeon_fence_count_emitted(
43
+
p->rdev, p->ring);
44
+
),
45
+
TP_printk("ring=%u, dw=%u, fences=%u",
46
+
__entry->ring, __entry->dw,
47
+
__entry->fences)
48
+
);
49
+
30
50
DECLARE_EVENT_CLASS(radeon_fence_request,
31
51
32
52
TP_PROTO(struct drm_device *dev, u32 seqno),
···
67
47
);
68
48
69
49
DEFINE_EVENT(radeon_fence_request, radeon_fence_emit,
70
-
71
-
TP_PROTO(struct drm_device *dev, u32 seqno),
72
-
73
-
TP_ARGS(dev, seqno)
74
-
);
75
-
76
-
DEFINE_EVENT(radeon_fence_request, radeon_fence_retire,
77
50
78
51
TP_PROTO(struct drm_device *dev, u32 seqno),
79
52
+7
drivers/gpu/drm/radeon/rs400.c
+7
drivers/gpu/drm/radeon/rs400.c
···
274
274
275
275
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
276
276
{
277
+
unsigned long flags;
277
278
uint32_t r;
278
279
280
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
279
281
WREG32(RS480_NB_MC_INDEX, reg & 0xff);
280
282
r = RREG32(RS480_NB_MC_DATA);
281
283
WREG32(RS480_NB_MC_INDEX, 0xff);
284
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
282
285
return r;
283
286
}
284
287
285
288
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
286
289
{
290
+
unsigned long flags;
291
+
292
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
287
293
WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
288
294
WREG32(RS480_NB_MC_DATA, (v));
289
295
WREG32(RS480_NB_MC_INDEX, 0xff);
296
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
290
297
}
291
298
292
299
#if defined(CONFIG_DEBUG_FS)
+11
-1
drivers/gpu/drm/radeon/rs600.c
+11
-1
drivers/gpu/drm/radeon/rs600.c
···
847
847
848
848
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
849
849
{
850
+
unsigned long flags;
851
+
u32 r;
852
+
853
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
850
854
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
851
855
S_000070_MC_IND_CITF_ARB0(1));
852
-
return RREG32(R_000074_MC_IND_DATA);
856
+
r = RREG32(R_000074_MC_IND_DATA);
857
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
858
+
return r;
853
859
}
854
860
855
861
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
856
862
{
863
+
unsigned long flags;
864
+
865
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
857
866
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
858
867
S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
859
868
WREG32(R_000074_MC_IND_DATA, v);
869
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
860
870
}
861
871
862
872
static void rs600_debugfs(struct radeon_device *rdev)
+7
drivers/gpu/drm/radeon/rs690.c
+7
drivers/gpu/drm/radeon/rs690.c
···
631
631
632
632
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
633
633
{
634
+
unsigned long flags;
634
635
uint32_t r;
635
636
637
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
636
638
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
637
639
r = RREG32(R_00007C_MC_DATA);
638
640
WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
641
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
639
642
return r;
640
643
}
641
644
642
645
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
643
646
{
647
+
unsigned long flags;
648
+
649
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
644
650
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
645
651
S_000078_MC_IND_WR_EN(1));
646
652
WREG32(R_00007C_MC_DATA, v);
647
653
WREG32(R_000078_MC_INDEX, 0x7F);
654
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
648
655
}
649
656
650
657
static void rs690_mc_program(struct radeon_device *rdev)
+92
-20
drivers/gpu/drm/radeon/rs780_dpm.c
+92
-20
drivers/gpu/drm/radeon/rs780_dpm.c
···
62
62
radeon_crtc = to_radeon_crtc(crtc);
63
63
pi->crtc_id = radeon_crtc->crtc_id;
64
64
if (crtc->mode.htotal && crtc->mode.vtotal)
65
-
pi->refresh_rate =
66
-
(crtc->mode.clock * 1000) /
67
-
(crtc->mode.htotal * crtc->mode.vtotal);
65
+
pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
68
66
break;
69
67
}
70
68
}
···
374
376
WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
375
377
}
376
378
377
-
static void rs780_force_voltage_to_high(struct radeon_device *rdev)
379
+
static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
378
380
{
379
-
struct igp_power_info *pi = rs780_get_pi(rdev);
380
381
struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
381
382
382
383
if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
···
387
390
udelay(1);
388
391
389
392
WREG32_P(FVTHROT_PWM_CTRL_REG0,
390
-
STARTING_PWM_HIGHTIME(pi->max_voltage),
393
+
STARTING_PWM_HIGHTIME(voltage),
391
394
~STARTING_PWM_HIGHTIME_MASK);
392
395
393
396
WREG32_P(FVTHROT_PWM_CTRL_REG0,
···
397
400
~RANGE_PWM_FEEDBACK_DIV_EN);
398
401
399
402
udelay(1);
403
+
404
+
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
405
+
}
406
+
407
+
static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
408
+
{
409
+
struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
410
+
411
+
if (current_state->sclk_low == current_state->sclk_high)
412
+
return;
413
+
414
+
WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
415
+
416
+
WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
417
+
~FORCED_FEEDBACK_DIV_MASK);
418
+
WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
419
+
~STARTING_FEEDBACK_DIV_MASK);
420
+
WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
421
+
422
+
udelay(100);
400
423
401
424
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
402
425
}
···
449
432
if (ret)
450
433
return ret;
451
434
452
-
WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
435
+
if ((min_dividers.ref_div != max_dividers.ref_div) ||
436
+
(min_dividers.post_div != max_dividers.post_div) ||
437
+
(max_dividers.ref_div != current_max_dividers.ref_div) ||
438
+
(max_dividers.post_div != current_max_dividers.post_div))
439
+
return -EINVAL;
453
440
454
-
WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div),
455
-
~FORCED_FEEDBACK_DIV_MASK);
456
-
WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div),
457
-
~STARTING_FEEDBACK_DIV_MASK);
458
-
WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
459
-
460
-
udelay(100);
461
-
462
-
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
441
+
rs780_force_fbdiv(rdev, max_dividers.fb_div);
463
442
464
443
if (max_dividers.fb_div > min_dividers.fb_div) {
465
444
WREG32_P(FVTHROT_FBDIV_REG0,
···
497
484
498
485
if ((new_state->sclk_high == old_state->sclk_high) &&
499
486
(new_state->sclk_low == old_state->sclk_low))
487
+
return;
488
+
489
+
if (new_state->sclk_high == new_state->sclk_low)
500
490
return;
501
491
502
492
rs780_clk_scaling_enable(rdev, true);
···
665
649
rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
666
650
667
651
if (pi->voltage_control) {
668
-
rs780_force_voltage_to_high(rdev);
652
+
rs780_force_voltage(rdev, pi->max_voltage);
669
653
mdelay(5);
670
654
}
671
655
···
733
717
if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
734
718
rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
735
719
rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
736
-
} else if (r600_is_uvd_state(rps->class, rps->class2)) {
737
-
rps->vclk = RS780_DEFAULT_VCLK_FREQ;
738
-
rps->dclk = RS780_DEFAULT_DCLK_FREQ;
739
720
} else {
740
721
rps->vclk = 0;
741
722
rps->dclk = 0;
723
+
}
724
+
725
+
if (r600_is_uvd_state(rps->class, rps->class2)) {
726
+
if ((rps->vclk == 0) || (rps->dclk == 0)) {
727
+
rps->vclk = RS780_DEFAULT_VCLK_FREQ;
728
+
rps->dclk = RS780_DEFAULT_DCLK_FREQ;
729
+
}
742
730
}
743
731
744
732
if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
···
1005
985
else
1006
986
seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
1007
987
ps->sclk_high, ps->max_voltage);
988
+
}
989
+
990
+
int rs780_dpm_force_performance_level(struct radeon_device *rdev,
991
+
enum radeon_dpm_forced_level level)
992
+
{
993
+
struct igp_power_info *pi = rs780_get_pi(rdev);
994
+
struct radeon_ps *rps = rdev->pm.dpm.current_ps;
995
+
struct igp_ps *ps = rs780_get_ps(rps);
996
+
struct atom_clock_dividers dividers;
997
+
int ret;
998
+
999
+
rs780_clk_scaling_enable(rdev, false);
1000
+
rs780_voltage_scaling_enable(rdev, false);
1001
+
1002
+
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1003
+
if (pi->voltage_control)
1004
+
rs780_force_voltage(rdev, pi->max_voltage);
1005
+
1006
+
ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1007
+
ps->sclk_high, false, ÷rs);
1008
+
if (ret)
1009
+
return ret;
1010
+
1011
+
rs780_force_fbdiv(rdev, dividers.fb_div);
1012
+
} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1013
+
ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1014
+
ps->sclk_low, false, ÷rs);
1015
+
if (ret)
1016
+
return ret;
1017
+
1018
+
rs780_force_fbdiv(rdev, dividers.fb_div);
1019
+
1020
+
if (pi->voltage_control)
1021
+
rs780_force_voltage(rdev, pi->min_voltage);
1022
+
} else {
1023
+
if (pi->voltage_control)
1024
+
rs780_force_voltage(rdev, pi->max_voltage);
1025
+
1026
+
if (ps->sclk_high != ps->sclk_low) {
1027
+
WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1028
+
rs780_clk_scaling_enable(rdev, true);
1029
+
}
1030
+
1031
+
if (pi->voltage_control) {
1032
+
rs780_voltage_scaling_enable(rdev, true);
1033
+
rs780_enable_voltage_scaling(rdev, rps);
1034
+
}
1035
+
}
1036
+
1037
+
rdev->pm.dpm.forced_level = level;
1038
+
1039
+
return 0;
1008
1040
}
+8
drivers/gpu/drm/radeon/rv515.c
+8
drivers/gpu/drm/radeon/rv515.c
···
209
209
210
210
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
211
211
{
212
+
unsigned long flags;
212
213
uint32_t r;
213
214
215
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
214
216
WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
215
217
r = RREG32(MC_IND_DATA);
216
218
WREG32(MC_IND_INDEX, 0);
219
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
220
+
217
221
return r;
218
222
}
219
223
220
224
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
221
225
{
226
+
unsigned long flags;
227
+
228
+
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
222
229
WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
223
230
WREG32(MC_IND_DATA, (v));
224
231
WREG32(MC_IND_INDEX, 0);
232
+
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
225
233
}
226
234
227
235
#if defined(CONFIG_DEBUG_FS)
-2
drivers/gpu/drm/radeon/rv6xx_dpm.c
-2
drivers/gpu/drm/radeon/rv6xx_dpm.c
+7
-9
drivers/gpu/drm/radeon/rv770_dpm.c
+7
-9
drivers/gpu/drm/radeon/rv770_dpm.c
···
2064
2064
rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps);
2065
2065
rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2066
2066
2067
-
ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
2068
-
if (ret) {
2069
-
DRM_ERROR("rv770_dpm_force_performance_level failed\n");
2070
-
return ret;
2071
-
}
2072
-
2073
2067
return 0;
2074
2068
}
2075
2069
···
2141
2147
if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2142
2148
rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2143
2149
rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2144
-
} else if (r600_is_uvd_state(rps->class, rps->class2)) {
2145
-
rps->vclk = RV770_DEFAULT_VCLK_FREQ;
2146
-
rps->dclk = RV770_DEFAULT_DCLK_FREQ;
2147
2150
} else {
2148
2151
rps->vclk = 0;
2149
2152
rps->dclk = 0;
2153
+
}
2154
+
2155
+
if (r600_is_uvd_state(rps->class, rps->class2)) {
2156
+
if ((rps->vclk == 0) || (rps->dclk == 0)) {
2157
+
rps->vclk = RV770_DEFAULT_VCLK_FREQ;
2158
+
rps->dclk = RV770_DEFAULT_DCLK_FREQ;
2159
+
}
2150
2160
}
2151
2161
2152
2162
if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
+27
-17
drivers/gpu/drm/radeon/rv770_smc.c
+27
-17
drivers/gpu/drm/radeon/rv770_smc.c
···
274
274
0x08, 0x72, 0x08, 0x72
275
275
};
276
276
277
-
int rv770_set_smc_sram_address(struct radeon_device *rdev,
278
-
u16 smc_address, u16 limit)
277
+
static int rv770_set_smc_sram_address(struct radeon_device *rdev,
278
+
u16 smc_address, u16 limit)
279
279
{
280
280
u32 addr;
281
281
···
296
296
u16 smc_start_address, const u8 *src,
297
297
u16 byte_count, u16 limit)
298
298
{
299
+
unsigned long flags;
299
300
u32 data, original_data, extra_shift;
300
301
u16 addr;
301
-
int ret;
302
+
int ret = 0;
302
303
303
304
if (smc_start_address & 3)
304
305
return -EINVAL;
···
308
307
309
308
addr = smc_start_address;
310
309
310
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
311
311
while (byte_count >= 4) {
312
312
/* SMC address space is BE */
313
313
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
314
314
315
315
ret = rv770_set_smc_sram_address(rdev, addr, limit);
316
316
if (ret)
317
-
return ret;
317
+
goto done;
318
318
319
319
WREG32(SMC_SRAM_DATA, data);
320
320
···
330
328
331
329
ret = rv770_set_smc_sram_address(rdev, addr, limit);
332
330
if (ret)
333
-
return ret;
331
+
goto done;
334
332
335
333
original_data = RREG32(SMC_SRAM_DATA);
336
334
···
348
346
349
347
ret = rv770_set_smc_sram_address(rdev, addr, limit);
350
348
if (ret)
351
-
return ret;
349
+
goto done;
352
350
353
351
WREG32(SMC_SRAM_DATA, data);
354
352
}
355
353
356
-
return 0;
354
+
done:
355
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
356
+
357
+
return ret;
357
358
}
358
359
359
360
static int rv770_program_interrupt_vectors(struct radeon_device *rdev,
···
466
461
467
462
static void rv770_clear_smc_sram(struct radeon_device *rdev, u16 limit)
468
463
{
464
+
unsigned long flags;
469
465
u16 i;
470
466
467
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
471
468
for (i = 0; i < limit; i += 4) {
472
469
rv770_set_smc_sram_address(rdev, i, limit);
473
470
WREG32(SMC_SRAM_DATA, 0);
474
471
}
472
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
475
473
}
476
474
477
475
int rv770_load_smc_ucode(struct radeon_device *rdev,
···
603
595
int rv770_read_smc_sram_dword(struct radeon_device *rdev,
604
596
u16 smc_address, u32 *value, u16 limit)
605
597
{
598
+
unsigned long flags;
606
599
int ret;
607
600
601
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
608
602
ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
609
-
if (ret)
610
-
return ret;
603
+
if (ret == 0)
604
+
*value = RREG32(SMC_SRAM_DATA);
605
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
611
606
612
-
*value = RREG32(SMC_SRAM_DATA);
613
-
614
-
return 0;
607
+
return ret;
615
608
}
616
609
617
610
int rv770_write_smc_sram_dword(struct radeon_device *rdev,
618
611
u16 smc_address, u32 value, u16 limit)
619
612
{
613
+
unsigned long flags;
620
614
int ret;
621
615
616
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
622
617
ret = rv770_set_smc_sram_address(rdev, smc_address, limit);
623
-
if (ret)
624
-
return ret;
618
+
if (ret == 0)
619
+
WREG32(SMC_SRAM_DATA, value);
620
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
625
621
626
-
WREG32(SMC_SRAM_DATA, value);
627
-
628
-
return 0;
622
+
return ret;
629
623
}
-2
drivers/gpu/drm/radeon/rv770_smc.h
-2
drivers/gpu/drm/radeon/rv770_smc.h
···
187
187
#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C
188
188
#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0
189
189
190
-
int rv770_set_smc_sram_address(struct radeon_device *rdev,
191
-
u16 smc_address, u16 limit);
192
190
int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
193
191
u16 smc_start_address, const u8 *src,
194
192
u16 byte_count, u16 limit);
+1
-1
drivers/gpu/drm/radeon/rv770d.h
+1
-1
drivers/gpu/drm/radeon/rv770d.h
···
852
852
#define AFMT_VBI_PACKET_CONTROL 0x7608
853
853
# define AFMT_GENERIC0_UPDATE (1 << 2)
854
854
#define AFMT_INFOFRAME_CONTROL0 0x760c
855
-
# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
855
+
# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
856
856
# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
857
857
# define AFMT_MPEG_INFO_UPDATE (1 << 10)
858
858
#define AFMT_GENERIC0_7 0x7610
+17
-4
drivers/gpu/drm/radeon/si.c
+17
-4
drivers/gpu/drm/radeon/si.c
···
83
83
uint64_t pe,
84
84
uint64_t addr, unsigned count,
85
85
uint32_t incr, uint32_t flags);
86
+
static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
87
+
bool enable);
86
88
87
89
static const u32 verde_rlc_save_restore_register_list[] =
88
90
{
···
3388
3386
u32 rb_bufsz;
3389
3387
int r;
3390
3388
3389
+
si_enable_gui_idle_interrupt(rdev, false);
3390
+
3391
3391
WREG32(CP_SEM_WAIT_TIMER, 0x0);
3392
3392
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3393
3393
···
3504
3500
if (r) {
3505
3501
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3506
3502
}
3503
+
3504
+
si_enable_gui_idle_interrupt(rdev, true);
3507
3505
3508
3506
return 0;
3509
3507
}
···
4894
4888
{
4895
4889
u32 tmp;
4896
4890
4897
-
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
4891
+
if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
4898
4892
tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
4899
4893
WREG32(RLC_TTOP_D, tmp);
4900
4894
···
5256
5250
u32 block, bool enable)
5257
5251
{
5258
5252
if (block & RADEON_CG_BLOCK_GFX) {
5253
+
si_enable_gui_idle_interrupt(rdev, false);
5259
5254
/* order matters! */
5260
5255
if (enable) {
5261
5256
si_enable_mgcg(rdev, true);
···
5265
5258
si_enable_cgcg(rdev, false);
5266
5259
si_enable_mgcg(rdev, false);
5267
5260
}
5261
+
si_enable_gui_idle_interrupt(rdev, true);
5268
5262
}
5269
5263
5270
5264
if (block & RADEON_CG_BLOCK_MC) {
···
5416
5408
si_init_dma_pg(rdev);
5417
5409
}
5418
5410
si_init_ao_cu_mask(rdev);
5419
-
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
5411
+
if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5420
5412
si_init_gfx_cgpg(rdev);
5421
5413
}
5422
5414
si_enable_dma_pg(rdev, true);
···
5568
5560
{
5569
5561
u32 tmp;
5570
5562
5571
-
WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5563
+
tmp = RREG32(CP_INT_CNTL_RING0) &
5564
+
(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5565
+
WREG32(CP_INT_CNTL_RING0, tmp);
5572
5566
WREG32(CP_INT_CNTL_RING1, 0);
5573
5567
WREG32(CP_INT_CNTL_RING2, 0);
5574
5568
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
···
5695
5685
5696
5686
int si_irq_set(struct radeon_device *rdev)
5697
5687
{
5698
-
u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
5688
+
u32 cp_int_cntl;
5699
5689
u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
5700
5690
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
5701
5691
u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
···
5715
5705
si_disable_interrupt_state(rdev);
5716
5706
return 0;
5717
5707
}
5708
+
5709
+
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
5710
+
(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5718
5711
5719
5712
if (!ASIC_IS_NODCE(rdev)) {
5720
5713
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
-6
drivers/gpu/drm/radeon/si_dpm.c
-6
drivers/gpu/drm/radeon/si_dpm.c
···
6075
6075
return ret;
6076
6076
}
6077
6077
6078
-
ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6079
-
if (ret) {
6080
-
DRM_ERROR("si_dpm_force_performance_level failed\n");
6081
-
return ret;
6082
-
}
6083
-
6084
6078
si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
6085
6079
RADEON_CG_BLOCK_MC |
6086
6080
RADEON_CG_BLOCK_SDMA |
+28
-15
drivers/gpu/drm/radeon/si_smc.c
+28
-15
drivers/gpu/drm/radeon/si_smc.c
···
29
29
#include "ppsmc.h"
30
30
#include "radeon_ucode.h"
31
31
32
-
int si_set_smc_sram_address(struct radeon_device *rdev,
33
-
u32 smc_address, u32 limit)
32
+
static int si_set_smc_sram_address(struct radeon_device *rdev,
33
+
u32 smc_address, u32 limit)
34
34
{
35
35
if (smc_address & 3)
36
36
return -EINVAL;
···
47
47
u32 smc_start_address,
48
48
const u8 *src, u32 byte_count, u32 limit)
49
49
{
50
-
int ret;
50
+
unsigned long flags;
51
+
int ret = 0;
51
52
u32 data, original_data, addr, extra_shift;
52
53
53
54
if (smc_start_address & 3)
···
58
57
59
58
addr = smc_start_address;
60
59
60
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
61
61
while (byte_count >= 4) {
62
62
/* SMC address space is BE */
63
63
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
64
64
65
65
ret = si_set_smc_sram_address(rdev, addr, limit);
66
66
if (ret)
67
-
return ret;
67
+
goto done;
68
68
69
69
WREG32(SMC_IND_DATA_0, data);
70
70
···
80
78
81
79
ret = si_set_smc_sram_address(rdev, addr, limit);
82
80
if (ret)
83
-
return ret;
81
+
goto done;
84
82
85
83
original_data = RREG32(SMC_IND_DATA_0);
86
84
···
98
96
99
97
ret = si_set_smc_sram_address(rdev, addr, limit);
100
98
if (ret)
101
-
return ret;
99
+
goto done;
102
100
103
101
WREG32(SMC_IND_DATA_0, data);
104
102
}
105
-
return 0;
103
+
104
+
done:
105
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
106
+
107
+
return ret;
106
108
}
107
109
108
110
void si_start_smc(struct radeon_device *rdev)
···
209
203
210
204
int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
211
205
{
206
+
unsigned long flags;
212
207
u32 ucode_start_address;
213
208
u32 ucode_size;
214
209
const u8 *src;
···
248
241
return -EINVAL;
249
242
250
243
src = (const u8 *)rdev->smc_fw->data;
244
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
251
245
WREG32(SMC_IND_INDEX_0, ucode_start_address);
252
246
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
253
247
while (ucode_size >= 4) {
···
261
253
ucode_size -= 4;
262
254
}
263
255
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
256
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
264
257
265
258
return 0;
266
259
}
···
269
260
int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
270
261
u32 *value, u32 limit)
271
262
{
263
+
unsigned long flags;
272
264
int ret;
273
265
266
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
274
267
ret = si_set_smc_sram_address(rdev, smc_address, limit);
275
-
if (ret)
276
-
return ret;
268
+
if (ret == 0)
269
+
*value = RREG32(SMC_IND_DATA_0);
270
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
277
271
278
-
*value = RREG32(SMC_IND_DATA_0);
279
-
return 0;
272
+
return ret;
280
273
}
281
274
282
275
int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
283
276
u32 value, u32 limit)
284
277
{
278
+
unsigned long flags;
285
279
int ret;
286
280
281
+
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
287
282
ret = si_set_smc_sram_address(rdev, smc_address, limit);
288
-
if (ret)
289
-
return ret;
283
+
if (ret == 0)
284
+
WREG32(SMC_IND_DATA_0, value);
285
+
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
290
286
291
-
WREG32(SMC_IND_DATA_0, value);
292
-
return 0;
287
+
return ret;
293
288
}
-2
drivers/gpu/drm/radeon/sumo_dpm.c
-2
drivers/gpu/drm/radeon/sumo_dpm.c
+16
-1
drivers/gpu/drm/radeon/trinity_dpm.c
+16
-1
drivers/gpu/drm/radeon/trinity_dpm.c
···
1068
1068
pi->requested_rps.ps_priv = &pi->requested_ps;
1069
1069
}
1070
1070
1071
+
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1072
+
{
1073
+
struct trinity_power_info *pi = trinity_get_pi(rdev);
1074
+
1075
+
if (pi->enable_bapm) {
1076
+
trinity_acquire_mutex(rdev);
1077
+
trinity_dpm_bapm_enable(rdev, enable);
1078
+
trinity_release_mutex(rdev);
1079
+
}
1080
+
}
1081
+
1071
1082
int trinity_dpm_enable(struct radeon_device *rdev)
1072
1083
{
1073
1084
struct trinity_power_info *pi = trinity_get_pi(rdev);
···
1102
1091
trinity_program_sclk_dpm(rdev);
1103
1092
trinity_start_dpm(rdev);
1104
1093
trinity_wait_for_dpm_enabled(rdev);
1094
+
trinity_dpm_bapm_enable(rdev, false);
1105
1095
trinity_release_mutex(rdev);
1106
1096
1107
1097
if (rdev->irq.installed &&
···
1128
1116
trinity_release_mutex(rdev);
1129
1117
return;
1130
1118
}
1119
+
trinity_dpm_bapm_enable(rdev, false);
1131
1120
trinity_disable_clock_power_gating(rdev);
1132
1121
sumo_clear_vc(rdev);
1133
1122
trinity_wait_for_level_0(rdev);
···
1225
1212
1226
1213
trinity_acquire_mutex(rdev);
1227
1214
if (pi->enable_dpm) {
1215
+
if (pi->enable_bapm)
1216
+
trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1228
1217
trinity_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1229
1218
trinity_enable_power_level_0(rdev);
1230
1219
trinity_force_level_0(rdev);
···
1236
1221
trinity_force_level_0(rdev);
1237
1222
trinity_unforce_levels(rdev);
1238
1223
trinity_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1239
-
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1240
1224
}
1241
1225
trinity_release_mutex(rdev);
1242
1226
···
1868
1854
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
1869
1855
pi->at[i] = TRINITY_AT_DFLT;
1870
1856
1857
+
pi->enable_bapm = true;
1871
1858
pi->enable_nbps_policy = true;
1872
1859
pi->enable_sclk_ds = true;
1873
1860
pi->enable_gfx_power_gating = true;
+2
drivers/gpu/drm/radeon/trinity_dpm.h
+2
drivers/gpu/drm/radeon/trinity_dpm.h
···
108
108
bool enable_auto_thermal_throttling;
109
109
bool enable_dpm;
110
110
bool enable_sclk_ds;
111
+
bool enable_bapm;
111
112
bool uvd_dpm;
112
113
struct radeon_ps current_rps;
113
114
struct trinity_ps current_ps;
···
119
118
#define TRINITY_AT_DFLT 30
120
119
121
120
/* trinity_smc.c */
121
+
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
122
122
int trinity_dpm_config(struct radeon_device *rdev, bool enable);
123
123
int trinity_uvd_dpm_config(struct radeon_device *rdev);
124
124
int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
+8
drivers/gpu/drm/radeon/trinity_smc.c
+8
drivers/gpu/drm/radeon/trinity_smc.c
···
56
56
return 0;
57
57
}
58
58
59
+
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable)
60
+
{
61
+
if (enable)
62
+
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_EnableBAPM);
63
+
else
64
+
return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DisableBAPM);
65
+
}
66
+
59
67
int trinity_dpm_config(struct radeon_device *rdev, bool enable)
60
68
{
61
69
if (enable)
+1
-1
drivers/gpu/drm/ttm/ttm_object.c
+1
-1
drivers/gpu/drm/ttm/ttm_object.c
+1
-1
drivers/gpu/drm/ttm/ttm_tt.c
+1
-1
drivers/gpu/drm/ttm/ttm_tt.c
-1
drivers/gpu/drm/udl/udl_gem.c
-1
drivers/gpu/drm/udl/udl_gem.c
+3
include/drm/drm_pciids.h
+3
include/drm/drm_pciids.h
···
12
12
{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
13
13
{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
14
14
{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
15
+
{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
15
16
{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
16
17
{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
17
18
{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
19
+
{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
18
20
{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
19
21
{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
22
+
{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
20
23
{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
21
24
{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
22
25
{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \