tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

PCI: Remove MRRS modification from MPS setting code

Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has
massive negative ramifications on some devices. Without knowing which
devices have this issue, do not modify from the default value when
walking the PCI-E bus in pcie_bus_safe mode. Also, make pcie_bus_safe
the default procedure.

Tested-by: Sven Schnelle <svens@stackframe.org>
Tested-by: Simon Kirby <sim@hostway.ca>
Tested-by: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Reported-and-tested-by: Eric Dumazet <eric.dumazet@gmail.com>
Reported-and-tested-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
References: https://bugzilla.kernel.org/show_bug.cgi?id=42162
Signed-off-by: Jon Mason <mason@myri.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Jon Mason and committed by
Linus Torvalds ed2888e9 5307f6d5

+23 -20
+1 -1
drivers/pci/pci.c
··· 77 77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 78 78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 79 79 80 - enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; 80 + enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; 81 81 82 82 /* 83 83 * The default CLS is used if arch didn't set CLS explicitly and not
+22 -19
drivers/pci/probe.c
··· 1396 1396 1397 1397 static void pcie_write_mrrs(struct pci_dev *dev, int mps) 1398 1398 { 1399 - int rc, mrrs; 1399 + int rc, mrrs, dev_mpss; 1400 1400 1401 - if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1402 - int dev_mpss = 128 << dev->pcie_mpss; 1401 + /* In the "safe" case, do not configure the MRRS. There appear to be 1402 + * issues with setting MRRS to 0 on a number of devices. 1403 + */ 1403 1404 1404 - /* For Max performance, the MRRS must be set to the largest 1405 - * supported value. However, it cannot be configured larger 1406 - * than the MPS the device or the bus can support. This assumes 1407 - * that the largest MRRS available on the device cannot be 1408 - * smaller than the device MPSS. 1409 - */ 1410 - mrrs = mps < dev_mpss ? mps : dev_mpss; 1411 - } else 1412 - /* In the "safe" case, configure the MRRS for fairness on the 1413 - * bus by making all devices have the same size 1414 - */ 1415 - mrrs = mps; 1405 + if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 1406 + return; 1416 1407 1408 + dev_mpss = 128 << dev->pcie_mpss; 1409 + 1410 + /* For Max performance, the MRRS must be set to the largest supported 1411 + * value. However, it cannot be configured larger than the MPS the 1412 + * device or the bus can support. This assumes that the largest MRRS 1413 + * available on the device cannot be smaller than the device MPSS. 1414 + */ 1415 + mrrs = min(mps, dev_mpss); 1417 1416 1418 1417 /* MRRS is a R/W register. Invalid values can be written, but a 1419 - * subsiquent read will verify if the value is acceptable or not. 1418 + * subsequent read will verify if the value is acceptable or not. 1420 1419 * If the MRRS value provided is not acceptable (e.g., too large), 1421 1420 * shrink the value until it is acceptable to the HW. 1422 1421 */ 1423 1422 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 1423 + dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value" 1424 + " to %d. If any issues are encountered, please try " 1425 + "running with pci=pcie_bus_safe\n", mrrs); 1424 1426 rc = pcie_set_readrq(dev, mrrs); 1425 1427 if (rc) 1426 - dev_err(&dev->dev, "Failed attempting to set the MRRS\n"); 1428 + dev_err(&dev->dev, 1429 + "Failed attempting to set the MRRS\n"); 1427 1430 1428 1431 mrrs /= 2; 1429 1432 } ··· 1439 1436 if (!pci_is_pcie(dev)) 1440 1437 return 0; 1441 1438 1442 - dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1439 + dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1443 1440 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1444 1441 1445 1442 pcie_write_mps(dev, mps); 1446 1443 pcie_write_mrrs(dev, mps); 1447 1444 1448 - dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1445 + dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1449 1446 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1450 1447 1451 1448 return 0;