Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-fixes-2017-01-05' of git://anongit.freedesktop.org/git/drm-intel
Pull i915 drm fixes from Jani Nikula:
"Here's a bunch of drm/i915 fixes for v4.10-rc3. It includes GVT-g
fixes.
My new year's resolution is to start using signed tags for pulls. If
that feels like a déjà vu, it's ((new year's) resolution), not (new
(year's resolution))"
[ Taking this directly from Jani because Dave Airlie is only partially
connected right now. - Linus ]
* tag 'drm-intel-fixes-2017-01-05' of git://anongit.freedesktop.org/git/drm-intel:
drm/i915: Prevent timeline updates whilst performing reset
drm/i915: Silence allocation failure during sg_trim()
drm/i915: Don't clflush before release phys object
drm/i915: Fix oops in overlay due to frontbuffer tracking
drm/i915: Fix oopses in the overlay code due to i915_gem_active stuff
drm/i915: Initialize overlay->last_flip properly
drm/i915: Move the min_pixclk[] handling to the end of readout
drm/i915: Force VDD off on the new power seqeuencer before starting to use it
drm/i915/gvt: fix typo in cfg_space range check
drm/i915/gvt: fix an issue in emulating cfg space PCI_COMMAND
drm/i915/gvt/kvmgt: trival: code cleanup
drm/i915/gvt/kvmgt: prevent double-release of vgpu
drm/i915/gvt/kvmgt: check returned slot for gfn
drm/i915/gvt/kvmgt: dereference the pointer within lock
drm/i915/gvt: reset the GGTT entry when vGPU created
drm/i915/gvt: fix an error in opregion handling
+191
-46
+2
-2
drivers/gpu/drm/i915/gvt/cfg_space.c
+2
-2
drivers/gpu/drm/i915/gvt/cfg_space.c
···
123
123
u8 changed = old ^ new;
124
124
int ret;
125
125
126
+
memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);
126
127
if (!(changed & PCI_COMMAND_MEMORY))
127
128
return 0;
128
129
···
143
142
return ret;
144
143
}
145
144
146
-
memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);
147
145
return 0;
148
146
}
149
147
···
240
240
if (WARN_ON(bytes > 4))
241
241
return -EINVAL;
242
242
243
-
if (WARN_ON(offset + bytes >= INTEL_GVT_MAX_CFG_SPACE_SZ))
243
+
if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
244
244
return -EINVAL;
245
245
246
246
/* First check if it's PCI_COMMAND */
+55
drivers/gpu/drm/i915/gvt/gtt.c
+55
drivers/gpu/drm/i915/gvt/gtt.c
···
1998
1998
INIT_LIST_HEAD(>t->oos_page_list_head);
1999
1999
INIT_LIST_HEAD(>t->post_shadow_list_head);
2000
2000
2001
+
intel_vgpu_reset_ggtt(vgpu);
2002
+
2001
2003
ggtt_mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_GGTT,
2002
2004
NULL, 1, 0);
2003
2005
if (IS_ERR(ggtt_mm)) {
···
2208
2206
int intel_gvt_init_gtt(struct intel_gvt *gvt)
2209
2207
{
2210
2208
int ret;
2209
+
void *page_addr;
2211
2210
2212
2211
gvt_dbg_core("init gtt\n");
2213
2212
···
2219
2216
gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
2220
2217
} else {
2221
2218
return -ENODEV;
2219
+
}
2220
+
2221
+
gvt->gtt.scratch_ggtt_page =
2222
+
alloc_page(GFP_KERNEL | GFP_ATOMIC | __GFP_ZERO);
2223
+
if (!gvt->gtt.scratch_ggtt_page) {
2224
+
gvt_err("fail to allocate scratch ggtt page\n");
2225
+
return -ENOMEM;
2226
+
}
2227
+
2228
+
page_addr = page_address(gvt->gtt.scratch_ggtt_page);
2229
+
2230
+
gvt->gtt.scratch_ggtt_mfn =
2231
+
intel_gvt_hypervisor_virt_to_mfn(page_addr);
2232
+
if (gvt->gtt.scratch_ggtt_mfn == INTEL_GVT_INVALID_ADDR) {
2233
+
gvt_err("fail to translate scratch ggtt page\n");
2234
+
__free_page(gvt->gtt.scratch_ggtt_page);
2235
+
return -EFAULT;
2222
2236
}
2223
2237
2224
2238
if (enable_out_of_sync) {
···
2259
2239
*/
2260
2240
void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2261
2241
{
2242
+
__free_page(gvt->gtt.scratch_ggtt_page);
2243
+
2262
2244
if (enable_out_of_sync)
2263
2245
clean_spt_oos(gvt);
2246
+
}
2247
+
2248
+
/**
2249
+
* intel_vgpu_reset_ggtt - reset the GGTT entry
2250
+
* @vgpu: a vGPU
2251
+
*
2252
+
* This function is called at the vGPU create stage
2253
+
* to reset all the GGTT entries.
2254
+
*
2255
+
*/
2256
+
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
2257
+
{
2258
+
struct intel_gvt *gvt = vgpu->gvt;
2259
+
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2260
+
u32 index;
2261
+
u32 offset;
2262
+
u32 num_entries;
2263
+
struct intel_gvt_gtt_entry e;
2264
+
2265
+
memset(&e, 0, sizeof(struct intel_gvt_gtt_entry));
2266
+
e.type = GTT_TYPE_GGTT_PTE;
2267
+
ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn);
2268
+
e.val64 |= _PAGE_PRESENT;
2269
+
2270
+
index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2271
+
num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2272
+
for (offset = 0; offset < num_entries; offset++)
2273
+
ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
2274
+
2275
+
index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2276
+
num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2277
+
for (offset = 0; offset < num_entries; offset++)
2278
+
ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
2264
2279
}
+4
drivers/gpu/drm/i915/gvt/gtt.h
+4
drivers/gpu/drm/i915/gvt/gtt.h
···
81
81
struct list_head oos_page_use_list_head;
82
82
struct list_head oos_page_free_list_head;
83
83
struct list_head mm_lru_list_head;
84
+
85
+
struct page *scratch_ggtt_page;
86
+
unsigned long scratch_ggtt_mfn;
84
87
};
85
88
86
89
enum {
···
205
202
206
203
extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
207
204
extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
205
+
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu);
208
206
209
207
extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
210
208
extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
+1
drivers/gpu/drm/i915/gvt/gvt.h
+1
drivers/gpu/drm/i915/gvt/gvt.h
+37
-11
drivers/gpu/drm/i915/gvt/kvmgt.c
+37
-11
drivers/gpu/drm/i915/gvt/kvmgt.c
···
114
114
static kvm_pfn_t gvt_cache_find(struct intel_vgpu *vgpu, gfn_t gfn)
115
115
{
116
116
struct gvt_dma *entry;
117
+
kvm_pfn_t pfn;
117
118
118
119
mutex_lock(&vgpu->vdev.cache_lock);
119
-
entry = __gvt_cache_find(vgpu, gfn);
120
-
mutex_unlock(&vgpu->vdev.cache_lock);
121
120
122
-
return entry == NULL ? 0 : entry->pfn;
121
+
entry = __gvt_cache_find(vgpu, gfn);
122
+
pfn = (entry == NULL) ? 0 : entry->pfn;
123
+
124
+
mutex_unlock(&vgpu->vdev.cache_lock);
125
+
return pfn;
123
126
}
124
127
125
128
static void gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, kvm_pfn_t pfn)
···
500
497
goto undo_iommu;
501
498
}
502
499
503
-
return kvmgt_guest_init(mdev);
500
+
ret = kvmgt_guest_init(mdev);
501
+
if (ret)
502
+
goto undo_group;
503
+
504
+
atomic_set(&vgpu->vdev.released, 0);
505
+
return ret;
506
+
507
+
undo_group:
508
+
vfio_unregister_notifier(&mdev->dev, VFIO_GROUP_NOTIFY,
509
+
&vgpu->vdev.group_notifier);
504
510
505
511
undo_iommu:
506
512
vfio_unregister_notifier(&mdev->dev, VFIO_IOMMU_NOTIFY,
···
521
509
static void __intel_vgpu_release(struct intel_vgpu *vgpu)
522
510
{
523
511
struct kvmgt_guest_info *info;
512
+
int ret;
524
513
525
514
if (!handle_valid(vgpu->handle))
526
515
return;
527
516
528
-
vfio_unregister_notifier(&vgpu->vdev.mdev->dev, VFIO_IOMMU_NOTIFY,
517
+
if (atomic_cmpxchg(&vgpu->vdev.released, 0, 1))
518
+
return;
519
+
520
+
ret = vfio_unregister_notifier(&vgpu->vdev.mdev->dev, VFIO_IOMMU_NOTIFY,
529
521
&vgpu->vdev.iommu_notifier);
530
-
vfio_unregister_notifier(&vgpu->vdev.mdev->dev, VFIO_GROUP_NOTIFY,
522
+
WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret);
523
+
524
+
ret = vfio_unregister_notifier(&vgpu->vdev.mdev->dev, VFIO_GROUP_NOTIFY,
531
525
&vgpu->vdev.group_notifier);
526
+
WARN(ret, "vfio_unregister_notifier for group failed: %d\n", ret);
532
527
533
528
info = (struct kvmgt_guest_info *)vgpu->handle;
534
529
kvmgt_guest_exit(info);
530
+
531
+
vgpu->vdev.kvm = NULL;
535
532
vgpu->handle = 0;
536
533
}
537
534
···
555
534
{
556
535
struct intel_vgpu *vgpu = container_of(work, struct intel_vgpu,
557
536
vdev.release_work);
537
+
558
538
__intel_vgpu_release(vgpu);
559
539
}
560
540
···
1156
1134
1157
1135
idx = srcu_read_lock(&kvm->srcu);
1158
1136
slot = gfn_to_memslot(kvm, gfn);
1137
+
if (!slot) {
1138
+
srcu_read_unlock(&kvm->srcu, idx);
1139
+
return -EINVAL;
1140
+
}
1159
1141
1160
1142
spin_lock(&kvm->mmu_lock);
1161
1143
···
1190
1164
1191
1165
idx = srcu_read_lock(&kvm->srcu);
1192
1166
slot = gfn_to_memslot(kvm, gfn);
1167
+
if (!slot) {
1168
+
srcu_read_unlock(&kvm->srcu, idx);
1169
+
return -EINVAL;
1170
+
}
1193
1171
1194
1172
spin_lock(&kvm->mmu_lock);
1195
1173
···
1341
1311
1342
1312
static bool kvmgt_guest_exit(struct kvmgt_guest_info *info)
1343
1313
{
1344
-
struct intel_vgpu *vgpu;
1345
-
1346
1314
if (!info) {
1347
1315
gvt_err("kvmgt_guest_info invalid\n");
1348
1316
return false;
1349
1317
}
1350
1318
1351
-
vgpu = info->vgpu;
1352
-
1353
1319
kvm_page_track_unregister_notifier(info->kvm, &info->track_node);
1354
1320
kvmgt_protect_table_destroy(info);
1355
-
gvt_cache_destroy(vgpu);
1321
+
gvt_cache_destroy(info->vgpu);
1356
1322
vfree(info);
1357
1323
1358
1324
return true;
+1
-1
drivers/gpu/drm/i915/gvt/opregion.c
+1
-1
drivers/gpu/drm/i915/gvt/opregion.c
···
65
65
int i, ret;
66
66
67
67
for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) {
68
-
mfn = intel_gvt_hypervisor_virt_to_mfn(vgpu_opregion(vgpu)
68
+
mfn = intel_gvt_hypervisor_virt_to_mfn(vgpu_opregion(vgpu)->va
69
69
+ i * PAGE_SIZE);
70
70
if (mfn == INTEL_GVT_INVALID_ADDR) {
71
71
gvt_err("fail to get MFN from VA\n");
+16
-6
drivers/gpu/drm/i915/i915_gem.c
+16
-6
drivers/gpu/drm/i915/i915_gem.c
···
244
244
245
245
static void
246
246
__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
247
-
struct sg_table *pages)
247
+
struct sg_table *pages,
248
+
bool needs_clflush)
248
249
{
249
250
GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
250
251
251
252
if (obj->mm.madv == I915_MADV_DONTNEED)
252
253
obj->mm.dirty = false;
253
254
254
-
if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
255
+
if (needs_clflush &&
256
+
(obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
255
257
!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
256
258
drm_clflush_sg(pages);
257
259
···
265
263
i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
266
264
struct sg_table *pages)
267
265
{
268
-
__i915_gem_object_release_shmem(obj, pages);
266
+
__i915_gem_object_release_shmem(obj, pages, false);
269
267
270
268
if (obj->mm.dirty) {
271
269
struct address_space *mapping = obj->base.filp->f_mapping;
···
2233
2231
struct sgt_iter sgt_iter;
2234
2232
struct page *page;
2235
2233
2236
-
__i915_gem_object_release_shmem(obj, pages);
2234
+
__i915_gem_object_release_shmem(obj, pages, true);
2237
2235
2238
2236
i915_gem_gtt_finish_pages(obj, pages);
2239
2237
···
2324
2322
if (orig_st->nents == orig_st->orig_nents)
2325
2323
return;
2326
2324
2327
-
if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL))
2325
+
if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2328
2326
return;
2329
2327
2330
2328
new_sg = new_st.sgl;
···
2730
2728
struct drm_i915_gem_request *request;
2731
2729
struct i915_gem_context *incomplete_ctx;
2732
2730
struct intel_timeline *timeline;
2731
+
unsigned long flags;
2733
2732
bool ring_hung;
2734
2733
2735
2734
if (engine->irq_seqno_barrier)
···
2766
2763
if (i915_gem_context_is_default(incomplete_ctx))
2767
2764
return;
2768
2765
2766
+
timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2767
+
2768
+
spin_lock_irqsave(&engine->timeline->lock, flags);
2769
+
spin_lock(&timeline->lock);
2770
+
2769
2771
list_for_each_entry_continue(request, &engine->timeline->requests, link)
2770
2772
if (request->ctx == incomplete_ctx)
2771
2773
reset_request(request);
2772
2774
2773
-
timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2774
2775
list_for_each_entry(request, &timeline->requests, link)
2775
2776
reset_request(request);
2777
+
2778
+
spin_unlock(&timeline->lock);
2779
+
spin_unlock_irqrestore(&engine->timeline->lock, flags);
2776
2780
}
2777
2781
2778
2782
void i915_gem_reset(struct drm_i915_private *dev_priv)
+19
drivers/gpu/drm/i915/i915_gem_request.h
+19
drivers/gpu/drm/i915/i915_gem_request.h
···
413
413
rcu_assign_pointer(active->request, request);
414
414
}
415
415
416
+
/**
417
+
* i915_gem_active_set_retire_fn - updates the retirement callback
418
+
* @active - the active tracker
419
+
* @fn - the routine called when the request is retired
420
+
* @mutex - struct_mutex used to guard retirements
421
+
*
422
+
* i915_gem_active_set_retire_fn() updates the function pointer that
423
+
* is called when the final request associated with the @active tracker
424
+
* is retired.
425
+
*/
426
+
static inline void
427
+
i915_gem_active_set_retire_fn(struct i915_gem_active *active,
428
+
i915_gem_retire_fn fn,
429
+
struct mutex *mutex)
430
+
{
431
+
lockdep_assert_held(mutex);
432
+
active->retire = fn ?: i915_gem_retire_noop;
433
+
}
434
+
416
435
static inline struct drm_i915_gem_request *
417
436
__i915_gem_active_peek(const struct i915_gem_active *active)
418
437
{
+16
-16
drivers/gpu/drm/i915/intel_display.c
+16
-16
drivers/gpu/drm/i915/intel_display.c
···
16791
16791
16792
16792
for_each_intel_crtc(dev, crtc) {
16793
16793
struct intel_crtc_state *crtc_state = crtc->config;
16794
-
int pixclk = 0;
16795
16794
16796
16795
__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16797
16796
memset(crtc_state, 0, sizeof(*crtc_state));
···
16802
16803
crtc->base.enabled = crtc_state->base.enable;
16803
16804
crtc->active = crtc_state->base.active;
16804
16805
16805
-
if (crtc_state->base.active) {
16806
+
if (crtc_state->base.active)
16806
16807
dev_priv->active_crtcs |= 1 << crtc->pipe;
16807
-
16808
-
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16809
-
pixclk = ilk_pipe_pixel_rate(crtc_state);
16810
-
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16811
-
pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16812
-
else
16813
-
WARN_ON(dev_priv->display.modeset_calc_cdclk);
16814
-
16815
-
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16816
-
if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16817
-
pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16818
-
}
16819
-
16820
-
dev_priv->min_pixclk[crtc->pipe] = pixclk;
16821
16808
16822
16809
readout_plane_state(crtc);
16823
16810
···
16877
16892
}
16878
16893
16879
16894
for_each_intel_crtc(dev, crtc) {
16895
+
int pixclk = 0;
16896
+
16880
16897
crtc->base.hwmode = crtc->config->base.adjusted_mode;
16881
16898
16882
16899
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
···
16906
16919
*/
16907
16920
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16908
16921
16922
+
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16923
+
pixclk = ilk_pipe_pixel_rate(crtc->config);
16924
+
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16925
+
pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16926
+
else
16927
+
WARN_ON(dev_priv->display.modeset_calc_cdclk);
16928
+
16929
+
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16930
+
if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16931
+
pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16932
+
16909
16933
drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16910
16934
update_scanline_offset(crtc);
16911
16935
}
16936
+
16937
+
dev_priv->min_pixclk[crtc->pipe] = pixclk;
16912
16938
16913
16939
intel_pipe_config_sanity_check(dev_priv, crtc->config);
16914
16940
}
+34
-7
drivers/gpu/drm/i915/intel_dp.c
+34
-7
drivers/gpu/drm/i915/intel_dp.c
···
355
355
struct intel_dp *intel_dp);
356
356
static void
357
357
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
358
-
struct intel_dp *intel_dp);
358
+
struct intel_dp *intel_dp,
359
+
bool force_disable_vdd);
359
360
static void
360
361
intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
361
362
···
517
516
518
517
/* init power sequencer on this pipe and port */
519
518
intel_dp_init_panel_power_sequencer(dev, intel_dp);
520
-
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
519
+
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
521
520
522
521
/*
523
522
* Even vdd force doesn't work until we've made
···
554
553
* Only the HW needs to be reprogrammed, the SW state is fixed and
555
554
* has been setup during connector init.
556
555
*/
557
-
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
556
+
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
558
557
559
558
return 0;
560
559
}
···
637
636
port_name(port), pipe_name(intel_dp->pps_pipe));
638
637
639
638
intel_dp_init_panel_power_sequencer(dev, intel_dp);
640
-
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
639
+
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
641
640
}
642
641
643
642
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
···
2913
2912
2914
2913
/* init power sequencer on this pipe and port */
2915
2914
intel_dp_init_panel_power_sequencer(dev, intel_dp);
2916
-
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2915
+
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2917
2916
}
2918
2917
2919
2918
static void vlv_pre_enable_dp(struct intel_encoder *encoder,
···
5056
5055
5057
5056
static void
5058
5057
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5059
-
struct intel_dp *intel_dp)
5058
+
struct intel_dp *intel_dp,
5059
+
bool force_disable_vdd)
5060
5060
{
5061
5061
struct drm_i915_private *dev_priv = to_i915(dev);
5062
5062
u32 pp_on, pp_off, pp_div, port_sel = 0;
···
5069
5067
lockdep_assert_held(&dev_priv->pps_mutex);
5070
5068
5071
5069
intel_pps_get_registers(dev_priv, intel_dp, ®s);
5070
+
5071
+
/*
5072
+
* On some VLV machines the BIOS can leave the VDD
5073
+
* enabled even on power seqeuencers which aren't
5074
+
* hooked up to any port. This would mess up the
5075
+
* power domain tracking the first time we pick
5076
+
* one of these power sequencers for use since
5077
+
* edp_panel_vdd_on() would notice that the VDD was
5078
+
* already on and therefore wouldn't grab the power
5079
+
* domain reference. Disable VDD first to avoid this.
5080
+
* This also avoids spuriously turning the VDD on as
5081
+
* soon as the new power seqeuencer gets initialized.
5082
+
*/
5083
+
if (force_disable_vdd) {
5084
+
u32 pp = ironlake_get_pp_control(intel_dp);
5085
+
5086
+
WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5087
+
5088
+
if (pp & EDP_FORCE_VDD)
5089
+
DRM_DEBUG_KMS("VDD already on, disabling first\n");
5090
+
5091
+
pp &= ~EDP_FORCE_VDD;
5092
+
5093
+
I915_WRITE(regs.pp_ctrl, pp);
5094
+
}
5072
5095
5073
5096
pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5074
5097
(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
···
5149
5122
vlv_initial_power_sequencer_setup(intel_dp);
5150
5123
} else {
5151
5124
intel_dp_init_panel_power_sequencer(dev, intel_dp);
5152
-
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5125
+
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5153
5126
}
5154
5127
}
5155
5128
+6
-3
drivers/gpu/drm/i915/intel_overlay.c
+6
-3
drivers/gpu/drm/i915/intel_overlay.c
···
216
216
{
217
217
GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
218
218
&overlay->i915->drm.struct_mutex));
219
-
overlay->last_flip.retire = retire;
219
+
i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
220
+
&overlay->i915->drm.struct_mutex);
220
221
i915_gem_active_set(&overlay->last_flip, req);
221
222
i915_add_request(req);
222
223
}
···
840
839
if (ret)
841
840
goto out_unpin;
842
841
843
-
i915_gem_track_fb(overlay->vma->obj, new_bo,
844
-
INTEL_FRONTBUFFER_OVERLAY(pipe));
842
+
i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
843
+
vma->obj, INTEL_FRONTBUFFER_OVERLAY(pipe));
845
844
846
845
overlay->old_vma = overlay->vma;
847
846
overlay->vma = vma;
···
1430
1429
overlay->brightness = -19;
1431
1430
overlay->contrast = 75;
1432
1431
overlay->saturation = 146;
1432
+
1433
+
init_request_active(&overlay->last_flip, NULL);
1433
1434
1434
1435
regs = intel_overlay_map_regs(overlay);
1435
1436
if (!regs)