tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'spi-fix-v6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
"Two device specific fixes here, one avoiding glitches on chip select
with the STM32 driver and one for incorrectly configured clocks on the
Microchip QSPI controller"

* tag 'spi-fix-v6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: microchip-core-qspi: fix setting spi bus clock rate
spi: stm32: enable controller before asserting CS

Linus Torvalds ed44935c 99dff484

+3 -12
+1
drivers/spi/spi-microchip-core-qspi.c
··· 283 283 } 284 284 285 285 control = readl_relaxed(qspi->regs + REG_CONTROL); 286 + control &= ~CONTROL_CLKRATE_MASK; 286 287 control |= baud_rate_val << CONTROL_CLKRATE_SHIFT; 287 288 writel_relaxed(control, qspi->regs + REG_CONTROL); 288 289 control = readl_relaxed(qspi->regs + REG_CONTROL);
+2 -12
drivers/spi/spi-stm32.c
··· 1016 1016 static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id) 1017 1017 { 1018 1018 struct spi_controller *ctrl = dev_id; 1019 - struct stm32_spi *spi = spi_controller_get_devdata(ctrl); 1020 1019 1021 1020 spi_finalize_current_transfer(ctrl); 1022 - stm32fx_spi_disable(spi); 1023 1021 1024 1022 return IRQ_HANDLED; 1025 1023 } ··· 1185 1187 ~clrb) | setb, 1186 1188 spi->base + spi->cfg->regs->cpol.reg); 1187 1189 1190 + stm32_spi_enable(spi); 1191 + 1188 1192 spin_unlock_irqrestore(&spi->lock, flags); 1189 1193 1190 1194 return 0; ··· 1204 1204 1205 1205 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { 1206 1206 spi_finalize_current_transfer(spi->ctrl); 1207 - stm32fx_spi_disable(spi); 1208 1207 } 1209 1208 } 1210 1209 ··· 1218 1219 struct stm32_spi *spi = data; 1219 1220 1220 1221 spi_finalize_current_transfer(spi->ctrl); 1221 - spi->cfg->disable(spi); 1222 1222 } 1223 1223 1224 1224 /** ··· 1305 1307 1306 1308 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2); 1307 1309 1308 - stm32_spi_enable(spi); 1309 - 1310 1310 /* starting data transfer when buffer is loaded */ 1311 1311 if (spi->tx_buf) 1312 1312 spi->cfg->write_tx(spi); ··· 1341 1345 1342 1346 spin_lock_irqsave(&spi->lock, flags); 1343 1347 1344 - stm32_spi_enable(spi); 1345 - 1346 1348 /* Be sure to have data in fifo before starting data transfer */ 1347 1349 if (spi->tx_buf) 1348 1350 stm32h7_spi_write_txfifo(spi); ··· 1372 1378 */ 1373 1379 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE); 1374 1380 } 1375 - 1376 - stm32_spi_enable(spi); 1377 1381 } 1378 1382 1379 1383 /** ··· 1404 1412 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE; 1405 1413 1406 1414 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier); 1407 - 1408 - stm32_spi_enable(spi); 1409 1415 1410 1416 if (STM32_SPI_HOST_MODE(spi)) 1411 1417 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);