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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pwm: mediatek: Lock and cache clock rate
This simplifies error handling and reduces the amount of clk_get_rate()
calls.
While touching the clk handling also allocate the clock array as part of
driver data and lock the clock rate to ensure that the output doesn't
change unexpectedly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250725154506.2610172-17-u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
authored by
Uwe Kleine-König
and committed by
Uwe Kleine-König
ed5902a2
849b064c
+35
-28
+35
-28
drivers/pwm/pwm-mediatek.c
+35
-28
drivers/pwm/pwm-mediatek.c
···
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* @regs: base address of PWM chip
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* @clk_top: the top clock generator
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* @clk_main: the clock used by PWM core
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-
* @clk_pwms: the clock used by each PWM channel
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* @soc: pointer to chip's platform data
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* @clk_pwms: the clock and clkrate used by each PWM channel
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*/
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struct pwm_mediatek_chip {
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void __iomem *regs;
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struct clk *clk_top;
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struct clk *clk_main;
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-
struct clk **clk_pwms;
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const struct pwm_mediatek_of_data *soc;
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struct {
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struct clk *clk;
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unsigned long rate;
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} clk_pwms[];
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};
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static inline struct pwm_mediatek_chip *
···
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if (ret < 0)
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goto disable_clk_top;
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-
ret = clk_prepare_enable(pc->clk_pwms[hwpwm]);
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ret = clk_prepare_enable(pc->clk_pwms[hwpwm].clk);
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if (ret < 0)
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goto disable_clk_main;
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if (!pc->clk_pwms[hwpwm].rate) {
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pc->clk_pwms[hwpwm].rate = clk_get_rate(pc->clk_pwms[hwpwm].clk);
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+
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/*
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* With the clk running with not more than 1 GHz the
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* calculations in .apply() won't overflow.
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*/
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if (!pc->clk_pwms[hwpwm].rate ||
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pc->clk_pwms[hwpwm].rate > 1000000000) {
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ret = -EINVAL;
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goto disable_clk_hwpwm;
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}
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}
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return 0;
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disable_clk_hwpwm:
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clk_disable_unprepare(pc->clk_pwms[hwpwm].clk);
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disable_clk_main:
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clk_disable_unprepare(pc->clk_main);
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disable_clk_top:
···
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static void pwm_mediatek_clk_disable(struct pwm_mediatek_chip *pc,
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unsigned int hwpwm)
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{
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clk_disable_unprepare(pc->clk_pwms[hwpwm]);
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clk_disable_unprepare(pc->clk_pwms[hwpwm].clk);
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clk_disable_unprepare(pc->clk_main);
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clk_disable_unprepare(pc->clk_top);
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}
···
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if (ret < 0)
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return ret;
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clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
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/*
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* With the clk running with not more than 1 GHz the calculations below
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* won't overflow
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*/
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if (!clk_rate || clk_rate > 1000000000) {
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ret = -EINVAL;
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goto out;
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}
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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/* Make sure we use the bus clock and not the 26MHz clock */
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if (pc->soc->pwm_ck_26m_sel_reg)
···
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u32 clkdiv, cnt_period, cnt_duty;
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unsigned long clk_rate;
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clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
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if (!clk_rate) {
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ret = -EINVAL;
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goto out;
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-
}
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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state->enabled = true;
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state->polarity = PWM_POLARITY_NORMAL;
···
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state->enabled = false;
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}
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out:
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pwm_mediatek_clk_disable(pc, pwm->hwpwm);
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return ret;
···
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soc = of_device_get_match_data(&pdev->dev);
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-
chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
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chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms,
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sizeof(*pc) + soc->num_pwms * sizeof(*pc->clk_pwms));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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pc = to_pwm_mediatek_chip(chip);
···
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pc->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pc->regs))
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return PTR_ERR(pc->regs);
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-
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pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
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sizeof(*pc->clk_pwms), GFP_KERNEL);
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if (!pc->clk_pwms)
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return -ENOMEM;
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pc->clk_top = devm_clk_get(&pdev->dev, "top");
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if (IS_ERR(pc->clk_top))
···
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snprintf(name, sizeof(name), "pwm%d", i + 1);
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-
pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(pc->clk_pwms[i]))
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-
return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
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pc->clk_pwms[i].clk = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(pc->clk_pwms[i].clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i].clk),
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"Failed to get %s clock\n", name);
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+
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ret = devm_clk_rate_exclusive_get(&pdev->dev, pc->clk_pwms[i].clk);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"Failed to lock clock rate for %s\n", name);
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}
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ret = pwm_mediatek_init_used_clks(pc);