Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/xe: Promote struct xe_mmio definition to own file
We already have separate .c and .h files for xe_mmio functions,
time to introduce _types.h to follow what other components do.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com> #v1
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260203211240.745-3-michal.wajdeczko@intel.com
+66
-45
+1
-39
drivers/gpu/drm/xe/xe_device_types.h
+1
-39
drivers/gpu/drm/xe/xe_device_types.h
···
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#include "xe_lmtt_types.h"
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#include "xe_memirq_types.h"
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#include "xe_mert.h"
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#include "xe_mmio_types.h"
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#include "xe_oa_types.h"
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#include "xe_pagefault_types.h"
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#include "xe_platform_types.h"
···
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_Generic(tile__, \
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const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \
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struct xe_tile * : (tile__)->xe)
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-
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/**
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* struct xe_mmio - register mmio structure
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*
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* Represents an MMIO region that the CPU may use to access registers. A
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* region may share its IO map with other regions (e.g., all GTs within a
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* tile share the same map with their parent tile, but represent different
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* subregions of the overall IO space).
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*/
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struct xe_mmio {
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/** @tile: Backpointer to tile, used for tracing */
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struct xe_tile *tile;
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/** @regs: Map used to access registers. */
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void __iomem *regs;
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/**
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* @sriov_vf_gt: Backpointer to GT.
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*
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* This pointer is only set for GT MMIO regions and only when running
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* as an SRIOV VF structure
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*/
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struct xe_gt *sriov_vf_gt;
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/**
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* @regs_size: Length of the register region within the map.
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*
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* The size of the iomap set in *regs is generally larger than the
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* register mmio space since it includes unused regions and/or
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* non-register regions such as the GGTT PTEs.
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*/
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size_t regs_size;
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/** @adj_limit: adjust MMIO address if address is below this value */
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u32 adj_limit;
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/** @adj_offset: offset to add to MMIO address when adjusting */
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u32 adj_offset;
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};
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/**
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* struct xe_tile - hardware tile structure
-5
drivers/gpu/drm/xe/xe_gt_types.h
-5
drivers/gpu/drm/xe/xe_gt_types.h
···
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typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(XE_MAX_EU_FUSE_BITS)];
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typedef unsigned long xe_l3_bank_mask_t[BITS_TO_LONGS(XE_MAX_L3_BANK_MASK_BITS)];
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struct xe_mmio_range {
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u32 start;
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u32 end;
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};
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/*
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* The hardware has multiple kinds of multicast register ranges that need
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* special register steering (and future platforms are expected to add
+1
-1
drivers/gpu/drm/xe/xe_mmio.h
+1
-1
drivers/gpu/drm/xe/xe_mmio.h
+64
drivers/gpu/drm/xe/xe_mmio_types.h
+64
drivers/gpu/drm/xe/xe_mmio_types.h
···
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022-2026 Intel Corporation
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*/
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#ifndef _XE_MMIO_TYPES_H_
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#define _XE_MMIO_TYPES_H_
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#include <linux/types.h>
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struct xe_gt;
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struct xe_tile;
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/**
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* struct xe_mmio - register mmio structure
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*
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* Represents an MMIO region that the CPU may use to access registers. A
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* region may share its IO map with other regions (e.g., all GTs within a
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* tile share the same map with their parent tile, but represent different
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* subregions of the overall IO space).
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*/
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struct xe_mmio {
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/** @tile: Backpointer to tile, used for tracing */
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struct xe_tile *tile;
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/** @regs: Map used to access registers. */
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void __iomem *regs;
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/**
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* @sriov_vf_gt: Backpointer to GT.
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*
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* This pointer is only set for GT MMIO regions and only when running
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* as an SRIOV VF structure
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*/
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struct xe_gt *sriov_vf_gt;
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/**
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* @regs_size: Length of the register region within the map.
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*
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* The size of the iomap set in *regs is generally larger than the
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* register mmio space since it includes unused regions and/or
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* non-register regions such as the GGTT PTEs.
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*/
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size_t regs_size;
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/** @adj_limit: adjust MMIO address if address is below this value */
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u32 adj_limit;
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/** @adj_offset: offset to add to MMIO address when adjusting */
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u32 adj_offset;
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};
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/**
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* struct xe_mmio_range - register range structure
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*
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* @start: first register offset in the range.
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* @end: last register offset in the range.
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*/
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struct xe_mmio_range {
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u32 start;
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u32 end;
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};
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#endif