Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"For this kernel cycle I managed an immutable branch for the PEF2256
WAN framer that has some pin control portions. It already landed in
your tree through the net pull request but here it is mentioned again.
The most interesting is perhaps the Samsung Exynos subdrivers for the
Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for
automotive. Along with the earlier merged Tesla FSD subdriver it shows
some of the versatile uses of the Samsung Exynos silicon. It is also
used in the latest version of Axis Communications ARTPEC chips so it
is a very widely deployed SoC family.
We also have the Intel Meteor Lake SoC which I think is for laptops.
It's a pretty interesting chip with Xe graphics and integrated PCH.
Core changes:
- A new PINCTRL_GROUP_DESC() infrastructure macro is added and used
in different drivers, generic group description struct group_desc
is now used all over the place.
New drivers:
- New driver for the Texas Instruments TPS6494 Power Management IC.
- New driver for the Lantic PEF2256 framer pin multiplexer. This IC
has some pins that can be reconfigured in different ways. The
actual driver comes on an immutable branch with the net WAN parts,
the IC is some latest-and-greatest serial line funnel for e.g.
wireless access points.
- New subdriver for the Samsung Exynos Auto V920 pin controller, used
for automotive applications.
- New subdriver for the Samsung "GS101" SoC pin controller, this is
the Google "Tensor" SoC used in the Google Pixel 6.
- New subdriver for the Intel Meteor Point SoC pin controller.
- New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS
pin controllers.
- New subdriver for the Qualcomm X1E80100 top level (TLMM) pin
controller.
- New subdriver for the Qualcomm SM4450 top level (TLMM) pin
controller.
- The "single" pin controller now supports the Texas Instruments
J7200 SoC.
Improvements:
- Intel has created a new (Intel-)generic pin controller driver that
is now used by all contemporary Intel platforms.
- Intel is now also making use of some cleanup helpers.
- Enble 910 Ohm bias in the Intel Tangier driver.
- The Samsung driver now suppors irq_set_affinity() in it's IRQ chip
giving support for non wake up external gpio interrupts"
* tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: samsung: constify iomem pointers
pinctrl: cy8c95x0: Cache muxed registers
dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp
pinctrl: qcom: lpass-lpi: remove duplicated include
dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent
dt-bindings: pinctrl: qcom: drop common properties
dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings
dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts
dt-bindings: pinctrl: qcom: create common LPASS LPI schema
pinctrl: qcom: sm4450: dd SM4450 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
dt-bindings: pinctrl: qcom,pmic-mpp: clean up example
pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support
pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins
pinctrl: renesas: rzg2l: Add output enable support
...
+8320
-1692
+1
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+1
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+4
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
+4
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 24
···
88
95
- compatible
89
96
- reg
90
97
91
-
additionalProperties: false
98
+
allOf:
99
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
100
+
101
+
unevaluatedProperties: false
92
102
93
103
examples:
94
104
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
···
26
26
interrupts:
27
27
maxItems: 1
28
28
29
-
interrupt-controller: true
30
-
"#interrupt-cells": true
31
-
gpio-controller: true
32
-
"#gpio-cells": true
33
-
gpio-ranges: true
34
-
wakeup-parent: true
35
-
36
29
gpio-reserved-ranges:
37
30
minItems: 1
38
31
maxItems: 27
···
93
100
- compatible
94
101
- reg
95
102
96
-
additionalProperties: false
103
+
unevaluatedProperties: false
97
104
98
105
examples:
99
106
- |
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
···
22
22
interrupts:
23
23
maxItems: 1
24
24
25
-
interrupt-controller: true
26
-
"#interrupt-cells": true
27
-
gpio-controller: true
28
-
"#gpio-cells": true
29
-
gpio-ranges: true
30
-
31
25
patternProperties:
32
26
"-state$":
33
27
oneOf:
···
94
100
- compatible
95
101
- reg
96
102
97
-
additionalProperties: false
103
+
unevaluatedProperties: false
98
104
99
105
examples:
100
106
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 35
···
96
103
- compatible
97
104
- reg
98
105
99
-
additionalProperties: false
106
+
unevaluatedProperties: false
100
107
101
108
examples:
102
109
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 33
···
90
97
- compatible
91
98
- reg
92
99
93
-
additionalProperties: false
100
+
unevaluatedProperties: false
94
101
95
102
examples:
96
103
- |
+75
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
+75
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SoC LPASS LPI TLMM Common Properties
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13
+
14
+
description:
15
+
Common properties for the Top Level Mode Multiplexer pin controllers in the
16
+
Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs.
17
+
18
+
properties:
19
+
gpio-controller: true
20
+
21
+
"#gpio-cells":
22
+
description:
23
+
Specifying the pin number and flags, as defined in
24
+
include/dt-bindings/gpio/gpio.h
25
+
const: 2
26
+
27
+
gpio-ranges:
28
+
maxItems: 1
29
+
30
+
required:
31
+
- gpio-controller
32
+
- "#gpio-cells"
33
+
- gpio-ranges
34
+
35
+
allOf:
36
+
- $ref: pinctrl.yaml#
37
+
38
+
additionalProperties: true
39
+
40
+
$defs:
41
+
qcom-tlmm-state:
42
+
properties:
43
+
drive-strength:
44
+
enum: [2, 4, 6, 8, 10, 12, 14, 16]
45
+
default: 2
46
+
description:
47
+
Selects the drive strength for the specified pins, in mA.
48
+
49
+
slew-rate:
50
+
enum: [0, 1, 2, 3]
51
+
default: 0
52
+
description: |
53
+
0: No adjustments
54
+
1: Higher Slew rate (faster edges)
55
+
2: Lower Slew rate (slower edges)
56
+
3: Reserved (No adjustments)
57
+
58
+
bias-bus-hold: true
59
+
bias-pull-down: true
60
+
bias-pull-up: true
61
+
bias-disable: true
62
+
input-enable: true
63
+
output-high: true
64
+
output-low: true
65
+
66
+
required:
67
+
- pins
68
+
- function
69
+
70
+
allOf:
71
+
- $ref: pincfg-node.yaml#
72
+
- $ref: pinmux-node.yaml#
73
+
74
+
additionalProperties: true
75
+
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
28
gpio-reserved-ranges: true
32
-
"#gpio-cells": true
33
-
gpio-ranges: true
34
-
wakeup-parent: true
35
-
36
-
required:
37
-
- compatible
38
-
- reg
39
-
40
-
additionalProperties: false
41
29
42
30
patternProperties:
43
31
"-state$":
···
97
109
98
110
required:
99
111
- pins
112
+
113
+
required:
114
+
- compatible
115
+
- reg
116
+
117
+
unevaluatedProperties: false
100
118
101
119
examples:
102
120
- |
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
'#interrupt-cells': true
28
-
gpio-controller: true
29
-
'#gpio-cells': true
30
-
gpio-ranges: true
31
-
32
-
required:
33
-
- compatible
34
-
- reg
35
-
36
-
additionalProperties: false
37
-
38
26
patternProperties:
39
27
"-state$":
40
28
oneOf:
···
61
73
62
74
required:
63
75
- pins
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
81
+
unevaluatedProperties: false
64
82
65
83
examples:
66
84
- |
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
32
26
gpio-reserved-ranges:
33
27
maxItems: 1
34
28
···
76
82
- compatible
77
83
- reg
78
84
79
-
additionalProperties: false
85
+
unevaluatedProperties: false
80
86
81
87
examples:
82
88
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 86
···
85
92
- compatible
86
93
- reg
87
94
88
-
additionalProperties: false
95
+
unevaluatedProperties: false
89
96
90
97
examples:
91
98
- |
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
28
gpio-reserved-ranges: true
32
-
"#gpio-cells": true
33
-
gpio-ranges: true
34
-
wakeup-parent: true
35
-
36
-
required:
37
-
- compatible
38
-
- reg
39
-
40
-
additionalProperties: false
41
29
42
30
patternProperties:
43
31
"-state$":
···
95
107
96
108
required:
97
109
- pins
110
+
111
+
required:
112
+
- compatible
113
+
- reg
114
+
115
+
unevaluatedProperties: false
98
116
99
117
examples:
100
118
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 61
···
107
114
- compatible
108
115
- reg
109
116
110
-
additionalProperties: false
117
+
unevaluatedProperties: false
111
118
112
119
examples:
113
120
- |
+1
-6
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+1
-6
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
···
22
22
interrupts:
23
23
maxItems: 1
24
24
25
-
interrupt-controller: true
26
-
"#interrupt-cells": true
27
-
gpio-controller: true
28
25
gpio-reserved-ranges: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
26
32
27
patternProperties:
33
28
"-state$":
···
112
117
- compatible
113
118
- reg
114
119
115
-
additionalProperties: false
120
+
unevaluatedProperties: false
116
121
117
122
examples:
118
123
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 76
···
101
108
- compatible
102
109
- reg
103
110
104
-
additionalProperties: false
111
+
unevaluatedProperties: false
105
112
106
113
examples:
107
114
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 73
···
117
124
- compatible
118
125
- reg
119
126
120
-
additionalProperties: false
127
+
unevaluatedProperties: false
121
128
122
129
examples:
123
130
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 73
···
97
104
- compatible
98
105
- reg
99
106
100
-
additionalProperties: false
107
+
unevaluatedProperties: false
101
108
102
109
examples:
103
110
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
-
"#gpio-cells": true
32
-
gpio-ranges: true
33
-
wakeup-parent: true
34
-
35
28
gpio-reserved-ranges:
36
29
minItems: 1
37
30
maxItems: 73
···
107
114
- compatible
108
115
- reg
109
116
110
-
additionalProperties: false
117
+
unevaluatedProperties: false
111
118
112
119
examples:
113
120
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 75
···
126
133
- compatible
127
134
- reg
128
135
129
-
additionalProperties: false
136
+
unevaluatedProperties: false
130
137
131
138
examples:
132
139
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
32
-
33
26
gpio-reserved-ranges:
34
27
minItems: 1
35
28
maxItems: 75
···
111
118
- compatible
112
119
- reg
113
120
114
-
additionalProperties: false
121
+
unevaluatedProperties: false
115
122
116
123
examples:
117
124
- |
+31
-25
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
+31
-25
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
···
158
158
- |
159
159
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
160
160
161
-
pm8841_mpp: mpps@a000 {
162
-
compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
163
-
reg = <0xa000 0>;
164
-
gpio-controller;
165
-
#gpio-cells = <2>;
166
-
gpio-ranges = <&pm8841_mpp 0 0 4>;
167
-
gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL",
168
-
"BT_LED_CTRL", "GPIO-F";
169
-
interrupt-controller;
170
-
#interrupt-cells = <2>;
161
+
pmic {
162
+
#address-cells = <1>;
163
+
#size-cells = <0>;
171
164
172
-
pinctrl-names = "default";
173
-
pinctrl-0 = <&pm8841_default>;
165
+
pm8841_mpp: mpps@a000 {
166
+
compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
167
+
reg = <0xa000>;
174
168
175
-
mpp1-state {
176
-
pins = "mpp1";
177
-
function = "digital";
178
-
input-enable;
179
-
power-source = <PM8841_MPP_S3>;
180
-
};
169
+
gpio-controller;
170
+
#gpio-cells = <2>;
171
+
gpio-ranges = <&pm8841_mpp 0 0 4>;
172
+
gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL",
173
+
"BT_LED_CTRL", "GPIO-F";
174
+
interrupt-controller;
175
+
#interrupt-cells = <2>;
181
176
182
-
default-state {
183
-
gpio-pins {
184
-
pins = "mpp1", "mpp2", "mpp3", "mpp4";
185
-
function = "digital";
186
-
input-enable;
187
-
power-source = <PM8841_MPP_S3>;
177
+
pinctrl-names = "default";
178
+
pinctrl-0 = <&pm8841_default>;
179
+
180
+
mpp1-state {
181
+
pins = "mpp1";
182
+
function = "digital";
183
+
input-enable;
184
+
power-source = <PM8841_MPP_S3>;
185
+
};
186
+
187
+
default-state {
188
+
gpio-pins {
189
+
pins = "mpp1", "mpp2", "mpp3", "mpp4";
190
+
function = "digital";
191
+
input-enable;
192
+
power-source = <PM8841_MPP_S3>;
193
+
};
194
+
};
188
195
};
189
-
};
190
196
};
191
197
...
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml
···
22
22
interrupts:
23
23
maxItems: 1
24
24
25
-
interrupt-controller: true
26
-
"#interrupt-cells": true
27
-
gpio-controller: true
28
-
"#gpio-cells": true
29
-
gpio-ranges: true
30
-
wakeup-parent: true
31
-
32
25
patternProperties:
33
26
"-state$":
34
27
oneOf:
···
85
92
- compatible
86
93
- reg
87
94
88
-
additionalProperties: false
95
+
unevaluatedProperties: false
89
96
90
97
examples:
91
98
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml
···
29
29
interrupts:
30
30
maxItems: 1
31
31
32
-
interrupt-controller: true
33
-
"#interrupt-cells": true
34
-
gpio-controller: true
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
-
wakeup-parent: true
38
-
39
32
gpio-reserved-ranges:
40
33
minItems: 1
41
34
maxItems: 60
···
123
130
- compatible
124
131
- reg
125
132
126
-
additionalProperties: false
133
+
unevaluatedProperties: false
127
134
128
135
examples:
129
136
- |
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml
···
23
23
reg:
24
24
maxItems: 1
25
25
26
-
interrupts: true
27
-
interrupt-controller: true
28
-
"#interrupt-cells": true
29
-
gpio-controller: true
26
+
interrupts:
27
+
maxItems: 1
30
28
31
29
gpio-reserved-ranges:
32
30
minItems: 1
···
32
34
33
35
gpio-line-names:
34
36
maxItems: 151
35
-
36
-
"#gpio-cells": true
37
-
gpio-ranges: true
38
-
wakeup-parent: true
39
37
40
38
patternProperties:
41
39
"-state$":
···
95
101
- compatible
96
102
- reg
97
103
98
-
additionalProperties: false
104
+
unevaluatedProperties: false
99
105
100
106
examples:
101
107
- |
+8
-13
Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
+8
-13
Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
···
22
22
reg:
23
23
maxItems: 1
24
24
25
-
interrupts: true
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
wakeup-parent: true
25
+
interrupts:
26
+
maxItems: 1
32
27
33
28
gpio-reserved-ranges:
34
29
minItems: 1
···
31
36
32
37
gpio-line-names:
33
38
maxItems: 148
34
-
35
-
required:
36
-
- compatible
37
-
- reg
38
-
39
-
additionalProperties: false
40
39
41
40
patternProperties:
42
41
"-state$":
···
96
107
97
108
required:
98
109
- pins
110
+
111
+
required:
112
+
- compatible
113
+
- reg
114
+
115
+
unevaluatedProperties: false
99
116
100
117
examples:
101
118
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
···
29
29
interrupts:
30
30
maxItems: 1
31
31
32
-
interrupt-controller: true
33
-
"#interrupt-cells": true
34
-
gpio-controller: true
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
-
wakeup-parent: true
38
-
39
32
gpio-reserved-ranges:
40
33
minItems: 1
41
34
maxItems: 60
···
105
112
- reg
106
113
- reg-names
107
114
108
-
additionalProperties: false
115
+
unevaluatedProperties: false
109
116
110
117
examples:
111
118
- |
+6
-43
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+6
-43
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
···
20
20
reg:
21
21
maxItems: 2
22
22
23
-
gpio-controller: true
24
-
25
-
"#gpio-cells":
26
-
description: Specifying the pin number and flags, as defined in
27
-
include/dt-bindings/gpio/gpio.h
28
-
const: 2
29
-
30
-
gpio-ranges:
31
-
maxItems: 1
32
-
33
23
patternProperties:
34
24
"-state$":
35
25
oneOf:
···
35
45
description:
36
46
Pinctrl node's client devices use subnodes for desired pin configuration.
37
47
Client device subnodes use below standard properties.
38
-
$ref: /schemas/pinctrl/pincfg-node.yaml
48
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
49
+
unevaluatedProperties: false
39
50
40
51
properties:
41
52
pins:
···
59
68
Specify the alternative function to be configured for the specified
60
69
pins.
61
70
62
-
drive-strength:
63
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
64
-
default: 2
65
-
description:
66
-
Selects the drive strength for the specified pins, in mA.
67
-
68
-
slew-rate:
69
-
enum: [0, 1, 2, 3]
70
-
default: 0
71
-
description: |
72
-
0: No adjustments
73
-
1: Higher Slew rate (faster edges)
74
-
2: Lower Slew rate (slower edges)
75
-
3: Reserved (No adjustments)
76
-
77
-
bias-pull-down: true
78
-
bias-pull-up: true
79
-
bias-bus-hold: true
80
-
bias-disable: true
81
-
output-high: true
82
-
output-low: true
83
-
84
-
required:
85
-
- pins
86
-
- function
87
-
88
-
additionalProperties: false
89
-
90
71
required:
91
72
- compatible
92
73
- reg
93
-
- gpio-controller
94
-
- "#gpio-cells"
95
-
- gpio-ranges
96
74
97
-
additionalProperties: false
75
+
allOf:
76
+
- $ref: qcom,lpass-lpi-common.yaml#
77
+
78
+
unevaluatedProperties: false
98
79
99
80
examples:
100
81
- |
+1
-27
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
+1
-27
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
···
23
23
description: Specifies the TLMM summary IRQ
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
28
-
'#interrupt-cells':
29
-
description:
30
-
Specifies the PIN numbers and Flags, as defined in defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
34
-
gpio-controller: true
35
-
36
-
'#gpio-cells':
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
43
-
44
26
gpio-reserved-ranges:
45
27
minItems: 1
46
28
maxItems: 88
47
29
48
30
gpio-line-names:
49
31
maxItems: 175
50
-
51
-
wakeup-parent: true
52
32
53
33
patternProperties:
54
34
"-state$":
···
104
124
required:
105
125
- compatible
106
126
- reg
107
-
- interrupts
108
-
- interrupt-controller
109
-
- '#interrupt-cells'
110
-
- gpio-controller
111
-
- '#gpio-cells'
112
-
- gpio-ranges
113
127
114
-
additionalProperties: false
128
+
unevaluatedProperties: false
115
129
116
130
examples:
117
131
- |
+7
-13
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml
+7
-13
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml
···
31
31
interrupts:
32
32
maxItems: 1
33
33
34
-
interrupt-controller: true
35
-
'#interrupt-cells': true
36
-
gpio-controller: true
37
34
gpio-reserved-ranges: true
38
-
'#gpio-cells': true
39
-
gpio-ranges: true
40
-
wakeup-parent: true
41
-
42
-
required:
43
-
- compatible
44
-
- reg
45
-
- reg-names
46
-
47
-
additionalProperties: false
48
35
49
36
patternProperties:
50
37
"-state$":
···
92
105
93
106
required:
94
107
- pins
108
+
109
+
required:
110
+
- compatible
111
+
- reg
112
+
- reg-names
113
+
114
+
unevaluatedProperties: false
95
115
96
116
examples:
97
117
- |
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
···
32
32
- const: core
33
33
- const: audio
34
34
35
-
gpio-controller: true
36
-
37
-
"#gpio-cells":
38
-
description: Specifying the pin number and flags, as defined in
39
-
include/dt-bindings/gpio/gpio.h
40
-
const: 2
41
-
42
-
gpio-ranges:
43
-
maxItems: 1
44
-
45
35
patternProperties:
46
36
"-state$":
47
37
oneOf:
···
47
57
description:
48
58
Pinctrl node's client devices use subnodes for desired pin configuration.
49
59
Client device subnodes use below standard properties.
50
-
$ref: /schemas/pinctrl/pincfg-node.yaml
60
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
61
+
unevaluatedProperties: false
51
62
52
63
properties:
53
64
pins:
···
70
79
Specify the alternative function to be configured for the specified
71
80
pins.
72
81
73
-
drive-strength:
74
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
75
-
default: 2
76
-
description:
77
-
Selects the drive strength for the specified pins, in mA.
78
-
79
-
slew-rate:
80
-
enum: [0, 1, 2, 3]
81
-
default: 0
82
-
description: |
83
-
0: No adjustments
84
-
1: Higher Slew rate (faster edges)
85
-
2: Lower Slew rate (slower edges)
86
-
3: Reserved (No adjustments)
87
-
88
-
bias-bus-hold: true
89
-
bias-pull-down: true
90
-
bias-pull-up: true
91
-
bias-disable: true
92
-
input-enable: true
93
-
output-high: true
94
-
output-low: true
95
-
96
-
required:
97
-
- pins
98
-
- function
99
-
100
-
additionalProperties: false
101
-
102
82
allOf:
103
-
- $ref: pinctrl.yaml#
83
+
- $ref: qcom,lpass-lpi-common.yaml#
104
84
105
85
required:
106
86
- compatible
107
87
- reg
108
88
- clocks
109
89
- clock-names
110
-
- gpio-controller
111
-
- "#gpio-cells"
112
-
- gpio-ranges
113
90
114
-
additionalProperties: false
91
+
unevaluatedProperties: false
115
92
116
93
examples:
117
94
- |
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
28
gpio-reserved-ranges: true
32
-
"#gpio-cells": true
33
-
gpio-ranges: true
34
-
wakeup-parent: true
35
-
36
-
required:
37
-
- compatible
38
-
- reg
39
-
40
-
additionalProperties: false
41
29
42
30
patternProperties:
43
31
"-state$":
···
95
107
96
108
required:
97
109
- pins
110
+
111
+
required:
112
+
- compatible
113
+
- reg
114
+
115
+
unevaluatedProperties: false
98
116
99
117
examples:
100
118
- |
+1
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml
+1
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml
···
34
34
interrupts:
35
35
maxItems: 1
36
36
37
-
interrupt-controller: true
38
-
"#interrupt-cells": true
39
-
gpio-controller: true
40
-
41
37
gpio-reserved-ranges:
42
38
minItems: 1
43
39
maxItems: 57
44
40
45
41
gpio-line-names:
46
42
maxItems: 114
47
-
48
-
"#gpio-cells": true
49
-
gpio-ranges: true
50
-
wakeup-parent: true
51
43
52
44
patternProperties:
53
45
"-state$":
···
122
130
- compatible
123
131
- reg
124
132
125
-
additionalProperties: false
133
+
unevaluatedProperties: false
126
134
127
135
examples:
128
136
- |
+6
-13
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml
+6
-13
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
28
gpio-reserved-ranges:
32
29
minItems: 1
33
30
maxItems: 75
34
-
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
-
wakeup-parent: true
38
-
39
-
required:
40
-
- compatible
41
-
- reg
42
-
43
-
additionalProperties: false
44
31
45
32
patternProperties:
46
33
"-state$":
···
84
97
85
98
required:
86
99
- pins
100
+
101
+
required:
102
+
- compatible
103
+
- reg
104
+
105
+
unevaluatedProperties: false
87
106
88
107
examples:
89
108
- |
+1
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
+1
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
···
26
26
interrupts:
27
27
maxItems: 1
28
28
29
-
interrupt-controller: true
30
-
"#interrupt-cells": true
31
-
gpio-controller: true
32
-
33
29
gpio-reserved-ranges:
34
30
minItems: 1
35
31
maxItems: 75
36
32
37
33
gpio-line-names:
38
34
maxItems: 150
39
-
40
-
"#gpio-cells": true
41
-
gpio-ranges: true
42
-
wakeup-parent: true
43
35
44
36
patternProperties:
45
37
"-state$":
···
102
110
- compatible
103
111
- reg
104
112
105
-
additionalProperties: false
113
+
unevaluatedProperties: false
106
114
107
115
examples:
108
116
- |
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
···
23
23
interrupts:
24
24
maxItems: 1
25
25
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
29
-
"#gpio-cells": true
30
-
gpio-ranges: true
31
-
32
26
gpio-reserved-ranges:
33
27
maxItems: 1
34
28
···
96
102
- compatible
97
103
- reg
98
104
99
-
additionalProperties: false
105
+
unevaluatedProperties: false
100
106
101
107
examples:
102
108
- |
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml
···
22
22
interrupts:
23
23
maxItems: 1
24
24
25
-
interrupt-controller: true
26
-
"#interrupt-cells": true
27
-
gpio-controller: true
28
-
"#gpio-cells": true
29
-
gpio-ranges: true
30
-
31
25
gpio-reserved-ranges:
32
26
maxItems: 1
33
27
···
116
122
- compatible
117
123
- reg
118
124
119
-
additionalProperties: false
125
+
unevaluatedProperties: false
120
126
121
127
examples:
122
128
- |
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml
···
22
22
reg:
23
23
maxItems: 1
24
24
25
-
interrupts: true
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
25
+
interrupts:
26
+
maxItems: 1
29
27
30
28
gpio-reserved-ranges:
31
29
minItems: 1
···
31
33
32
34
gpio-line-names:
33
35
maxItems: 133
34
-
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
-
wakeup-parent: true
38
36
39
37
patternProperties:
40
38
"-state$":
···
94
100
- compatible
95
101
- reg
96
102
97
-
additionalProperties: false
103
+
unevaluatedProperties: false
98
104
99
105
examples:
100
106
- |
+151
Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml
+151
Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. SM4450 TLMM block
8
+
9
+
maintainers:
10
+
- Tengfei Fan <quic_tengfan@quicinc.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,sm4450-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts: true
26
+
interrupt-controller: true
27
+
"#interrupt-cells": true
28
+
gpio-controller: true
29
+
30
+
gpio-reserved-ranges:
31
+
minItems: 1
32
+
maxItems: 68
33
+
34
+
gpio-line-names:
35
+
maxItems: 136
36
+
37
+
"#gpio-cells": true
38
+
gpio-ranges: true
39
+
wakeup-parent: true
40
+
41
+
patternProperties:
42
+
"-state$":
43
+
oneOf:
44
+
- $ref: "#/$defs/qcom-sm4450-tlmm-state"
45
+
- patternProperties:
46
+
"-pins$":
47
+
$ref: "#/$defs/qcom-sm4450-tlmm-state"
48
+
additionalProperties: false
49
+
50
+
$defs:
51
+
qcom-sm4450-tlmm-state:
52
+
type: object
53
+
description:
54
+
Pinctrl node's client devices use subnodes for desired pin configuration.
55
+
Client device subnodes use below standard properties.
56
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57
+
unevaluatedProperties: false
58
+
59
+
properties:
60
+
pins:
61
+
description:
62
+
List of gpio pins affected by the properties specified in this
63
+
subnode.
64
+
items:
65
+
oneOf:
66
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
67
+
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
68
+
minItems: 1
69
+
maxItems: 36
70
+
71
+
function:
72
+
description:
73
+
Specify the alternative function to be configured for the specified
74
+
pins.
75
+
enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
76
+
atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
77
+
atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
78
+
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
79
+
cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
80
+
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
81
+
dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
82
+
jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
83
+
mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
84
+
mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
85
+
mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
86
+
phase_flag0, phase_flag1, phase_flag10, phase_flag11,
87
+
phase_flag12, phase_flag13, phase_flag14, phase_flag15,
88
+
phase_flag16, phase_flag17, phase_flag18, phase_flag19,
89
+
phase_flag2, phase_flag20, phase_flag21, phase_flag22,
90
+
phase_flag23, phase_flag24, phase_flag25, phase_flag26,
91
+
phase_flag27, phase_flag28, phase_flag29, phase_flag3,
92
+
phase_flag30, phase_flag31, phase_flag4, phase_flag5,
93
+
phase_flag6, phase_flag7, phase_flag8, phase_flag9,
94
+
pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
95
+
prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
96
+
qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
97
+
qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
98
+
qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
99
+
qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
100
+
qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
101
+
qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
102
+
qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
103
+
qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
104
+
tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
105
+
tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
106
+
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
107
+
uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
108
+
vsense_trigger ]
109
+
110
+
required:
111
+
- pins
112
+
113
+
required:
114
+
- compatible
115
+
- reg
116
+
117
+
additionalProperties: false
118
+
119
+
examples:
120
+
- |
121
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
122
+
tlmm: pinctrl@f100000 {
123
+
compatible = "qcom,sm4450-tlmm";
124
+
reg = <0x0f100000 0x300000>;
125
+
gpio-controller;
126
+
#gpio-cells = <2>;
127
+
gpio-ranges = <&tlmm 0 0 137>;
128
+
interrupt-controller;
129
+
#interrupt-cells = <2>;
130
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
131
+
132
+
gpio-wo-state {
133
+
pins = "gpio1";
134
+
function = "gpio";
135
+
};
136
+
137
+
uart-w-state {
138
+
rx-pins {
139
+
pins = "gpio23";
140
+
function = "qup1_se2";
141
+
bias-pull-up;
142
+
};
143
+
144
+
tx-pins {
145
+
pins = "gpio22";
146
+
function = "qup1_se2";
147
+
bias-disable;
148
+
};
149
+
};
150
+
};
151
+
...
+4
-44
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
+4
-44
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
···
31
31
items:
32
32
- const: audio
33
33
34
-
gpio-controller: true
35
-
36
-
"#gpio-cells":
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
43
-
44
34
patternProperties:
45
35
"-state$":
46
36
oneOf:
···
46
56
description:
47
57
Pinctrl node's client devices use subnodes for desired pin configuration.
48
58
Client device subnodes use below standard properties.
49
-
$ref: /schemas/pinctrl/pincfg-node.yaml
59
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
60
+
unevaluatedProperties: false
50
61
51
62
properties:
52
63
pins:
···
66
75
Specify the alternative function to be configured for the specified
67
76
pins.
68
77
69
-
drive-strength:
70
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
71
-
default: 2
72
-
description:
73
-
Selects the drive strength for the specified pins, in mA.
74
-
75
-
slew-rate:
76
-
enum: [0, 1, 2, 3]
77
-
default: 0
78
-
description: |
79
-
0: No adjustments
80
-
1: Higher Slew rate (faster edges)
81
-
2: Lower Slew rate (slower edges)
82
-
3: Reserved (No adjustments)
83
-
84
-
bias-bus-hold: true
85
-
bias-pull-down: true
86
-
bias-pull-up: true
87
-
bias-disable: true
88
-
input-enable: true
89
-
output-high: true
90
-
output-low: true
91
-
92
-
required:
93
-
- pins
94
-
- function
95
-
96
-
additionalProperties: false
97
78
98
79
allOf:
99
-
- $ref: pinctrl.yaml#
80
+
- $ref: qcom,lpass-lpi-common.yaml#
100
81
101
82
required:
102
83
- compatible
103
84
- reg
104
85
- clocks
105
86
- clock-names
106
-
- gpio-controller
107
-
- "#gpio-cells"
108
-
- gpio-ranges
109
87
110
-
additionalProperties: false
88
+
unevaluatedProperties: false
111
89
112
90
examples:
113
91
- |
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml
+1
-7
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml
···
29
29
interrupts:
30
30
maxItems: 1
31
31
32
-
interrupt-controller: true
33
-
"#interrupt-cells": true
34
-
gpio-controller: true
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
32
gpio-reserved-ranges: true
38
-
wakeup-parent: true
39
33
40
34
patternProperties:
41
35
"-state$":
···
91
97
- reg
92
98
- reg-names
93
99
94
-
additionalProperties: false
100
+
unevaluatedProperties: false
95
101
96
102
examples:
97
103
- |
+7
-13
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml
+7
-13
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml
···
30
30
interrupts:
31
31
maxItems: 1
32
32
33
-
interrupt-controller: true
34
-
"#interrupt-cells": true
35
-
gpio-controller: true
36
33
gpio-reserved-ranges: true
37
-
"#gpio-cells": true
38
-
gpio-ranges: true
39
-
wakeup-parent: true
40
-
41
-
required:
42
-
- compatible
43
-
- reg
44
-
- reg-names
45
-
46
-
additionalProperties: false
47
34
48
35
patternProperties:
49
36
"-state$":
···
91
104
92
105
required:
93
106
- pins
107
+
108
+
required:
109
+
- compatible
110
+
- reg
111
+
- reg-names
112
+
113
+
unevaluatedProperties: false
94
114
95
115
examples:
96
116
- |
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml
···
26
26
minItems: 9
27
27
maxItems: 9
28
28
29
-
interrupt-controller: true
30
-
"#interrupt-cells": true
31
-
gpio-controller: true
32
-
33
29
gpio-reserved-ranges:
34
30
minItems: 1
35
31
maxItems: 78
36
32
37
33
gpio-line-names:
38
34
maxItems: 156
39
-
40
-
"#gpio-cells": true
41
-
gpio-ranges: true
42
-
wakeup-parent: true
43
-
44
-
required:
45
-
- compatible
46
-
- reg
47
-
48
-
additionalProperties: false
49
35
50
36
patternProperties:
51
37
"-state$":
···
97
111
98
112
required:
99
113
- pins
114
+
115
+
required:
116
+
- compatible
117
+
- reg
118
+
119
+
unevaluatedProperties: false
100
120
101
121
examples:
102
122
- |
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
+6
-12
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
28
gpio-reserved-ranges: true
32
-
"#gpio-cells": true
33
-
gpio-ranges: true
34
-
wakeup-parent: true
35
-
36
-
required:
37
-
- compatible
38
-
- reg
39
-
40
-
additionalProperties: false
41
29
42
30
patternProperties:
43
31
"-state$":
···
100
112
101
113
required:
102
114
- pins
115
+
116
+
required:
117
+
- compatible
118
+
- reg
119
+
120
+
unevaluatedProperties: false
103
121
104
122
examples:
105
123
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml
···
32
32
interrupts:
33
33
maxItems: 1
34
34
35
-
interrupt-controller: true
36
-
"#interrupt-cells": true
37
-
gpio-controller: true
38
-
"#gpio-cells": true
39
-
gpio-ranges: true
40
-
wakeup-parent: true
41
-
42
35
gpio-reserved-ranges:
43
36
minItems: 1
44
37
maxItems: 60
···
104
111
- reg
105
112
- reg-names
106
113
107
-
additionalProperties: false
114
+
unevaluatedProperties: false
108
115
109
116
examples:
110
117
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
···
30
30
interrupts:
31
31
maxItems: 1
32
32
33
-
interrupt-controller: true
34
-
"#interrupt-cells": true
35
-
gpio-controller: true
36
-
"#gpio-cells": true
37
-
gpio-ranges: true
38
-
wakeup-parent: true
39
-
40
33
gpio-reserved-ranges:
41
34
minItems: 1
42
35
maxItems: 88
···
106
113
- reg
107
114
- reg-names
108
115
109
-
additionalProperties: false
116
+
unevaluatedProperties: false
110
117
111
118
examples:
112
119
- |
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
···
30
30
- const: core
31
31
- const: audio
32
32
33
-
gpio-controller: true
34
-
35
-
"#gpio-cells":
36
-
description: Specifying the pin number and flags, as defined in
37
-
include/dt-bindings/gpio/gpio.h
38
-
const: 2
39
-
40
-
gpio-ranges:
41
-
maxItems: 1
42
-
43
33
patternProperties:
44
34
"-state$":
45
35
oneOf:
···
45
55
description:
46
56
Pinctrl node's client devices use subnodes for desired pin configuration.
47
57
Client device subnodes use below standard properties.
48
-
$ref: /schemas/pinctrl/pincfg-node.yaml
58
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
59
+
unevaluatedProperties: false
49
60
50
61
properties:
51
62
pins:
···
69
78
Specify the alternative function to be configured for the specified
70
79
pins.
71
80
72
-
drive-strength:
73
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
74
-
default: 2
75
-
description:
76
-
Selects the drive strength for the specified pins, in mA.
77
-
78
-
slew-rate:
79
-
enum: [0, 1, 2, 3]
80
-
default: 0
81
-
description: |
82
-
0: No adjustments
83
-
1: Higher Slew rate (faster edges)
84
-
2: Lower Slew rate (slower edges)
85
-
3: Reserved (No adjustments)
86
-
87
-
bias-pull-down: true
88
-
bias-pull-up: true
89
-
bias-bus-hold: true
90
-
bias-disable: true
91
-
input-enable: true
92
-
output-high: true
93
-
output-low: true
94
-
95
-
required:
96
-
- pins
97
-
- function
98
-
99
-
additionalProperties: false
100
-
101
81
allOf:
102
-
- $ref: pinctrl.yaml#
82
+
- $ref: qcom,lpass-lpi-common.yaml#
103
83
104
84
required:
105
85
- compatible
106
86
- reg
107
87
- clocks
108
88
- clock-names
109
-
- gpio-controller
110
-
- "#gpio-cells"
111
-
- gpio-ranges
112
89
113
-
additionalProperties: false
90
+
unevaluatedProperties: false
114
91
115
92
examples:
116
93
- |
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
+1
-8
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
···
28
28
interrupts:
29
29
maxItems: 1
30
30
31
-
interrupt-controller: true
32
-
"#interrupt-cells": true
33
-
gpio-controller: true
34
-
"#gpio-cells": true
35
-
gpio-ranges: true
36
-
wakeup-parent: true
37
-
38
31
gpio-reserved-ranges:
39
32
minItems: 1
40
33
maxItems: 90
···
99
106
- reg
100
107
- reg-names
101
108
102
-
additionalProperties: false
109
+
unevaluatedProperties: false
103
110
104
111
examples:
105
112
- |
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
···
33
33
- const: core
34
34
- const: audio
35
35
36
-
gpio-controller: true
37
-
38
-
"#gpio-cells":
39
-
description: Specifying the pin number and flags, as defined in
40
-
include/dt-bindings/gpio/gpio.h
41
-
const: 2
42
-
43
-
gpio-ranges:
44
-
maxItems: 1
45
-
46
36
patternProperties:
47
37
"-state$":
48
38
oneOf:
···
48
58
description:
49
59
Pinctrl node's client devices use subnodes for desired pin configuration.
50
60
Client device subnodes use below standard properties.
51
-
$ref: /schemas/pinctrl/pincfg-node.yaml
61
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
62
+
unevaluatedProperties: false
52
63
53
64
properties:
54
65
pins:
···
72
81
Specify the alternative function to be configured for the specified
73
82
pins.
74
83
75
-
drive-strength:
76
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
77
-
default: 2
78
-
description:
79
-
Selects the drive strength for the specified pins, in mA.
80
-
81
-
slew-rate:
82
-
enum: [0, 1, 2, 3]
83
-
default: 0
84
-
description: |
85
-
0: No adjustments
86
-
1: Higher Slew rate (faster edges)
87
-
2: Lower Slew rate (slower edges)
88
-
3: Reserved (No adjustments)
89
-
90
-
bias-bus-hold: true
91
-
bias-pull-down: true
92
-
bias-pull-up: true
93
-
bias-disable: true
94
-
input-enable: true
95
-
output-high: true
96
-
output-low: true
97
-
98
-
required:
99
-
- pins
100
-
- function
101
-
102
-
additionalProperties: false
103
-
104
84
allOf:
105
-
- $ref: pinctrl.yaml#
85
+
- $ref: qcom,lpass-lpi-common.yaml#
106
86
107
87
required:
108
88
- compatible
109
89
- reg
110
90
- clocks
111
91
- clock-names
112
-
- gpio-controller
113
-
- "#gpio-cells"
114
-
- gpio-ranges
115
92
116
-
additionalProperties: false
93
+
unevaluatedProperties: false
117
94
118
95
examples:
119
96
- |
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
-
32
28
gpio-reserved-ranges:
33
29
minItems: 1
34
30
maxItems: 102
35
31
36
32
gpio-line-names:
37
33
maxItems: 203
38
-
39
-
"#gpio-cells": true
40
-
gpio-ranges: true
41
-
wakeup-parent: true
42
-
43
-
required:
44
-
- compatible
45
-
- reg
46
-
47
-
additionalProperties: false
48
34
49
35
patternProperties:
50
36
"-state$":
···
93
107
94
108
required:
95
109
- pins
110
+
111
+
required:
112
+
- compatible
113
+
- reg
114
+
115
+
unevaluatedProperties: false
96
116
97
117
examples:
98
118
- |
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+4
-45
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
···
32
32
- const: core
33
33
- const: audio
34
34
35
-
gpio-controller: true
36
-
37
-
"#gpio-cells":
38
-
description: Specifying the pin number and flags, as defined in
39
-
include/dt-bindings/gpio/gpio.h
40
-
const: 2
41
-
42
-
gpio-ranges:
43
-
maxItems: 1
44
-
45
35
patternProperties:
46
36
"-state$":
47
37
oneOf:
···
47
57
description:
48
58
Pinctrl node's client devices use subnodes for desired pin configuration.
49
59
Client device subnodes use below standard properties.
50
-
$ref: /schemas/pinctrl/pincfg-node.yaml
60
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
61
+
unevaluatedProperties: false
51
62
52
63
properties:
53
64
pins:
···
72
81
Specify the alternative function to be configured for the specified
73
82
pins.
74
83
75
-
drive-strength:
76
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
77
-
default: 2
78
-
description:
79
-
Selects the drive strength for the specified pins, in mA.
80
-
81
-
slew-rate:
82
-
enum: [0, 1, 2, 3]
83
-
default: 0
84
-
description: |
85
-
0: No adjustments
86
-
1: Higher Slew rate (faster edges)
87
-
2: Lower Slew rate (slower edges)
88
-
3: Reserved (No adjustments)
89
-
90
-
bias-bus-hold: true
91
-
bias-pull-down: true
92
-
bias-pull-up: true
93
-
bias-disable: true
94
-
input-enable: true
95
-
output-high: true
96
-
output-low: true
97
-
98
-
required:
99
-
- pins
100
-
- function
101
-
102
-
additionalProperties: false
103
-
104
84
allOf:
105
-
- $ref: pinctrl.yaml#
85
+
- $ref: qcom,lpass-lpi-common.yaml#
106
86
107
87
required:
108
88
- compatible
109
89
- reg
110
90
- clocks
111
91
- clock-names
112
-
- gpio-controller
113
-
- "#gpio-cells"
114
-
- gpio-ranges
115
92
116
-
additionalProperties: false
93
+
unevaluatedProperties: false
117
94
118
95
examples:
119
96
- |
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml
+6
-14
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml
···
25
25
interrupts:
26
26
maxItems: 1
27
27
28
-
interrupt-controller: true
29
-
"#interrupt-cells": true
30
-
gpio-controller: true
31
-
32
28
gpio-reserved-ranges:
33
29
minItems: 1
34
30
maxItems: 105
35
31
36
32
gpio-line-names:
37
33
maxItems: 210
38
-
39
-
"#gpio-cells": true
40
-
gpio-ranges: true
41
-
wakeup-parent: true
42
-
43
-
required:
44
-
- compatible
45
-
- reg
46
-
47
-
additionalProperties: false
48
34
49
35
patternProperties:
50
36
"-state$":
···
92
106
93
107
required:
94
108
- pins
109
+
110
+
required:
111
+
- compatible
112
+
- reg
113
+
114
+
unevaluatedProperties: false
95
115
96
116
examples:
97
117
- |
+9
-46
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
+9
-46
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
···
16
16
17
17
properties:
18
18
compatible:
19
-
const: qcom,sm8550-lpass-lpi-pinctrl
19
+
oneOf:
20
+
- const: qcom,sm8550-lpass-lpi-pinctrl
21
+
- items:
22
+
- const: qcom,x1e80100-lpass-lpi-pinctrl
23
+
- const: qcom,sm8550-lpass-lpi-pinctrl
20
24
21
25
reg:
22
26
items:
···
37
33
- const: core
38
34
- const: audio
39
35
40
-
gpio-controller: true
41
-
42
-
"#gpio-cells":
43
-
description: Specifying the pin number and flags, as defined in
44
-
include/dt-bindings/gpio/gpio.h
45
-
const: 2
46
-
47
-
gpio-ranges:
48
-
maxItems: 1
49
-
50
36
patternProperties:
51
37
"-state$":
52
38
oneOf:
···
52
58
description:
53
59
Pinctrl node's client devices use subnodes for desired pin configuration.
54
60
Client device subnodes use below standard properties.
55
-
$ref: /schemas/pinctrl/pincfg-node.yaml
61
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
62
+
unevaluatedProperties: false
56
63
57
64
properties:
58
65
pins:
···
76
81
Specify the alternative function to be configured for the specified
77
82
pins.
78
83
79
-
drive-strength:
80
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
81
-
default: 2
82
-
description:
83
-
Selects the drive strength for the specified pins, in mA.
84
-
85
-
slew-rate:
86
-
enum: [0, 1, 2, 3]
87
-
default: 0
88
-
description: |
89
-
0: No adjustments
90
-
1: Higher Slew rate (faster edges)
91
-
2: Lower Slew rate (slower edges)
92
-
3: Reserved (No adjustments)
93
-
94
-
bias-bus-hold: true
95
-
bias-pull-down: true
96
-
bias-pull-up: true
97
-
bias-disable: true
98
-
input-enable: true
99
-
output-high: true
100
-
output-low: true
101
-
102
-
required:
103
-
- pins
104
-
- function
105
-
106
-
additionalProperties: false
107
-
108
84
allOf:
109
-
- $ref: pinctrl.yaml#
85
+
- $ref: qcom,lpass-lpi-common.yaml#
110
86
111
87
required:
112
88
- compatible
113
89
- reg
114
90
- clocks
115
91
- clock-names
116
-
- gpio-controller
117
-
- "#gpio-cells"
118
-
- gpio-ranges
119
92
120
-
additionalProperties: false
93
+
unevaluatedProperties: false
121
94
122
95
examples:
123
96
- |
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml
+3
-9
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml
···
22
22
reg:
23
23
maxItems: 1
24
24
25
-
interrupts: true
26
-
interrupt-controller: true
27
-
"#interrupt-cells": true
28
-
gpio-controller: true
25
+
interrupts:
26
+
maxItems: 1
29
27
30
28
gpio-reserved-ranges:
31
29
minItems: 1
···
31
33
32
34
gpio-line-names:
33
35
maxItems: 210
34
-
35
-
"#gpio-cells": true
36
-
gpio-ranges: true
37
-
wakeup-parent: true
38
36
39
37
patternProperties:
40
38
"-state$":
···
111
117
- compatible
112
118
- reg
113
119
114
-
additionalProperties: false
120
+
unevaluatedProperties: false
115
121
116
122
examples:
117
123
- |
+107
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
+107
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8650 SoC LPASS LPI TLMM
8
+
9
+
maintainers:
10
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11
+
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
15
+
(LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
16
+
17
+
properties:
18
+
compatible:
19
+
const: qcom,sm8650-lpass-lpi-pinctrl
20
+
21
+
reg:
22
+
items:
23
+
- description: LPASS LPI TLMM Control and Status registers
24
+
25
+
clocks:
26
+
items:
27
+
- description: LPASS Core voting clock
28
+
- description: LPASS Audio voting clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: core
33
+
- const: audio
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-sm8650-lpass-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-sm8650-lpass-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-sm8650-lpass-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
60
+
61
+
function:
62
+
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
63
+
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
64
+
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
65
+
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
66
+
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
67
+
i2s4_data, i2s4_ws, qca_swr_clk, qca_swr_data, slimbus_clk,
68
+
slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data,
69
+
wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
70
+
description:
71
+
Specify the alternative function to be configured for the specified
72
+
pins.
73
+
74
+
allOf:
75
+
- $ref: qcom,lpass-lpi-common.yaml#
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
- clocks
81
+
- clock-names
82
+
83
+
unevaluatedProperties: false
84
+
85
+
examples:
86
+
- |
87
+
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
88
+
89
+
lpass_tlmm: pinctrl@6e80000 {
90
+
compatible = "qcom,sm8650-lpass-lpi-pinctrl";
91
+
reg = <0x06e80000 0x20000>;
92
+
93
+
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
94
+
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
95
+
clock-names = "core", "audio";
96
+
97
+
gpio-controller;
98
+
#gpio-cells = <2>;
99
+
gpio-ranges = <&lpass_tlmm 0 0 23>;
100
+
101
+
tx-swr-sleep-clk-state {
102
+
pins = "gpio0";
103
+
function = "swr_tx_clk";
104
+
drive-strength = <2>;
105
+
bias-pull-down;
106
+
};
107
+
};
+141
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml
+141
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. SM8650 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,sm8650-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 105
31
+
32
+
gpio-line-names:
33
+
maxItems: 210
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-sm8650-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-sm8650-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-sm8650-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
61
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
70
+
audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
71
+
cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
72
+
cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
73
+
coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete,
74
+
ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
75
+
ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1,
76
+
gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0,
77
+
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
78
+
i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
79
+
i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
80
+
i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c,
81
+
jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
82
+
mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0,
83
+
nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n,
84
+
pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
85
+
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
86
+
qdss_gpio, qlink_big_enable, qlink_big_request,
87
+
qlink_little_enable, qlink_little_request, qlink_wmss,
88
+
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0,
89
+
qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,
90
+
qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
91
+
qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41,
92
+
sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
93
+
tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
94
+
tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
95
+
tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk,
96
+
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
97
+
uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1,
98
+
vsense_trigger_mirnat ]
99
+
100
+
required:
101
+
- pins
102
+
103
+
required:
104
+
- compatible
105
+
- reg
106
+
107
+
unevaluatedProperties: false
108
+
109
+
examples:
110
+
- |
111
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
112
+
tlmm: pinctrl@f100000 {
113
+
compatible = "qcom,sm8650-tlmm";
114
+
reg = <0x0f100000 0x300000>;
115
+
gpio-controller;
116
+
#gpio-cells = <2>;
117
+
gpio-ranges = <&tlmm 0 0 211>;
118
+
interrupt-controller;
119
+
#interrupt-cells = <2>;
120
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
121
+
122
+
gpio-wo-state {
123
+
pins = "gpio1";
124
+
function = "gpio";
125
+
};
126
+
127
+
uart-w-state {
128
+
rx-pins {
129
+
pins = "gpio60";
130
+
function = "qup1_se7";
131
+
bias-pull-up;
132
+
};
133
+
134
+
tx-pins {
135
+
pins = "gpio61";
136
+
function = "qup1_se7";
137
+
bias-disable;
138
+
};
139
+
};
140
+
};
141
+
...
+137
Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml
+137
Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. X1E80100 TLMM block
8
+
9
+
maintainers:
10
+
- Rajendra Nayak <quic_rjendra@quicinc.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,x1e80100-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 119
31
+
32
+
gpio-line-names:
33
+
maxItems: 238
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-x1e80100-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-x1e80100-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-x1e80100-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
61
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
70
+
atest_char1, atest_char2, atest_char3, atest_usb,
71
+
audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
72
+
cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
73
+
cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
74
+
cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
75
+
ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
76
+
edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
77
+
eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
78
+
gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
79
+
i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
80
+
mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
81
+
mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
82
+
pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
83
+
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
84
+
qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
85
+
qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
86
+
qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
87
+
qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
88
+
qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
89
+
sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
90
+
tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
91
+
tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
92
+
tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
93
+
usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
94
+
usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
95
+
96
+
required:
97
+
- pins
98
+
99
+
required:
100
+
- compatible
101
+
- reg
102
+
103
+
unevaluatedProperties: false
104
+
105
+
examples:
106
+
- |
107
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
108
+
tlmm: pinctrl@f100000 {
109
+
compatible = "qcom,x1e80100-tlmm";
110
+
reg = <0x0f100000 0xf00000>;
111
+
gpio-controller;
112
+
#gpio-cells = <2>;
113
+
gpio-ranges = <&tlmm 0 0 239>;
114
+
interrupt-controller;
115
+
#interrupt-cells = <2>;
116
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
117
+
118
+
gpio-wo-state {
119
+
pins = "gpio1";
120
+
function = "gpio";
121
+
};
122
+
123
+
uart-w-state {
124
+
rx-pins {
125
+
pins = "gpio26";
126
+
function = "qup2_se7";
127
+
bias-pull-up;
128
+
};
129
+
130
+
tx-pins {
131
+
pins = "gpio27";
132
+
function = "qup2_se7";
133
+
bias-disable;
134
+
};
135
+
};
136
+
};
137
+
...
+1
-1
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
+30
-15
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+30
-15
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
···
28
28
29
29
properties:
30
30
compatible:
31
-
enum:
32
-
- samsung,s3c2410-wakeup-eint
33
-
- samsung,s3c2412-wakeup-eint
34
-
- samsung,s3c64xx-wakeup-eint
35
-
- samsung,s5pv210-wakeup-eint
36
-
- samsung,exynos4210-wakeup-eint
37
-
- samsung,exynos7-wakeup-eint
38
-
- samsung,exynos850-wakeup-eint
39
-
- samsung,exynosautov9-wakeup-eint
31
+
oneOf:
32
+
- enum:
33
+
- samsung,s3c2410-wakeup-eint
34
+
- samsung,s3c2412-wakeup-eint
35
+
- samsung,s3c64xx-wakeup-eint
36
+
- samsung,s5pv210-wakeup-eint
37
+
- samsung,exynos4210-wakeup-eint
38
+
- samsung,exynos7-wakeup-eint
39
+
- samsung,exynosautov920-wakeup-eint
40
+
- items:
41
+
- enum:
42
+
- samsung,exynos5433-wakeup-eint
43
+
- samsung,exynos7885-wakeup-eint
44
+
- samsung,exynos850-wakeup-eint
45
+
- const: samsung,exynos7-wakeup-eint
46
+
- items:
47
+
- enum:
48
+
- google,gs101-wakeup-eint
49
+
- samsung,exynosautov9-wakeup-eint
50
+
- const: samsung,exynos850-wakeup-eint
51
+
- const: samsung,exynos7-wakeup-eint
40
52
41
53
interrupts:
42
54
description:
···
91
79
- if:
92
80
properties:
93
81
compatible:
94
-
contains:
95
-
enum:
96
-
- samsung,s5pv210-wakeup-eint
97
-
- samsung,exynos4210-wakeup-eint
98
-
- samsung,exynos7-wakeup-eint
82
+
# Match without "contains", to skip newer variants which are still
83
+
# compatible with samsung,exynos7-wakeup-eint
84
+
enum:
85
+
- samsung,s5pv210-wakeup-eint
86
+
- samsung,exynos4210-wakeup-eint
87
+
- samsung,exynos5433-wakeup-eint
88
+
- samsung,exynos7-wakeup-eint
89
+
- samsung,exynos7885-wakeup-eint
99
90
then:
100
91
properties:
101
92
interrupts:
···
113
98
contains:
114
99
enum:
115
100
- samsung,exynos850-wakeup-eint
116
-
- samsung,exynosautov9-wakeup-eint
101
+
- samsung,exynosautov920-wakeup-eint
117
102
then:
118
103
properties:
119
104
interrupts: false
+4
-1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+4
-1
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
···
35
35
36
36
compatible:
37
37
enum:
38
+
- google,gs101-pinctrl
38
39
- samsung,s3c2412-pinctrl
39
40
- samsung,s3c2416-pinctrl
40
41
- samsung,s3c2440-pinctrl
···
54
53
- samsung,exynos7885-pinctrl
55
54
- samsung,exynos850-pinctrl
56
55
- samsung,exynosautov9-pinctrl
56
+
- samsung,exynosautov920-pinctrl
57
57
- tesla,fsd-pinctrl
58
58
59
59
interrupts:
···
315
313
pinctrl-0 = <&initial_alive>;
316
314
317
315
wakeup-interrupt-controller {
318
-
compatible = "samsung,exynos7-wakeup-eint";
316
+
compatible = "samsung,exynos5433-wakeup-eint",
317
+
"samsung,exynos7-wakeup-eint";
319
318
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
320
319
};
321
320
+1
-1
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
-1
MAINTAINERS
-1
MAINTAINERS
···
19288
19288
L: linux-samsung-soc@vger.kernel.org
19289
19289
S: Maintained
19290
19290
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
19291
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
19292
19291
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
19293
19292
F: Documentation/devicetree/bindings/clock/samsung,s3c*
19294
19293
F: drivers/clk/samsung/
+16
drivers/pinctrl/Kconfig
+16
drivers/pinctrl/Kconfig
···
484
484
depends on OF && ARC_PLAT_TB10X
485
485
select GPIOLIB
486
486
487
+
config PINCTRL_TPS6594
488
+
tristate "Pinctrl and GPIO driver for TI TPS6594 PMIC"
489
+
depends on OF && MFD_TPS6594
490
+
default MFD_TPS6594
491
+
select PINMUX
492
+
select GPIOLIB
493
+
select REGMAP
494
+
select GPIO_REGMAP
495
+
select GENERIC_PINCONF
496
+
help
497
+
Say Y to select the pinmuxing and GPIOs driver for the TPS6594
498
+
PMICs chip family.
499
+
500
+
This driver can also be built as a module
501
+
called tps6594-pinctrl.
502
+
487
503
config PINCTRL_ZYNQ
488
504
bool "Pinctrl driver for Xilinx Zynq"
489
505
depends on ARCH_ZYNQ
+1
drivers/pinctrl/Makefile
+1
drivers/pinctrl/Makefile
···
49
49
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
50
50
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
51
51
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
52
+
obj-$(CONFIG_PINCTRL_TPS6594) += pinctrl-tps6594.o
52
53
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
53
54
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
54
55
+2
-2
drivers/pinctrl/bcm/pinctrl-ns.c
+2
-2
drivers/pinctrl/bcm/pinctrl-ns.c
+27
-32
drivers/pinctrl/core.c
+27
-32
drivers/pinctrl/core.c
···
13
13
#define pr_fmt(fmt) "pinctrl core: " fmt
14
14
15
15
#include <linux/array_size.h>
16
+
#include <linux/cleanup.h>
16
17
#include <linux/debugfs.h>
17
18
#include <linux/device.h>
18
19
#include <linux/err.h>
···
24
23
#include <linux/seq_file.h>
25
24
#include <linux/slab.h>
26
25
26
+
#include <linux/gpio.h>
27
27
#include <linux/gpio/driver.h>
28
28
29
29
#include <linux/pinctrl/consumer.h>
30
30
#include <linux/pinctrl/devinfo.h>
31
31
#include <linux/pinctrl/machine.h>
32
32
#include <linux/pinctrl/pinctrl.h>
33
-
34
-
#ifdef CONFIG_GPIOLIB
35
-
#include "../gpio/gpiolib.h"
36
-
#endif
37
33
38
34
#include "core.h"
39
35
#include "devicetree.h"
···
143
145
*/
144
146
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
145
147
{
146
-
unsigned i, pin;
148
+
unsigned int i, pin;
147
149
148
150
/* The pin number can be retrived from the pin controller descriptor */
149
151
for (i = 0; i < pctldev->desc->npins; i++) {
···
164
166
* @pctldev: the pin control device to lookup the pin on
165
167
* @pin: pin number/id to look up
166
168
*/
167
-
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
169
+
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned int pin)
168
170
{
169
171
const struct pin_desc *desc;
170
172
···
182
184
/* Deletes a range of pin descriptors */
183
185
static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
184
186
const struct pinctrl_pin_desc *pins,
185
-
unsigned num_pins)
187
+
unsigned int num_pins)
186
188
{
187
189
int i;
188
190
···
250
252
251
253
static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
252
254
const struct pinctrl_pin_desc *pins,
253
-
unsigned num_descs)
255
+
unsigned int num_descs)
254
256
{
255
-
unsigned i;
257
+
unsigned int i;
256
258
int ret = 0;
257
259
258
260
for (i = 0; i < num_descs; i++) {
···
426
428
427
429
void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
428
430
struct pinctrl_gpio_range *ranges,
429
-
unsigned nranges)
431
+
unsigned int nranges)
430
432
{
431
433
int i;
432
434
···
457
459
EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
458
460
459
461
int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
460
-
const unsigned **pins, unsigned *num_pins)
462
+
const unsigned int **pins, unsigned int *num_pins)
461
463
{
462
464
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
463
465
int gs;
···
557
559
if (!group)
558
560
return NULL;
559
561
560
-
return group->name;
562
+
return group->grp.name;
561
563
}
562
564
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_name);
563
565
···
583
585
return -EINVAL;
584
586
}
585
587
586
-
*pins = group->pins;
587
-
*num_pins = group->num_pins;
588
+
*pins = group->grp.pins;
589
+
*num_pins = group->grp.npins;
588
590
589
591
return 0;
590
592
}
···
640
642
* Note that the caller must take care of locking.
641
643
*/
642
644
int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
643
-
int *pins, int num_pins, void *data)
645
+
const unsigned int *pins, int num_pins, void *data)
644
646
{
645
647
struct group_desc *group;
646
648
int selector, error;
···
658
660
if (!group)
659
661
return -ENOMEM;
660
662
661
-
group->name = name;
662
-
group->pins = pins;
663
-
group->num_pins = num_pins;
664
-
group->data = data;
663
+
*group = PINCTRL_GROUP_DESC(name, pins, num_pins, data);
665
664
666
665
error = radix_tree_insert(&pctldev->pin_group_tree, selector, group);
667
666
if (error)
···
729
734
const char *pin_group)
730
735
{
731
736
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
732
-
unsigned ngroups = pctlops->get_groups_count(pctldev);
733
-
unsigned group_selector = 0;
737
+
unsigned int ngroups = pctlops->get_groups_count(pctldev);
738
+
unsigned int group_selector = 0;
734
739
735
740
while (group_selector < ngroups) {
736
741
const char *gname = pctlops->get_group_name(pctldev,
···
1427
1432
* @num_maps: the number of maps in the mapping table
1428
1433
*/
1429
1434
int pinctrl_register_mappings(const struct pinctrl_map *maps,
1430
-
unsigned num_maps)
1435
+
unsigned int num_maps)
1431
1436
{
1432
1437
int i, ret;
1433
1438
struct pinctrl_maps *maps_node;
···
1642
1647
{
1643
1648
struct pinctrl_dev *pctldev = s->private;
1644
1649
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1645
-
unsigned i, pin;
1650
+
unsigned int i, pin;
1646
1651
#ifdef CONFIG_GPIOLIB
1652
+
struct gpio_device *gdev __free(gpio_device_put) = NULL;
1647
1653
struct pinctrl_gpio_range *range;
1648
-
struct gpio_chip *chip;
1649
1654
int gpio_num;
1650
1655
#endif
1651
1656
···
1680
1685
* we need to get rid of the range->base eventually and
1681
1686
* get the descriptor directly from the gpio_chip.
1682
1687
*/
1683
-
chip = gpiod_to_chip(gpio_to_desc(gpio_num));
1684
-
else
1685
-
chip = NULL;
1686
-
if (chip)
1687
-
seq_printf(s, "%u:%s ", gpio_num - chip->gpiodev->base, chip->label);
1688
+
gdev = gpiod_to_gpio_device(gpio_to_desc(gpio_num));
1689
+
if (gdev)
1690
+
seq_printf(s, "%u:%s ",
1691
+
gpio_num - gpio_device_get_base(gdev),
1692
+
gpio_device_get_label(gdev));
1688
1693
else
1689
1694
seq_puts(s, "0:? ");
1690
1695
#endif
···
1706
1711
{
1707
1712
struct pinctrl_dev *pctldev = s->private;
1708
1713
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1709
-
unsigned ngroups, selector = 0;
1714
+
unsigned int ngroups, selector = 0;
1710
1715
1711
1716
mutex_lock(&pctldev->mutex);
1712
1717
···
1714
1719
1715
1720
seq_puts(s, "registered pin groups:\n");
1716
1721
while (selector < ngroups) {
1717
-
const unsigned *pins = NULL;
1718
-
unsigned num_pins = 0;
1722
+
const unsigned int *pins = NULL;
1723
+
unsigned int num_pins = 0;
1719
1724
const char *gname = ops->get_group_name(pctldev, selector);
1720
1725
const char *pname;
1721
1726
int ret = 0;
+19
-14
drivers/pinctrl/core.h
+19
-14
drivers/pinctrl/core.h
···
111
111
* @func: the function selector to program
112
112
*/
113
113
struct pinctrl_setting_mux {
114
-
unsigned group;
115
-
unsigned func;
114
+
unsigned int group;
115
+
unsigned int func;
116
116
};
117
117
118
118
/**
···
124
124
* @num_configs: the number of entries in array @configs
125
125
*/
126
126
struct pinctrl_setting_configs {
127
-
unsigned group_or_pin;
127
+
unsigned int group_or_pin;
128
128
unsigned long *configs;
129
-
unsigned num_configs;
129
+
unsigned int num_configs;
130
130
};
131
131
132
132
/**
···
173
173
void *drv_data;
174
174
/* These fields only added when supporting pinmux drivers */
175
175
#ifdef CONFIG_PINMUX
176
-
unsigned mux_usecount;
176
+
unsigned int mux_usecount;
177
177
const char *mux_owner;
178
178
const struct pinctrl_setting_mux *mux_setting;
179
179
const char *gpio_owner;
···
189
189
struct pinctrl_maps {
190
190
struct list_head node;
191
191
const struct pinctrl_map *maps;
192
-
unsigned num_maps;
192
+
unsigned int num_maps;
193
193
};
194
194
195
195
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
196
196
197
+
#include <linux/pinctrl/pinctrl.h>
198
+
197
199
/**
198
200
* struct group_desc - generic pin group descriptor
199
-
* @name: name of the pin group
200
-
* @pins: array of pins that belong to the group
201
-
* @num_pins: number of pins in the group
201
+
* @grp: generic data of the pin group (name and pins)
202
202
* @data: pin controller driver specific data
203
203
*/
204
204
struct group_desc {
205
-
const char *name;
206
-
int *pins;
207
-
int num_pins;
205
+
struct pingroup grp;
208
206
void *data;
209
207
};
208
+
209
+
/* Convenience macro to define a generic pin group descriptor */
210
+
#define PINCTRL_GROUP_DESC(_name, _pins, _num_pins, _data) \
211
+
(struct group_desc) { \
212
+
.grp = PINCTRL_PINGROUP(_name, _pins, _num_pins), \
213
+
.data = _data, \
214
+
}
210
215
211
216
int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
212
217
···
227
222
unsigned int group_selector);
228
223
229
224
int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
230
-
int *gpins, int ngpins, void *data);
225
+
const unsigned int *pins, int num_pins, void *data);
231
226
232
227
int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
233
228
unsigned int group_selector);
···
237
232
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
238
233
struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
239
234
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
240
-
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
235
+
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned int pin);
241
236
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
242
237
const char *pin_group);
243
238
+4
-4
drivers/pinctrl/devicetree.c
+4
-4
drivers/pinctrl/devicetree.c
···
24
24
struct list_head node;
25
25
struct pinctrl_dev *pctldev;
26
26
struct pinctrl_map *map;
27
-
unsigned num_maps;
27
+
unsigned int num_maps;
28
28
};
29
29
30
30
static void dt_free_map(struct pinctrl_dev *pctldev,
31
-
struct pinctrl_map *map, unsigned num_maps)
31
+
struct pinctrl_map *map, unsigned int num_maps)
32
32
{
33
33
int i;
34
34
···
64
64
65
65
static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
66
66
struct pinctrl_dev *pctldev,
67
-
struct pinctrl_map *map, unsigned num_maps)
67
+
struct pinctrl_map *map, unsigned int num_maps)
68
68
{
69
69
int i;
70
70
struct pinctrl_dt_map *dt_map;
···
116
116
const struct pinctrl_ops *ops;
117
117
int ret;
118
118
struct pinctrl_map *map;
119
-
unsigned num_maps;
119
+
unsigned int num_maps;
120
120
bool allow_default = false;
121
121
122
122
/* Find the pin controller containing np_config */
+21
-23
drivers/pinctrl/freescale/pinctrl-imx.c
+21
-23
drivers/pinctrl/freescale/pinctrl-imx.c
···
42
42
43
43
for (i = 0; i < pctldev->num_groups; i++) {
44
44
grp = pinctrl_generic_get_group(pctldev, i);
45
-
if (grp && !strcmp(grp->name, name))
45
+
if (grp && !strcmp(grp->grp.name, name))
46
46
break;
47
47
}
48
48
···
79
79
}
80
80
81
81
if (info->flags & IMX_USE_SCU) {
82
-
map_num += grp->num_pins;
82
+
map_num += grp->grp.npins;
83
83
} else {
84
-
for (i = 0; i < grp->num_pins; i++) {
84
+
for (i = 0; i < grp->grp.npins; i++) {
85
85
pin = &((struct imx_pin *)(grp->data))[i];
86
86
if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
87
87
map_num++;
···
109
109
110
110
/* create config map */
111
111
new_map++;
112
-
for (i = j = 0; i < grp->num_pins; i++) {
112
+
for (i = j = 0; i < grp->grp.npins; i++) {
113
113
pin = &((struct imx_pin *)(grp->data))[i];
114
114
115
115
/*
···
263
263
if (!func)
264
264
return -EINVAL;
265
265
266
-
npins = grp->num_pins;
266
+
npins = grp->grp.npins;
267
267
268
268
dev_dbg(ipctl->dev, "enable function %s group %s\n",
269
-
func->name, grp->name);
269
+
func->name, grp->grp.name);
270
270
271
271
for (i = 0; i < npins; i++) {
272
272
/*
···
423
423
if (!grp)
424
424
return;
425
425
426
-
for (i = 0; i < grp->num_pins; i++) {
426
+
for (i = 0; i < grp->grp.npins; i++) {
427
427
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
428
428
429
429
name = pin_get_name(pctldev, pin->pin);
···
511
511
{
512
512
const struct imx_pinctrl_soc_info *info = ipctl->info;
513
513
struct imx_pin *pin;
514
+
unsigned int *pins;
514
515
int size, pin_size;
515
516
const __be32 *list;
516
517
int i;
···
526
525
pin_size = FSL_PIN_SIZE;
527
526
528
527
/* Initialise group */
529
-
grp->name = np->name;
528
+
grp->grp.name = np->name;
530
529
531
530
/*
532
531
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
···
554
553
return -EINVAL;
555
554
}
556
555
557
-
grp->num_pins = size / pin_size;
558
-
grp->data = devm_kcalloc(ipctl->dev,
559
-
grp->num_pins, sizeof(struct imx_pin),
560
-
GFP_KERNEL);
561
-
grp->pins = devm_kcalloc(ipctl->dev,
562
-
grp->num_pins, sizeof(unsigned int),
563
-
GFP_KERNEL);
564
-
if (!grp->pins || !grp->data)
556
+
grp->grp.npins = size / pin_size;
557
+
grp->data = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL);
558
+
if (!grp->data)
565
559
return -ENOMEM;
566
560
567
-
for (i = 0; i < grp->num_pins; i++) {
561
+
pins = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL);
562
+
if (!pins)
563
+
return -ENOMEM;
564
+
grp->grp.pins = pins;
565
+
566
+
for (i = 0; i < grp->grp.npins; i++) {
568
567
pin = &((struct imx_pin *)(grp->data))[i];
569
568
if (info->flags & IMX_USE_SCU)
570
-
info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
571
-
pin, &list);
569
+
info->imx_pinctrl_parse_pin(ipctl, &pins[i], pin, &list);
572
570
else
573
-
imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
574
-
pin, &list, np);
571
+
imx_pinctrl_parse_pin_mmio(ipctl, &pins[i], pin, &list, np);
575
572
}
576
573
577
574
return 0;
···
611
612
612
613
i = 0;
613
614
for_each_child_of_node(np, child) {
614
-
grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
615
-
GFP_KERNEL);
615
+
grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL);
616
616
if (!grp) {
617
617
of_node_put(child);
618
618
return -ENOMEM;
+20
-1
drivers/pinctrl/intel/Kconfig
+20
-1
drivers/pinctrl/intel/Kconfig
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
# Intel pin control drivers
3
3
menu "Intel pinctrl drivers"
4
-
depends on ACPI && (X86 || COMPILE_TEST)
4
+
depends on (ACPI && X86) || COMPILE_TEST
5
5
6
6
config PINCTRL_BAYTRAIL
7
7
bool "Intel Baytrail GPIO pin control"
···
36
36
select GENERIC_PINCONF
37
37
select GPIOLIB
38
38
select GPIOLIB_IRQCHIP
39
+
40
+
config PINCTRL_INTEL_PLATFORM
41
+
tristate "Intel pinctrl and GPIO platform driver"
42
+
depends on ACPI
43
+
select PINCTRL_INTEL
44
+
help
45
+
This pinctrl driver provides an interface that allows configuring
46
+
of Intel PCH pins and using them as GPIOs. Currently the following
47
+
Intel SoCs / platforms require this to be functional:
48
+
- Lunar Lake
39
49
40
50
config PINCTRL_ALDERLAKE
41
51
tristate "Intel Alder Lake pinctrl and GPIO driver"
···
137
127
help
138
128
This pinctrl driver provides an interface that allows configuring
139
129
of Intel Meteor Lake pins and using them as GPIOs.
130
+
131
+
config PINCTRL_METEORPOINT
132
+
tristate "Intel Meteor Point pinctrl and GPIO driver"
133
+
depends on ACPI
134
+
select PINCTRL_INTEL
135
+
help
136
+
Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver
137
+
provides an interface that allows configuring of PCH pins and
138
+
using them as GPIOs.
140
139
141
140
config PINCTRL_SUNRISEPOINT
142
141
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
+2
drivers/pinctrl/intel/Makefile
+2
drivers/pinctrl/intel/Makefile
···
8
8
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
9
9
obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o
10
10
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
11
+
obj-$(CONFIG_PINCTRL_INTEL_PLATFORM) += pinctrl-intel-platform.o
11
12
obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o
12
13
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
13
14
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
···
22
21
obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o
23
22
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
24
23
obj-$(CONFIG_PINCTRL_METEORLAKE) += pinctrl-meteorlake.o
24
+
obj-$(CONFIG_PINCTRL_METEORPOINT) += pinctrl-meteorpoint.o
25
25
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
26
26
obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
+2
-3
drivers/pinctrl/intel/pinctrl-alderlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-alderlake.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
734
733
};
735
734
MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
736
735
737
-
static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops);
738
-
739
736
static struct platform_driver adl_pinctrl_driver = {
740
737
.probe = intel_pinctrl_probe_by_hid,
741
738
.driver = {
742
739
.name = "alderlake-pinctrl",
743
740
.acpi_match_table = adl_pinctrl_acpi_match,
744
-
.pm = &adl_pinctrl_pm_ops,
741
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
745
742
},
746
743
};
747
744
module_platform_driver(adl_pinctrl_driver);
+91
-138
drivers/pinctrl/intel/pinctrl-baytrail.c
+91
-138
drivers/pinctrl/intel/pinctrl-baytrail.c
···
588
588
const struct intel_pingroup group,
589
589
unsigned int func)
590
590
{
591
-
unsigned long flags;
592
591
int i;
593
592
594
-
raw_spin_lock_irqsave(&byt_lock, flags);
593
+
guard(raw_spinlock_irqsave)(&byt_lock);
595
594
596
595
for (i = 0; i < group.grp.npins; i++) {
597
596
void __iomem *padcfg0;
···
608
609
value |= func;
609
610
writel(value, padcfg0);
610
611
}
611
-
612
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
613
612
}
614
613
615
614
static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
616
615
const struct intel_pingroup group,
617
616
const unsigned int *func)
618
617
{
619
-
unsigned long flags;
620
618
int i;
621
619
622
-
raw_spin_lock_irqsave(&byt_lock, flags);
620
+
guard(raw_spinlock_irqsave)(&byt_lock);
623
621
624
622
for (i = 0; i < group.grp.npins; i++) {
625
623
void __iomem *padcfg0;
···
634
638
value |= func[i];
635
639
writel(value, padcfg0);
636
640
}
637
-
638
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
639
641
}
640
642
641
643
static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
···
671
677
static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
672
678
{
673
679
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
674
-
unsigned long flags;
675
680
u32 value;
676
681
677
-
raw_spin_lock_irqsave(&byt_lock, flags);
682
+
guard(raw_spinlock_irqsave)(&byt_lock);
683
+
678
684
value = readl(reg);
679
685
680
686
/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
···
682
688
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
683
689
684
690
writel(value, reg);
685
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
686
691
}
687
692
688
693
static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
···
691
698
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
692
699
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
693
700
u32 value, gpio_mux;
694
-
unsigned long flags;
695
701
696
-
raw_spin_lock_irqsave(&byt_lock, flags);
702
+
guard(raw_spinlock_irqsave)(&byt_lock);
697
703
698
704
/*
699
705
* In most cases, func pin mux 000 means GPIO function.
···
705
713
*/
706
714
value = readl(reg) & BYT_PIN_MUX;
707
715
gpio_mux = byt_get_gpio_mux(vg, offset);
708
-
if (gpio_mux != value) {
709
-
value = readl(reg) & ~BYT_PIN_MUX;
710
-
value |= gpio_mux;
711
-
writel(value, reg);
716
+
if (gpio_mux == value)
717
+
return 0;
712
718
713
-
dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
714
-
}
719
+
value = readl(reg) & ~BYT_PIN_MUX;
720
+
value |= gpio_mux;
721
+
writel(value, reg);
715
722
716
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
723
+
dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
717
724
718
725
return 0;
719
726
}
···
750
759
{
751
760
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
752
761
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
753
-
unsigned long flags;
754
762
u32 value;
755
763
756
-
raw_spin_lock_irqsave(&byt_lock, flags);
764
+
guard(raw_spinlock_irqsave)(&byt_lock);
757
765
758
766
value = readl(val_reg);
759
767
value &= ~BYT_DIR_MASK;
···
762
772
byt_gpio_direct_irq_check(vg, offset);
763
773
764
774
writel(value, val_reg);
765
-
766
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
767
775
768
776
return 0;
769
777
}
···
799
811
*reg &= ~BYT_PULL_STR_MASK;
800
812
801
813
switch (strength) {
814
+
case 1: /* Set default strength value in case none is given */
802
815
case 2000:
803
816
*reg |= BYT_PULL_STR_2K;
804
817
break;
···
819
830
return 0;
820
831
}
821
832
833
+
static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset)
834
+
{
835
+
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
836
+
u32 value;
837
+
838
+
value = readl(reg);
839
+
if (!(value & BYT_INPUT_EN))
840
+
return;
841
+
842
+
/*
843
+
* Pull assignment is only applicable in input mode. If
844
+
* chip is not in input mode, set it and warn about it.
845
+
*/
846
+
value &= ~BYT_INPUT_EN;
847
+
writel(value, reg);
848
+
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
849
+
}
850
+
822
851
static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
823
852
unsigned long *config)
824
853
{
···
845
838
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
846
839
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
847
840
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
848
-
unsigned long flags;
849
841
u32 conf, pull, val, debounce;
850
842
u16 arg = 0;
851
843
852
-
raw_spin_lock_irqsave(&byt_lock, flags);
853
-
conf = readl(conf_reg);
844
+
scoped_guard(raw_spinlock_irqsave, &byt_lock) {
845
+
conf = readl(conf_reg);
846
+
val = readl(val_reg);
847
+
}
848
+
854
849
pull = conf & BYT_PULL_ASSIGN_MASK;
855
-
val = readl(val_reg);
856
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
857
850
858
851
switch (param) {
859
852
case PIN_CONFIG_BIAS_DISABLE:
···
880
873
if (!(conf & BYT_DEBOUNCE_EN))
881
874
return -EINVAL;
882
875
883
-
raw_spin_lock_irqsave(&byt_lock, flags);
884
-
debounce = readl(db_reg);
885
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
876
+
scoped_guard(raw_spinlock_irqsave, &byt_lock)
877
+
debounce = readl(db_reg);
886
878
887
879
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
888
880
case BYT_DEBOUNCE_PULSE_375US:
···
925
919
unsigned int num_configs)
926
920
{
927
921
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
928
-
unsigned int param, arg;
929
922
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
930
-
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
931
923
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
932
-
u32 conf, val, db_pulse, debounce;
933
-
unsigned long flags;
934
-
int i, ret = 0;
924
+
u32 conf, db_pulse, debounce;
925
+
enum pin_config_param param;
926
+
int i, ret;
927
+
u32 arg;
935
928
936
-
raw_spin_lock_irqsave(&byt_lock, flags);
929
+
guard(raw_spinlock_irqsave)(&byt_lock);
937
930
938
931
conf = readl(conf_reg);
939
-
val = readl(val_reg);
940
932
941
933
for (i = 0; i < num_configs; i++) {
942
934
param = pinconf_to_config_param(configs[i]);
···
945
941
conf &= ~BYT_PULL_ASSIGN_MASK;
946
942
break;
947
943
case PIN_CONFIG_BIAS_PULL_DOWN:
948
-
/* Set default strength value in case none is given */
949
-
if (arg == 1)
950
-
arg = 2000;
951
-
952
-
/*
953
-
* Pull assignment is only applicable in input mode. If
954
-
* chip is not in input mode, set it and warn about it.
955
-
*/
956
-
if (val & BYT_INPUT_EN) {
957
-
val &= ~BYT_INPUT_EN;
958
-
writel(val, val_reg);
959
-
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
960
-
}
944
+
byt_gpio_force_input_mode(vg, offset);
961
945
962
946
conf &= ~BYT_PULL_ASSIGN_MASK;
963
947
conf |= BYT_PULL_ASSIGN_DOWN;
964
948
ret = byt_set_pull_strength(&conf, arg);
949
+
if (ret)
950
+
return ret;
965
951
966
952
break;
967
953
case PIN_CONFIG_BIAS_PULL_UP:
968
-
/* Set default strength value in case none is given */
969
-
if (arg == 1)
970
-
arg = 2000;
971
-
972
-
/*
973
-
* Pull assignment is only applicable in input mode. If
974
-
* chip is not in input mode, set it and warn about it.
975
-
*/
976
-
if (val & BYT_INPUT_EN) {
977
-
val &= ~BYT_INPUT_EN;
978
-
writel(val, val_reg);
979
-
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
980
-
}
954
+
byt_gpio_force_input_mode(vg, offset);
981
955
982
956
conf &= ~BYT_PULL_ASSIGN_MASK;
983
957
conf |= BYT_PULL_ASSIGN_UP;
984
958
ret = byt_set_pull_strength(&conf, arg);
959
+
if (ret)
960
+
return ret;
985
961
986
962
break;
987
963
case PIN_CONFIG_INPUT_DEBOUNCE:
988
-
if (arg) {
989
-
conf |= BYT_DEBOUNCE_EN;
990
-
} else {
991
-
conf &= ~BYT_DEBOUNCE_EN;
992
-
993
-
/*
994
-
* No need to update the pulse value.
995
-
* Debounce is going to be disabled.
996
-
*/
997
-
break;
998
-
}
999
-
1000
964
switch (arg) {
965
+
case 0:
966
+
db_pulse = 0;
967
+
break;
1001
968
case 375:
1002
969
db_pulse = BYT_DEBOUNCE_PULSE_375US;
1003
970
break;
···
991
1016
db_pulse = BYT_DEBOUNCE_PULSE_24MS;
992
1017
break;
993
1018
default:
994
-
if (arg)
995
-
ret = -EINVAL;
996
-
break;
1019
+
return -EINVAL;
997
1020
}
998
1021
999
-
if (ret)
1000
-
break;
1022
+
if (db_pulse) {
1023
+
debounce = readl(db_reg);
1024
+
debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1025
+
writel(debounce, db_reg);
1001
1026
1002
-
debounce = readl(db_reg);
1003
-
debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1004
-
writel(debounce, db_reg);
1027
+
conf |= BYT_DEBOUNCE_EN;
1028
+
} else {
1029
+
conf &= ~BYT_DEBOUNCE_EN;
1030
+
}
1005
1031
1006
1032
break;
1007
1033
default:
1008
-
ret = -ENOTSUPP;
1034
+
return -ENOTSUPP;
1009
1035
}
1010
-
1011
-
if (ret)
1012
-
break;
1013
1036
}
1014
1037
1015
-
if (!ret)
1016
-
writel(conf, conf_reg);
1038
+
writel(conf, conf_reg);
1017
1039
1018
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1019
-
1020
-
return ret;
1040
+
return 0;
1021
1041
}
1022
1042
1023
1043
static const struct pinconf_ops byt_pinconf_ops = {
···
1032
1062
{
1033
1063
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1034
1064
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1035
-
unsigned long flags;
1036
1065
u32 val;
1037
1066
1038
-
raw_spin_lock_irqsave(&byt_lock, flags);
1039
-
val = readl(reg);
1040
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1067
+
scoped_guard(raw_spinlock_irqsave, &byt_lock)
1068
+
val = readl(reg);
1041
1069
1042
1070
return !!(val & BYT_LEVEL);
1043
1071
}
···
1043
1075
static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1044
1076
{
1045
1077
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1046
-
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1047
-
unsigned long flags;
1078
+
void __iomem *reg;
1048
1079
u32 old_val;
1049
1080
1081
+
reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1050
1082
if (!reg)
1051
1083
return;
1052
1084
1053
-
raw_spin_lock_irqsave(&byt_lock, flags);
1085
+
guard(raw_spinlock_irqsave)(&byt_lock);
1086
+
1054
1087
old_val = readl(reg);
1055
1088
if (value)
1056
1089
writel(old_val | BYT_LEVEL, reg);
1057
1090
else
1058
1091
writel(old_val & ~BYT_LEVEL, reg);
1059
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1060
1092
}
1061
1093
1062
1094
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1063
1095
{
1064
1096
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1065
-
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1066
-
unsigned long flags;
1097
+
void __iomem *reg;
1067
1098
u32 value;
1068
1099
1100
+
reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1069
1101
if (!reg)
1070
1102
return -EINVAL;
1071
1103
1072
-
raw_spin_lock_irqsave(&byt_lock, flags);
1073
-
value = readl(reg);
1074
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1104
+
scoped_guard(raw_spinlock_irqsave, &byt_lock)
1105
+
value = readl(reg);
1075
1106
1076
1107
if (!(value & BYT_OUTPUT_EN))
1077
1108
return GPIO_LINE_DIRECTION_OUT;
···
1084
1117
{
1085
1118
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1086
1119
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1087
-
unsigned long flags;
1088
1120
u32 reg;
1089
1121
1090
-
raw_spin_lock_irqsave(&byt_lock, flags);
1122
+
guard(raw_spinlock_irqsave)(&byt_lock);
1091
1123
1092
1124
reg = readl(val_reg);
1093
1125
reg &= ~BYT_DIR_MASK;
1094
1126
reg |= BYT_OUTPUT_EN;
1095
1127
writel(reg, val_reg);
1096
1128
1097
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1098
1129
return 0;
1099
1130
}
1100
1131
···
1107
1142
{
1108
1143
struct intel_pinctrl *vg = gpiochip_get_data(chip);
1109
1144
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1110
-
unsigned long flags;
1111
1145
u32 reg;
1112
1146
1113
-
raw_spin_lock_irqsave(&byt_lock, flags);
1147
+
guard(raw_spinlock_irqsave)(&byt_lock);
1114
1148
1115
1149
byt_gpio_direct_irq_check(vg, offset);
1116
1150
···
1122
1158
1123
1159
writel(reg, val_reg);
1124
1160
1125
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1126
1161
return 0;
1127
1162
}
1128
1163
···
1136
1173
void __iomem *conf_reg, *val_reg;
1137
1174
const char *pull_str = NULL;
1138
1175
const char *pull = NULL;
1139
-
unsigned long flags;
1140
1176
unsigned int pin;
1141
1177
1142
1178
pin = vg->soc->pins[i].number;
···
1152
1190
continue;
1153
1191
}
1154
1192
1155
-
raw_spin_lock_irqsave(&byt_lock, flags);
1156
-
conf0 = readl(conf_reg);
1157
-
val = readl(val_reg);
1158
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1193
+
scoped_guard(raw_spinlock_irqsave, &byt_lock) {
1194
+
conf0 = readl(conf_reg);
1195
+
val = readl(val_reg);
1196
+
}
1159
1197
1160
1198
comm = intel_get_community(vg, pin);
1161
1199
if (!comm) {
···
1240
1278
if (!reg)
1241
1279
return;
1242
1280
1243
-
raw_spin_lock(&byt_lock);
1281
+
guard(raw_spinlock)(&byt_lock);
1282
+
1244
1283
writel(BIT(hwirq % 32), reg);
1245
-
raw_spin_unlock(&byt_lock);
1246
1284
}
1247
1285
1248
1286
static void byt_irq_mask(struct irq_data *d)
···
1260
1298
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1261
1299
struct intel_pinctrl *vg = gpiochip_get_data(gc);
1262
1300
irq_hw_number_t hwirq = irqd_to_hwirq(d);
1263
-
unsigned long flags;
1264
1301
void __iomem *reg;
1265
1302
u32 value;
1266
1303
···
1269
1308
if (!reg)
1270
1309
return;
1271
1310
1272
-
raw_spin_lock_irqsave(&byt_lock, flags);
1311
+
guard(raw_spinlock_irqsave)(&byt_lock);
1312
+
1273
1313
value = readl(reg);
1274
1314
1275
1315
switch (irqd_get_trigger_type(d)) {
···
1292
1330
}
1293
1331
1294
1332
writel(value, reg);
1295
-
1296
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1297
1333
}
1298
1334
1299
1335
static int byt_irq_type(struct irq_data *d, unsigned int type)
1300
1336
{
1301
1337
struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1302
1338
irq_hw_number_t hwirq = irqd_to_hwirq(d);
1303
-
u32 value;
1304
-
unsigned long flags;
1305
1339
void __iomem *reg;
1340
+
u32 value;
1306
1341
1307
1342
reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1308
1343
if (!reg)
1309
1344
return -EINVAL;
1310
1345
1311
-
raw_spin_lock_irqsave(&byt_lock, flags);
1346
+
guard(raw_spinlock_irqsave)(&byt_lock);
1347
+
1312
1348
value = readl(reg);
1313
1349
1314
1350
WARN(value & BYT_DIRECT_IRQ_EN,
···
1327
1367
irq_set_handler_locked(d, handle_edge_irq);
1328
1368
else if (type & IRQ_TYPE_LEVEL_MASK)
1329
1369
irq_set_handler_locked(d, handle_level_irq);
1330
-
1331
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1332
1370
1333
1371
return 0;
1334
1372
}
···
1359
1401
continue;
1360
1402
}
1361
1403
1362
-
raw_spin_lock(&byt_lock);
1363
-
pending = readl(reg);
1364
-
raw_spin_unlock(&byt_lock);
1404
+
scoped_guard(raw_spinlock, &byt_lock)
1405
+
pending = readl(reg);
1365
1406
for_each_set_bit(pin, &pending, 32)
1366
1407
generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1367
1408
}
···
1623
1666
static int byt_gpio_suspend(struct device *dev)
1624
1667
{
1625
1668
struct intel_pinctrl *vg = dev_get_drvdata(dev);
1626
-
unsigned long flags;
1627
1669
int i;
1628
1670
1629
-
raw_spin_lock_irqsave(&byt_lock, flags);
1671
+
guard(raw_spinlock_irqsave)(&byt_lock);
1630
1672
1631
1673
for (i = 0; i < vg->soc->npins; i++) {
1632
1674
void __iomem *reg;
···
1649
1693
vg->context.pads[i].val = value;
1650
1694
}
1651
1695
1652
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1653
1696
return 0;
1654
1697
}
1655
1698
1656
1699
static int byt_gpio_resume(struct device *dev)
1657
1700
{
1658
1701
struct intel_pinctrl *vg = dev_get_drvdata(dev);
1659
-
unsigned long flags;
1660
1702
int i;
1661
1703
1662
-
raw_spin_lock_irqsave(&byt_lock, flags);
1704
+
guard(raw_spinlock_irqsave)(&byt_lock);
1663
1705
1664
1706
for (i = 0; i < vg->soc->npins; i++) {
1665
1707
void __iomem *reg;
···
1697
1743
}
1698
1744
}
1699
1745
1700
-
raw_spin_unlock_irqrestore(&byt_lock, flags);
1701
1746
return 0;
1702
1747
}
1703
1748
+2
-3
drivers/pinctrl/intel/pinctrl-broxton.c
+2
-3
drivers/pinctrl/intel/pinctrl-broxton.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
1001
1000
};
1002
1001
MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);
1003
1002
1004
-
static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
1005
-
1006
1003
static struct platform_driver bxt_pinctrl_driver = {
1007
1004
.probe = intel_pinctrl_probe_by_uid,
1008
1005
.driver = {
1009
1006
.name = "broxton-pinctrl",
1010
1007
.acpi_match_table = bxt_pinctrl_acpi_match,
1011
-
.pm = &bxt_pinctrl_pm_ops,
1008
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
1012
1009
},
1013
1010
.id_table = bxt_pinctrl_platform_ids,
1014
1011
};
+2
-3
drivers/pinctrl/intel/pinctrl-cannonlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-cannonlake.c
···
10
10
#include <linux/mod_devicetable.h>
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/pm.h>
13
14
14
15
#include <linux/pinctrl/pinctrl.h>
15
16
···
825
824
};
826
825
MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
827
826
828
-
static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
829
-
830
827
static struct platform_driver cnl_pinctrl_driver = {
831
828
.probe = intel_pinctrl_probe_by_hid,
832
829
.driver = {
833
830
.name = "cannonlake-pinctrl",
834
831
.acpi_match_table = cnl_pinctrl_acpi_match,
835
-
.pm = &cnl_pinctrl_pm_ops,
832
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
836
833
},
837
834
};
838
835
module_platform_driver(cnl_pinctrl_driver);
+2
-3
drivers/pinctrl/intel/pinctrl-cedarfork.c
+2
-3
drivers/pinctrl/intel/pinctrl-cedarfork.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
320
319
.ncommunities = ARRAY_SIZE(cdf_communities),
321
320
};
322
321
323
-
static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
324
-
325
322
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
326
323
{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
327
324
{ }
···
331
332
.driver = {
332
333
.name = "cedarfork-pinctrl",
333
334
.acpi_match_table = cdf_pinctrl_acpi_match,
334
-
.pm = &cdf_pinctrl_pm_ops,
335
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
335
336
},
336
337
};
337
338
+2
-3
drivers/pinctrl/intel/pinctrl-denverton.c
+2
-3
drivers/pinctrl/intel/pinctrl-denverton.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
250
249
.ncommunities = ARRAY_SIZE(dnv_communities),
251
250
};
252
251
253
-
static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
254
-
255
252
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
256
253
{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
257
254
{ }
···
267
268
.driver = {
268
269
.name = "denverton-pinctrl",
269
270
.acpi_match_table = dnv_pinctrl_acpi_match,
270
-
.pm = &dnv_pinctrl_pm_ops,
271
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
271
272
},
272
273
.id_table = dnv_pinctrl_platform_ids,
273
274
};
+2
-3
drivers/pinctrl/intel/pinctrl-elkhartlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-elkhartlake.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
486
485
};
487
486
MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
488
487
489
-
static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
490
-
491
488
static struct platform_driver ehl_pinctrl_driver = {
492
489
.probe = intel_pinctrl_probe_by_uid,
493
490
.driver = {
494
491
.name = "elkhartlake-pinctrl",
495
492
.acpi_match_table = ehl_pinctrl_acpi_match,
496
-
.pm = &ehl_pinctrl_pm_ops,
493
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
497
494
},
498
495
};
499
496
module_platform_driver(ehl_pinctrl_driver);
+2
-3
drivers/pinctrl/intel/pinctrl-emmitsburg.c
+2
-3
drivers/pinctrl/intel/pinctrl-emmitsburg.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
359
358
};
360
359
MODULE_DEVICE_TABLE(acpi, ebg_pinctrl_acpi_match);
361
360
362
-
static INTEL_PINCTRL_PM_OPS(ebg_pinctrl_pm_ops);
363
-
364
361
static struct platform_driver ebg_pinctrl_driver = {
365
362
.probe = intel_pinctrl_probe_by_hid,
366
363
.driver = {
367
364
.name = "emmitsburg-pinctrl",
368
365
.acpi_match_table = ebg_pinctrl_acpi_match,
369
-
.pm = &ebg_pinctrl_pm_ops,
366
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
370
367
},
371
368
};
372
369
module_platform_driver(ebg_pinctrl_driver);
+2
-3
drivers/pinctrl/intel/pinctrl-geminilake.c
+2
-3
drivers/pinctrl/intel/pinctrl-geminilake.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
448
447
};
449
448
MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
450
449
451
-
static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
452
-
453
450
static struct platform_driver glk_pinctrl_driver = {
454
451
.probe = intel_pinctrl_probe_by_uid,
455
452
.driver = {
456
453
.name = "geminilake-pinctrl",
457
454
.acpi_match_table = glk_pinctrl_acpi_match,
458
-
.pm = &glk_pinctrl_pm_ops,
455
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
459
456
},
460
457
};
461
458
+2
-3
drivers/pinctrl/intel/pinctrl-icelake.c
+2
-3
drivers/pinctrl/intel/pinctrl-icelake.c
···
10
10
#include <linux/acpi.h>
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/pm.h>
13
14
14
15
#include <linux/pinctrl/pinctrl.h>
15
16
···
669
668
.ncommunities = ARRAY_SIZE(icln_communities),
670
669
};
671
670
672
-
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
673
-
674
671
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
675
672
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
676
673
{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
···
681
682
.driver = {
682
683
.name = "icelake-pinctrl",
683
684
.acpi_match_table = icl_pinctrl_acpi_match,
684
-
.pm = &icl_pinctrl_pm_ops,
685
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
685
686
},
686
687
};
687
688
module_platform_driver(icl_pinctrl_driver);
+225
drivers/pinctrl/intel/pinctrl-intel-platform.c
+225
drivers/pinctrl/intel/pinctrl-intel-platform.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Intel PCH pinctrl/GPIO driver
4
+
*
5
+
* Copyright (C) 2021-2023, Intel Corporation
6
+
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7
+
*/
8
+
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
13
+
#include <linux/property.h>
14
+
#include <linux/string_helpers.h>
15
+
16
+
#include <linux/pinctrl/pinctrl.h>
17
+
18
+
#include "pinctrl-intel.h"
19
+
20
+
struct intel_platform_pins {
21
+
struct pinctrl_pin_desc *pins;
22
+
size_t npins;
23
+
};
24
+
25
+
static int intel_platform_pinctrl_prepare_pins(struct device *dev, size_t base,
26
+
const char *name, u32 size,
27
+
struct intel_platform_pins *pins)
28
+
{
29
+
struct pinctrl_pin_desc *descs;
30
+
char **pin_names;
31
+
unsigned int i;
32
+
33
+
pin_names = devm_kasprintf_strarray(dev, name, size);
34
+
if (IS_ERR(pin_names))
35
+
return PTR_ERR(pin_names);
36
+
37
+
descs = devm_krealloc_array(dev, pins->pins, base + size, sizeof(*descs), GFP_KERNEL);
38
+
if (!descs)
39
+
return -ENOMEM;
40
+
41
+
for (i = 0; i < size; i++) {
42
+
unsigned int pin_number = base + i;
43
+
char *pin_name = pin_names[i];
44
+
struct pinctrl_pin_desc *desc;
45
+
46
+
/* Unify delimiter for pin name */
47
+
strreplace(pin_name, '-', '_');
48
+
49
+
desc = &descs[pin_number];
50
+
desc->number = pin_number;
51
+
desc->name = pin_name;
52
+
}
53
+
54
+
pins->pins = descs;
55
+
pins->npins = base + size;
56
+
57
+
return 0;
58
+
}
59
+
60
+
static int intel_platform_pinctrl_prepare_group(struct device *dev,
61
+
struct fwnode_handle *child,
62
+
struct intel_padgroup *gpp,
63
+
struct intel_platform_pins *pins)
64
+
{
65
+
size_t base = pins->npins;
66
+
const char *name;
67
+
u32 size;
68
+
int ret;
69
+
70
+
ret = fwnode_property_read_string(child, "intc-gpio-group-name", &name);
71
+
if (ret)
72
+
return ret;
73
+
74
+
ret = fwnode_property_read_u32(child, "intc-gpio-pad-count", &size);
75
+
if (ret)
76
+
return ret;
77
+
78
+
ret = intel_platform_pinctrl_prepare_pins(dev, base, name, size, pins);
79
+
if (ret)
80
+
return ret;
81
+
82
+
gpp->base = base;
83
+
gpp->size = size;
84
+
gpp->gpio_base = INTEL_GPIO_BASE_MATCH;
85
+
86
+
return 0;
87
+
}
88
+
89
+
static int intel_platform_pinctrl_prepare_community(struct device *dev,
90
+
struct intel_community *community,
91
+
struct intel_platform_pins *pins)
92
+
{
93
+
struct fwnode_handle *child;
94
+
struct intel_padgroup *gpps;
95
+
unsigned int group;
96
+
size_t ngpps;
97
+
u32 offset;
98
+
int ret;
99
+
100
+
ret = device_property_read_u32(dev, "intc-gpio-pad-ownership-offset", &offset);
101
+
if (ret)
102
+
return ret;
103
+
community->padown_offset = offset;
104
+
105
+
ret = device_property_read_u32(dev, "intc-gpio-pad-configuration-lock-offset", &offset);
106
+
if (ret)
107
+
return ret;
108
+
community->padcfglock_offset = offset;
109
+
110
+
ret = device_property_read_u32(dev, "intc-gpio-host-software-pad-ownership-offset", &offset);
111
+
if (ret)
112
+
return ret;
113
+
community->hostown_offset = offset;
114
+
115
+
ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-status-offset", &offset);
116
+
if (ret)
117
+
return ret;
118
+
community->is_offset = offset;
119
+
120
+
ret = device_property_read_u32(dev, "intc-gpio-gpi-interrupt-enable-offset", &offset);
121
+
if (ret)
122
+
return ret;
123
+
community->ie_offset = offset;
124
+
125
+
ngpps = device_get_child_node_count(dev);
126
+
if (!ngpps)
127
+
return -ENODEV;
128
+
129
+
gpps = devm_kcalloc(dev, ngpps, sizeof(*gpps), GFP_KERNEL);
130
+
if (!gpps)
131
+
return -ENOMEM;
132
+
133
+
group = 0;
134
+
device_for_each_child_node(dev, child) {
135
+
struct intel_padgroup *gpp = &gpps[group];
136
+
137
+
gpp->reg_num = group;
138
+
139
+
ret = intel_platform_pinctrl_prepare_group(dev, child, gpp, pins);
140
+
if (ret)
141
+
return ret;
142
+
143
+
group++;
144
+
}
145
+
146
+
community->ngpps = ngpps;
147
+
community->gpps = gpps;
148
+
149
+
return 0;
150
+
}
151
+
152
+
static int intel_platform_pinctrl_prepare_soc_data(struct device *dev,
153
+
struct intel_pinctrl_soc_data *data)
154
+
{
155
+
struct intel_platform_pins pins = {};
156
+
struct intel_community *communities;
157
+
size_t ncommunities;
158
+
unsigned int i;
159
+
int ret;
160
+
161
+
/* Version 1.0 of the specification assumes only a single community per device node */
162
+
ncommunities = 1,
163
+
communities = devm_kcalloc(dev, ncommunities, sizeof(*communities), GFP_KERNEL);
164
+
if (!communities)
165
+
return -ENOMEM;
166
+
167
+
for (i = 0; i < ncommunities; i++) {
168
+
struct intel_community *community = &communities[i];
169
+
170
+
community->barno = i;
171
+
community->pin_base = pins.npins;
172
+
173
+
ret = intel_platform_pinctrl_prepare_community(dev, community, &pins);
174
+
if (ret)
175
+
return ret;
176
+
177
+
community->npins = pins.npins - community->pin_base;
178
+
}
179
+
180
+
data->ncommunities = ncommunities;
181
+
data->communities = communities;
182
+
183
+
data->npins = pins.npins;
184
+
data->pins = pins.pins;
185
+
186
+
return 0;
187
+
}
188
+
189
+
static int intel_platform_pinctrl_probe(struct platform_device *pdev)
190
+
{
191
+
struct intel_pinctrl_soc_data *data;
192
+
struct device *dev = &pdev->dev;
193
+
int ret;
194
+
195
+
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
196
+
if (!data)
197
+
return -ENOMEM;
198
+
199
+
ret = intel_platform_pinctrl_prepare_soc_data(dev, data);
200
+
if (ret)
201
+
return ret;
202
+
203
+
return intel_pinctrl_probe(pdev, data);
204
+
}
205
+
206
+
static const struct acpi_device_id intel_platform_pinctrl_acpi_match[] = {
207
+
{ "INTC105F" },
208
+
{ }
209
+
};
210
+
MODULE_DEVICE_TABLE(acpi, intel_platform_pinctrl_acpi_match);
211
+
212
+
static struct platform_driver intel_platform_pinctrl_driver = {
213
+
.probe = intel_platform_pinctrl_probe,
214
+
.driver = {
215
+
.name = "intel-pinctrl",
216
+
.acpi_match_table = intel_platform_pinctrl_acpi_match,
217
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
218
+
},
219
+
};
220
+
module_platform_driver(intel_platform_pinctrl_driver);
221
+
222
+
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
223
+
MODULE_DESCRIPTION("Intel PCH pinctrl/GPIO driver");
224
+
MODULE_LICENSE("GPL v2");
225
+
MODULE_IMPORT_NS(PINCTRL_INTEL);
+15
-17
drivers/pinctrl/intel/pinctrl-intel.c
+15
-17
drivers/pinctrl/intel/pinctrl-intel.c
···
677
677
u32 term = 0, up = 0, value;
678
678
void __iomem *padcfg1;
679
679
680
-
/* Set default strength value in case none is given */
681
-
if (arg == 1)
682
-
arg = 5000;
683
-
684
680
switch (param) {
685
681
case PIN_CONFIG_BIAS_DISABLE:
686
682
break;
···
686
690
case 20000:
687
691
term = PADCFG1_TERM_20K;
688
692
break;
693
+
case 1: /* Set default strength value in case none is given */
689
694
case 5000:
690
695
term = PADCFG1_TERM_5K;
691
696
break;
···
713
716
case 20000:
714
717
term = PADCFG1_TERM_20K;
715
718
break;
719
+
case 1: /* Set default strength value in case none is given */
716
720
case 5000:
717
721
term = PADCFG1_TERM_5K;
718
722
break;
···
897
899
*
898
900
* Return: a GPIO offset, or negative error code if translation can't be done.
899
901
*/
900
-
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
902
+
static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
901
903
{
902
904
const struct intel_community *community;
903
905
const struct intel_padgroup *padgrp;
···
1504
1506
return PTR_ERR_OR_ZERO(pwm);
1505
1507
}
1506
1508
1507
-
static int intel_pinctrl_probe(struct platform_device *pdev,
1508
-
const struct intel_pinctrl_soc_data *soc_data)
1509
+
int intel_pinctrl_probe(struct platform_device *pdev,
1510
+
const struct intel_pinctrl_soc_data *soc_data)
1509
1511
{
1510
1512
struct device *dev = &pdev->dev;
1511
1513
struct intel_pinctrl *pctrl;
···
1623
1625
1624
1626
return 0;
1625
1627
}
1628
+
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, PINCTRL_INTEL);
1626
1629
1627
1630
int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1628
1631
{
···
1652
1653
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1653
1654
{
1654
1655
const struct intel_pinctrl_soc_data * const *table;
1655
-
const struct intel_pinctrl_soc_data *data = NULL;
1656
+
const struct intel_pinctrl_soc_data *data;
1656
1657
struct device *dev = &pdev->dev;
1657
1658
1658
1659
table = device_get_match_data(dev);
···
1661
1662
unsigned int i;
1662
1663
1663
1664
for (i = 0; table[i]; i++) {
1664
-
if (acpi_dev_uid_match(adev, table[i]->uid)) {
1665
-
data = table[i];
1665
+
if (acpi_dev_uid_match(adev, table[i]->uid))
1666
1666
break;
1667
-
}
1668
1667
}
1668
+
data = table[i];
1669
1669
} else {
1670
1670
const struct platform_device_id *id;
1671
1671
···
1680
1682
}
1681
1683
EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
1682
1684
1683
-
#ifdef CONFIG_PM_SLEEP
1684
1685
static bool __intel_gpio_is_direct_irq(u32 value)
1685
1686
{
1686
1687
return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
···
1725
1728
return false;
1726
1729
}
1727
1730
1728
-
int intel_pinctrl_suspend_noirq(struct device *dev)
1731
+
static int intel_pinctrl_suspend_noirq(struct device *dev)
1729
1732
{
1730
1733
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1731
1734
struct intel_community_context *communities;
···
1768
1771
1769
1772
return 0;
1770
1773
}
1771
-
EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1772
1774
1773
1775
static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1774
1776
{
···
1834
1838
dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1835
1839
}
1836
1840
1837
-
int intel_pinctrl_resume_noirq(struct device *dev)
1841
+
static int intel_pinctrl_resume_noirq(struct device *dev)
1838
1842
{
1839
1843
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1840
1844
const struct intel_community_context *communities;
···
1878
1882
1879
1883
return 0;
1880
1884
}
1881
-
EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1882
-
#endif
1885
+
1886
+
EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = {
1887
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq)
1888
+
};
1883
1889
1884
1890
MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1885
1891
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+4
-10
drivers/pinctrl/intel/pinctrl-intel.h
+4
-10
drivers/pinctrl/intel/pinctrl-intel.h
···
252
252
int irq;
253
253
};
254
254
255
+
int intel_pinctrl_probe(struct platform_device *pdev,
256
+
const struct intel_pinctrl_soc_data *soc_data);
257
+
255
258
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
256
259
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
257
260
258
-
#ifdef CONFIG_PM_SLEEP
259
-
int intel_pinctrl_suspend_noirq(struct device *dev);
260
-
int intel_pinctrl_resume_noirq(struct device *dev);
261
-
#endif
262
-
263
-
#define INTEL_PINCTRL_PM_OPS(_name) \
264
-
const struct dev_pm_ops _name = { \
265
-
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
266
-
intel_pinctrl_resume_noirq) \
267
-
}
261
+
extern const struct dev_pm_ops intel_pinctrl_pm_ops;
268
262
269
263
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin);
270
264
+2
-3
drivers/pinctrl/intel/pinctrl-jasperlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-jasperlake.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
327
326
};
328
327
MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
329
328
330
-
static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
331
-
332
329
static struct platform_driver jsl_pinctrl_driver = {
333
330
.probe = intel_pinctrl_probe_by_hid,
334
331
.driver = {
335
332
.name = "jasperlake-pinctrl",
336
333
.acpi_match_table = jsl_pinctrl_acpi_match,
337
-
.pm = &jsl_pinctrl_pm_ops,
334
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
338
335
},
339
336
};
340
337
module_platform_driver(jsl_pinctrl_driver);
+2
-3
drivers/pinctrl/intel/pinctrl-lakefield.c
+2
-3
drivers/pinctrl/intel/pinctrl-lakefield.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
348
347
};
349
348
MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match);
350
349
351
-
static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops);
352
-
353
350
static struct platform_driver lkf_pinctrl_driver = {
354
351
.probe = intel_pinctrl_probe_by_hid,
355
352
.driver = {
356
353
.name = "lakefield-pinctrl",
357
354
.acpi_match_table = lkf_pinctrl_acpi_match,
358
-
.pm = &lkf_pinctrl_pm_ops,
355
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
359
356
},
360
357
};
361
358
module_platform_driver(lkf_pinctrl_driver);
+2
-3
drivers/pinctrl/intel/pinctrl-lewisburg.c
+2
-3
drivers/pinctrl/intel/pinctrl-lewisburg.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
302
301
.ncommunities = ARRAY_SIZE(lbg_communities),
303
302
};
304
303
305
-
static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
306
-
307
304
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
308
305
{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
309
306
{ }
···
313
314
.driver = {
314
315
.name = "lewisburg-pinctrl",
315
316
.acpi_match_table = lbg_pinctrl_acpi_match,
316
-
.pm = &lbg_pinctrl_pm_ops,
317
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
317
318
},
318
319
};
319
320
module_platform_driver(lbg_pinctrl_driver);
+21
-51
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+21
-51
drivers/pinctrl/intel/pinctrl-lynxpoint.c
···
10
10
#include <linux/acpi.h>
11
11
#include <linux/array_size.h>
12
12
#include <linux/bitops.h>
13
+
#include <linux/cleanup.h>
13
14
#include <linux/gpio/driver.h>
14
15
#include <linux/interrupt.h>
15
16
#include <linux/io.h>
···
292
291
{
293
292
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
294
293
const struct intel_pingroup *grp = &lg->soc->groups[group];
295
-
unsigned long flags;
296
294
int i;
297
295
298
-
raw_spin_lock_irqsave(&lg->lock, flags);
296
+
guard(raw_spinlock_irqsave)(&lg->lock);
299
297
300
298
/* Now enable the mux setting for each pin in the group */
301
299
for (i = 0; i < grp->grp.npins; i++) {
···
311
311
312
312
iowrite32(value, reg);
313
313
}
314
-
315
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
316
314
317
315
return 0;
318
316
}
···
332
334
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
333
335
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
334
336
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
335
-
unsigned long flags;
336
337
u32 value;
337
338
338
-
raw_spin_lock_irqsave(&lg->lock, flags);
339
+
guard(raw_spinlock_irqsave)(&lg->lock);
339
340
340
341
/*
341
342
* Reconfigure pin to GPIO mode if needed and issue a warning,
···
349
352
/* Enable input sensing */
350
353
lp_gpio_enable_input(conf2);
351
354
352
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
353
-
354
355
return 0;
355
356
}
356
357
···
358
363
{
359
364
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
360
365
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
361
-
unsigned long flags;
362
366
363
-
raw_spin_lock_irqsave(&lg->lock, flags);
367
+
guard(raw_spinlock_irqsave)(&lg->lock);
364
368
365
369
/* Disable input sensing */
366
370
lp_gpio_disable_input(conf2);
367
-
368
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
369
371
}
370
372
371
373
static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
···
371
379
{
372
380
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
373
381
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
374
-
unsigned long flags;
375
382
u32 value;
376
383
377
-
raw_spin_lock_irqsave(&lg->lock, flags);
384
+
guard(raw_spinlock_irqsave)(&lg->lock);
378
385
379
386
value = ioread32(reg);
380
387
value &= ~DIR_BIT;
···
390
399
"Potential Error: Setting GPIO to output with IOxAPIC redirection");
391
400
}
392
401
iowrite32(value, reg);
393
-
394
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
395
402
396
403
return 0;
397
404
}
···
410
421
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
411
422
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
412
423
enum pin_config_param param = pinconf_to_config_param(*config);
413
-
unsigned long flags;
414
424
u32 value, pull;
415
425
u16 arg;
416
426
417
-
raw_spin_lock_irqsave(&lg->lock, flags);
418
-
value = ioread32(conf2);
419
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
427
+
scoped_guard(raw_spinlock_irqsave, &lg->lock)
428
+
value = ioread32(conf2);
420
429
421
430
pull = value & GPIWP_MASK;
422
431
···
451
464
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
452
465
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
453
466
enum pin_config_param param;
454
-
unsigned long flags;
455
-
int i, ret = 0;
467
+
unsigned int i;
456
468
u32 value;
457
469
458
-
raw_spin_lock_irqsave(&lg->lock, flags);
470
+
guard(raw_spinlock_irqsave)(&lg->lock);
459
471
460
472
value = ioread32(conf2);
461
473
···
475
489
value |= GPIWP_UP;
476
490
break;
477
491
default:
478
-
ret = -ENOTSUPP;
492
+
return -ENOTSUPP;
479
493
}
480
-
481
-
if (ret)
482
-
break;
483
494
}
484
495
485
-
if (!ret)
486
-
iowrite32(value, conf2);
496
+
iowrite32(value, conf2);
487
497
488
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
489
-
490
-
return ret;
498
+
return 0;
491
499
}
492
500
493
501
static const struct pinconf_ops lptlp_pinconf_ops = {
···
507
527
{
508
528
struct intel_pinctrl *lg = gpiochip_get_data(chip);
509
529
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
510
-
unsigned long flags;
511
530
512
-
raw_spin_lock_irqsave(&lg->lock, flags);
531
+
guard(raw_spinlock_irqsave)(&lg->lock);
513
532
514
533
if (value)
515
534
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
516
535
else
517
536
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
518
-
519
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
520
537
}
521
538
522
539
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
569
592
struct intel_pinctrl *lg = gpiochip_get_data(gc);
570
593
irq_hw_number_t hwirq = irqd_to_hwirq(d);
571
594
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
572
-
unsigned long flags;
573
595
574
-
raw_spin_lock_irqsave(&lg->lock, flags);
596
+
guard(raw_spinlock_irqsave)(&lg->lock);
597
+
575
598
iowrite32(BIT(hwirq % 32), reg);
576
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
577
599
}
578
600
579
601
static void lp_irq_unmask(struct irq_data *d)
···
589
613
struct intel_pinctrl *lg = gpiochip_get_data(gc);
590
614
irq_hw_number_t hwirq = irqd_to_hwirq(d);
591
615
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
592
-
unsigned long flags;
593
616
594
617
gpiochip_enable_irq(gc, hwirq);
595
618
596
-
raw_spin_lock_irqsave(&lg->lock, flags);
597
-
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
598
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
619
+
scoped_guard(raw_spinlock_irqsave, &lg->lock)
620
+
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
599
621
}
600
622
601
623
static void lp_irq_disable(struct irq_data *d)
···
602
628
struct intel_pinctrl *lg = gpiochip_get_data(gc);
603
629
irq_hw_number_t hwirq = irqd_to_hwirq(d);
604
630
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
605
-
unsigned long flags;
606
631
607
-
raw_spin_lock_irqsave(&lg->lock, flags);
608
-
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
609
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
632
+
scoped_guard(raw_spinlock_irqsave, &lg->lock)
633
+
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
610
634
611
635
gpiochip_disable_irq(gc, hwirq);
612
636
}
···
614
642
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
615
643
struct intel_pinctrl *lg = gpiochip_get_data(gc);
616
644
irq_hw_number_t hwirq = irqd_to_hwirq(d);
617
-
unsigned long flags;
618
645
void __iomem *reg;
619
646
u32 value;
620
647
···
627
656
return -EBUSY;
628
657
}
629
658
630
-
raw_spin_lock_irqsave(&lg->lock, flags);
659
+
guard(raw_spinlock_irqsave)(&lg->lock);
660
+
631
661
value = ioread32(reg);
632
662
633
663
/* set both TRIG_SEL and INV bits to 0 for rising edge */
···
653
681
irq_set_handler_locked(d, handle_edge_irq);
654
682
else if (type & IRQ_TYPE_LEVEL_MASK)
655
683
irq_set_handler_locked(d, handle_level_irq);
656
-
657
-
raw_spin_unlock_irqrestore(&lg->lock, flags);
658
684
659
685
return 0;
660
686
}
+2
-3
drivers/pinctrl/intel/pinctrl-meteorlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-meteorlake.c
···
9
9
#include <linux/mod_devicetable.h>
10
10
#include <linux/module.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
12
13
13
14
#include <linux/pinctrl/pinctrl.h>
14
15
···
590
589
};
591
590
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
592
591
593
-
static INTEL_PINCTRL_PM_OPS(mtl_pinctrl_pm_ops);
594
-
595
592
static struct platform_driver mtl_pinctrl_driver = {
596
593
.probe = intel_pinctrl_probe_by_hid,
597
594
.driver = {
598
595
.name = "meteorlake-pinctrl",
599
596
.acpi_match_table = mtl_pinctrl_acpi_match,
600
-
.pm = &mtl_pinctrl_pm_ops,
597
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
601
598
},
602
599
};
603
600
module_platform_driver(mtl_pinctrl_driver);
+465
drivers/pinctrl/intel/pinctrl-meteorpoint.c
+465
drivers/pinctrl/intel/pinctrl-meteorpoint.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Intel Meteor Point PCH pinctrl/GPIO driver
4
+
*
5
+
* Copyright (C) 2022-2023, Intel Corporation
6
+
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7
+
*/
8
+
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/pm.h>
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
16
+
#include "pinctrl-intel.h"
17
+
18
+
#define MTP_PAD_OWN 0x0b0
19
+
#define MTP_PADCFGLOCK 0x110
20
+
#define MTP_HOSTSW_OWN 0x150
21
+
#define MTP_GPI_IS 0x200
22
+
#define MTP_GPI_IE 0x220
23
+
24
+
#define MTP_GPP(r, s, e, g) \
25
+
{ \
26
+
.reg_num = (r), \
27
+
.base = (s), \
28
+
.size = ((e) - (s) + 1), \
29
+
.gpio_base = (g), \
30
+
}
31
+
32
+
#define MTP_COMMUNITY(b, s, e, g) \
33
+
INTEL_COMMUNITY_GPPS(b, s, e, g, MTP)
34
+
35
+
/* Meteor Point-S */
36
+
static const struct pinctrl_pin_desc mtps_pins[] = {
37
+
/* GPP_D */
38
+
PINCTRL_PIN(0, "GPP_D_0"),
39
+
PINCTRL_PIN(1, "GPP_D_1"),
40
+
PINCTRL_PIN(2, "GPP_D_2"),
41
+
PINCTRL_PIN(3, "GPP_D_3"),
42
+
PINCTRL_PIN(4, "GPP_D_4"),
43
+
PINCTRL_PIN(5, "CNV_RF_RESET_B"),
44
+
PINCTRL_PIN(6, "CRF_CLKREQ"),
45
+
PINCTRL_PIN(7, "GPP_D_7"),
46
+
PINCTRL_PIN(8, "GPP_D_8"),
47
+
PINCTRL_PIN(9, "SML0CLK"),
48
+
PINCTRL_PIN(10, "SML0DATA"),
49
+
PINCTRL_PIN(11, "GPP_D_11"),
50
+
PINCTRL_PIN(12, "GPP_D_12"),
51
+
PINCTRL_PIN(13, "GPP_D_13"),
52
+
PINCTRL_PIN(14, "GPP_D_14"),
53
+
PINCTRL_PIN(15, "GPP_D_15"),
54
+
PINCTRL_PIN(16, "GPP_D_16"),
55
+
PINCTRL_PIN(17, "GPP_D_17"),
56
+
PINCTRL_PIN(18, "GPP_D_18"),
57
+
PINCTRL_PIN(19, "GPP_D_19"),
58
+
PINCTRL_PIN(20, "GPP_D_20"),
59
+
PINCTRL_PIN(21, "GPP_D_21"),
60
+
PINCTRL_PIN(22, "GPP_D_22"),
61
+
PINCTRL_PIN(23, "GPP_D_23"),
62
+
PINCTRL_PIN(24, "GSPI3_CLK_LOOPBK"),
63
+
/* GPP_R */
64
+
PINCTRL_PIN(25, "HDA_BCLK"),
65
+
PINCTRL_PIN(26, "HDA_SYNC"),
66
+
PINCTRL_PIN(27, "HDA_SDO"),
67
+
PINCTRL_PIN(28, "HDA_SDI_0"),
68
+
PINCTRL_PIN(29, "HDA_RSTB"),
69
+
PINCTRL_PIN(30, "GPP_R_5"),
70
+
PINCTRL_PIN(31, "GPP_R_6"),
71
+
PINCTRL_PIN(32, "GPP_R_7"),
72
+
PINCTRL_PIN(33, "GPP_R_8"),
73
+
PINCTRL_PIN(34, "GPP_R_9"),
74
+
PINCTRL_PIN(35, "GPP_R_10"),
75
+
PINCTRL_PIN(36, "GPP_R_11"),
76
+
PINCTRL_PIN(37, "GPP_R_12"),
77
+
PINCTRL_PIN(38, "GSPI2_CLK_LOOPBK"),
78
+
/* GPP_J */
79
+
PINCTRL_PIN(39, "GPP_J_0"),
80
+
PINCTRL_PIN(40, "CNV_BRI_DT"),
81
+
PINCTRL_PIN(41, "CNV_BRI_RSP"),
82
+
PINCTRL_PIN(42, "CNV_RGI_DT"),
83
+
PINCTRL_PIN(43, "CNV_RGI_RSP"),
84
+
PINCTRL_PIN(44, "GPP_J_5"),
85
+
PINCTRL_PIN(45, "GPP_J_6"),
86
+
PINCTRL_PIN(46, "BOOTHALT_B"),
87
+
PINCTRL_PIN(47, "RTCCLKOUT"),
88
+
PINCTRL_PIN(48, "BPKI3C_SDA"),
89
+
PINCTRL_PIN(49, "BPKI3C_SCL"),
90
+
PINCTRL_PIN(50, "DAM"),
91
+
PINCTRL_PIN(51, "HDACPU_SDI"),
92
+
PINCTRL_PIN(52, "HDACPU_SDO"),
93
+
PINCTRL_PIN(53, "HDACPU_BCLK"),
94
+
PINCTRL_PIN(54, "AUX_PWRGD"),
95
+
PINCTRL_PIN(55, "GLB_RST_WARN_B"),
96
+
PINCTRL_PIN(56, "RESET_SYNCB"),
97
+
/* vGPIO */
98
+
PINCTRL_PIN(57, "CNV_BTEN"),
99
+
PINCTRL_PIN(58, "CNV_BT_HOST_WAKEB"),
100
+
PINCTRL_PIN(59, "CNV_BT_IF_SELECT"),
101
+
PINCTRL_PIN(60, "vCNV_BT_UART_TXD"),
102
+
PINCTRL_PIN(61, "vCNV_BT_UART_RXD"),
103
+
PINCTRL_PIN(62, "vCNV_BT_UART_CTS_B"),
104
+
PINCTRL_PIN(63, "vCNV_BT_UART_RTS_B"),
105
+
PINCTRL_PIN(64, "vCNV_MFUART1_TXD"),
106
+
PINCTRL_PIN(65, "vCNV_MFUART1_RXD"),
107
+
PINCTRL_PIN(66, "vCNV_MFUART1_CTS_B"),
108
+
PINCTRL_PIN(67, "vCNV_MFUART1_RTS_B"),
109
+
PINCTRL_PIN(68, "vUART0_TXD"),
110
+
PINCTRL_PIN(69, "vUART0_RXD"),
111
+
PINCTRL_PIN(70, "vUART0_CTS_B"),
112
+
PINCTRL_PIN(71, "vUART0_RTS_B"),
113
+
PINCTRL_PIN(72, "vISH_UART0_TXD"),
114
+
PINCTRL_PIN(73, "vISH_UART0_RXD"),
115
+
PINCTRL_PIN(74, "vISH_UART0_CTS_B"),
116
+
PINCTRL_PIN(75, "vISH_UART0_RTS_B"),
117
+
PINCTRL_PIN(76, "vCNV_BT_I2S_BCLK"),
118
+
PINCTRL_PIN(77, "vCNV_BT_I2S_WS_SYNC"),
119
+
PINCTRL_PIN(78, "vCNV_BT_I2S_SDO"),
120
+
PINCTRL_PIN(79, "vCNV_BT_I2S_SDI"),
121
+
PINCTRL_PIN(80, "vI2S2_SCLK"),
122
+
PINCTRL_PIN(81, "vI2S2_SFRM"),
123
+
PINCTRL_PIN(82, "vI2S2_TXD"),
124
+
PINCTRL_PIN(83, "vI2S2_RXD"),
125
+
PINCTRL_PIN(84, "THC0_WOT_INT"),
126
+
PINCTRL_PIN(85, "THC1_WOT_INT"),
127
+
PINCTRL_PIN(86, "THC0_WHC_INT"),
128
+
PINCTRL_PIN(87, "THC1_WHC_INT"),
129
+
/* GPP_A */
130
+
PINCTRL_PIN(88, "ESPI_IO_0"),
131
+
PINCTRL_PIN(89, "ESPI_IO_1"),
132
+
PINCTRL_PIN(90, "ESPI_IO_2"),
133
+
PINCTRL_PIN(91, "ESPI_IO_3"),
134
+
PINCTRL_PIN(92, "ESPI_CS0B"),
135
+
PINCTRL_PIN(93, "ESPI_CLK"),
136
+
PINCTRL_PIN(94, "ESPI_RESETB"),
137
+
PINCTRL_PIN(95, "ESPI_CS1B"),
138
+
PINCTRL_PIN(96, "ESPI_CS2B"),
139
+
PINCTRL_PIN(97, "ESPI_CS3B"),
140
+
PINCTRL_PIN(98, "ESPI_ALERT0B"),
141
+
PINCTRL_PIN(99, "ESPI_ALERT1B"),
142
+
PINCTRL_PIN(100, "ESPI_ALERT2B"),
143
+
PINCTRL_PIN(101, "ESPI_ALERT3B"),
144
+
PINCTRL_PIN(102, "ESPI_CLK_LOOPBK"),
145
+
/* DIR_ESPI */
146
+
PINCTRL_PIN(103, "PWRBTNB_OUT"),
147
+
PINCTRL_PIN(104, "DMI_PERSTB"),
148
+
PINCTRL_PIN(105, "DMI_CLKREQB"),
149
+
PINCTRL_PIN(106, "DIR_ESPI_IO_0"),
150
+
PINCTRL_PIN(107, "DIR_ESPI_IO_1"),
151
+
PINCTRL_PIN(108, "DIR_ESPI_IO_2"),
152
+
PINCTRL_PIN(109, "DIR_ESPI_IO_3"),
153
+
PINCTRL_PIN(110, "DIR_ESPI_CSB"),
154
+
PINCTRL_PIN(111, "DIR_ESPI_RESETB"),
155
+
PINCTRL_PIN(112, "DIR_ESPI_CLK"),
156
+
PINCTRL_PIN(113, "DIR_ESPI_RCLK"),
157
+
PINCTRL_PIN(114, "DIR_ESPI_ALERTB"),
158
+
/* GPP_B */
159
+
PINCTRL_PIN(115, "GPP_B_0"),
160
+
PINCTRL_PIN(116, "GPP_B_1"),
161
+
PINCTRL_PIN(117, "GPP_B_2"),
162
+
PINCTRL_PIN(118, "GPP_B_3"),
163
+
PINCTRL_PIN(119, "GPP_B_4"),
164
+
PINCTRL_PIN(120, "GPP_B_5"),
165
+
PINCTRL_PIN(121, "CLKOUT_48"),
166
+
PINCTRL_PIN(122, "GPP_B_7"),
167
+
PINCTRL_PIN(123, "GPP_B_8"),
168
+
PINCTRL_PIN(124, "GPP_B_9"),
169
+
PINCTRL_PIN(125, "GPP_B_10"),
170
+
PINCTRL_PIN(126, "GPP_B_11"),
171
+
PINCTRL_PIN(127, "SLP_S0B"),
172
+
PINCTRL_PIN(128, "PLTRSTB"),
173
+
PINCTRL_PIN(129, "GPP_B_14"),
174
+
PINCTRL_PIN(130, "GPP_B_15"),
175
+
PINCTRL_PIN(131, "GPP_B_16"),
176
+
PINCTRL_PIN(132, "GPP_B_17"),
177
+
PINCTRL_PIN(133, "GPP_B_18"),
178
+
PINCTRL_PIN(134, "FUSA_DIAGTEST_EN"),
179
+
PINCTRL_PIN(135, "FUSA_DIAGTEST_MODE"),
180
+
PINCTRL_PIN(136, "GPP_B_21"),
181
+
/* SPI0 */
182
+
PINCTRL_PIN(137, "SPI0_IO_2"),
183
+
PINCTRL_PIN(138, "SPI0_IO_3"),
184
+
PINCTRL_PIN(139, "SPI0_MOSI_IO_0"),
185
+
PINCTRL_PIN(140, "SPI0_MISO_IO_1"),
186
+
PINCTRL_PIN(141, "SPI0_TPM_CSB"),
187
+
PINCTRL_PIN(142, "SPI0_FLASH_0_CSB"),
188
+
PINCTRL_PIN(143, "SPI0_FLASH_1_CSB"),
189
+
PINCTRL_PIN(144, "SPI0_CLK"),
190
+
PINCTRL_PIN(145, "SPI0_CLK_LOOPBK"),
191
+
/* GPP_C */
192
+
PINCTRL_PIN(146, "SMBCLK"),
193
+
PINCTRL_PIN(147, "SMBDATA"),
194
+
PINCTRL_PIN(148, "SMBALERTB"),
195
+
PINCTRL_PIN(149, "GPP_C_3"),
196
+
PINCTRL_PIN(150, "GPP_C_4"),
197
+
PINCTRL_PIN(151, "GPP_C_5"),
198
+
PINCTRL_PIN(152, "GPP_C_6"),
199
+
PINCTRL_PIN(153, "GPP_C_7"),
200
+
PINCTRL_PIN(154, "GPP_C_8"),
201
+
PINCTRL_PIN(155, "GPP_C_9"),
202
+
PINCTRL_PIN(156, "GPP_C_10"),
203
+
PINCTRL_PIN(157, "GPP_C_11"),
204
+
PINCTRL_PIN(158, "GPP_C_12"),
205
+
PINCTRL_PIN(159, "GPP_C_13"),
206
+
PINCTRL_PIN(160, "GPP_C_14"),
207
+
PINCTRL_PIN(161, "GPP_C_15"),
208
+
PINCTRL_PIN(162, "GPP_C_16"),
209
+
PINCTRL_PIN(163, "GPP_C_17"),
210
+
PINCTRL_PIN(164, "GPP_C_18"),
211
+
PINCTRL_PIN(165, "GPP_C_19"),
212
+
PINCTRL_PIN(166, "GPP_C_20"),
213
+
PINCTRL_PIN(167, "GPP_C_21"),
214
+
PINCTRL_PIN(168, "GPP_C_22"),
215
+
PINCTRL_PIN(169, "GPP_C_23"),
216
+
/* GPP_H */
217
+
PINCTRL_PIN(170, "GPP_H_0"),
218
+
PINCTRL_PIN(171, "GPP_H_1"),
219
+
PINCTRL_PIN(172, "GPP_H_2"),
220
+
PINCTRL_PIN(173, "GPP_H_3"),
221
+
PINCTRL_PIN(174, "GPP_H_4"),
222
+
PINCTRL_PIN(175, "GPP_H_5"),
223
+
PINCTRL_PIN(176, "GPP_H_6"),
224
+
PINCTRL_PIN(177, "GPP_H_7"),
225
+
PINCTRL_PIN(178, "GPP_H_8"),
226
+
PINCTRL_PIN(179, "GPP_H_9"),
227
+
PINCTRL_PIN(180, "GPP_H_10"),
228
+
PINCTRL_PIN(181, "GPP_H_11"),
229
+
PINCTRL_PIN(182, "GPP_H_12"),
230
+
PINCTRL_PIN(183, "GPP_H_13"),
231
+
PINCTRL_PIN(184, "GPP_H_14"),
232
+
PINCTRL_PIN(185, "GPP_H_15"),
233
+
PINCTRL_PIN(186, "GPP_H_16"),
234
+
PINCTRL_PIN(187, "GPP_H_17"),
235
+
PINCTRL_PIN(188, "GPP_H_18"),
236
+
PINCTRL_PIN(189, "GPP_H_19"),
237
+
/* vGPIO_3 */
238
+
PINCTRL_PIN(190, "CPU_PCIE_LNK_DN_0"),
239
+
PINCTRL_PIN(191, "CPU_PCIE_LNK_DN_1"),
240
+
PINCTRL_PIN(192, "CPU_PCIE_LNK_DN_2"),
241
+
PINCTRL_PIN(193, "CPU_PCIE_LNK_DN_3"),
242
+
/* vGPIO_0 */
243
+
PINCTRL_PIN(194, "ESPI_USB_OCB_0"),
244
+
PINCTRL_PIN(195, "ESPI_USB_OCB_1"),
245
+
PINCTRL_PIN(196, "ESPI_USB_OCB_2"),
246
+
PINCTRL_PIN(197, "ESPI_USB_OCB_3"),
247
+
PINCTRL_PIN(198, "USB_CPU_OCB_0"),
248
+
PINCTRL_PIN(199, "USB_CPU_OCB_1"),
249
+
PINCTRL_PIN(200, "USB_CPU_OCB_2"),
250
+
PINCTRL_PIN(201, "USB_CPU_OCB_3"),
251
+
/* vGPIO_4 */
252
+
PINCTRL_PIN(202, "ESPI_ISCLK_XTAL_CLKREQ"),
253
+
PINCTRL_PIN(203, "ISCLK_ESPI_XTAL_CLKACK"),
254
+
PINCTRL_PIN(204, "ME_SLPC_FTPM_ENABLE"),
255
+
PINCTRL_PIN(205, "GP_SLPC_DTFUS_CORE_SPITPM_DIS"),
256
+
PINCTRL_PIN(206, "GP_SLPC_SPI_STRAP_TOS"),
257
+
PINCTRL_PIN(207, "GP_SLPC_DTFUS_CORE_SPITPM_DIS_L01"),
258
+
PINCTRL_PIN(208, "GP_SLPC_SPI_STRAP_TOS_L01"),
259
+
PINCTRL_PIN(209, "LPC_PRR_TS_OVR"),
260
+
PINCTRL_PIN(210, "ITSS_KU1_SHTDWN"),
261
+
PINCTRL_PIN(211, "vGPIO_SPARE_0"),
262
+
PINCTRL_PIN(212, "vGPIO_SPARE_1"),
263
+
PINCTRL_PIN(213, "vGPIO_SPARE_2"),
264
+
PINCTRL_PIN(214, "vGPIO_SPARE_3"),
265
+
PINCTRL_PIN(215, "vGPIO_SPARE_4"),
266
+
PINCTRL_PIN(216, "vGPIO_SPARE_5"),
267
+
PINCTRL_PIN(217, "vGPIO_SPARE_6"),
268
+
PINCTRL_PIN(218, "vGPIO_SPARE_7"),
269
+
PINCTRL_PIN(219, "vGPIO_SPARE_8"),
270
+
PINCTRL_PIN(220, "vGPIO_SPARE_9"),
271
+
PINCTRL_PIN(221, "vGPIO_SPARE_10"),
272
+
PINCTRL_PIN(222, "vGPIO_SPARE_11"),
273
+
PINCTRL_PIN(223, "vGPIO_SPARE_12"),
274
+
PINCTRL_PIN(224, "vGPIO_SPARE_13"),
275
+
PINCTRL_PIN(225, "vGPIO_SPARE_14"),
276
+
PINCTRL_PIN(226, "vGPIO_SPARE_15"),
277
+
PINCTRL_PIN(227, "vGPIO_SPARE_16"),
278
+
PINCTRL_PIN(228, "vGPIO_SPARE_17"),
279
+
PINCTRL_PIN(229, "vGPIO_SPARE_18"),
280
+
PINCTRL_PIN(230, "vGPIO_SPARE_19"),
281
+
PINCTRL_PIN(231, "vGPIO_SPARE_20"),
282
+
PINCTRL_PIN(232, "vGPIO_SPARE_21"),
283
+
/* GPP_S */
284
+
PINCTRL_PIN(233, "GPP_S_0"),
285
+
PINCTRL_PIN(234, "GPP_S_1"),
286
+
PINCTRL_PIN(235, "GPP_S_2"),
287
+
PINCTRL_PIN(236, "GPP_S_3"),
288
+
PINCTRL_PIN(237, "GPP_S_4"),
289
+
PINCTRL_PIN(238, "GPP_S_5"),
290
+
PINCTRL_PIN(239, "GPP_S_6"),
291
+
PINCTRL_PIN(240, "GPP_S_7"),
292
+
/* GPP_E */
293
+
PINCTRL_PIN(241, "GPP_E_0"),
294
+
PINCTRL_PIN(242, "GPP_E_1"),
295
+
PINCTRL_PIN(243, "GPP_E_2"),
296
+
PINCTRL_PIN(244, "GPP_E_3"),
297
+
PINCTRL_PIN(245, "GPP_E_4"),
298
+
PINCTRL_PIN(246, "GPP_E_5"),
299
+
PINCTRL_PIN(247, "GPP_E_6"),
300
+
PINCTRL_PIN(248, "GPP_E_7"),
301
+
PINCTRL_PIN(249, "GPP_E_8"),
302
+
PINCTRL_PIN(250, "GPP_E_9"),
303
+
PINCTRL_PIN(251, "GPP_E_10"),
304
+
PINCTRL_PIN(252, "GPP_E_11"),
305
+
PINCTRL_PIN(253, "GPP_E_12"),
306
+
PINCTRL_PIN(254, "GPP_E_13"),
307
+
PINCTRL_PIN(255, "GPP_E_14"),
308
+
PINCTRL_PIN(256, "GPP_E_15"),
309
+
PINCTRL_PIN(257, "GPP_E_16"),
310
+
PINCTRL_PIN(258, "GPP_E_17"),
311
+
PINCTRL_PIN(259, "GPP_E_18"),
312
+
PINCTRL_PIN(260, "GPP_E_19"),
313
+
PINCTRL_PIN(261, "GPP_E_20"),
314
+
PINCTRL_PIN(262, "GPP_E_21"),
315
+
PINCTRL_PIN(263, "SPI1_CLK_LOOPBK"),
316
+
/* GPP_K */
317
+
PINCTRL_PIN(264, "GPP_K_0"),
318
+
PINCTRL_PIN(265, "GPP_K_1"),
319
+
PINCTRL_PIN(266, "GPP_K_2"),
320
+
PINCTRL_PIN(267, "GPP_K_3"),
321
+
PINCTRL_PIN(268, "GPP_K_4"),
322
+
PINCTRL_PIN(269, "GPP_K_5"),
323
+
PINCTRL_PIN(270, "FUSE_SORT_BUMP_0"),
324
+
PINCTRL_PIN(271, "FUSE_SORT_BUMP_1"),
325
+
PINCTRL_PIN(272, "CORE_VID_0"),
326
+
PINCTRL_PIN(273, "CORE_VID_1"),
327
+
PINCTRL_PIN(274, "FUSE_SORT_BUMP_2"),
328
+
PINCTRL_PIN(275, "MISC_SPARE"),
329
+
PINCTRL_PIN(276, "SYS_RESETB"),
330
+
PINCTRL_PIN(277, "MLK_RSTB"),
331
+
/* GPP_F */
332
+
PINCTRL_PIN(278, "SATAXPCIE_3"),
333
+
PINCTRL_PIN(279, "SATAXPCIE_4"),
334
+
PINCTRL_PIN(280, "SATAXPCIE_5"),
335
+
PINCTRL_PIN(281, "SATAXPCIE_6"),
336
+
PINCTRL_PIN(282, "SATAXPCIE_7"),
337
+
PINCTRL_PIN(283, "SATA_DEVSLP_3"),
338
+
PINCTRL_PIN(284, "SATA_DEVSLP_4"),
339
+
PINCTRL_PIN(285, "SATA_DEVSLP_5"),
340
+
PINCTRL_PIN(286, "SATA_DEVSLP_6"),
341
+
PINCTRL_PIN(287, "GPP_F_9"),
342
+
PINCTRL_PIN(288, "GPP_F_10"),
343
+
PINCTRL_PIN(289, "GPP_F_11"),
344
+
PINCTRL_PIN(290, "GPP_F_12"),
345
+
PINCTRL_PIN(291, "GPP_F_13"),
346
+
PINCTRL_PIN(292, "GPP_F_14"),
347
+
PINCTRL_PIN(293, "GPP_F_15"),
348
+
PINCTRL_PIN(294, "GPP_F_16"),
349
+
PINCTRL_PIN(295, "GPP_F_17"),
350
+
PINCTRL_PIN(296, "GPP_F_18"),
351
+
PINCTRL_PIN(297, "DNX_FORCE_RELOAD"),
352
+
PINCTRL_PIN(298, "GPP_F_20"),
353
+
PINCTRL_PIN(299, "GPP_F_21"),
354
+
PINCTRL_PIN(300, "GPP_F_22"),
355
+
PINCTRL_PIN(301, "GPP_F_23"),
356
+
/* GPP_I */
357
+
PINCTRL_PIN(302, "GPP_I_0"),
358
+
PINCTRL_PIN(303, "GPP_I_1"),
359
+
PINCTRL_PIN(304, "GPP_I_2"),
360
+
PINCTRL_PIN(305, "GPP_I_3"),
361
+
PINCTRL_PIN(306, "GPP_I_4"),
362
+
PINCTRL_PIN(307, "GPP_I_5"),
363
+
PINCTRL_PIN(308, "GPP_I_6"),
364
+
PINCTRL_PIN(309, "GPP_I_7"),
365
+
PINCTRL_PIN(310, "GPP_I_8"),
366
+
PINCTRL_PIN(311, "GPP_I_9"),
367
+
PINCTRL_PIN(312, "GPP_I_10"),
368
+
PINCTRL_PIN(313, "GPP_I_11"),
369
+
PINCTRL_PIN(314, "GPP_I_12"),
370
+
PINCTRL_PIN(315, "GPP_I_13"),
371
+
PINCTRL_PIN(316, "GPP_I_14"),
372
+
PINCTRL_PIN(317, "GPP_I_15"),
373
+
PINCTRL_PIN(318, "GPP_I_16"),
374
+
PINCTRL_PIN(319, "GSPI0_CLK_LOOPBK"),
375
+
PINCTRL_PIN(320, "GSPI1_CLK_LOOPBK"),
376
+
PINCTRL_PIN(321, "ISH_I3C0_CLK_LOOPBK"),
377
+
PINCTRL_PIN(322, "I3C0_CLK_LOOPBK"),
378
+
/* JTAG_CPU */
379
+
PINCTRL_PIN(323, "JTAG_TDO"),
380
+
PINCTRL_PIN(324, "JTAGX"),
381
+
PINCTRL_PIN(325, "PRDYB"),
382
+
PINCTRL_PIN(326, "PREQB"),
383
+
PINCTRL_PIN(327, "JTAG_TDI"),
384
+
PINCTRL_PIN(328, "JTAG_TMS"),
385
+
PINCTRL_PIN(329, "JTAG_TCK"),
386
+
PINCTRL_PIN(330, "DBG_PMODE"),
387
+
PINCTRL_PIN(331, "CPU_TRSTB"),
388
+
PINCTRL_PIN(332, "CPUPWRGD"),
389
+
PINCTRL_PIN(333, "PM_SPARE0"),
390
+
PINCTRL_PIN(334, "PM_SPARE1"),
391
+
PINCTRL_PIN(335, "CRASHLOG_TRIG_N"),
392
+
PINCTRL_PIN(336, "TRIGGER_IN"),
393
+
PINCTRL_PIN(337, "TRIGGER_OUT"),
394
+
PINCTRL_PIN(338, "FBRK_OUT_N"),
395
+
};
396
+
397
+
static const struct intel_padgroup mtps_community0_gpps[] = {
398
+
MTP_GPP(0, 0, 24, 0), /* GPP_D */
399
+
MTP_GPP(1, 25, 38, 32), /* GPP_R */
400
+
MTP_GPP(2, 39, 56, 64), /* GPP_J */
401
+
MTP_GPP(3, 57, 87, 96), /* vGPIO */
402
+
};
403
+
404
+
static const struct intel_padgroup mtps_community1_gpps[] = {
405
+
MTP_GPP(0, 88, 102, 128), /* GPP_A */
406
+
MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */
407
+
MTP_GPP(2, 115, 136, 192), /* GPP_B */
408
+
};
409
+
410
+
static const struct intel_padgroup mtps_community3_gpps[] = {
411
+
MTP_GPP(0, 137, 145, 224), /* SPI0 */
412
+
MTP_GPP(1, 146, 169, 256), /* GPP_C */
413
+
MTP_GPP(2, 170, 189, 288), /* GPP_H */
414
+
MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */
415
+
MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */
416
+
MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */
417
+
};
418
+
419
+
static const struct intel_padgroup mtps_community4_gpps[] = {
420
+
MTP_GPP(0, 233, 240, 416), /* GPP_S */
421
+
MTP_GPP(1, 241, 263, 448), /* GPP_E */
422
+
MTP_GPP(2, 264, 277, 480), /* GPP_K */
423
+
MTP_GPP(3, 278, 301, 512), /* GPP_F */
424
+
};
425
+
426
+
static const struct intel_padgroup mtps_community5_gpps[] = {
427
+
MTP_GPP(0, 302, 322, 544), /* GPP_I */
428
+
MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */
429
+
};
430
+
431
+
static const struct intel_community mtps_communities[] = {
432
+
MTP_COMMUNITY(0, 0, 87, mtps_community0_gpps),
433
+
MTP_COMMUNITY(1, 88, 136, mtps_community1_gpps),
434
+
MTP_COMMUNITY(2, 137, 232, mtps_community3_gpps),
435
+
MTP_COMMUNITY(3, 233, 301, mtps_community4_gpps),
436
+
MTP_COMMUNITY(4, 302, 338, mtps_community5_gpps),
437
+
};
438
+
439
+
static const struct intel_pinctrl_soc_data mtps_soc_data = {
440
+
.pins = mtps_pins,
441
+
.npins = ARRAY_SIZE(mtps_pins),
442
+
.communities = mtps_communities,
443
+
.ncommunities = ARRAY_SIZE(mtps_communities),
444
+
};
445
+
446
+
static const struct acpi_device_id mtp_pinctrl_acpi_match[] = {
447
+
{ "INTC1084", (kernel_ulong_t)&mtps_soc_data },
448
+
{ }
449
+
};
450
+
MODULE_DEVICE_TABLE(acpi, mtp_pinctrl_acpi_match);
451
+
452
+
static struct platform_driver mtp_pinctrl_driver = {
453
+
.probe = intel_pinctrl_probe_by_hid,
454
+
.driver = {
455
+
.name = "meteorpoint-pinctrl",
456
+
.acpi_match_table = mtp_pinctrl_acpi_match,
457
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
458
+
},
459
+
};
460
+
module_platform_driver(mtp_pinctrl_driver);
461
+
462
+
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
463
+
MODULE_DESCRIPTION("Intel Meteor Point PCH pinctrl/GPIO driver");
464
+
MODULE_LICENSE("GPL v2");
465
+
MODULE_IMPORT_NS(PINCTRL_INTEL);
+2
-3
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+2
-3
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
···
10
10
#include <linux/mod_devicetable.h>
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/pm.h>
13
14
14
15
#include <linux/pinctrl/pinctrl.h>
15
16
···
580
579
};
581
580
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
582
581
583
-
static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
584
-
585
582
static struct platform_driver spt_pinctrl_driver = {
586
583
.probe = intel_pinctrl_probe_by_hid,
587
584
.driver = {
588
585
.name = "sunrisepoint-pinctrl",
589
586
.acpi_match_table = spt_pinctrl_acpi_match,
590
-
.pm = &spt_pinctrl_pm_ops,
587
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
591
588
},
592
589
};
593
590
+15
-17
drivers/pinctrl/intel/pinctrl-tangier.c
+15
-17
drivers/pinctrl/intel/pinctrl-tangier.c
···
9
9
*/
10
10
11
11
#include <linux/bits.h>
12
+
#include <linux/cleanup.h>
12
13
#include <linux/device.h>
13
14
#include <linux/err.h>
14
15
#include <linux/errno.h>
···
221
220
const struct intel_pingroup *grp = &tp->groups[group];
222
221
u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
223
222
u32 mask = BUFCFG_PINMODE_MASK;
224
-
unsigned long flags;
225
223
unsigned int i;
226
224
227
225
/*
···
232
232
return -EBUSY;
233
233
}
234
234
235
+
guard(raw_spinlock_irqsave)(&tp->lock);
236
+
235
237
/* Now enable the mux setting for each pin in the group */
236
-
raw_spin_lock_irqsave(&tp->lock, flags);
237
238
for (i = 0; i < grp->grp.npins; i++)
238
239
tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask);
239
-
raw_spin_unlock_irqrestore(&tp->lock, flags);
240
240
241
241
return 0;
242
242
}
···
248
248
struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
249
249
u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
250
250
u32 mask = BUFCFG_PINMODE_MASK;
251
-
unsigned long flags;
252
251
253
252
if (!tng_buf_available(tp, pin))
254
253
return -EBUSY;
255
254
256
-
raw_spin_lock_irqsave(&tp->lock, flags);
255
+
guard(raw_spinlock_irqsave)(&tp->lock);
256
+
257
257
tng_update_bufcfg(tp, pin, bits, mask);
258
-
raw_spin_unlock_irqrestore(&tp->lock, flags);
259
258
260
259
return 0;
261
260
}
···
359
360
unsigned int param = pinconf_to_config_param(config);
360
361
unsigned int arg = pinconf_to_config_argument(config);
361
362
u32 mask, term, value = 0;
362
-
unsigned long flags;
363
363
364
364
switch (param) {
365
365
case PIN_CONFIG_BIAS_DISABLE:
···
366
368
break;
367
369
368
370
case PIN_CONFIG_BIAS_PULL_UP:
369
-
/* Set default strength value in case none is given */
370
-
if (arg == 1)
371
-
arg = 20000;
372
-
373
371
switch (arg) {
374
372
case 50000:
375
373
term = BUFCFG_PUPD_VAL_50K;
376
374
break;
375
+
case 1: /* Set default strength value in case none is given */
377
376
case 20000:
378
377
term = BUFCFG_PUPD_VAL_20K;
379
378
break;
380
379
case 2000:
381
380
term = BUFCFG_PUPD_VAL_2K;
381
+
break;
382
+
case 910:
383
+
term = BUFCFG_PUPD_VAL_910;
382
384
break;
383
385
default:
384
386
return -EINVAL;
···
389
391
break;
390
392
391
393
case PIN_CONFIG_BIAS_PULL_DOWN:
392
-
/* Set default strength value in case none is given */
393
-
if (arg == 1)
394
-
arg = 20000;
395
-
396
394
switch (arg) {
397
395
case 50000:
398
396
term = BUFCFG_PUPD_VAL_50K;
399
397
break;
398
+
case 1: /* Set default strength value in case none is given */
400
399
case 20000:
401
400
term = BUFCFG_PUPD_VAL_20K;
402
401
break;
403
402
case 2000:
404
403
term = BUFCFG_PUPD_VAL_2K;
404
+
break;
405
+
case 910:
406
+
term = BUFCFG_PUPD_VAL_910;
405
407
break;
406
408
default:
407
409
return -EINVAL;
···
430
432
return -EINVAL;
431
433
}
432
434
433
-
raw_spin_lock_irqsave(&tp->lock, flags);
435
+
guard(raw_spinlock_irqsave)(&tp->lock);
436
+
434
437
tng_update_bufcfg(tp, pin, value, mask);
435
-
raw_spin_unlock_irqrestore(&tp->lock, flags);
436
438
437
439
return 0;
438
440
}
+2
-3
drivers/pinctrl/intel/pinctrl-tigerlake.c
+2
-3
drivers/pinctrl/intel/pinctrl-tigerlake.c
···
10
10
#include <linux/mod_devicetable.h>
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/pm.h>
13
14
14
15
#include <linux/pinctrl/pinctrl.h>
15
16
···
744
743
};
745
744
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
746
745
747
-
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
748
-
749
746
static struct platform_driver tgl_pinctrl_driver = {
750
747
.probe = intel_pinctrl_probe_by_hid,
751
748
.driver = {
752
749
.name = "tigerlake-pinctrl",
753
750
.acpi_match_table = tgl_pinctrl_acpi_match,
754
-
.pm = &tgl_pinctrl_pm_ops,
751
+
.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
755
752
},
756
753
};
757
754
module_platform_driver(tgl_pinctrl_driver);
+6
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
+6
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
···
56
56
return -EINVAL;
57
57
58
58
dev_dbg(pctldev->dev, "enable function %s group %s\n",
59
-
func->name, grp->name);
59
+
func->name, grp->grp.name);
60
60
61
-
for (i = 0; i < grp->num_pins; i++) {
61
+
for (i = 0; i < grp->grp.npins; i++) {
62
62
const struct mtk_pin_desc *desc;
63
63
int *pin_modes = grp->data;
64
-
int pin = grp->pins[i];
64
+
int pin = grp->grp.pins[i];
65
65
66
66
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
67
67
if (!desc->name)
···
602
602
603
603
for (i = 0; i < hw->soc->ngrps; i++) {
604
604
const struct group_desc *group = hw->soc->grps + i;
605
+
const struct pingroup *grp = &group->grp;
605
606
606
-
err = pinctrl_generic_add_group(hw->pctrl, group->name,
607
-
group->pins, group->num_pins,
607
+
err = pinctrl_generic_add_group(hw->pctrl, grp->name, grp->pins, grp->npins,
608
608
group->data);
609
609
if (err < 0) {
610
-
dev_err(hw->dev, "Failed to register group %s\n",
611
-
group->name);
610
+
dev_err(hw->dev, "Failed to register group %s\n", grp->name);
612
611
return err;
613
612
}
614
613
}
+4
-6
drivers/pinctrl/mediatek/pinctrl-moore.h
+4
-6
drivers/pinctrl/mediatek/pinctrl-moore.h
···
37
37
.funcs = NULL, \
38
38
}
39
39
40
-
#define PINCTRL_PIN_GROUP(name, id) \
41
-
{ \
42
-
name, \
43
-
id##_pins, \
44
-
ARRAY_SIZE(id##_pins), \
45
-
id##_funcs, \
40
+
#define PINCTRL_PIN_GROUP(_name_, id) \
41
+
{ \
42
+
.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \
43
+
.data = id##_funcs, \
46
44
}
47
45
48
46
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt2701.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt2701.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt2712.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt2712.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt6795.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt6795.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8167.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8167.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8173.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8173.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8183.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8183.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8186.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8186.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8188.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8188.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8192.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8192.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8195.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8195.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8516.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt8516.c
+2
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+2
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
914
914
return mtk_eint_do_resume(pctl->eint);
915
915
}
916
916
917
-
const struct dev_pm_ops mtk_eint_pm_ops = {
918
-
.suspend_noirq = mtk_eint_suspend,
919
-
.resume_noirq = mtk_eint_resume,
917
+
EXPORT_GPL_DEV_SLEEP_PM_OPS(mtk_eint_pm_ops) = {
918
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_eint_suspend, mtk_eint_resume)
920
919
};
921
920
922
921
static int mtk_pctrl_build_state(struct platform_device *pdev)
+2
-3
drivers/pinctrl/mediatek/pinctrl-paris.c
+2
-3
drivers/pinctrl/mediatek/pinctrl-paris.c
···
1131
1131
return mtk_eint_do_resume(pctl->eint);
1132
1132
}
1133
1133
1134
-
const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
1135
-
.suspend_noirq = mtk_paris_pinctrl_suspend,
1136
-
.resume_noirq = mtk_paris_pinctrl_resume,
1134
+
EXPORT_GPL_DEV_SLEEP_PM_OPS(mtk_paris_pinctrl_pm_ops) = {
1135
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_paris_pinctrl_suspend, mtk_paris_pinctrl_resume)
1137
1136
};
1138
1137
1139
1138
MODULE_LICENSE("GPL v2");
+4
-6
drivers/pinctrl/mediatek/pinctrl-paris.h
+4
-6
drivers/pinctrl/mediatek/pinctrl-paris.h
···
49
49
__VA_ARGS__, { } }, \
50
50
}
51
51
52
-
#define PINCTRL_PIN_GROUP(name, id) \
53
-
{ \
54
-
name, \
55
-
id##_pins, \
56
-
ARRAY_SIZE(id##_pins), \
57
-
id##_funcs, \
52
+
#define PINCTRL_PIN_GROUP(_name_, id) \
53
+
{ \
54
+
.grp = PINCTRL_PINGROUP(_name_,id##_pins, ARRAY_SIZE(id##_pins)), \
55
+
.data = id##_funcs, \
58
56
}
59
57
60
58
int mtk_paris_pinctrl_probe(struct platform_device *pdev);
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
···
1790
1790
bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
1791
1791
break;
1792
1792
case PIN_CONFIG_OUTPUT:
1793
-
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1794
1793
bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
1794
+
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1795
1795
break;
1796
1796
case PIN_CONFIG_DRIVE_PUSH_PULL:
1797
1797
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
+4
-5
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+4
-5
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
···
474
474
#undef WPCM450_GRP
475
475
};
476
476
477
-
static struct group_desc wpcm450_groups[] = {
478
-
#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
479
-
.num_pins = ARRAY_SIZE(x ## _pins) }
477
+
static struct pingroup wpcm450_groups[] = {
478
+
#define WPCM450_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins))
480
479
WPCM450_GRPS
481
480
#undef WPCM450_GRP
482
481
};
···
851
852
const unsigned int **pins,
852
853
unsigned int *npins)
853
854
{
854
-
*npins = wpcm450_groups[selector].num_pins;
855
+
*npins = wpcm450_groups[selector].npins;
855
856
*pins = wpcm450_groups[selector].pins;
856
857
857
858
return 0;
···
900
901
struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
901
902
902
903
wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
903
-
wpcm450_groups[group].num_pins, function);
904
+
wpcm450_groups[group].npins, function);
904
905
905
906
return 0;
906
907
}
+8
-8
drivers/pinctrl/pinconf-generic.c
+8
-8
drivers/pinctrl/pinconf-generic.c
···
57
57
58
58
static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
59
59
struct seq_file *s, const char *gname,
60
-
unsigned pin,
60
+
unsigned int pin,
61
61
const struct pin_config_item *items,
62
62
int nitems, int *print_sep)
63
63
{
···
110
110
* to be specified the other can be NULL/0.
111
111
*/
112
112
void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s,
113
-
const char *gname, unsigned pin)
113
+
const char *gname, unsigned int pin)
114
114
{
115
115
const struct pinconf_ops *ops = pctldev->desc->confops;
116
116
int print_sep = 0;
···
295
295
296
296
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
297
297
struct device_node *np, struct pinctrl_map **map,
298
-
unsigned *reserved_maps, unsigned *num_maps,
298
+
unsigned int *reserved_maps, unsigned int *num_maps,
299
299
enum pinctrl_map_type type)
300
300
{
301
301
int ret;
302
302
const char *function;
303
303
struct device *dev = pctldev->dev;
304
304
unsigned long *configs = NULL;
305
-
unsigned num_configs = 0;
306
-
unsigned reserve, strings_count;
305
+
unsigned int num_configs = 0;
306
+
unsigned int reserve, strings_count;
307
307
struct property *prop;
308
308
const char *group;
309
309
const char *subnode_target_type = "pins";
···
379
379
380
380
int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
381
381
struct device_node *np_config, struct pinctrl_map **map,
382
-
unsigned *num_maps, enum pinctrl_map_type type)
382
+
unsigned int *num_maps, enum pinctrl_map_type type)
383
383
{
384
-
unsigned reserved_maps;
384
+
unsigned int reserved_maps;
385
385
struct device_node *np;
386
386
int ret;
387
387
···
412
412
413
413
void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev,
414
414
struct pinctrl_map *map,
415
-
unsigned num_maps)
415
+
unsigned int num_maps)
416
416
{
417
417
pinctrl_utils_free_map(pctldev, map, num_maps);
418
418
}
+7
-7
drivers/pinctrl/pinconf.c
+7
-7
drivers/pinctrl/pinconf.c
···
55
55
return 0;
56
56
}
57
57
58
-
int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
58
+
int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned int pin,
59
59
unsigned long *config)
60
60
{
61
61
const struct pinconf_ops *ops = pctldev->desc->confops;
···
199
199
return 0;
200
200
}
201
201
202
-
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
202
+
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned int pin,
203
203
unsigned long *configs, size_t nconfigs)
204
204
{
205
205
const struct pinconf_ops *ops;
···
214
214
#ifdef CONFIG_DEBUG_FS
215
215
216
216
static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev,
217
-
unsigned long *configs, unsigned num_configs)
217
+
unsigned long *configs, unsigned int num_configs)
218
218
{
219
219
const struct pinconf_ops *confops;
220
220
int i;
···
304
304
static int pinconf_pins_show(struct seq_file *s, void *what)
305
305
{
306
306
struct pinctrl_dev *pctldev = s->private;
307
-
unsigned i, pin;
307
+
unsigned int i, pin;
308
308
309
309
seq_puts(s, "Pin config settings per pin\n");
310
310
seq_puts(s, "Format: pin (name): configs\n");
···
333
333
}
334
334
335
335
static void pinconf_dump_group(struct pinctrl_dev *pctldev,
336
-
struct seq_file *s, unsigned selector,
336
+
struct seq_file *s, unsigned int selector,
337
337
const char *gname)
338
338
{
339
339
const struct pinconf_ops *ops = pctldev->desc->confops;
···
348
348
{
349
349
struct pinctrl_dev *pctldev = s->private;
350
350
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
351
-
unsigned ngroups = pctlops->get_groups_count(pctldev);
352
-
unsigned selector = 0;
351
+
unsigned int ngroups = pctlops->get_groups_count(pctldev);
352
+
unsigned int selector = 0;
353
353
354
354
seq_puts(s, "Pin config settings per pin group\n");
355
355
seq_puts(s, "Format: group (name): configs\n");
+5
-5
drivers/pinctrl/pinconf.h
+5
-5
drivers/pinctrl/pinconf.h
···
29
29
void pinconf_free_setting(const struct pinctrl_setting *setting);
30
30
int pinconf_apply_setting(const struct pinctrl_setting *setting);
31
31
32
-
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
32
+
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned int pin,
33
33
unsigned long *configs, size_t nconfigs);
34
34
35
35
/*
36
36
* You will only be interested in these if you're using PINCONF
37
37
* so don't supply any stubs for these.
38
38
*/
39
-
int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
39
+
int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned int pin,
40
40
unsigned long *config);
41
41
int pin_config_group_get(const char *dev_name, const char *pin_group,
42
42
unsigned long *config);
···
68
68
return 0;
69
69
}
70
70
71
-
static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
71
+
static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned int pin,
72
72
unsigned long *configs, size_t nconfigs)
73
73
{
74
74
return -ENOTSUPP;
···
112
112
113
113
void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev,
114
114
struct seq_file *s, const char *gname,
115
-
unsigned pin);
115
+
unsigned int pin);
116
116
117
117
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
118
118
struct seq_file *s, unsigned long config);
···
120
120
121
121
static inline void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev,
122
122
struct seq_file *s,
123
-
const char *gname, unsigned pin)
123
+
const char *gname, unsigned int pin)
124
124
{
125
125
return;
126
126
}
+2
-15
drivers/pinctrl/pinctrl-as3722.c
+2
-15
drivers/pinctrl/pinctrl-as3722.c
···
542
542
543
543
as_pci->dev = &pdev->dev;
544
544
as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
545
-
platform_set_drvdata(pdev, as_pci);
546
545
547
546
as_pci->pins = as3722_pins_desc;
548
547
as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
···
561
562
562
563
as_pci->gpio_chip = as3722_gpio_chip;
563
564
as_pci->gpio_chip.parent = &pdev->dev;
564
-
ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
565
+
ret = devm_gpiochip_add_data(&pdev->dev, &as_pci->gpio_chip, as_pci);
565
566
if (ret < 0) {
566
567
dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
567
568
return ret;
···
571
572
0, 0, AS3722_PIN_NUM);
572
573
if (ret < 0) {
573
574
dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
574
-
goto fail_range_add;
575
+
return ret;
575
576
}
576
577
577
578
return 0;
578
-
579
-
fail_range_add:
580
-
gpiochip_remove(&as_pci->gpio_chip);
581
-
return ret;
582
-
}
583
-
584
-
static void as3722_pinctrl_remove(struct platform_device *pdev)
585
-
{
586
-
struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
587
-
588
-
gpiochip_remove(&as_pci->gpio_chip);
589
579
}
590
580
591
581
static const struct of_device_id as3722_pinctrl_of_match[] = {
···
589
601
.of_match_table = as3722_pinctrl_of_match,
590
602
},
591
603
.probe = as3722_pinctrl_probe,
592
-
.remove_new = as3722_pinctrl_remove,
593
604
};
594
605
module_platform_driver(as3722_pinctrl_driver);
595
606
+315
-143
drivers/pinctrl/pinctrl-cy8c95x0.c
+315
-143
drivers/pinctrl/pinctrl-cy8c95x0.c
···
58
58
59
59
#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
60
60
61
+
#define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE)
62
+
#define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK)
63
+
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
64
+
61
65
static const struct i2c_device_id cy8c95x0_id[] = {
62
66
{ "cy8c9520", 20, },
63
67
{ "cy8c9540", 40, },
···
123
119
#define MAX_BANK 8
124
120
#define BANK_SZ 8
125
121
#define MAX_LINE (MAX_BANK * BANK_SZ)
126
-
122
+
#define MUXED_STRIDE 16
127
123
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
128
124
129
125
/**
130
126
* struct cy8c95x0_pinctrl - driver data
131
-
* @regmap: Device's regmap
127
+
* @regmap: Device's regmap. Only direct access registers.
128
+
* @muxed_regmap: Regmap for all muxed registers.
132
129
* @irq_lock: IRQ bus lock
133
130
* @i2c_lock: Mutex for the device internal mux register
134
131
* @irq_mask: I/O bits affected by interrupts
···
152
147
*/
153
148
struct cy8c95x0_pinctrl {
154
149
struct regmap *regmap;
150
+
struct regmap *muxed_regmap;
155
151
struct mutex irq_lock;
156
152
struct mutex i2c_lock;
157
153
DECLARE_BITMAP(irq_mask, MAX_LINE);
···
385
379
}
386
380
}
387
381
382
+
static bool cy8c95x0_muxed_register(unsigned int reg)
383
+
{
384
+
switch (reg) {
385
+
case CY8C95X0_INTMASK:
386
+
case CY8C95X0_PWMSEL:
387
+
case CY8C95X0_INVERT:
388
+
case CY8C95X0_DIRECTION:
389
+
case CY8C95X0_DRV_PU:
390
+
case CY8C95X0_DRV_PD:
391
+
case CY8C95X0_DRV_ODH:
392
+
case CY8C95X0_DRV_ODL:
393
+
case CY8C95X0_DRV_PP_FAST:
394
+
case CY8C95X0_DRV_PP_SLOW:
395
+
case CY8C95X0_DRV_HIZ:
396
+
return true;
397
+
default:
398
+
return false;
399
+
}
400
+
}
401
+
402
+
static bool cy8c95x0_wc_register(unsigned int reg)
403
+
{
404
+
switch (reg) {
405
+
case CY8C95X0_DRV_PU:
406
+
case CY8C95X0_DRV_PD:
407
+
case CY8C95X0_DRV_ODH:
408
+
case CY8C95X0_DRV_ODL:
409
+
case CY8C95X0_DRV_PP_FAST:
410
+
case CY8C95X0_DRV_PP_SLOW:
411
+
case CY8C95X0_DRV_HIZ:
412
+
return true;
413
+
default:
414
+
return false;
415
+
}
416
+
}
417
+
418
+
static bool cy8c95x0_quick_path_register(unsigned int reg)
419
+
{
420
+
switch (reg) {
421
+
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
422
+
case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
423
+
case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):
424
+
return true;
425
+
default:
426
+
return false;
427
+
}
428
+
}
429
+
388
430
static const struct reg_default cy8c95x0_reg_defaults[] = {
389
431
{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
390
432
{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
···
446
392
{ CY8C95X0_PWMSEL, 0 },
447
393
};
448
394
395
+
static int
396
+
cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val)
397
+
{
398
+
struct cy8c95x0_pinctrl *chip = context;
399
+
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
400
+
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
401
+
402
+
mutex_lock(&chip->i2c_lock);
403
+
/* Select the correct bank */
404
+
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
405
+
if (ret < 0)
406
+
goto out;
407
+
408
+
/*
409
+
* Read the register through direct access regmap. The target range
410
+
* is marked volatile.
411
+
*/
412
+
ret = regmap_read(chip->regmap, reg, val);
413
+
out:
414
+
mutex_unlock(&chip->i2c_lock);
415
+
416
+
return ret;
417
+
}
418
+
419
+
static int
420
+
cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val)
421
+
{
422
+
struct cy8c95x0_pinctrl *chip = context;
423
+
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
424
+
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
425
+
426
+
mutex_lock(&chip->i2c_lock);
427
+
/* Select the correct bank */
428
+
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
429
+
if (ret < 0)
430
+
goto out;
431
+
432
+
/*
433
+
* Write the register through direct access regmap. The target range
434
+
* is marked volatile.
435
+
*/
436
+
ret = regmap_write(chip->regmap, reg, val);
437
+
out:
438
+
mutex_unlock(&chip->i2c_lock);
439
+
440
+
return ret;
441
+
}
442
+
443
+
static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
444
+
{
445
+
struct i2c_client *i2c = to_i2c_client(dev);
446
+
struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(i2c);
447
+
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
448
+
u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
449
+
450
+
if (port >= chip->nport)
451
+
return false;
452
+
453
+
return cy8c95x0_muxed_register(reg);
454
+
}
455
+
456
+
static struct regmap_bus cy8c95x0_regmap_bus = {
457
+
.reg_read = cy8c95x0_mux_reg_read,
458
+
.reg_write = cy8c95x0_mux_reg_write,
459
+
};
460
+
461
+
/* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */
462
+
static const struct regmap_config cy8c95x0_muxed_regmap = {
463
+
.name = "muxed",
464
+
.reg_bits = 8,
465
+
.val_bits = 8,
466
+
.cache_type = REGCACHE_FLAT,
467
+
.use_single_read = true,
468
+
.use_single_write = true,
469
+
.max_register = MUXED_STRIDE * BANK_SZ,
470
+
.num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
471
+
.readable_reg = cy8c95x0_mux_accessible_register,
472
+
.writeable_reg = cy8c95x0_mux_accessible_register,
473
+
};
474
+
475
+
/* Direct access regmap */
449
476
static const struct regmap_config cy8c95x0_i2c_regmap = {
477
+
.name = "direct",
450
478
.reg_bits = 8,
451
479
.val_bits = 8,
452
480
···
544
408
.max_register = CY8C95X0_COMMAND,
545
409
};
546
410
411
+
static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
412
+
unsigned int reg,
413
+
unsigned int port,
414
+
unsigned int mask,
415
+
unsigned int val,
416
+
bool *change, bool async,
417
+
bool force)
418
+
{
419
+
struct regmap *regmap;
420
+
int ret, off, i, read_val;
421
+
422
+
/* Caller should never modify PORTSEL directly */
423
+
if (reg == CY8C95X0_PORTSEL)
424
+
return -EINVAL;
425
+
426
+
/* Registers behind the PORTSEL mux have their own regmap */
427
+
if (cy8c95x0_muxed_register(reg)) {
428
+
regmap = chip->muxed_regmap;
429
+
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
430
+
} else {
431
+
regmap = chip->regmap;
432
+
/* Quick path direct access registers honor the port argument */
433
+
if (cy8c95x0_quick_path_register(reg))
434
+
off = reg + port;
435
+
else
436
+
off = reg;
437
+
}
438
+
439
+
ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
440
+
if (ret < 0)
441
+
return ret;
442
+
443
+
/* Update the cache when a WC bit is written */
444
+
if (cy8c95x0_wc_register(reg) && (mask & val)) {
445
+
for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
446
+
if (i == reg)
447
+
continue;
448
+
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
449
+
450
+
ret = regmap_read(regmap, off, &read_val);
451
+
if (ret < 0)
452
+
continue;
453
+
454
+
if (!(read_val & mask & val))
455
+
continue;
456
+
457
+
regcache_cache_only(regmap, true);
458
+
regmap_update_bits(regmap, off, mask & val, 0);
459
+
regcache_cache_only(regmap, false);
460
+
}
461
+
}
462
+
463
+
return ret;
464
+
}
465
+
466
+
/**
467
+
* cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
468
+
* @chip: The pinctrl to work on
469
+
* @reg: The register to write to. Can be direct access or muxed register.
470
+
* MUST NOT be the PORTSEL register.
471
+
* @port: The port to be used for muxed registers or quick path direct access
472
+
* registers. Otherwise unused.
473
+
* @mask: Bitmask to change
474
+
* @val: New value for bitmask
475
+
*
476
+
* This function handles the register writes to the direct access registers and
477
+
* the muxed registers while caching all register accesses, internally handling
478
+
* the correct state of the PORTSEL register and protecting the access to muxed
479
+
* registers.
480
+
* The caller must only use this function to change registers behind the PORTSEL mux.
481
+
*
482
+
* Return: 0 for successful request, else a corresponding error value
483
+
*/
484
+
static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
485
+
unsigned int port, unsigned int mask, unsigned int val)
486
+
{
487
+
return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);
488
+
}
489
+
490
+
/**
491
+
* cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
492
+
* @chip: The pinctrl to work on
493
+
* @reg: The register to write to. Can be direct access or muxed register.
494
+
* MUST NOT be the PORTSEL register.
495
+
* @port: The port to be used for muxed registers or quick path direct access
496
+
* registers. Otherwise unused.
497
+
* @mask: Bitmask to change
498
+
* @val: New value for bitmask
499
+
*
500
+
* This function handles the register updates to the direct access registers and
501
+
* the muxed registers while caching all register accesses, internally handling
502
+
* the correct state of the PORTSEL register and protecting the access to muxed
503
+
* registers.
504
+
* The caller must only use this function to change registers behind the PORTSEL mux.
505
+
*
506
+
* Return: 0 for successful request, else a corresponding error value
507
+
*/
508
+
static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
509
+
unsigned int port, unsigned int mask, unsigned int val)
510
+
{
511
+
return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);
512
+
}
513
+
514
+
/**
515
+
* cy8c95x0_regmap_read() - reads a register using the regmap cache
516
+
* @chip: The pinctrl to work on
517
+
* @reg: The register to read from. Can be direct access or muxed register.
518
+
* @port: The port to be used for muxed registers or quick path direct access
519
+
* registers. Otherwise unused.
520
+
* @read_val: Value read from hardware or cache
521
+
*
522
+
* This function handles the register reads from the direct access registers and
523
+
* the muxed registers while caching all register accesses, internally handling
524
+
* the correct state of the PORTSEL register and protecting the access to muxed
525
+
* registers.
526
+
* The caller must only use this function to read registers behind the PORTSEL mux.
527
+
*
528
+
* Return: 0 for successful request, else a corresponding error value
529
+
*/
530
+
static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
531
+
unsigned int port, unsigned int *read_val)
532
+
{
533
+
struct regmap *regmap;
534
+
int off;
535
+
536
+
/* Registers behind the PORTSEL mux have their own regmap */
537
+
if (cy8c95x0_muxed_register(reg)) {
538
+
regmap = chip->muxed_regmap;
539
+
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
540
+
} else {
541
+
regmap = chip->regmap;
542
+
/* Quick path direct access registers honor the port argument */
543
+
if (cy8c95x0_quick_path_register(reg))
544
+
off = reg + port;
545
+
else
546
+
off = reg;
547
+
}
548
+
549
+
return regmap_read(regmap, off, read_val);
550
+
}
551
+
547
552
static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
548
553
unsigned long *val, unsigned long *mask)
549
554
{
···
692
415
DECLARE_BITMAP(tval, MAX_LINE);
693
416
int write_val;
694
417
int ret = 0;
695
-
int i, off = 0;
418
+
int i;
696
419
u8 bits;
697
420
698
421
/* Add the 4 bit gap of Gport2 */
···
704
427
bitmap_shift_left(tval, tval, 4, MAX_LINE);
705
428
bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
706
429
707
-
mutex_lock(&chip->i2c_lock);
708
430
for (i = 0; i < chip->nport; i++) {
709
431
/* Skip over unused banks */
710
432
bits = bitmap_get_value8(tmask, i * BANK_SZ);
711
433
if (!bits)
712
434
continue;
713
435
714
-
switch (reg) {
715
-
/* Muxed registers */
716
-
case CY8C95X0_INTMASK:
717
-
case CY8C95X0_PWMSEL:
718
-
case CY8C95X0_INVERT:
719
-
case CY8C95X0_DIRECTION:
720
-
case CY8C95X0_DRV_PU:
721
-
case CY8C95X0_DRV_PD:
722
-
case CY8C95X0_DRV_ODH:
723
-
case CY8C95X0_DRV_ODL:
724
-
case CY8C95X0_DRV_PP_FAST:
725
-
case CY8C95X0_DRV_PP_SLOW:
726
-
case CY8C95X0_DRV_HIZ:
727
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
728
-
if (ret < 0)
729
-
goto out;
730
-
off = reg;
731
-
break;
732
-
/* Direct access registers */
733
-
case CY8C95X0_INPUT:
734
-
case CY8C95X0_OUTPUT:
735
-
case CY8C95X0_INTSTATUS:
736
-
off = reg + i;
737
-
break;
738
-
default:
739
-
ret = -EINVAL;
740
-
goto out;
741
-
}
742
-
743
436
write_val = bitmap_get_value8(tval, i * BANK_SZ);
744
437
745
-
ret = regmap_update_bits(chip->regmap, off, bits, write_val);
438
+
ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);
746
439
if (ret < 0)
747
440
goto out;
748
441
}
749
442
out:
750
-
mutex_unlock(&chip->i2c_lock);
751
443
752
444
if (ret < 0)
753
-
dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
445
+
dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret);
754
446
755
447
return ret;
756
448
}
···
732
486
DECLARE_BITMAP(tmp, MAX_LINE);
733
487
int read_val;
734
488
int ret = 0;
735
-
int i, off = 0;
489
+
int i;
736
490
u8 bits;
737
491
738
492
/* Add the 4 bit gap of Gport2 */
···
744
498
bitmap_shift_left(tval, tval, 4, MAX_LINE);
745
499
bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
746
500
747
-
mutex_lock(&chip->i2c_lock);
748
501
for (i = 0; i < chip->nport; i++) {
749
502
/* Skip over unused banks */
750
503
bits = bitmap_get_value8(tmask, i * BANK_SZ);
751
504
if (!bits)
752
505
continue;
753
506
754
-
switch (reg) {
755
-
/* Muxed registers */
756
-
case CY8C95X0_INTMASK:
757
-
case CY8C95X0_PWMSEL:
758
-
case CY8C95X0_INVERT:
759
-
case CY8C95X0_DIRECTION:
760
-
case CY8C95X0_DRV_PU:
761
-
case CY8C95X0_DRV_PD:
762
-
case CY8C95X0_DRV_ODH:
763
-
case CY8C95X0_DRV_ODL:
764
-
case CY8C95X0_DRV_PP_FAST:
765
-
case CY8C95X0_DRV_PP_SLOW:
766
-
case CY8C95X0_DRV_HIZ:
767
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
768
-
if (ret < 0)
769
-
goto out;
770
-
off = reg;
771
-
break;
772
-
/* Direct access registers */
773
-
case CY8C95X0_INPUT:
774
-
case CY8C95X0_OUTPUT:
775
-
case CY8C95X0_INTSTATUS:
776
-
off = reg + i;
777
-
break;
778
-
default:
779
-
ret = -EINVAL;
780
-
goto out;
781
-
}
782
-
783
-
ret = regmap_read(chip->regmap, off, &read_val);
507
+
ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);
784
508
if (ret < 0)
785
509
goto out;
786
510
···
764
548
bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
765
549
766
550
out:
767
-
mutex_unlock(&chip->i2c_lock);
768
-
769
551
if (ret < 0)
770
-
dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
552
+
dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret);
771
553
772
554
return ret;
773
555
}
···
780
566
{
781
567
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
782
568
u8 port = cypress_get_port(chip, off);
783
-
u8 outreg = CY8C95X0_OUTPUT_(port);
784
569
u8 bit = cypress_get_pin_mask(chip, off);
785
570
int ret;
786
571
787
572
/* Set output level */
788
-
ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
573
+
ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
789
574
if (ret)
790
575
return ret;
791
576
···
794
581
static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
795
582
{
796
583
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
797
-
u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
584
+
u8 port = cypress_get_port(chip, off);
798
585
u8 bit = cypress_get_pin_mask(chip, off);
799
586
u32 reg_val;
800
587
int ret;
801
588
802
-
ret = regmap_read(chip->regmap, inreg, ®_val);
589
+
ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val);
803
590
if (ret < 0) {
804
591
/*
805
592
* NOTE:
···
817
604
int val)
818
605
{
819
606
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
820
-
u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
607
+
u8 port = cypress_get_port(chip, off);
821
608
u8 bit = cypress_get_pin_mask(chip, off);
822
609
823
-
regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
610
+
cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
824
611
}
825
612
826
613
static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
···
831
618
u32 reg_val;
832
619
int ret;
833
620
834
-
mutex_lock(&chip->i2c_lock);
835
-
836
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
621
+
ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val);
837
622
if (ret < 0)
838
623
goto out;
839
-
840
-
ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, ®_val);
841
-
if (ret < 0)
842
-
goto out;
843
-
844
-
mutex_unlock(&chip->i2c_lock);
845
624
846
625
if (reg_val & bit)
847
626
return GPIO_LINE_DIRECTION_IN;
848
627
849
628
return GPIO_LINE_DIRECTION_OUT;
850
629
out:
851
-
mutex_unlock(&chip->i2c_lock);
852
630
return ret;
853
631
}
854
632
···
854
650
u32 reg_val;
855
651
u16 arg = 0;
856
652
int ret;
857
-
858
-
mutex_lock(&chip->i2c_lock);
859
-
860
-
/* Select port */
861
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
862
-
if (ret < 0)
863
-
goto out;
864
653
865
654
switch (param) {
866
655
case PIN_CONFIG_BIAS_PULL_UP:
···
881
684
reg = CY8C95X0_PWMSEL;
882
685
break;
883
686
case PIN_CONFIG_OUTPUT:
884
-
reg = CY8C95X0_OUTPUT_(port);
687
+
reg = CY8C95X0_OUTPUT;
885
688
break;
886
689
case PIN_CONFIG_OUTPUT_ENABLE:
887
690
reg = CY8C95X0_DIRECTION;
···
909
712
* Writing 1 to one of the drive mode registers will automatically
910
713
* clear conflicting set bits in the other drive mode registers.
911
714
*/
912
-
ret = regmap_read(chip->regmap, reg, ®_val);
715
+
ret = cy8c95x0_regmap_read(chip, reg, port, ®_val);
716
+
if (ret < 0)
717
+
goto out;
718
+
913
719
if (reg_val & bit)
914
720
arg = 1;
915
721
if (param == PIN_CONFIG_OUTPUT_ENABLE)
···
920
720
921
721
*config = pinconf_to_config_packed(param, (u16)arg);
922
722
out:
923
-
mutex_unlock(&chip->i2c_lock);
924
-
925
723
return ret;
926
724
}
927
725
···
933
735
unsigned long arg = pinconf_to_config_argument(config);
934
736
unsigned int reg;
935
737
int ret;
936
-
937
-
mutex_lock(&chip->i2c_lock);
938
-
939
-
/* Select port */
940
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
941
-
if (ret < 0)
942
-
goto out;
943
738
944
739
switch (param) {
945
740
case PIN_CONFIG_BIAS_PULL_UP:
···
976
785
* Writing 1 to one of the drive mode registers will automatically
977
786
* clear conflicting set bits in the other drive mode registers.
978
787
*/
979
-
ret = regmap_write_bits(chip->regmap, reg, bit, bit);
980
-
788
+
ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);
981
789
out:
982
-
mutex_unlock(&chip->i2c_lock);
983
790
return ret;
984
791
}
985
792
···
1294
1105
{
1295
1106
u8 port = cypress_get_port(chip, off);
1296
1107
u8 bit = cypress_get_pin_mask(chip, off);
1297
-
int ret;
1298
1108
1299
-
/* Select port */
1300
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1301
-
if (ret < 0)
1302
-
return ret;
1303
-
1304
-
return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0);
1109
+
return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
1305
1110
}
1306
1111
1307
1112
static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
···
1313
1130
return 0;
1314
1131
1315
1132
/* Set direction to output & set output to 1 so that PWM can work */
1316
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1133
+
ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);
1317
1134
if (ret < 0)
1318
1135
return ret;
1319
1136
1320
-
return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1137
+
return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);
1321
1138
}
1322
1139
1323
1140
static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1324
1141
unsigned int group)
1325
1142
{
1326
1143
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1327
-
int ret;
1328
1144
1329
-
mutex_lock(&chip->i2c_lock);
1330
-
ret = cy8c95x0_pinmux_mode(chip, selector, group);
1331
-
mutex_unlock(&chip->i2c_lock);
1332
-
1333
-
return ret;
1145
+
return cy8c95x0_pinmux_mode(chip, selector, group);
1334
1146
}
1335
1147
1336
1148
static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
···
1333
1155
unsigned int pin)
1334
1156
{
1335
1157
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1336
-
int ret;
1337
1158
1338
-
mutex_lock(&chip->i2c_lock);
1339
-
ret = cy8c95x0_set_mode(chip, pin, false);
1340
-
mutex_unlock(&chip->i2c_lock);
1341
-
1342
-
return ret;
1159
+
return cy8c95x0_set_mode(chip, pin, false);
1343
1160
}
1344
1161
1345
1162
static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
···
1344
1171
u8 bit = cypress_get_pin_mask(chip, pin);
1345
1172
int ret;
1346
1173
1347
-
/* Select port... */
1348
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1349
-
if (ret)
1350
-
return ret;
1351
-
1352
-
/* ...then direction */
1353
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0);
1174
+
ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);
1354
1175
if (ret)
1355
1176
return ret;
1356
1177
···
1353
1186
* the direction register isn't sufficient in Push-Pull mode.
1354
1187
*/
1355
1188
if (input && test_bit(pin, chip->push_pull)) {
1356
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
1189
+
ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);
1357
1190
if (ret)
1358
1191
return ret;
1359
1192
···
1368
1201
unsigned int pin, bool input)
1369
1202
{
1370
1203
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1371
-
int ret;
1372
1204
1373
-
mutex_lock(&chip->i2c_lock);
1374
-
ret = cy8c95x0_pinmux_direction(chip, pin, input);
1375
-
mutex_unlock(&chip->i2c_lock);
1376
-
1377
-
return ret;
1205
+
return cy8c95x0_pinmux_direction(chip, pin, input);
1378
1206
}
1379
1207
1380
1208
static const struct pinmux_ops cy8c95x0_pmxops = {
···
1571
1409
gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1572
1410
}
1573
1411
1412
+
/* Generic regmap for direct access registers */
1574
1413
chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1575
1414
if (IS_ERR(chip->regmap)) {
1576
1415
ret = PTR_ERR(chip->regmap);
1416
+
goto err_exit;
1417
+
}
1418
+
1419
+
/* Port specific regmap behind PORTSEL mux */
1420
+
chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus,
1421
+
chip, &cy8c95x0_muxed_regmap);
1422
+
if (IS_ERR(chip->muxed_regmap)) {
1423
+
ret = dev_err_probe(&client->dev, PTR_ERR(chip->muxed_regmap),
1424
+
"Failed to register muxed regmap\n");
1577
1425
goto err_exit;
1578
1426
}
1579
1427
+21
-21
drivers/pinctrl/pinctrl-equilibrium.c
+21
-21
drivers/pinctrl/pinctrl-equilibrium.c
···
331
331
return -EINVAL;
332
332
333
333
pinmux = grp->data;
334
-
for (i = 0; i < grp->num_pins; i++)
335
-
eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
334
+
for (i = 0; i < grp->grp.npins; i++)
335
+
eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]);
336
336
337
337
return 0;
338
338
}
···
704
704
{
705
705
struct device *dev = drvdata->dev;
706
706
struct device_node *node = dev->of_node;
707
-
unsigned int *pinmux, pin_id, pinmux_id;
708
-
struct group_desc group;
707
+
unsigned int *pins, *pinmux, pin_id, pinmux_id;
708
+
struct pingroup group, *grp = &group;
709
709
struct device_node *np;
710
710
struct property *prop;
711
711
int j, err;
···
715
715
if (!prop)
716
716
continue;
717
717
718
-
group.num_pins = of_property_count_u32_elems(np, "pins");
719
-
if (group.num_pins < 0) {
718
+
err = of_property_count_u32_elems(np, "pins");
719
+
if (err < 0) {
720
720
dev_err(dev, "No pins in the group: %s\n", prop->name);
721
721
of_node_put(np);
722
-
return -EINVAL;
722
+
return err;
723
723
}
724
-
group.name = prop->value;
725
-
group.pins = devm_kcalloc(dev, group.num_pins,
726
-
sizeof(*(group.pins)), GFP_KERNEL);
727
-
if (!group.pins) {
724
+
grp->npins = err;
725
+
grp->name = prop->value;
726
+
pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL);
727
+
if (!pins) {
728
728
of_node_put(np);
729
729
return -ENOMEM;
730
730
}
731
+
grp->pins = pins;
731
732
732
-
pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
733
-
GFP_KERNEL);
733
+
pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL);
734
734
if (!pinmux) {
735
735
of_node_put(np);
736
736
return -ENOMEM;
737
737
}
738
738
739
-
for (j = 0; j < group.num_pins; j++) {
739
+
for (j = 0; j < grp->npins; j++) {
740
740
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
741
741
dev_err(dev, "Group %s: Read intel pins id failed\n",
742
-
group.name);
742
+
grp->name);
743
743
of_node_put(np);
744
744
return -EINVAL;
745
745
}
746
746
if (pin_id >= drvdata->pctl_desc.npins) {
747
747
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
748
-
group.name, j, pin_id);
748
+
grp->name, j, pin_id);
749
749
of_node_put(np);
750
750
return -EINVAL;
751
751
}
752
-
group.pins[j] = pin_id;
752
+
pins[j] = pin_id;
753
753
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
754
754
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
755
-
group.name);
755
+
grp->name);
756
756
of_node_put(np);
757
757
return -EINVAL;
758
758
}
759
759
pinmux[j] = pinmux_id;
760
760
}
761
761
762
-
err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
763
-
group.pins, group.num_pins,
762
+
err = pinctrl_generic_add_group(drvdata->pctl_dev,
763
+
grp->name, grp->pins, grp->npins,
764
764
pinmux);
765
765
if (err < 0) {
766
-
dev_err(dev, "Failed to register group %s\n", group.name);
766
+
dev_err(dev, "Failed to register group %s\n", grp->name);
767
767
of_node_put(np);
768
768
return err;
769
769
}
+18
-17
drivers/pinctrl/pinctrl-ingenic.c
+18
-17
drivers/pinctrl/pinctrl-ingenic.c
···
82
82
#define PINS_PER_GPIO_CHIP 32
83
83
#define JZ4730_PINS_PER_PAIRED_REG 16
84
84
85
-
#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
86
-
{ \
87
-
name, \
88
-
id##_pins, \
89
-
ARRAY_SIZE(id##_pins), \
90
-
funcs, \
85
+
#define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs) \
86
+
{ \
87
+
.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \
88
+
.data = funcs, \
91
89
}
92
90
93
-
#define INGENIC_PIN_GROUP(name, id, func) \
94
-
INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
91
+
#define INGENIC_PIN_GROUP(_name_, id, func) \
92
+
{ \
93
+
.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \
94
+
.data = (void *)func, \
95
+
}
95
96
96
97
enum jz_version {
97
98
ID_JZ4730,
···
3762
3761
return -EINVAL;
3763
3762
3764
3763
dev_dbg(pctldev->dev, "enable function %s group %s\n",
3765
-
func->name, grp->name);
3764
+
func->name, grp->grp.name);
3766
3765
3767
3766
mode = (uintptr_t)grp->data;
3768
3767
if (mode <= 3) {
3769
-
for (i = 0; i < grp->num_pins; i++)
3770
-
ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
3768
+
for (i = 0; i < grp->grp.npins; i++)
3769
+
ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);
3771
3770
} else {
3772
3771
pin_modes = grp->data;
3773
3772
3774
-
for (i = 0; i < grp->num_pins; i++)
3775
-
ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
3773
+
for (i = 0; i < grp->grp.npins; i++)
3774
+
ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);
3776
3775
}
3777
3776
3778
3777
return 0;
···
4299
4298
4300
4299
for (i = 0; i < chip_info->num_groups; i++) {
4301
4300
const struct group_desc *group = &chip_info->groups[i];
4301
+
const struct pingroup *grp = &group->grp;
4302
4302
4303
-
err = pinctrl_generic_add_group(jzpc->pctl, group->name,
4304
-
group->pins, group->num_pins, group->data);
4303
+
err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,
4304
+
group->data);
4305
4305
if (err < 0) {
4306
-
dev_err(dev, "Failed to register group %s\n",
4307
-
group->name);
4306
+
dev_err(dev, "Failed to register group %s\n", grp->name);
4308
4307
return err;
4309
4308
}
4310
4309
}
+3
-3
drivers/pinctrl/pinctrl-keembay.c
+3
-3
drivers/pinctrl/pinctrl-keembay.c
···
945
945
return -EINVAL;
946
946
947
947
/* Change modes for pins in the selected group */
948
-
pin = *grp->pins;
948
+
pin = *grp->grp.pins;
949
949
pin_mode = *(u8 *)(func->data);
950
950
951
951
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
···
1517
1517
1518
1518
static int keembay_build_groups(struct keembay_pinctrl *kpc)
1519
1519
{
1520
-
struct group_desc *grp;
1520
+
struct pingroup *grp;
1521
1521
unsigned int i;
1522
1522
1523
1523
kpc->ngroups = kpc->npins;
···
1528
1528
/* Each pin is categorised as one group */
1529
1529
for (i = 0; i < kpc->ngroups; i++) {
1530
1530
const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
1531
-
struct group_desc *kmb_grp = grp + i;
1531
+
struct pingroup *kmb_grp = grp + i;
1532
1532
1533
1533
kmb_grp->name = pdesc->name;
1534
1534
kmb_grp->pins = (int *)&pdesc->number;
+5
drivers/pinctrl/pinctrl-single.c
+5
drivers/pinctrl/pinctrl-single.c
···
1955
1955
.irq_status_mask = (1 << 30), /* WKUP_EVT */
1956
1956
};
1957
1957
1958
+
static const struct pcs_soc_data pinctrl_single_j7200 = {
1959
+
.flags = PCS_CONTEXT_LOSS_OFF,
1960
+
};
1961
+
1958
1962
static const struct pcs_soc_data pinctrl_single = {
1959
1963
};
1960
1964
···
1973
1969
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1974
1970
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1975
1971
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1972
+
{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
1976
1973
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
1977
1974
{ .compatible = "pinconf-single", .data = &pinconf_single },
1978
1975
{ },
+373
drivers/pinctrl/pinctrl-tps6594.c
+373
drivers/pinctrl/pinctrl-tps6594.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Pinmux and GPIO driver for tps6594 PMIC
4
+
*
5
+
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6
+
*/
7
+
8
+
#include <linux/gpio/driver.h>
9
+
#include <linux/gpio/regmap.h>
10
+
#include <linux/module.h>
11
+
#include <linux/pinctrl/pinmux.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/mod_devicetable.h>
14
+
15
+
#include <linux/mfd/tps6594.h>
16
+
17
+
#define TPS6594_PINCTRL_PINS_NB 11
18
+
19
+
#define TPS6594_PINCTRL_GPIO_FUNCTION 0
20
+
#define TPS6594_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION 1
21
+
#define TPS6594_PINCTRL_TRIG_WDOG_FUNCTION 1
22
+
#define TPS6594_PINCTRL_CLK32KOUT_FUNCTION 1
23
+
#define TPS6594_PINCTRL_SCLK_SPMI_FUNCTION 1
24
+
#define TPS6594_PINCTRL_SDATA_SPMI_FUNCTION 1
25
+
#define TPS6594_PINCTRL_NERR_MCU_FUNCTION 1
26
+
#define TPS6594_PINCTRL_PDOG_FUNCTION 1
27
+
#define TPS6594_PINCTRL_SYNCCLKIN_FUNCTION 1
28
+
#define TPS6594_PINCTRL_NRSTOUT_SOC_FUNCTION 2
29
+
#define TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION 2
30
+
#define TPS6594_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION 2
31
+
#define TPS6594_PINCTRL_NERR_SOC_FUNCTION 2
32
+
#define TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION 3
33
+
#define TPS6594_PINCTRL_NSLEEP1_FUNCTION 4
34
+
#define TPS6594_PINCTRL_NSLEEP2_FUNCTION 5
35
+
#define TPS6594_PINCTRL_WKUP1_FUNCTION 6
36
+
#define TPS6594_PINCTRL_WKUP2_FUNCTION 7
37
+
38
+
/* Special muxval for recalcitrant pins */
39
+
#define TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8 2
40
+
#define TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8 3
41
+
#define TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9 3
42
+
43
+
#define TPS6594_OFFSET_GPIO_SEL 5
44
+
45
+
#define FUNCTION(fname, v) \
46
+
{ \
47
+
.pinfunction = PINCTRL_PINFUNCTION(#fname, \
48
+
tps6594_##fname##_func_group_names, \
49
+
ARRAY_SIZE(tps6594_##fname##_func_group_names)),\
50
+
.muxval = v, \
51
+
}
52
+
53
+
static const struct pinctrl_pin_desc tps6594_pins[TPS6594_PINCTRL_PINS_NB] = {
54
+
PINCTRL_PIN(0, "GPIO0"), PINCTRL_PIN(1, "GPIO1"),
55
+
PINCTRL_PIN(2, "GPIO2"), PINCTRL_PIN(3, "GPIO3"),
56
+
PINCTRL_PIN(4, "GPIO4"), PINCTRL_PIN(5, "GPIO5"),
57
+
PINCTRL_PIN(6, "GPIO6"), PINCTRL_PIN(7, "GPIO7"),
58
+
PINCTRL_PIN(8, "GPIO8"), PINCTRL_PIN(9, "GPIO9"),
59
+
PINCTRL_PIN(10, "GPIO10"),
60
+
};
61
+
62
+
static const char *const tps6594_gpio_func_group_names[] = {
63
+
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
64
+
"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
65
+
};
66
+
67
+
static const char *const tps6594_nsleep1_func_group_names[] = {
68
+
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
69
+
"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
70
+
};
71
+
72
+
static const char *const tps6594_nsleep2_func_group_names[] = {
73
+
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
74
+
"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
75
+
};
76
+
77
+
static const char *const tps6594_wkup1_func_group_names[] = {
78
+
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
79
+
"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
80
+
};
81
+
82
+
static const char *const tps6594_wkup2_func_group_names[] = {
83
+
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
84
+
"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
85
+
};
86
+
87
+
static const char *const tps6594_scl_i2c2_cs_spi_func_group_names[] = {
88
+
"GPIO0",
89
+
"GPIO1",
90
+
};
91
+
92
+
static const char *const tps6594_nrstout_soc_func_group_names[] = {
93
+
"GPIO0",
94
+
"GPIO10",
95
+
};
96
+
97
+
static const char *const tps6594_trig_wdog_func_group_names[] = {
98
+
"GPIO1",
99
+
"GPIO10",
100
+
};
101
+
102
+
static const char *const tps6594_sda_i2c2_sdo_spi_func_group_names[] = {
103
+
"GPIO1",
104
+
};
105
+
106
+
static const char *const tps6594_clk32kout_func_group_names[] = {
107
+
"GPIO2",
108
+
"GPIO3",
109
+
"GPIO7",
110
+
};
111
+
112
+
static const char *const tps6594_nerr_soc_func_group_names[] = {
113
+
"GPIO2",
114
+
};
115
+
116
+
static const char *const tps6594_sclk_spmi_func_group_names[] = {
117
+
"GPIO4",
118
+
};
119
+
120
+
static const char *const tps6594_sdata_spmi_func_group_names[] = {
121
+
"GPIO5",
122
+
};
123
+
124
+
static const char *const tps6594_nerr_mcu_func_group_names[] = {
125
+
"GPIO6",
126
+
};
127
+
128
+
static const char *const tps6594_syncclkout_func_group_names[] = {
129
+
"GPIO7",
130
+
"GPIO9",
131
+
};
132
+
133
+
static const char *const tps6594_disable_wdog_func_group_names[] = {
134
+
"GPIO7",
135
+
"GPIO8",
136
+
};
137
+
138
+
static const char *const tps6594_pdog_func_group_names[] = {
139
+
"GPIO8",
140
+
};
141
+
142
+
static const char *const tps6594_syncclkin_func_group_names[] = {
143
+
"GPIO9",
144
+
};
145
+
146
+
struct tps6594_pinctrl_function {
147
+
struct pinfunction pinfunction;
148
+
u8 muxval;
149
+
};
150
+
151
+
static const struct tps6594_pinctrl_function pinctrl_functions[] = {
152
+
FUNCTION(gpio, TPS6594_PINCTRL_GPIO_FUNCTION),
153
+
FUNCTION(nsleep1, TPS6594_PINCTRL_NSLEEP1_FUNCTION),
154
+
FUNCTION(nsleep2, TPS6594_PINCTRL_NSLEEP2_FUNCTION),
155
+
FUNCTION(wkup1, TPS6594_PINCTRL_WKUP1_FUNCTION),
156
+
FUNCTION(wkup2, TPS6594_PINCTRL_WKUP2_FUNCTION),
157
+
FUNCTION(scl_i2c2_cs_spi, TPS6594_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION),
158
+
FUNCTION(nrstout_soc, TPS6594_PINCTRL_NRSTOUT_SOC_FUNCTION),
159
+
FUNCTION(trig_wdog, TPS6594_PINCTRL_TRIG_WDOG_FUNCTION),
160
+
FUNCTION(sda_i2c2_sdo_spi, TPS6594_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION),
161
+
FUNCTION(clk32kout, TPS6594_PINCTRL_CLK32KOUT_FUNCTION),
162
+
FUNCTION(nerr_soc, TPS6594_PINCTRL_NERR_SOC_FUNCTION),
163
+
FUNCTION(sclk_spmi, TPS6594_PINCTRL_SCLK_SPMI_FUNCTION),
164
+
FUNCTION(sdata_spmi, TPS6594_PINCTRL_SDATA_SPMI_FUNCTION),
165
+
FUNCTION(nerr_mcu, TPS6594_PINCTRL_NERR_MCU_FUNCTION),
166
+
FUNCTION(syncclkout, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION),
167
+
FUNCTION(disable_wdog, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION),
168
+
FUNCTION(pdog, TPS6594_PINCTRL_PDOG_FUNCTION),
169
+
FUNCTION(syncclkin, TPS6594_PINCTRL_SYNCCLKIN_FUNCTION),
170
+
};
171
+
172
+
struct tps6594_pinctrl {
173
+
struct tps6594 *tps;
174
+
struct gpio_regmap *gpio_regmap;
175
+
struct pinctrl_dev *pctl_dev;
176
+
const struct tps6594_pinctrl_function *funcs;
177
+
const struct pinctrl_pin_desc *pins;
178
+
};
179
+
180
+
static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio,
181
+
unsigned int base, unsigned int offset,
182
+
unsigned int *reg, unsigned int *mask)
183
+
{
184
+
unsigned int line = offset % 8;
185
+
unsigned int stride = offset / 8;
186
+
187
+
switch (base) {
188
+
case TPS6594_REG_GPIOX_CONF(0):
189
+
*reg = TPS6594_REG_GPIOX_CONF(offset);
190
+
*mask = TPS6594_BIT_GPIO_DIR;
191
+
return 0;
192
+
case TPS6594_REG_GPIO_IN_1:
193
+
case TPS6594_REG_GPIO_OUT_1:
194
+
*reg = base + stride;
195
+
*mask = BIT(line);
196
+
return 0;
197
+
default:
198
+
return -EINVAL;
199
+
}
200
+
}
201
+
202
+
static int tps6594_pmx_func_cnt(struct pinctrl_dev *pctldev)
203
+
{
204
+
return ARRAY_SIZE(pinctrl_functions);
205
+
}
206
+
207
+
static const char *tps6594_pmx_func_name(struct pinctrl_dev *pctldev,
208
+
unsigned int selector)
209
+
{
210
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
211
+
212
+
return pinctrl->funcs[selector].pinfunction.name;
213
+
}
214
+
215
+
static int tps6594_pmx_func_groups(struct pinctrl_dev *pctldev,
216
+
unsigned int selector,
217
+
const char *const **groups,
218
+
unsigned int *num_groups)
219
+
{
220
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
221
+
222
+
*groups = pinctrl->funcs[selector].pinfunction.groups;
223
+
*num_groups = pinctrl->funcs[selector].pinfunction.ngroups;
224
+
225
+
return 0;
226
+
}
227
+
228
+
static int tps6594_pmx_set(struct tps6594_pinctrl *pinctrl, unsigned int pin,
229
+
u8 muxval)
230
+
{
231
+
u8 mux_sel_val = muxval << TPS6594_OFFSET_GPIO_SEL;
232
+
233
+
return regmap_update_bits(pinctrl->tps->regmap,
234
+
TPS6594_REG_GPIOX_CONF(pin),
235
+
TPS6594_MASK_GPIO_SEL, mux_sel_val);
236
+
}
237
+
238
+
static int tps6594_pmx_set_mux(struct pinctrl_dev *pctldev,
239
+
unsigned int function, unsigned int group)
240
+
{
241
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
242
+
u8 muxval = pinctrl->funcs[function].muxval;
243
+
244
+
/* Some pins don't have the same muxval for the same function... */
245
+
if (group == 8) {
246
+
if (muxval == TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION)
247
+
muxval = TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8;
248
+
else if (muxval == TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION)
249
+
muxval = TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8;
250
+
} else if (group == 9) {
251
+
if (muxval == TPS6594_PINCTRL_CLK32KOUT_FUNCTION)
252
+
muxval = TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9;
253
+
}
254
+
255
+
return tps6594_pmx_set(pinctrl, group, muxval);
256
+
}
257
+
258
+
static int tps6594_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
259
+
struct pinctrl_gpio_range *range,
260
+
unsigned int offset, bool input)
261
+
{
262
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
263
+
u8 muxval = pinctrl->funcs[TPS6594_PINCTRL_GPIO_FUNCTION].muxval;
264
+
265
+
return tps6594_pmx_set(pinctrl, offset, muxval);
266
+
}
267
+
268
+
static const struct pinmux_ops tps6594_pmx_ops = {
269
+
.get_functions_count = tps6594_pmx_func_cnt,
270
+
.get_function_name = tps6594_pmx_func_name,
271
+
.get_function_groups = tps6594_pmx_func_groups,
272
+
.set_mux = tps6594_pmx_set_mux,
273
+
.gpio_set_direction = tps6594_pmx_gpio_set_direction,
274
+
.strict = true,
275
+
};
276
+
277
+
static int tps6594_groups_cnt(struct pinctrl_dev *pctldev)
278
+
{
279
+
return ARRAY_SIZE(tps6594_pins);
280
+
}
281
+
282
+
static int tps6594_group_pins(struct pinctrl_dev *pctldev,
283
+
unsigned int selector, const unsigned int **pins,
284
+
unsigned int *num_pins)
285
+
{
286
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
287
+
288
+
*pins = &pinctrl->pins[selector].number;
289
+
*num_pins = 1;
290
+
291
+
return 0;
292
+
}
293
+
294
+
static const char *tps6594_group_name(struct pinctrl_dev *pctldev,
295
+
unsigned int selector)
296
+
{
297
+
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
298
+
299
+
return pinctrl->pins[selector].name;
300
+
}
301
+
302
+
static const struct pinctrl_ops tps6594_pctrl_ops = {
303
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
304
+
.dt_free_map = pinconf_generic_dt_free_map,
305
+
.get_groups_count = tps6594_groups_cnt,
306
+
.get_group_name = tps6594_group_name,
307
+
.get_group_pins = tps6594_group_pins,
308
+
};
309
+
310
+
static int tps6594_pinctrl_probe(struct platform_device *pdev)
311
+
{
312
+
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
313
+
struct device *dev = &pdev->dev;
314
+
struct tps6594_pinctrl *pinctrl;
315
+
struct pinctrl_desc *pctrl_desc;
316
+
struct gpio_regmap_config config = {};
317
+
318
+
pctrl_desc = devm_kzalloc(dev, sizeof(*pctrl_desc), GFP_KERNEL);
319
+
if (!pctrl_desc)
320
+
return -ENOMEM;
321
+
pctrl_desc->name = dev_name(dev);
322
+
pctrl_desc->owner = THIS_MODULE;
323
+
pctrl_desc->pins = tps6594_pins;
324
+
pctrl_desc->npins = ARRAY_SIZE(tps6594_pins);
325
+
pctrl_desc->pctlops = &tps6594_pctrl_ops;
326
+
pctrl_desc->pmxops = &tps6594_pmx_ops;
327
+
328
+
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
329
+
if (!pinctrl)
330
+
return -ENOMEM;
331
+
pinctrl->tps = dev_get_drvdata(dev->parent);
332
+
pinctrl->funcs = pinctrl_functions;
333
+
pinctrl->pins = tps6594_pins;
334
+
pinctrl->pctl_dev = devm_pinctrl_register(dev, pctrl_desc, pinctrl);
335
+
if (IS_ERR(pinctrl->pctl_dev))
336
+
return dev_err_probe(dev, PTR_ERR(pinctrl->pctl_dev),
337
+
"Couldn't register pinctrl driver\n");
338
+
339
+
config.parent = tps->dev;
340
+
config.regmap = tps->regmap;
341
+
config.ngpio = TPS6594_PINCTRL_PINS_NB;
342
+
config.ngpio_per_reg = 8;
343
+
config.reg_dat_base = TPS6594_REG_GPIO_IN_1;
344
+
config.reg_set_base = TPS6594_REG_GPIO_OUT_1;
345
+
config.reg_dir_out_base = TPS6594_REG_GPIOX_CONF(0);
346
+
config.reg_mask_xlate = tps6594_gpio_regmap_xlate;
347
+
348
+
pinctrl->gpio_regmap = devm_gpio_regmap_register(dev, &config);
349
+
if (IS_ERR(pinctrl->gpio_regmap))
350
+
return dev_err_probe(dev, PTR_ERR(pinctrl->gpio_regmap),
351
+
"Couldn't register gpio_regmap driver\n");
352
+
353
+
return 0;
354
+
}
355
+
356
+
static const struct platform_device_id tps6594_pinctrl_id_table[] = {
357
+
{ "tps6594-pinctrl", },
358
+
{}
359
+
};
360
+
MODULE_DEVICE_TABLE(platform, tps6594_pinctrl_id_table);
361
+
362
+
static struct platform_driver tps6594_pinctrl_driver = {
363
+
.probe = tps6594_pinctrl_probe,
364
+
.driver = {
365
+
.name = "tps6594-pinctrl",
366
+
},
367
+
.id_table = tps6594_pinctrl_id_table,
368
+
};
369
+
module_platform_driver(tps6594_pinctrl_driver);
370
+
371
+
MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");
372
+
MODULE_DESCRIPTION("TPS6594 pinctrl and GPIO driver");
373
+
MODULE_LICENSE("GPL");
+13
-13
drivers/pinctrl/pinctrl-utils.c
+13
-13
drivers/pinctrl/pinctrl-utils.c
···
18
18
#include "pinctrl-utils.h"
19
19
20
20
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
21
-
struct pinctrl_map **map, unsigned *reserved_maps,
22
-
unsigned *num_maps, unsigned reserve)
21
+
struct pinctrl_map **map, unsigned int *reserved_maps,
22
+
unsigned int *num_maps, unsigned int reserve)
23
23
{
24
-
unsigned old_num = *reserved_maps;
25
-
unsigned new_num = *num_maps + reserve;
24
+
unsigned int old_num = *reserved_maps;
25
+
unsigned int new_num = *num_maps + reserve;
26
26
struct pinctrl_map *new_map;
27
27
28
28
if (old_num >= new_num)
···
43
43
EXPORT_SYMBOL_GPL(pinctrl_utils_reserve_map);
44
44
45
45
int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev,
46
-
struct pinctrl_map **map, unsigned *reserved_maps,
47
-
unsigned *num_maps, const char *group,
46
+
struct pinctrl_map **map, unsigned int *reserved_maps,
47
+
unsigned int *num_maps, const char *group,
48
48
const char *function)
49
49
{
50
50
if (WARN_ON(*num_maps == *reserved_maps))
···
60
60
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_mux);
61
61
62
62
int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
63
-
struct pinctrl_map **map, unsigned *reserved_maps,
64
-
unsigned *num_maps, const char *group,
65
-
unsigned long *configs, unsigned num_configs,
63
+
struct pinctrl_map **map, unsigned int *reserved_maps,
64
+
unsigned int *num_maps, const char *group,
65
+
unsigned long *configs, unsigned int num_configs,
66
66
enum pinctrl_map_type type)
67
67
{
68
68
unsigned long *dup_configs;
···
86
86
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_configs);
87
87
88
88
int pinctrl_utils_add_config(struct pinctrl_dev *pctldev,
89
-
unsigned long **configs, unsigned *num_configs,
89
+
unsigned long **configs, unsigned int *num_configs,
90
90
unsigned long config)
91
91
{
92
-
unsigned old_num = *num_configs;
93
-
unsigned new_num = old_num + 1;
92
+
unsigned int old_num = *num_configs;
93
+
unsigned int new_num = old_num + 1;
94
94
unsigned long *new_configs;
95
95
96
96
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
···
110
110
EXPORT_SYMBOL_GPL(pinctrl_utils_add_config);
111
111
112
112
void pinctrl_utils_free_map(struct pinctrl_dev *pctldev,
113
-
struct pinctrl_map *map, unsigned num_maps)
113
+
struct pinctrl_map *map, unsigned int num_maps)
114
114
{
115
115
int i;
116
116
+9
-9
drivers/pinctrl/pinctrl-utils.h
+9
-9
drivers/pinctrl/pinctrl-utils.h
···
15
15
struct pinctrl_map;
16
16
17
17
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
18
-
struct pinctrl_map **map, unsigned *reserved_maps,
19
-
unsigned *num_maps, unsigned reserve);
18
+
struct pinctrl_map **map, unsigned int *reserved_maps,
19
+
unsigned int *num_maps, unsigned int reserve);
20
20
int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev,
21
-
struct pinctrl_map **map, unsigned *reserved_maps,
22
-
unsigned *num_maps, const char *group,
21
+
struct pinctrl_map **map, unsigned int *reserved_maps,
22
+
unsigned int *num_maps, const char *group,
23
23
const char *function);
24
24
int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
25
-
struct pinctrl_map **map, unsigned *reserved_maps,
26
-
unsigned *num_maps, const char *group,
27
-
unsigned long *configs, unsigned num_configs,
25
+
struct pinctrl_map **map, unsigned int *reserved_maps,
26
+
unsigned int *num_maps, const char *group,
27
+
unsigned long *configs, unsigned int num_configs,
28
28
enum pinctrl_map_type type);
29
29
int pinctrl_utils_add_config(struct pinctrl_dev *pctldev,
30
-
unsigned long **configs, unsigned *num_configs,
30
+
unsigned long **configs, unsigned int *num_configs,
31
31
unsigned long config);
32
32
void pinctrl_utils_free_map(struct pinctrl_dev *pctldev,
33
-
struct pinctrl_map *map, unsigned num_maps);
33
+
struct pinctrl_map *map, unsigned int num_maps);
34
34
35
35
#endif /* __PINCTRL_UTILS_H__ */
+18
-18
drivers/pinctrl/pinmux.c
+18
-18
drivers/pinctrl/pinmux.c
···
35
35
int pinmux_check_ops(struct pinctrl_dev *pctldev)
36
36
{
37
37
const struct pinmux_ops *ops = pctldev->desc->pmxops;
38
-
unsigned nfuncs;
39
-
unsigned selector = 0;
38
+
unsigned int nfuncs;
39
+
unsigned int selector = 0;
40
40
41
41
/* Check that we implement required operations */
42
42
if (!ops ||
···
84
84
* Controllers not defined as strict will always return true,
85
85
* menaning that the gpio can be used.
86
86
*/
87
-
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin)
87
+
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned int pin)
88
88
{
89
89
struct pin_desc *desc = pin_desc_get(pctldev, pin);
90
90
const struct pinmux_ops *ops = pctldev->desc->pmxops;
···
262
262
*/
263
263
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
264
264
struct pinctrl_gpio_range *range,
265
-
unsigned pin, unsigned gpio)
265
+
unsigned int pin, unsigned int gpio)
266
266
{
267
267
const char *owner;
268
268
int ret;
···
285
285
* @pin: the affected currently GPIO-muxed in pin
286
286
* @range: applicable GPIO range
287
287
*/
288
-
void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin,
288
+
void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned int pin,
289
289
struct pinctrl_gpio_range *range)
290
290
{
291
291
const char *owner;
···
303
303
*/
304
304
int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
305
305
struct pinctrl_gpio_range *range,
306
-
unsigned pin, bool input)
306
+
unsigned int pin, bool input)
307
307
{
308
308
const struct pinmux_ops *ops;
309
309
int ret;
···
322
322
const char *function)
323
323
{
324
324
const struct pinmux_ops *ops = pctldev->desc->pmxops;
325
-
unsigned nfuncs = ops->get_functions_count(pctldev);
326
-
unsigned selector = 0;
325
+
unsigned int nfuncs = ops->get_functions_count(pctldev);
326
+
unsigned int selector = 0;
327
327
328
328
/* See if this pctldev has this function */
329
329
while (selector < nfuncs) {
···
344
344
struct pinctrl_dev *pctldev = setting->pctldev;
345
345
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
346
346
char const * const *groups;
347
-
unsigned num_groups;
347
+
unsigned int num_groups;
348
348
int ret;
349
349
const char *group;
350
350
···
409
409
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
410
410
const struct pinmux_ops *ops = pctldev->desc->pmxops;
411
411
int ret = 0;
412
-
const unsigned *pins = NULL;
413
-
unsigned num_pins = 0;
412
+
const unsigned int *pins = NULL;
413
+
unsigned int num_pins = 0;
414
414
int i;
415
415
struct pin_desc *desc;
416
416
···
489
489
struct pinctrl_dev *pctldev = setting->pctldev;
490
490
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
491
491
int ret = 0;
492
-
const unsigned *pins = NULL;
493
-
unsigned num_pins = 0;
492
+
const unsigned int *pins = NULL;
493
+
unsigned int num_pins = 0;
494
494
int i;
495
495
struct pin_desc *desc;
496
496
···
541
541
{
542
542
struct pinctrl_dev *pctldev = s->private;
543
543
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
544
-
unsigned nfuncs;
545
-
unsigned func_selector = 0;
544
+
unsigned int nfuncs;
545
+
unsigned int func_selector = 0;
546
546
547
547
if (!pmxops)
548
548
return 0;
···
553
553
const char *func = pmxops->get_function_name(pctldev,
554
554
func_selector);
555
555
const char * const *groups;
556
-
unsigned num_groups;
556
+
unsigned int num_groups;
557
557
int ret;
558
558
int i;
559
559
···
584
584
struct pinctrl_dev *pctldev = s->private;
585
585
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
586
586
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
587
-
unsigned i, pin;
587
+
unsigned int i, pin;
588
588
589
589
if (!pmxops)
590
590
return 0;
···
818
818
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
819
819
unsigned int selector,
820
820
const char * const **groups,
821
-
unsigned * const num_groups)
821
+
unsigned int * const num_groups)
822
822
{
823
823
struct function_desc *function;
824
824
+10
-10
drivers/pinctrl/pinmux.h
+10
-10
drivers/pinctrl/pinmux.h
···
26
26
27
27
int pinmux_validate_map(const struct pinctrl_map *map, int i);
28
28
29
-
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin);
29
+
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned int pin);
30
30
31
31
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
32
32
struct pinctrl_gpio_range *range,
33
-
unsigned pin, unsigned gpio);
34
-
void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin,
33
+
unsigned int pin, unsigned int gpio);
34
+
void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned int pin,
35
35
struct pinctrl_gpio_range *range);
36
36
int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
37
37
struct pinctrl_gpio_range *range,
38
-
unsigned pin, bool input);
38
+
unsigned int pin, bool input);
39
39
40
40
int pinmux_map_to_setting(const struct pinctrl_map *map,
41
41
struct pinctrl_setting *setting);
···
56
56
}
57
57
58
58
static inline bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev,
59
-
unsigned pin)
59
+
unsigned int pin)
60
60
{
61
61
return true;
62
62
}
63
63
64
64
static inline int pinmux_request_gpio(struct pinctrl_dev *pctldev,
65
65
struct pinctrl_gpio_range *range,
66
-
unsigned pin, unsigned gpio)
66
+
unsigned int pin, unsigned int gpio)
67
67
{
68
68
return 0;
69
69
}
70
70
71
71
static inline void pinmux_free_gpio(struct pinctrl_dev *pctldev,
72
-
unsigned pin,
72
+
unsigned int pin,
73
73
struct pinctrl_gpio_range *range)
74
74
{
75
75
}
76
76
77
77
static inline int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
78
78
struct pinctrl_gpio_range *range,
79
-
unsigned pin, bool input)
79
+
unsigned int pin, bool input)
80
80
{
81
81
return 0;
82
82
}
···
154
154
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
155
155
unsigned int selector,
156
156
const char * const **groups,
157
-
unsigned * const num_groups);
157
+
unsigned int * const num_groups);
158
158
159
159
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
160
160
unsigned int selector);
···
162
162
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
163
163
const char *name,
164
164
const char * const *groups,
165
-
unsigned const num_groups,
165
+
unsigned int const num_groups,
166
166
void *data);
167
167
168
168
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
+10
drivers/pinctrl/qcom/Kconfig
+10
drivers/pinctrl/qcom/Kconfig
···
124
124
(Low Power Island) found on the Qualcomm Technologies Inc SM8550
125
125
platform.
126
126
127
+
config PINCTRL_SM8650_LPASS_LPI
128
+
tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver"
129
+
depends on ARM64 || COMPILE_TEST
130
+
depends on PINCTRL_LPASS_LPI
131
+
help
132
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
133
+
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
134
+
(Low Power Island) found on the Qualcomm Technologies Inc SM8650
135
+
platform.
136
+
127
137
endif
+26
drivers/pinctrl/qcom/Kconfig.msm
+26
drivers/pinctrl/qcom/Kconfig.msm
···
286
286
Qualcomm Technologies Inc TLMM block found on the Qualcomm
287
287
Technologies Inc SDX75 platform.
288
288
289
+
config PINCTRL_SM4450
290
+
tristate "Qualcomm Technologies Inc SM4450 pin controller driver"
291
+
depends on ARM64 || COMPILE_TEST
292
+
help
293
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
294
+
Qualcomm Technologies Inc TLMM block found on the Qualcomm
295
+
Technologies Inc SM4450 platform.
296
+
289
297
config PINCTRL_SM6115
290
298
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
291
299
depends on ARM64 || COMPILE_TEST
···
373
365
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
374
366
Qualcomm Technologies Inc TLMM block found on the Qualcomm
375
367
Technologies Inc SM8550 platform.
368
+
369
+
config PINCTRL_SM8650
370
+
tristate "Qualcomm Technologies Inc SM8650 pin controller driver"
371
+
depends on ARM64 || COMPILE_TEST
372
+
help
373
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
374
+
Qualcomm Technologies Inc TLMM block found on the Qualcomm
375
+
Technologies Inc SM8650 platform.
376
+
377
+
config PINCTRL_X1E80100
378
+
tristate "Qualcomm Technologies Inc X1E80100 pin controller driver"
379
+
depends on ARM64 || COMPILE_TEST
380
+
help
381
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
382
+
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
383
+
block found on the Qualcomm Technologies Inc X1E80100 platform.
384
+
Say Y here to compile statically, or M here to compile it as a module.
385
+
If unsure, say N.
376
386
377
387
endif
+4
drivers/pinctrl/qcom/Makefile
+4
drivers/pinctrl/qcom/Makefile
···
43
43
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
44
44
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
45
45
obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
46
+
obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
46
47
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
47
48
obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
48
49
obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
···
59
58
obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
60
59
obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o
61
60
obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o
61
+
obj-$(CONFIG_PINCTRL_SM8650) += pinctrl-sm8650.o
62
+
obj-$(CONFIG_PINCTRL_SM8650_LPASS_LPI) += pinctrl-sm8650-lpass-lpi.o
62
63
obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
63
64
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
65
+
obj-$(CONFIG_PINCTRL_X1E80100) += pinctrl-x1e80100.o
+45
-25
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+45
-25
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
···
186
186
return 0;
187
187
}
188
188
189
+
static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
190
+
const struct lpi_pingroup *g,
191
+
unsigned int group, unsigned int slew)
192
+
{
193
+
unsigned long sval;
194
+
void __iomem *reg;
195
+
int slew_offset;
196
+
197
+
if (slew > LPI_SLEW_RATE_MAX) {
198
+
dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
199
+
slew, group);
200
+
return -EINVAL;
201
+
}
202
+
203
+
slew_offset = g->slew_offset;
204
+
if (slew_offset == LPI_NO_SLEW)
205
+
return 0;
206
+
207
+
if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
208
+
reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
209
+
else
210
+
reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
211
+
212
+
mutex_lock(&pctrl->lock);
213
+
214
+
sval = ioread32(reg);
215
+
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
216
+
sval |= slew << slew_offset;
217
+
iowrite32(sval, reg);
218
+
219
+
mutex_unlock(&pctrl->lock);
220
+
221
+
return 0;
222
+
}
223
+
189
224
static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
190
225
unsigned long *configs, unsigned int nconfs)
191
226
{
···
228
193
unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
229
194
bool value, output_enabled = false;
230
195
const struct lpi_pingroup *g;
231
-
unsigned long sval;
232
-
int i, slew_offset;
196
+
int i, ret;
233
197
u32 val;
234
198
235
199
g = &pctrl->data->groups[group];
···
260
226
strength = arg;
261
227
break;
262
228
case PIN_CONFIG_SLEW_RATE:
263
-
if (arg > LPI_SLEW_RATE_MAX) {
264
-
dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
265
-
arg, group);
266
-
return -EINVAL;
267
-
}
268
-
269
-
slew_offset = g->slew_offset;
270
-
if (slew_offset == LPI_NO_SLEW)
271
-
break;
272
-
273
-
mutex_lock(&pctrl->lock);
274
-
275
-
sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
276
-
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
277
-
sval |= arg << slew_offset;
278
-
iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
279
-
280
-
mutex_unlock(&pctrl->lock);
229
+
ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
230
+
if (ret)
231
+
return ret;
281
232
break;
282
233
default:
283
234
return -EINVAL;
···
338
319
}
339
320
340
321
#ifdef CONFIG_DEBUG_FS
341
-
#include <linux/seq_file.h>
342
322
343
323
static unsigned int lpi_regval_to_drive(u32 val)
344
324
{
···
457
439
return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
458
440
"TLMM resource not provided\n");
459
441
460
-
pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
461
-
if (IS_ERR(pctrl->slew_base))
462
-
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
463
-
"Slew resource not provided\n");
442
+
if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) {
443
+
pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
444
+
if (IS_ERR(pctrl->slew_base))
445
+
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
446
+
"Slew resource not provided\n");
447
+
}
464
448
465
449
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
466
450
if (ret)
+8
-5
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+8
-5
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
···
6
6
#ifndef __PINCTRL_LPASS_LPI_H__
7
7
#define __PINCTRL_LPASS_LPI_H__
8
8
9
+
#include <linux/array_size.h>
9
10
#include <linux/bits.h>
10
-
#include <linux/kernel.h>
11
11
12
12
#include "../core.h"
13
13
···
45
45
46
46
#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
47
47
{ \
48
-
.group.name = "gpio" #id, \
49
-
.group.pins = gpio##id##_pins, \
50
48
.pin = id, \
51
49
.slew_offset = soff, \
52
-
.group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
53
50
.funcs = (int[]){ \
54
51
LPI_MUX_gpio, \
55
52
LPI_MUX_##f1, \
···
57
60
.nfuncs = 5, \
58
61
}
59
62
63
+
/*
64
+
* Slew rate control is done in the same register as rest of the
65
+
* pin configuration.
66
+
*/
67
+
#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0)
68
+
60
69
struct lpi_pingroup {
61
-
struct group_desc group;
62
70
unsigned int pin;
63
71
/* Bit offset in slew register for SoundWire pins only */
64
72
int slew_offset;
···
84
82
int ngroups;
85
83
const struct lpi_function *functions;
86
84
int nfunctions;
85
+
unsigned int flags;
87
86
};
88
87
89
88
int lpi_pinctrl_probe(struct platform_device *pdev);
+46
drivers/pinctrl/qcom/pinctrl-msm.c
+46
drivers/pinctrl/qcom/pinctrl-msm.c
···
358
358
int ret;
359
359
u32 val;
360
360
361
+
/* Pin information can only be requested from valid pin groups */
362
+
if (!gpiochip_line_is_valid(&pctrl->chip, group))
363
+
return -EINVAL;
364
+
361
365
g = &pctrl->soc->groups[group];
362
366
363
367
ret = msm_config_reg(pctrl, g, param, &mask, &bit);
···
1200
1196
{
1201
1197
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1202
1198
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1199
+
const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1200
+
unsigned long flags;
1203
1201
int ret;
1204
1202
1205
1203
if (!try_module_get(gc->owner))
···
1227
1221
*/
1228
1222
irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1229
1223
1224
+
/*
1225
+
* If the wakeup_enable bit is present and marked as available for the
1226
+
* requested GPIO, it should be enabled when the GPIO is marked as
1227
+
* wake irq in order to allow the interrupt event to be transfered to
1228
+
* the PDC HW.
1229
+
* While the name implies only the wakeup event, it's also required for
1230
+
* the interrupt event.
1231
+
*/
1232
+
if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1233
+
u32 intr_cfg;
1234
+
1235
+
raw_spin_lock_irqsave(&pctrl->lock, flags);
1236
+
1237
+
intr_cfg = msm_readl_intr_cfg(pctrl, g);
1238
+
if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1239
+
intr_cfg |= BIT(g->intr_wakeup_enable_bit);
1240
+
msm_writel_intr_cfg(intr_cfg, pctrl, g);
1241
+
}
1242
+
1243
+
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1244
+
}
1245
+
1230
1246
return 0;
1231
1247
out:
1232
1248
module_put(gc->owner);
···
1258
1230
static void msm_gpio_irq_relres(struct irq_data *d)
1259
1231
{
1260
1232
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1233
+
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1234
+
const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1235
+
unsigned long flags;
1236
+
1237
+
/* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */
1238
+
if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1239
+
u32 intr_cfg;
1240
+
1241
+
raw_spin_lock_irqsave(&pctrl->lock, flags);
1242
+
1243
+
intr_cfg = msm_readl_intr_cfg(pctrl, g);
1244
+
if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1245
+
intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);
1246
+
msm_writel_intr_cfg(intr_cfg, pctrl, g);
1247
+
}
1248
+
1249
+
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1250
+
}
1261
1251
1262
1252
gpiochip_unlock_as_irq(gc, d->hwirq);
1263
1253
module_put(gc->owner);
+5
drivers/pinctrl/qcom/pinctrl-msm.h
+5
drivers/pinctrl/qcom/pinctrl-msm.h
···
58
58
* @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
59
59
* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
60
60
* status.
61
+
* @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate
62
+
* wakeup events.
63
+
* @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO.
61
64
* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
62
65
* @intr_target_width: Number of bits used for specifying interrupt routing target.
63
66
* @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
···
103
100
unsigned intr_status_bit:5;
104
101
unsigned intr_ack_high:1;
105
102
103
+
unsigned intr_wakeup_present_bit:5;
104
+
unsigned intr_wakeup_enable_bit:5;
106
105
unsigned intr_target_bit:5;
107
106
unsigned intr_target_width:5;
108
107
unsigned intr_target_kpss_val:5;
-16
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
-16
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
···
36
36
LPI_MUX__,
37
37
};
38
38
39
-
static int gpio0_pins[] = { 0 };
40
-
static int gpio1_pins[] = { 1 };
41
-
static int gpio2_pins[] = { 2 };
42
-
static int gpio3_pins[] = { 3 };
43
-
static int gpio4_pins[] = { 4 };
44
-
static int gpio5_pins[] = { 5 };
45
-
static int gpio6_pins[] = { 6 };
46
-
static int gpio7_pins[] = { 7 };
47
-
static int gpio8_pins[] = { 8 };
48
-
static int gpio9_pins[] = { 9 };
49
-
static int gpio10_pins[] = { 10 };
50
-
static int gpio11_pins[] = { 11 };
51
-
static int gpio12_pins[] = { 12 };
52
-
static int gpio13_pins[] = { 13 };
53
-
static int gpio14_pins[] = { 14 };
54
-
55
39
static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
56
40
PINCTRL_PIN(0, "gpio0"),
57
41
PINCTRL_PIN(1, "gpio1"),
-20
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
-20
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
···
45
45
LPI_MUX__,
46
46
};
47
47
48
-
static int gpio0_pins[] = { 0 };
49
-
static int gpio1_pins[] = { 1 };
50
-
static int gpio2_pins[] = { 2 };
51
-
static int gpio3_pins[] = { 3 };
52
-
static int gpio4_pins[] = { 4 };
53
-
static int gpio5_pins[] = { 5 };
54
-
static int gpio6_pins[] = { 6 };
55
-
static int gpio7_pins[] = { 7 };
56
-
static int gpio8_pins[] = { 8 };
57
-
static int gpio9_pins[] = { 9 };
58
-
static int gpio10_pins[] = { 10 };
59
-
static int gpio11_pins[] = { 11 };
60
-
static int gpio12_pins[] = { 12 };
61
-
static int gpio13_pins[] = { 13 };
62
-
static int gpio14_pins[] = { 14 };
63
-
static int gpio15_pins[] = { 15 };
64
-
static int gpio16_pins[] = { 16 };
65
-
static int gpio17_pins[] = { 17 };
66
-
static int gpio18_pins[] = { 18 };
67
-
68
48
static const struct pinctrl_pin_desc sc8280xp_lpi_pins[] = {
69
49
PINCTRL_PIN(0, "gpio0"),
70
50
PINCTRL_PIN(1, "gpio1"),
+1014
drivers/pinctrl/qcom/pinctrl-sm4450.c
+1014
drivers/pinctrl/qcom/pinctrl-sm4450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
14
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15
+
{ \
16
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
17
+
gpio##id##_pins, \
18
+
ARRAY_SIZE(gpio##id##_pins)), \
19
+
.funcs = (int[]){ \
20
+
msm_mux_gpio, /* gpio mode */ \
21
+
msm_mux_##f1, \
22
+
msm_mux_##f2, \
23
+
msm_mux_##f3, \
24
+
msm_mux_##f4, \
25
+
msm_mux_##f5, \
26
+
msm_mux_##f6, \
27
+
msm_mux_##f7, \
28
+
msm_mux_##f8, \
29
+
msm_mux_##f9 \
30
+
}, \
31
+
.nfuncs = 10, \
32
+
.ctl_reg = REG_SIZE * id, \
33
+
.io_reg = 0x4 + REG_SIZE * id, \
34
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
+
.intr_status_reg = 0xc + REG_SIZE * id, \
36
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
+
.mux_bit = 2, \
38
+
.pull_bit = 0, \
39
+
.drv_bit = 6, \
40
+
.egpio_enable = 12, \
41
+
.egpio_present = 11, \
42
+
.oe_bit = 9, \
43
+
.in_bit = 0, \
44
+
.out_bit = 1, \
45
+
.intr_enable_bit = 0, \
46
+
.intr_status_bit = 0, \
47
+
.intr_target_bit = 5, \
48
+
.intr_target_kpss_val = 3, \
49
+
.intr_raw_status_bit = 4, \
50
+
.intr_polarity_bit = 1, \
51
+
.intr_detection_bit = 2, \
52
+
.intr_detection_width = 2, \
53
+
}
54
+
55
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
56
+
{ \
57
+
.grp = PINCTRL_PINGROUP(#pg_name, \
58
+
pg_name##_pins, \
59
+
ARRAY_SIZE(pg_name##_pins)), \
60
+
.ctl_reg = ctl, \
61
+
.io_reg = 0, \
62
+
.intr_cfg_reg = 0, \
63
+
.intr_status_reg = 0, \
64
+
.intr_target_reg = 0, \
65
+
.mux_bit = -1, \
66
+
.pull_bit = pull, \
67
+
.drv_bit = drv, \
68
+
.oe_bit = -1, \
69
+
.in_bit = -1, \
70
+
.out_bit = -1, \
71
+
.intr_enable_bit = -1, \
72
+
.intr_status_bit = -1, \
73
+
.intr_target_bit = -1, \
74
+
.intr_raw_status_bit = -1, \
75
+
.intr_polarity_bit = -1, \
76
+
.intr_detection_bit = -1, \
77
+
.intr_detection_width = -1, \
78
+
}
79
+
80
+
#define UFS_RESET(pg_name, offset) \
81
+
{ \
82
+
.grp = PINCTRL_PINGROUP(#pg_name, \
83
+
pg_name##_pins, \
84
+
ARRAY_SIZE(pg_name##_pins)), \
85
+
.ctl_reg = offset, \
86
+
.io_reg = offset + 0x4, \
87
+
.intr_cfg_reg = 0, \
88
+
.intr_status_reg = 0, \
89
+
.intr_target_reg = 0, \
90
+
.mux_bit = -1, \
91
+
.pull_bit = 3, \
92
+
.drv_bit = 0, \
93
+
.oe_bit = -1, \
94
+
.in_bit = -1, \
95
+
.out_bit = 0, \
96
+
.intr_enable_bit = -1, \
97
+
.intr_status_bit = -1, \
98
+
.intr_target_bit = -1, \
99
+
.intr_raw_status_bit = -1, \
100
+
.intr_polarity_bit = -1, \
101
+
.intr_detection_bit = -1, \
102
+
.intr_detection_width = -1, \
103
+
}
104
+
105
+
#define QUP_I3C(qup_mode, qup_offset) \
106
+
{ \
107
+
.mode = qup_mode, \
108
+
.offset = qup_offset, \
109
+
}
110
+
111
+
112
+
static const struct pinctrl_pin_desc sm4450_pins[] = {
113
+
PINCTRL_PIN(0, "GPIO_0"),
114
+
PINCTRL_PIN(1, "GPIO_1"),
115
+
PINCTRL_PIN(2, "GPIO_2"),
116
+
PINCTRL_PIN(3, "GPIO_3"),
117
+
PINCTRL_PIN(4, "GPIO_4"),
118
+
PINCTRL_PIN(5, "GPIO_5"),
119
+
PINCTRL_PIN(6, "GPIO_6"),
120
+
PINCTRL_PIN(7, "GPIO_7"),
121
+
PINCTRL_PIN(8, "GPIO_8"),
122
+
PINCTRL_PIN(9, "GPIO_9"),
123
+
PINCTRL_PIN(10, "GPIO_10"),
124
+
PINCTRL_PIN(11, "GPIO_11"),
125
+
PINCTRL_PIN(12, "GPIO_12"),
126
+
PINCTRL_PIN(13, "GPIO_13"),
127
+
PINCTRL_PIN(14, "GPIO_14"),
128
+
PINCTRL_PIN(15, "GPIO_15"),
129
+
PINCTRL_PIN(16, "GPIO_16"),
130
+
PINCTRL_PIN(17, "GPIO_17"),
131
+
PINCTRL_PIN(18, "GPIO_18"),
132
+
PINCTRL_PIN(19, "GPIO_19"),
133
+
PINCTRL_PIN(20, "GPIO_20"),
134
+
PINCTRL_PIN(21, "GPIO_21"),
135
+
PINCTRL_PIN(22, "GPIO_22"),
136
+
PINCTRL_PIN(23, "GPIO_23"),
137
+
PINCTRL_PIN(24, "GPIO_24"),
138
+
PINCTRL_PIN(25, "GPIO_25"),
139
+
PINCTRL_PIN(26, "GPIO_26"),
140
+
PINCTRL_PIN(27, "GPIO_27"),
141
+
PINCTRL_PIN(28, "GPIO_28"),
142
+
PINCTRL_PIN(29, "GPIO_29"),
143
+
PINCTRL_PIN(30, "GPIO_30"),
144
+
PINCTRL_PIN(31, "GPIO_31"),
145
+
PINCTRL_PIN(32, "GPIO_32"),
146
+
PINCTRL_PIN(33, "GPIO_33"),
147
+
PINCTRL_PIN(34, "GPIO_34"),
148
+
PINCTRL_PIN(35, "GPIO_35"),
149
+
PINCTRL_PIN(36, "GPIO_36"),
150
+
PINCTRL_PIN(37, "GPIO_37"),
151
+
PINCTRL_PIN(38, "GPIO_38"),
152
+
PINCTRL_PIN(39, "GPIO_39"),
153
+
PINCTRL_PIN(40, "GPIO_40"),
154
+
PINCTRL_PIN(41, "GPIO_41"),
155
+
PINCTRL_PIN(42, "GPIO_42"),
156
+
PINCTRL_PIN(43, "GPIO_43"),
157
+
PINCTRL_PIN(44, "GPIO_44"),
158
+
PINCTRL_PIN(45, "GPIO_45"),
159
+
PINCTRL_PIN(46, "GPIO_46"),
160
+
PINCTRL_PIN(47, "GPIO_47"),
161
+
PINCTRL_PIN(48, "GPIO_48"),
162
+
PINCTRL_PIN(49, "GPIO_49"),
163
+
PINCTRL_PIN(50, "GPIO_50"),
164
+
PINCTRL_PIN(51, "GPIO_51"),
165
+
PINCTRL_PIN(52, "GPIO_52"),
166
+
PINCTRL_PIN(53, "GPIO_53"),
167
+
PINCTRL_PIN(54, "GPIO_54"),
168
+
PINCTRL_PIN(55, "GPIO_55"),
169
+
PINCTRL_PIN(56, "GPIO_56"),
170
+
PINCTRL_PIN(57, "GPIO_57"),
171
+
PINCTRL_PIN(58, "GPIO_58"),
172
+
PINCTRL_PIN(59, "GPIO_59"),
173
+
PINCTRL_PIN(60, "GPIO_60"),
174
+
PINCTRL_PIN(61, "GPIO_61"),
175
+
PINCTRL_PIN(62, "GPIO_62"),
176
+
PINCTRL_PIN(63, "GPIO_63"),
177
+
PINCTRL_PIN(64, "GPIO_64"),
178
+
PINCTRL_PIN(65, "GPIO_65"),
179
+
PINCTRL_PIN(66, "GPIO_66"),
180
+
PINCTRL_PIN(67, "GPIO_67"),
181
+
PINCTRL_PIN(68, "GPIO_68"),
182
+
PINCTRL_PIN(69, "GPIO_69"),
183
+
PINCTRL_PIN(70, "GPIO_70"),
184
+
PINCTRL_PIN(71, "GPIO_71"),
185
+
PINCTRL_PIN(72, "GPIO_72"),
186
+
PINCTRL_PIN(73, "GPIO_73"),
187
+
PINCTRL_PIN(74, "GPIO_74"),
188
+
PINCTRL_PIN(75, "GPIO_75"),
189
+
PINCTRL_PIN(76, "GPIO_76"),
190
+
PINCTRL_PIN(77, "GPIO_77"),
191
+
PINCTRL_PIN(78, "GPIO_78"),
192
+
PINCTRL_PIN(79, "GPIO_79"),
193
+
PINCTRL_PIN(80, "GPIO_80"),
194
+
PINCTRL_PIN(81, "GPIO_81"),
195
+
PINCTRL_PIN(82, "GPIO_82"),
196
+
PINCTRL_PIN(83, "GPIO_83"),
197
+
PINCTRL_PIN(84, "GPIO_84"),
198
+
PINCTRL_PIN(85, "GPIO_85"),
199
+
PINCTRL_PIN(86, "GPIO_86"),
200
+
PINCTRL_PIN(87, "GPIO_87"),
201
+
PINCTRL_PIN(88, "GPIO_88"),
202
+
PINCTRL_PIN(89, "GPIO_89"),
203
+
PINCTRL_PIN(90, "GPIO_90"),
204
+
PINCTRL_PIN(91, "GPIO_91"),
205
+
PINCTRL_PIN(92, "GPIO_92"),
206
+
PINCTRL_PIN(93, "GPIO_93"),
207
+
PINCTRL_PIN(94, "GPIO_94"),
208
+
PINCTRL_PIN(95, "GPIO_95"),
209
+
PINCTRL_PIN(96, "GPIO_96"),
210
+
PINCTRL_PIN(97, "GPIO_97"),
211
+
PINCTRL_PIN(98, "GPIO_98"),
212
+
PINCTRL_PIN(99, "GPIO_99"),
213
+
PINCTRL_PIN(100, "GPIO_100"),
214
+
PINCTRL_PIN(101, "GPIO_101"),
215
+
PINCTRL_PIN(102, "GPIO_102"),
216
+
PINCTRL_PIN(103, "GPIO_103"),
217
+
PINCTRL_PIN(104, "GPIO_104"),
218
+
PINCTRL_PIN(105, "GPIO_105"),
219
+
PINCTRL_PIN(106, "GPIO_106"),
220
+
PINCTRL_PIN(107, "GPIO_107"),
221
+
PINCTRL_PIN(108, "GPIO_108"),
222
+
PINCTRL_PIN(109, "GPIO_109"),
223
+
PINCTRL_PIN(110, "GPIO_110"),
224
+
PINCTRL_PIN(111, "GPIO_111"),
225
+
PINCTRL_PIN(112, "GPIO_112"),
226
+
PINCTRL_PIN(113, "GPIO_113"),
227
+
PINCTRL_PIN(114, "GPIO_114"),
228
+
PINCTRL_PIN(115, "GPIO_115"),
229
+
PINCTRL_PIN(116, "GPIO_116"),
230
+
PINCTRL_PIN(117, "GPIO_117"),
231
+
PINCTRL_PIN(118, "GPIO_118"),
232
+
PINCTRL_PIN(119, "GPIO_119"),
233
+
PINCTRL_PIN(120, "GPIO_120"),
234
+
PINCTRL_PIN(121, "GPIO_121"),
235
+
PINCTRL_PIN(122, "GPIO_122"),
236
+
PINCTRL_PIN(123, "GPIO_123"),
237
+
PINCTRL_PIN(124, "GPIO_124"),
238
+
PINCTRL_PIN(125, "GPIO_125"),
239
+
PINCTRL_PIN(126, "GPIO_126"),
240
+
PINCTRL_PIN(127, "GPIO_127"),
241
+
PINCTRL_PIN(128, "GPIO_128"),
242
+
PINCTRL_PIN(129, "GPIO_129"),
243
+
PINCTRL_PIN(130, "GPIO_130"),
244
+
PINCTRL_PIN(131, "GPIO_131"),
245
+
PINCTRL_PIN(132, "GPIO_132"),
246
+
PINCTRL_PIN(133, "GPIO_133"),
247
+
PINCTRL_PIN(134, "GPIO_134"),
248
+
PINCTRL_PIN(135, "GPIO_135"),
249
+
PINCTRL_PIN(136, "UFS_RESET"),
250
+
PINCTRL_PIN(137, "SDC1_RCLK"),
251
+
PINCTRL_PIN(138, "SDC1_CLK"),
252
+
PINCTRL_PIN(139, "SDC1_CMD"),
253
+
PINCTRL_PIN(140, "SDC1_DATA"),
254
+
PINCTRL_PIN(141, "SDC2_CLK"),
255
+
PINCTRL_PIN(142, "SDC2_CMD"),
256
+
PINCTRL_PIN(143, "SDC2_DATA"),
257
+
};
258
+
259
+
#define DECLARE_MSM_GPIO_PINS(pin) \
260
+
static const unsigned int gpio##pin##_pins[] = { pin }
261
+
DECLARE_MSM_GPIO_PINS(0);
262
+
DECLARE_MSM_GPIO_PINS(1);
263
+
DECLARE_MSM_GPIO_PINS(2);
264
+
DECLARE_MSM_GPIO_PINS(3);
265
+
DECLARE_MSM_GPIO_PINS(4);
266
+
DECLARE_MSM_GPIO_PINS(5);
267
+
DECLARE_MSM_GPIO_PINS(6);
268
+
DECLARE_MSM_GPIO_PINS(7);
269
+
DECLARE_MSM_GPIO_PINS(8);
270
+
DECLARE_MSM_GPIO_PINS(9);
271
+
DECLARE_MSM_GPIO_PINS(10);
272
+
DECLARE_MSM_GPIO_PINS(11);
273
+
DECLARE_MSM_GPIO_PINS(12);
274
+
DECLARE_MSM_GPIO_PINS(13);
275
+
DECLARE_MSM_GPIO_PINS(14);
276
+
DECLARE_MSM_GPIO_PINS(15);
277
+
DECLARE_MSM_GPIO_PINS(16);
278
+
DECLARE_MSM_GPIO_PINS(17);
279
+
DECLARE_MSM_GPIO_PINS(18);
280
+
DECLARE_MSM_GPIO_PINS(19);
281
+
DECLARE_MSM_GPIO_PINS(20);
282
+
DECLARE_MSM_GPIO_PINS(21);
283
+
DECLARE_MSM_GPIO_PINS(22);
284
+
DECLARE_MSM_GPIO_PINS(23);
285
+
DECLARE_MSM_GPIO_PINS(24);
286
+
DECLARE_MSM_GPIO_PINS(25);
287
+
DECLARE_MSM_GPIO_PINS(26);
288
+
DECLARE_MSM_GPIO_PINS(27);
289
+
DECLARE_MSM_GPIO_PINS(28);
290
+
DECLARE_MSM_GPIO_PINS(29);
291
+
DECLARE_MSM_GPIO_PINS(30);
292
+
DECLARE_MSM_GPIO_PINS(31);
293
+
DECLARE_MSM_GPIO_PINS(32);
294
+
DECLARE_MSM_GPIO_PINS(33);
295
+
DECLARE_MSM_GPIO_PINS(34);
296
+
DECLARE_MSM_GPIO_PINS(35);
297
+
DECLARE_MSM_GPIO_PINS(36);
298
+
DECLARE_MSM_GPIO_PINS(37);
299
+
DECLARE_MSM_GPIO_PINS(38);
300
+
DECLARE_MSM_GPIO_PINS(39);
301
+
DECLARE_MSM_GPIO_PINS(40);
302
+
DECLARE_MSM_GPIO_PINS(41);
303
+
DECLARE_MSM_GPIO_PINS(42);
304
+
DECLARE_MSM_GPIO_PINS(43);
305
+
DECLARE_MSM_GPIO_PINS(44);
306
+
DECLARE_MSM_GPIO_PINS(45);
307
+
DECLARE_MSM_GPIO_PINS(46);
308
+
DECLARE_MSM_GPIO_PINS(47);
309
+
DECLARE_MSM_GPIO_PINS(48);
310
+
DECLARE_MSM_GPIO_PINS(49);
311
+
DECLARE_MSM_GPIO_PINS(50);
312
+
DECLARE_MSM_GPIO_PINS(51);
313
+
DECLARE_MSM_GPIO_PINS(52);
314
+
DECLARE_MSM_GPIO_PINS(53);
315
+
DECLARE_MSM_GPIO_PINS(54);
316
+
DECLARE_MSM_GPIO_PINS(55);
317
+
DECLARE_MSM_GPIO_PINS(56);
318
+
DECLARE_MSM_GPIO_PINS(57);
319
+
DECLARE_MSM_GPIO_PINS(58);
320
+
DECLARE_MSM_GPIO_PINS(59);
321
+
DECLARE_MSM_GPIO_PINS(60);
322
+
DECLARE_MSM_GPIO_PINS(61);
323
+
DECLARE_MSM_GPIO_PINS(62);
324
+
DECLARE_MSM_GPIO_PINS(63);
325
+
DECLARE_MSM_GPIO_PINS(64);
326
+
DECLARE_MSM_GPIO_PINS(65);
327
+
DECLARE_MSM_GPIO_PINS(66);
328
+
DECLARE_MSM_GPIO_PINS(67);
329
+
DECLARE_MSM_GPIO_PINS(68);
330
+
DECLARE_MSM_GPIO_PINS(69);
331
+
DECLARE_MSM_GPIO_PINS(70);
332
+
DECLARE_MSM_GPIO_PINS(71);
333
+
DECLARE_MSM_GPIO_PINS(72);
334
+
DECLARE_MSM_GPIO_PINS(73);
335
+
DECLARE_MSM_GPIO_PINS(74);
336
+
DECLARE_MSM_GPIO_PINS(75);
337
+
DECLARE_MSM_GPIO_PINS(76);
338
+
DECLARE_MSM_GPIO_PINS(77);
339
+
DECLARE_MSM_GPIO_PINS(78);
340
+
DECLARE_MSM_GPIO_PINS(79);
341
+
DECLARE_MSM_GPIO_PINS(80);
342
+
DECLARE_MSM_GPIO_PINS(81);
343
+
DECLARE_MSM_GPIO_PINS(82);
344
+
DECLARE_MSM_GPIO_PINS(83);
345
+
DECLARE_MSM_GPIO_PINS(84);
346
+
DECLARE_MSM_GPIO_PINS(85);
347
+
DECLARE_MSM_GPIO_PINS(86);
348
+
DECLARE_MSM_GPIO_PINS(87);
349
+
DECLARE_MSM_GPIO_PINS(88);
350
+
DECLARE_MSM_GPIO_PINS(89);
351
+
DECLARE_MSM_GPIO_PINS(90);
352
+
DECLARE_MSM_GPIO_PINS(91);
353
+
DECLARE_MSM_GPIO_PINS(92);
354
+
DECLARE_MSM_GPIO_PINS(93);
355
+
DECLARE_MSM_GPIO_PINS(94);
356
+
DECLARE_MSM_GPIO_PINS(95);
357
+
DECLARE_MSM_GPIO_PINS(96);
358
+
DECLARE_MSM_GPIO_PINS(97);
359
+
DECLARE_MSM_GPIO_PINS(98);
360
+
DECLARE_MSM_GPIO_PINS(99);
361
+
DECLARE_MSM_GPIO_PINS(100);
362
+
DECLARE_MSM_GPIO_PINS(101);
363
+
DECLARE_MSM_GPIO_PINS(102);
364
+
DECLARE_MSM_GPIO_PINS(103);
365
+
DECLARE_MSM_GPIO_PINS(104);
366
+
DECLARE_MSM_GPIO_PINS(105);
367
+
DECLARE_MSM_GPIO_PINS(106);
368
+
DECLARE_MSM_GPIO_PINS(107);
369
+
DECLARE_MSM_GPIO_PINS(108);
370
+
DECLARE_MSM_GPIO_PINS(109);
371
+
DECLARE_MSM_GPIO_PINS(110);
372
+
DECLARE_MSM_GPIO_PINS(111);
373
+
DECLARE_MSM_GPIO_PINS(112);
374
+
DECLARE_MSM_GPIO_PINS(113);
375
+
DECLARE_MSM_GPIO_PINS(114);
376
+
DECLARE_MSM_GPIO_PINS(115);
377
+
DECLARE_MSM_GPIO_PINS(116);
378
+
DECLARE_MSM_GPIO_PINS(117);
379
+
DECLARE_MSM_GPIO_PINS(118);
380
+
DECLARE_MSM_GPIO_PINS(119);
381
+
DECLARE_MSM_GPIO_PINS(120);
382
+
DECLARE_MSM_GPIO_PINS(121);
383
+
DECLARE_MSM_GPIO_PINS(122);
384
+
DECLARE_MSM_GPIO_PINS(123);
385
+
DECLARE_MSM_GPIO_PINS(124);
386
+
DECLARE_MSM_GPIO_PINS(125);
387
+
DECLARE_MSM_GPIO_PINS(126);
388
+
DECLARE_MSM_GPIO_PINS(127);
389
+
DECLARE_MSM_GPIO_PINS(128);
390
+
DECLARE_MSM_GPIO_PINS(129);
391
+
DECLARE_MSM_GPIO_PINS(130);
392
+
DECLARE_MSM_GPIO_PINS(131);
393
+
DECLARE_MSM_GPIO_PINS(132);
394
+
DECLARE_MSM_GPIO_PINS(133);
395
+
DECLARE_MSM_GPIO_PINS(134);
396
+
DECLARE_MSM_GPIO_PINS(135);
397
+
398
+
static const unsigned int ufs_reset_pins[] = { 136 };
399
+
static const unsigned int sdc1_rclk_pins[] = { 137 };
400
+
static const unsigned int sdc1_clk_pins[] = { 138 };
401
+
static const unsigned int sdc1_cmd_pins[] = { 139 };
402
+
static const unsigned int sdc1_data_pins[] = { 140 };
403
+
static const unsigned int sdc2_clk_pins[] = { 141 };
404
+
static const unsigned int sdc2_cmd_pins[] = { 142 };
405
+
static const unsigned int sdc2_data_pins[] = { 143 };
406
+
407
+
enum sm4450_functions {
408
+
msm_mux_gpio,
409
+
msm_mux_atest_char,
410
+
msm_mux_atest_usb0,
411
+
msm_mux_audio_ref_clk,
412
+
msm_mux_cam_mclk,
413
+
msm_mux_cci_async_in0,
414
+
msm_mux_cci_i2c,
415
+
msm_mux_cci,
416
+
msm_mux_cmu_rng,
417
+
msm_mux_coex_uart1_rx,
418
+
msm_mux_coex_uart1_tx,
419
+
msm_mux_cri_trng,
420
+
msm_mux_dbg_out_clk,
421
+
msm_mux_ddr_bist,
422
+
msm_mux_ddr_pxi0_test,
423
+
msm_mux_ddr_pxi1_test,
424
+
msm_mux_gcc_gp1_clk,
425
+
msm_mux_gcc_gp2_clk,
426
+
msm_mux_gcc_gp3_clk,
427
+
msm_mux_host2wlan_sol,
428
+
msm_mux_ibi_i3c_qup0,
429
+
msm_mux_ibi_i3c_qup1,
430
+
msm_mux_jitter_bist_ref,
431
+
msm_mux_mdp_vsync0_out,
432
+
msm_mux_mdp_vsync1_out,
433
+
msm_mux_mdp_vsync2_out,
434
+
msm_mux_mdp_vsync3_out,
435
+
msm_mux_mdp_vsync,
436
+
msm_mux_nav,
437
+
msm_mux_pcie0_clk_req,
438
+
msm_mux_phase_flag,
439
+
msm_mux_pll_bist_sync,
440
+
msm_mux_pll_clk_aux,
441
+
msm_mux_prng_rosc,
442
+
msm_mux_qdss_cti_trig0,
443
+
msm_mux_qdss_cti_trig1,
444
+
msm_mux_qdss_gpio,
445
+
msm_mux_qlink0_enable,
446
+
msm_mux_qlink0_request,
447
+
msm_mux_qlink0_wmss_reset,
448
+
msm_mux_qup0_se0,
449
+
msm_mux_qup0_se1,
450
+
msm_mux_qup0_se2,
451
+
msm_mux_qup0_se3,
452
+
msm_mux_qup0_se4,
453
+
msm_mux_qup1_se0,
454
+
msm_mux_qup1_se1,
455
+
msm_mux_qup1_se2,
456
+
msm_mux_qup1_se3,
457
+
msm_mux_qup1_se4,
458
+
msm_mux_sd_write_protect,
459
+
msm_mux_tb_trig_sdc1,
460
+
msm_mux_tb_trig_sdc2,
461
+
msm_mux_tgu_ch0_trigout,
462
+
msm_mux_tgu_ch1_trigout,
463
+
msm_mux_tgu_ch2_trigout,
464
+
msm_mux_tgu_ch3_trigout,
465
+
msm_mux_tmess_prng,
466
+
msm_mux_tsense_pwm1_out,
467
+
msm_mux_tsense_pwm2_out,
468
+
msm_mux_uim0,
469
+
msm_mux_uim1,
470
+
msm_mux_usb0_hs_ac,
471
+
msm_mux_usb0_phy_ps,
472
+
msm_mux_vfr_0_mira,
473
+
msm_mux_vfr_0_mirb,
474
+
msm_mux_vfr_1,
475
+
msm_mux_vsense_trigger_mirnat,
476
+
msm_mux_wlan1_adc_dtest0,
477
+
msm_mux_wlan1_adc_dtest1,
478
+
msm_mux__,
479
+
};
480
+
481
+
static const char * const gpio_groups[] = {
482
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
483
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
484
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
485
+
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
486
+
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
487
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
488
+
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
489
+
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
490
+
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
491
+
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
492
+
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
493
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
494
+
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
495
+
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
496
+
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
497
+
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
498
+
"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
499
+
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
500
+
"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
501
+
"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
502
+
"gpio135",
503
+
};
504
+
static const char * const atest_char_groups[] = {
505
+
"gpio95", "gpio97", "gpio98", "gpio99", "gpio100",
506
+
};
507
+
static const char * const atest_usb0_groups[] = {
508
+
"gpio75", "gpio10", "gpio78", "gpio79", "gpio80",
509
+
};
510
+
static const char * const audio_ref_clk_groups[] = {
511
+
"gpio71",
512
+
};
513
+
static const char * const cam_mclk_groups[] = {
514
+
"gpio36", "gpio37", "gpio38", "gpio39",
515
+
};
516
+
static const char * const cci_async_in0_groups[] = {
517
+
"gpio40",
518
+
};
519
+
static const char * const cci_i2c_groups[] = {
520
+
"gpio45", "gpio47", "gpio49", "gpio44",
521
+
"gpio46", "gpio48",
522
+
};
523
+
static const char * const cci_groups[] = {
524
+
"gpio40", "gpio41", "gpio42", "gpio43",
525
+
};
526
+
static const char * const cmu_rng_groups[] = {
527
+
"gpio28", "gpio3", "gpio1", "gpio0",
528
+
};
529
+
static const char * const coex_uart1_rx_groups[] = {
530
+
"gpio54",
531
+
};
532
+
static const char * const coex_uart1_tx_groups[] = {
533
+
"gpio55",
534
+
};
535
+
static const char * const cri_trng_groups[] = {
536
+
"gpio42", "gpio40", "gpio41",
537
+
};
538
+
static const char * const dbg_out_clk_groups[] = {
539
+
"gpio80",
540
+
};
541
+
static const char * const ddr_bist_groups[] = {
542
+
"gpio32", "gpio29", "gpio30", "gpio31",
543
+
};
544
+
static const char * const ddr_pxi0_test_groups[] = {
545
+
"gpio90", "gpio127",
546
+
};
547
+
static const char * const ddr_pxi1_test_groups[] = {
548
+
"gpio118", "gpio122",
549
+
};
550
+
static const char * const gcc_gp1_clk_groups[] = {
551
+
"gpio37", "gpio48",
552
+
};
553
+
static const char * const gcc_gp2_clk_groups[] = {
554
+
"gpio30", "gpio49",
555
+
};
556
+
static const char * const gcc_gp3_clk_groups[] = {
557
+
"gpio3", "gpio50",
558
+
};
559
+
static const char * const host2wlan_sol_groups[] = {
560
+
"gpio106",
561
+
};
562
+
static const char * const ibi_i3c_qup0_groups[] = {
563
+
"gpio4", "gpio5",
564
+
};
565
+
static const char * const ibi_i3c_qup1_groups[] = {
566
+
"gpio0", "gpio1",
567
+
};
568
+
static const char * const jitter_bist_ref_groups[] = {
569
+
"gpio90",
570
+
};
571
+
static const char * const mdp_vsync0_out_groups[] = {
572
+
"gpio93",
573
+
};
574
+
static const char * const mdp_vsync1_out_groups[] = {
575
+
"gpio93",
576
+
};
577
+
static const char * const mdp_vsync2_out_groups[] = {
578
+
"gpio22",
579
+
};
580
+
static const char * const mdp_vsync3_out_groups[] = {
581
+
"gpio22",
582
+
};
583
+
static const char * const mdp_vsync_groups[] = {
584
+
"gpio26", "gpio22", "gpio30", "gpio34", "gpio93", "gpio97",
585
+
};
586
+
static const char * const nav_groups[] = {
587
+
"gpio81", "gpio83", "gpio84",
588
+
};
589
+
static const char * const pcie0_clk_req_groups[] = {
590
+
"gpio107",
591
+
};
592
+
static const char * const phase_flag_groups[] = {
593
+
"gpio7", "gpio8", "gpio9", "gpio11", "gpio13", "gpio14", "gpio15",
594
+
"gpio17", "gpio18", "gpio19", "gpio21", "gpio24", "gpio25", "gpio31",
595
+
"gpio32", "gpio33", "gpio35", "gpio61", "gpio72", "gpio82", "gpio91",
596
+
"gpio95", "gpio97", "gpio98", "gpio99", "gpio100", "gpio105", "gpio115",
597
+
"gpio116", "gpio117", "gpio133", "gpio135",
598
+
};
599
+
static const char * const pll_bist_sync_groups[] = {
600
+
"gpio73",
601
+
};
602
+
static const char * const pll_clk_aux_groups[] = {
603
+
"gpio108",
604
+
};
605
+
static const char * const prng_rosc_groups[] = {
606
+
"gpio36", "gpio37", "gpio38", "gpio39",
607
+
};
608
+
static const char * const qdss_cti_trig0_groups[] = {
609
+
"gpio26", "gpio60", "gpio113", "gpio114",
610
+
};
611
+
static const char * const qdss_cti_trig1_groups[] = {
612
+
"gpio6", "gpio27", "gpio57", "gpio58",
613
+
};
614
+
static const char * const qdss_gpio_groups[] = {
615
+
"gpio0", "gpio1", "gpio3", "gpio4", "gpio5", "gpio7", "gpio8",
616
+
"gpio9", "gpio14", "gpio15", "gpio17", "gpio23", "gpio31", "gpio32",
617
+
"gpio33", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
618
+
"gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
619
+
"gpio49", "gpio59", "gpio62", "gpio118", "gpio121", "gpio122", "gpio126",
620
+
"gpio127",
621
+
};
622
+
static const char * const qlink0_enable_groups[] = {
623
+
"gpio88",
624
+
};
625
+
static const char * const qlink0_request_groups[] = {
626
+
"gpio87",
627
+
};
628
+
static const char * const qlink0_wmss_reset_groups[] = {
629
+
"gpio89",
630
+
};
631
+
static const char * const qup0_se0_groups[] = {
632
+
"gpio4", "gpio5", "gpio34", "gpio35",
633
+
};
634
+
static const char * const qup0_se1_groups[] = {
635
+
"gpio10", "gpio11", "gpio12", "gpio13",
636
+
};
637
+
static const char * const qup0_se2_groups[] = {
638
+
"gpio14", "gpio15", "gpio16", "gpio17",
639
+
};
640
+
static const char * const qup0_se3_groups[] = {
641
+
"gpio18", "gpio19", "gpio20", "gpio21",
642
+
};
643
+
static const char * const qup0_se4_groups[] = {
644
+
"gpio6", "gpio7", "gpio8", "gpio9",
645
+
"gpio26", "gpio27", "gpio34",
646
+
};
647
+
static const char * const qup1_se0_groups[] = {
648
+
"gpio0", "gpio1", "gpio2", "gpio3",
649
+
};
650
+
static const char * const qup1_se1_groups[] = {
651
+
"gpio26", "gpio27", "gpio50", "gpio51",
652
+
};
653
+
static const char * const qup1_se2_groups[] = {
654
+
"gpio22", "gpio23", "gpio31", "gpio32",
655
+
};
656
+
static const char * const qup1_se3_groups[] = {
657
+
"gpio24", "gpio25", "gpio51", "gpio50",
658
+
};
659
+
static const char * const qup1_se4_groups[] = {
660
+
"gpio43", "gpio48", "gpio49", "gpio90",
661
+
"gpio91",
662
+
};
663
+
static const char * const sd_write_protect_groups[] = {
664
+
"gpio102",
665
+
};
666
+
static const char * const tb_trig_sdc1_groups[] = {
667
+
"gpio128",
668
+
};
669
+
static const char * const tb_trig_sdc2_groups[] = {
670
+
"gpio51",
671
+
};
672
+
static const char * const tgu_ch0_trigout_groups[] = {
673
+
"gpio20",
674
+
};
675
+
static const char * const tgu_ch1_trigout_groups[] = {
676
+
"gpio21",
677
+
};
678
+
static const char * const tgu_ch2_trigout_groups[] = {
679
+
"gpio22",
680
+
};
681
+
static const char * const tgu_ch3_trigout_groups[] = {
682
+
"gpio23",
683
+
};
684
+
static const char * const tmess_prng_groups[] = {
685
+
"gpio57", "gpio58", "gpio59", "gpio60",
686
+
};
687
+
static const char * const tsense_pwm1_out_groups[] = {
688
+
"gpio134",
689
+
};
690
+
static const char * const tsense_pwm2_out_groups[] = {
691
+
"gpio134",
692
+
};
693
+
static const char * const uim0_groups[] = {
694
+
"gpio64", "gpio63", "gpio66", "gpio65",
695
+
};
696
+
static const char * const uim1_groups[] = {
697
+
"gpio68", "gpio67", "gpio69", "gpio70",
698
+
};
699
+
static const char * const usb0_hs_ac_groups[] = {
700
+
"gpio99",
701
+
};
702
+
static const char * const usb0_phy_ps_groups[] = {
703
+
"gpio94",
704
+
};
705
+
static const char * const vfr_0_mira_groups[] = {
706
+
"gpio19",
707
+
};
708
+
static const char * const vfr_0_mirb_groups[] = {
709
+
"gpio100",
710
+
};
711
+
static const char * const vfr_1_groups[] = {
712
+
"gpio84",
713
+
};
714
+
static const char * const vsense_trigger_mirnat_groups[] = {
715
+
"gpio75",
716
+
};
717
+
static const char * const wlan1_adc_dtest0_groups[] = {
718
+
"gpio79",
719
+
};
720
+
static const char * const wlan1_adc_dtest1_groups[] = {
721
+
"gpio80",
722
+
};
723
+
724
+
static const struct pinfunction sm4450_functions[] = {
725
+
MSM_PIN_FUNCTION(gpio),
726
+
MSM_PIN_FUNCTION(atest_char),
727
+
MSM_PIN_FUNCTION(atest_usb0),
728
+
MSM_PIN_FUNCTION(audio_ref_clk),
729
+
MSM_PIN_FUNCTION(cam_mclk),
730
+
MSM_PIN_FUNCTION(cci_async_in0),
731
+
MSM_PIN_FUNCTION(cci_i2c),
732
+
MSM_PIN_FUNCTION(cci),
733
+
MSM_PIN_FUNCTION(cmu_rng),
734
+
MSM_PIN_FUNCTION(coex_uart1_rx),
735
+
MSM_PIN_FUNCTION(coex_uart1_tx),
736
+
MSM_PIN_FUNCTION(cri_trng),
737
+
MSM_PIN_FUNCTION(dbg_out_clk),
738
+
MSM_PIN_FUNCTION(ddr_bist),
739
+
MSM_PIN_FUNCTION(ddr_pxi0_test),
740
+
MSM_PIN_FUNCTION(ddr_pxi1_test),
741
+
MSM_PIN_FUNCTION(gcc_gp1_clk),
742
+
MSM_PIN_FUNCTION(gcc_gp2_clk),
743
+
MSM_PIN_FUNCTION(gcc_gp3_clk),
744
+
MSM_PIN_FUNCTION(host2wlan_sol),
745
+
MSM_PIN_FUNCTION(ibi_i3c_qup0),
746
+
MSM_PIN_FUNCTION(ibi_i3c_qup1),
747
+
MSM_PIN_FUNCTION(jitter_bist_ref),
748
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
749
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
750
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
751
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
752
+
MSM_PIN_FUNCTION(mdp_vsync),
753
+
MSM_PIN_FUNCTION(nav),
754
+
MSM_PIN_FUNCTION(pcie0_clk_req),
755
+
MSM_PIN_FUNCTION(phase_flag),
756
+
MSM_PIN_FUNCTION(pll_bist_sync),
757
+
MSM_PIN_FUNCTION(pll_clk_aux),
758
+
MSM_PIN_FUNCTION(prng_rosc),
759
+
MSM_PIN_FUNCTION(qdss_cti_trig0),
760
+
MSM_PIN_FUNCTION(qdss_cti_trig1),
761
+
MSM_PIN_FUNCTION(qdss_gpio),
762
+
MSM_PIN_FUNCTION(qlink0_enable),
763
+
MSM_PIN_FUNCTION(qlink0_request),
764
+
MSM_PIN_FUNCTION(qlink0_wmss_reset),
765
+
MSM_PIN_FUNCTION(qup0_se0),
766
+
MSM_PIN_FUNCTION(qup0_se1),
767
+
MSM_PIN_FUNCTION(qup0_se2),
768
+
MSM_PIN_FUNCTION(qup0_se3),
769
+
MSM_PIN_FUNCTION(qup0_se4),
770
+
MSM_PIN_FUNCTION(qup1_se0),
771
+
MSM_PIN_FUNCTION(qup1_se1),
772
+
MSM_PIN_FUNCTION(qup1_se2),
773
+
MSM_PIN_FUNCTION(qup1_se3),
774
+
MSM_PIN_FUNCTION(qup1_se4),
775
+
MSM_PIN_FUNCTION(sd_write_protect),
776
+
MSM_PIN_FUNCTION(tb_trig_sdc1),
777
+
MSM_PIN_FUNCTION(tb_trig_sdc2),
778
+
MSM_PIN_FUNCTION(tgu_ch0_trigout),
779
+
MSM_PIN_FUNCTION(tgu_ch1_trigout),
780
+
MSM_PIN_FUNCTION(tgu_ch2_trigout),
781
+
MSM_PIN_FUNCTION(tgu_ch3_trigout),
782
+
MSM_PIN_FUNCTION(tmess_prng),
783
+
MSM_PIN_FUNCTION(tsense_pwm1_out),
784
+
MSM_PIN_FUNCTION(tsense_pwm2_out),
785
+
MSM_PIN_FUNCTION(uim0),
786
+
MSM_PIN_FUNCTION(uim1),
787
+
MSM_PIN_FUNCTION(usb0_hs_ac),
788
+
MSM_PIN_FUNCTION(usb0_phy_ps),
789
+
MSM_PIN_FUNCTION(vfr_0_mira),
790
+
MSM_PIN_FUNCTION(vfr_0_mirb),
791
+
MSM_PIN_FUNCTION(vfr_1),
792
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
793
+
MSM_PIN_FUNCTION(wlan1_adc_dtest0),
794
+
MSM_PIN_FUNCTION(wlan1_adc_dtest1),
795
+
};
796
+
797
+
/*
798
+
* Every pin is maintained as a single group, and missing or non-existing pin
799
+
* would be maintained as dummy group to synchronize pin group index with
800
+
* pin descriptor registered with pinctrl core.
801
+
* Clients would not be able to request these dummy pin groups.
802
+
*/
803
+
static const struct msm_pingroup sm4450_groups[] = {
804
+
[0] = PINGROUP(0, qup1_se0, ibi_i3c_qup1, cmu_rng, qdss_gpio, _, _, _, _, _),
805
+
[1] = PINGROUP(1, qup1_se0, ibi_i3c_qup1, cmu_rng, qdss_gpio, _, _, _, _, _),
806
+
[2] = PINGROUP(2, qup1_se0, _, _, _, _, _, _, _, _),
807
+
[3] = PINGROUP(3, qup1_se0, gcc_gp3_clk, cmu_rng, qdss_gpio, _, _, _, _, _),
808
+
[4] = PINGROUP(4, qup0_se0, ibi_i3c_qup0, qdss_gpio, _, _, _, _, _, _),
809
+
[5] = PINGROUP(5, qup0_se0, ibi_i3c_qup0, qdss_gpio, _, _, _, _, _, _),
810
+
[6] = PINGROUP(6, qup0_se4, qdss_cti_trig1, _, _, _, _, _, _, _),
811
+
[7] = PINGROUP(7, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
812
+
[8] = PINGROUP(8, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
813
+
[9] = PINGROUP(9, qup0_se4, _, phase_flag, qdss_gpio, _, _, _, _, _),
814
+
[10] = PINGROUP(10, qup0_se1, _, atest_usb0, _, _, _, _, _, _),
815
+
[11] = PINGROUP(11, qup0_se1, _, phase_flag, _, _, _, _, _, _),
816
+
[12] = PINGROUP(12, qup0_se1, _, _, _, _, _, _, _, _),
817
+
[13] = PINGROUP(13, qup0_se1, _, phase_flag, _, _, _, _, _, _),
818
+
[14] = PINGROUP(14, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
819
+
[15] = PINGROUP(15, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
820
+
[16] = PINGROUP(16, qup0_se2, _, _, _, _, _, _, _, _),
821
+
[17] = PINGROUP(17, qup0_se2, _, phase_flag, _, qdss_gpio, _, _, _, _),
822
+
[18] = PINGROUP(18, qup0_se3, _, phase_flag, _, _, _, _, _, _),
823
+
[19] = PINGROUP(19, qup0_se3, vfr_0_mira, _, phase_flag, _, _, _, _, _),
824
+
[20] = PINGROUP(20, qup0_se3, tgu_ch0_trigout, _, _, _, _, _, _, _),
825
+
[21] = PINGROUP(21, qup0_se3, _, phase_flag, tgu_ch1_trigout, _, _, _, _, _),
826
+
[22] = PINGROUP(22, qup1_se2, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, tgu_ch2_trigout, _, _, _, _),
827
+
[23] = PINGROUP(23, qup1_se2, tgu_ch3_trigout, qdss_gpio, _, _, _, _, _, _),
828
+
[24] = PINGROUP(24, qup1_se3, _, phase_flag, _, _, _, _, _, _),
829
+
[25] = PINGROUP(25, qup1_se3, _, phase_flag, _, _, _, _, _, _),
830
+
[26] = PINGROUP(26, qup1_se1, mdp_vsync, qup0_se4, qdss_cti_trig0, _, _, _, _, _),
831
+
[27] = PINGROUP(27, qup1_se1, qup0_se4, qdss_cti_trig1, _, _, _, _, _, _),
832
+
[28] = PINGROUP(28, cmu_rng, _, _, _, _, _, _, _, _),
833
+
[29] = PINGROUP(29, ddr_bist, _, _, _, _, _, _, _, _),
834
+
[30] = PINGROUP(30, mdp_vsync, gcc_gp2_clk, ddr_bist, _, _, _, _, _, _),
835
+
[31] = PINGROUP(31, qup1_se2, _, phase_flag, ddr_bist, qdss_gpio, _, _, _, _),
836
+
[32] = PINGROUP(32, qup1_se2, _, phase_flag, ddr_bist, qdss_gpio, _, _, _, _),
837
+
[33] = PINGROUP(33, _, phase_flag, qdss_gpio, _, _, _, _, _, _),
838
+
[34] = PINGROUP(34, qup0_se0, qup0_se4, mdp_vsync, _, _, _, _, _, _),
839
+
[35] = PINGROUP(35, qup0_se0, _, phase_flag, qdss_gpio, _, _, _, _, _),
840
+
[36] = PINGROUP(36, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
841
+
[37] = PINGROUP(37, cam_mclk, gcc_gp1_clk, prng_rosc, qdss_gpio, _, _, _, _, _),
842
+
[38] = PINGROUP(38, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
843
+
[39] = PINGROUP(39, cam_mclk, prng_rosc, qdss_gpio, _, _, _, _, _, _),
844
+
[40] = PINGROUP(40, cci, cci_async_in0, cri_trng, qdss_gpio, _, _, _, _, _),
845
+
[41] = PINGROUP(41, cci, cri_trng, qdss_gpio, _, _, _, _, _, _),
846
+
[42] = PINGROUP(42, cci, cri_trng, qdss_gpio, _, _, _, _, _, _),
847
+
[43] = PINGROUP(43, cci, qup1_se4, qdss_gpio, _, _, _, _, _, _),
848
+
[44] = PINGROUP(44, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
849
+
[45] = PINGROUP(45, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
850
+
[46] = PINGROUP(46, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
851
+
[47] = PINGROUP(47, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
852
+
[48] = PINGROUP(48, cci_i2c, qup1_se4, gcc_gp1_clk, _, _, _, _, _, _),
853
+
[49] = PINGROUP(49, cci_i2c, qup1_se4, gcc_gp2_clk, qdss_gpio, _, _, _, _, _),
854
+
[50] = PINGROUP(50, qup1_se1, qup1_se3, _, gcc_gp3_clk, _, _, _, _, _),
855
+
[51] = PINGROUP(51, qup1_se1, qup1_se3, _, tb_trig_sdc2, _, _, _, _, _),
856
+
[52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
857
+
[53] = PINGROUP(53, _, _, _, _, _, _, _, _, _),
858
+
[54] = PINGROUP(54, coex_uart1_rx, _, _, _, _, _, _, _, _),
859
+
[55] = PINGROUP(55, coex_uart1_tx, _, _, _, _, _, _, _, _),
860
+
[56] = PINGROUP(56, _, _, _, _, _, _, _, _, _),
861
+
[57] = PINGROUP(57, tmess_prng, qdss_cti_trig1, _, _, _, _, _, _, _),
862
+
[58] = PINGROUP(58, tmess_prng, qdss_cti_trig1, _, _, _, _, _, _, _),
863
+
[59] = PINGROUP(59, tmess_prng, qdss_gpio, _, _, _, _, _, _, _),
864
+
[60] = PINGROUP(60, tmess_prng, qdss_cti_trig0, _, _, _, _, _, _, _),
865
+
[61] = PINGROUP(61, _, phase_flag, _, _, _, _, _, _, _),
866
+
[62] = PINGROUP(62, qdss_gpio, _, _, _, _, _, _, _, _),
867
+
[63] = PINGROUP(63, uim0, _, _, _, _, _, _, _, _),
868
+
[64] = PINGROUP(64, uim0, _, _, _, _, _, _, _, _),
869
+
[65] = PINGROUP(65, uim0, _, _, _, _, _, _, _, _),
870
+
[66] = PINGROUP(66, uim0, _, _, _, _, _, _, _, _),
871
+
[67] = PINGROUP(67, uim1, _, _, _, _, _, _, _, _),
872
+
[68] = PINGROUP(68, uim1, _, _, _, _, _, _, _, _),
873
+
[69] = PINGROUP(69, uim1, _, _, _, _, _, _, _, _),
874
+
[70] = PINGROUP(70, uim1, _, _, _, _, _, _, _, _),
875
+
[71] = PINGROUP(71, _, _, _, audio_ref_clk, _, _, _, _, _),
876
+
[72] = PINGROUP(72, _, _, _, phase_flag, _, _, _, _, _),
877
+
[73] = PINGROUP(73, _, _, _, pll_bist_sync, _, _, _, _, _),
878
+
[74] = PINGROUP(74, _, _, _, _, _, _, _, _, _),
879
+
[75] = PINGROUP(75, _, _, _, vsense_trigger_mirnat, atest_usb0, _, _, _, _),
880
+
[76] = PINGROUP(76, _, _, _, _, _, _, _, _, _),
881
+
[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
882
+
[78] = PINGROUP(78, _, _, _, atest_usb0, _, _, _, _, _),
883
+
[79] = PINGROUP(79, _, _, _, wlan1_adc_dtest0, atest_usb0, _, _, _, _),
884
+
[80] = PINGROUP(80, _, _, dbg_out_clk, wlan1_adc_dtest1, atest_usb0, _, _, _, _),
885
+
[81] = PINGROUP(81, _, nav, _, _, _, _, _, _, _),
886
+
[82] = PINGROUP(82, _, _, phase_flag, _, _, _, _, _, _),
887
+
[83] = PINGROUP(83, nav, _, _, _, _, _, _, _, _),
888
+
[84] = PINGROUP(84, nav, vfr_1, _, _, _, _, _, _, _),
889
+
[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
890
+
[86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
891
+
[87] = PINGROUP(87, qlink0_request, _, _, _, _, _, _, _, _),
892
+
[88] = PINGROUP(88, qlink0_enable, _, _, _, _, _, _, _, _),
893
+
[89] = PINGROUP(89, qlink0_wmss_reset, _, _, _, _, _, _, _, _),
894
+
[90] = PINGROUP(90, qup1_se4, jitter_bist_ref, ddr_pxi0_test, _, _, _, _, _, _),
895
+
[91] = PINGROUP(91, qup1_se4, _, phase_flag, _, _, _, _, _, _),
896
+
[92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
897
+
[93] = PINGROUP(93, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, _, _, _, _, _, _),
898
+
[94] = PINGROUP(94, usb0_phy_ps, _, _, _, _, _, _, _, _),
899
+
[95] = PINGROUP(95, _, phase_flag, atest_char, _, _, _, _, _, _),
900
+
[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
901
+
[97] = PINGROUP(97, mdp_vsync, _, phase_flag, atest_char, _, _, _, _, _),
902
+
[98] = PINGROUP(98, _, phase_flag, atest_char, _, _, _, _, _, _),
903
+
[99] = PINGROUP(99, usb0_hs_ac, _, phase_flag, atest_char, _, _, _, _, _),
904
+
[100] = PINGROUP(100, vfr_0_mirb, _, phase_flag, atest_char, _, _, _, _, _),
905
+
[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _),
906
+
[102] = PINGROUP(102, sd_write_protect, _, _, _, _, _, _, _, _),
907
+
[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _),
908
+
[104] = PINGROUP(104, _, _, _, _, _, _, _, _, _),
909
+
[105] = PINGROUP(105, _, phase_flag, _, _, _, _, _, _, _),
910
+
[106] = PINGROUP(106, host2wlan_sol, _, _, _, _, _, _, _, _),
911
+
[107] = PINGROUP(107, pcie0_clk_req, _, _, _, _, _, _, _, _),
912
+
[108] = PINGROUP(108, pll_clk_aux, _, _, _, _, _, _, _, _),
913
+
[109] = PINGROUP(109, _, _, _, _, _, _, _, _, _),
914
+
[110] = PINGROUP(110, _, _, _, _, _, _, _, _, _),
915
+
[111] = PINGROUP(111, _, _, _, _, _, _, _, _, _),
916
+
[112] = PINGROUP(112, _, _, _, _, _, _, _, _, _),
917
+
[113] = PINGROUP(113, qdss_cti_trig0, _, _, _, _, _, _, _, _),
918
+
[114] = PINGROUP(114, qdss_cti_trig0, _, _, _, _, _, _, _, _),
919
+
[115] = PINGROUP(115, _, phase_flag, _, _, _, _, _, _, _),
920
+
[116] = PINGROUP(116, _, phase_flag, _, _, _, _, _, _, _),
921
+
[117] = PINGROUP(117, _, phase_flag, _, _, _, _, _, _, _),
922
+
[118] = PINGROUP(118, qdss_gpio, _, ddr_pxi1_test, _, _, _, _, _, _),
923
+
[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
924
+
[120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
925
+
[121] = PINGROUP(121, qdss_gpio, _, _, _, _, _, _, _, _),
926
+
[122] = PINGROUP(122, qdss_gpio, _, ddr_pxi1_test, _, _, _, _, _, _),
927
+
[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
928
+
[124] = PINGROUP(124, _, _, _, _, _, _, _, _, _),
929
+
[125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
930
+
[126] = PINGROUP(126, qdss_gpio, _, _, _, _, _, _, _, _),
931
+
[127] = PINGROUP(127, qdss_gpio, ddr_pxi0_test, _, _, _, _, _, _, _),
932
+
[128] = PINGROUP(128, tb_trig_sdc1, _, _, _, _, _, _, _, _),
933
+
[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
934
+
[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
935
+
[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
936
+
[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
937
+
[133] = PINGROUP(133, _, phase_flag, _, _, _, _, _, _, _),
938
+
[134] = PINGROUP(134, tsense_pwm1_out, tsense_pwm2_out, _, _, _, _, _, _, _),
939
+
[135] = PINGROUP(135, _, phase_flag, _, _, _, _, _, _, _),
940
+
[136] = UFS_RESET(ufs_reset, 0x97000),
941
+
[137] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x8c004, 0, 0),
942
+
[138] = SDC_QDSD_PINGROUP(sdc1_clk, 0x8c000, 13, 6),
943
+
[139] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x8c000, 11, 3),
944
+
[140] = SDC_QDSD_PINGROUP(sdc1_data, 0x8c000, 9, 0),
945
+
[141] = SDC_QDSD_PINGROUP(sdc2_clk, 0x8f000, 14, 6),
946
+
[142] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x8f000, 11, 3),
947
+
[143] = SDC_QDSD_PINGROUP(sdc2_data, 0x8f000, 9, 0),
948
+
};
949
+
950
+
static const struct msm_gpio_wakeirq_map sm4450_pdc_map[] = {
951
+
{ 0, 67 }, { 3, 82 }, { 4, 69 }, { 5, 70 }, { 6, 44 }, { 7, 43 },
952
+
{ 8, 71 }, { 9, 86 }, { 10, 48 }, { 11, 77 }, { 12, 90 },
953
+
{ 13, 54 }, { 14, 91 }, { 17, 97 }, { 18, 102 }, { 21, 103 },
954
+
{ 22, 104 }, { 23, 105 }, { 24, 53 }, { 25, 106 }, { 26, 65 },
955
+
{ 27, 55 }, { 28, 89 }, { 30, 80 }, { 31, 109 }, { 33, 87 },
956
+
{ 34, 81 }, { 35, 75 }, { 40, 88 }, { 41, 98 }, { 42, 110 },
957
+
{ 43, 95 }, { 47, 118 }, { 50, 111 }, { 52, 52 }, { 53, 114 },
958
+
{ 54, 115 }, { 55, 99 }, { 56, 45 }, { 57, 85 }, { 58, 56 },
959
+
{ 59, 84 }, { 60, 83 }, { 61, 96 }, { 62, 93 }, { 66, 116 },
960
+
{ 67, 113 }, { 70, 42 }, { 71, 122 }, { 73, 119 }, { 75, 121 },
961
+
{ 77, 120 }, { 79, 123 }, { 81, 124 }, { 83, 64 }, { 84, 128 },
962
+
{ 86, 129 }, { 87, 63 }, { 91, 92 }, { 92, 66 }, { 93, 125 },
963
+
{ 94, 76 }, { 95, 62 }, { 96, 132 }, { 97, 135 }, { 98, 73 },
964
+
{ 99, 133 }, { 101, 46 }, { 102, 134 }, { 103, 49 }, { 105, 58 },
965
+
{ 107, 94 }, { 110, 59 }, { 113, 57 }, { 114, 60 }, { 118, 107 },
966
+
{ 120, 61 }, { 121, 108 }, { 123, 68 }, { 125, 72 }, { 128, 112 },
967
+
};
968
+
969
+
static const struct msm_pinctrl_soc_data sm4450_tlmm = {
970
+
.pins = sm4450_pins,
971
+
.npins = ARRAY_SIZE(sm4450_pins),
972
+
.functions = sm4450_functions,
973
+
.nfunctions = ARRAY_SIZE(sm4450_functions),
974
+
.groups = sm4450_groups,
975
+
.ngroups = ARRAY_SIZE(sm4450_groups),
976
+
.ngpios = 137,
977
+
.wakeirq_map = sm4450_pdc_map,
978
+
.nwakeirq_map = ARRAY_SIZE(sm4450_pdc_map),
979
+
};
980
+
981
+
static int sm4450_tlmm_probe(struct platform_device *pdev)
982
+
{
983
+
return msm_pinctrl_probe(pdev, &sm4450_tlmm);
984
+
}
985
+
986
+
static const struct of_device_id sm4450_tlmm_of_match[] = {
987
+
{ .compatible = "qcom,sm4450-tlmm", },
988
+
{ }
989
+
};
990
+
991
+
static struct platform_driver sm4450_tlmm_driver = {
992
+
.driver = {
993
+
.name = "sm4450-tlmm",
994
+
.of_match_table = sm4450_tlmm_of_match,
995
+
},
996
+
.probe = sm4450_tlmm_probe,
997
+
.remove_new = msm_pinctrl_remove,
998
+
};
999
+
MODULE_DEVICE_TABLE(of, sm4450_tlmm_of_match);
1000
+
1001
+
static int __init sm4450_tlmm_init(void)
1002
+
{
1003
+
return platform_driver_register(&sm4450_tlmm_driver);
1004
+
}
1005
+
arch_initcall(sm4450_tlmm_init);
1006
+
1007
+
static void __exit sm4450_tlmm_exit(void)
1008
+
{
1009
+
platform_driver_unregister(&sm4450_tlmm_driver);
1010
+
}
1011
+
module_exit(sm4450_tlmm_exit);
1012
+
1013
+
MODULE_DESCRIPTION("QTI SM4450 TLMM driver");
1014
+
MODULE_LICENSE("GPL");
-20
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
-20
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
···
36
36
LPI_MUX__,
37
37
};
38
38
39
-
static int gpio0_pins[] = { 0 };
40
-
static int gpio1_pins[] = { 1 };
41
-
static int gpio2_pins[] = { 2 };
42
-
static int gpio3_pins[] = { 3 };
43
-
static int gpio4_pins[] = { 4 };
44
-
static int gpio5_pins[] = { 5 };
45
-
static int gpio6_pins[] = { 6 };
46
-
static int gpio7_pins[] = { 7 };
47
-
static int gpio8_pins[] = { 8 };
48
-
static int gpio9_pins[] = { 9 };
49
-
static int gpio10_pins[] = { 10 };
50
-
static int gpio11_pins[] = { 11 };
51
-
static int gpio12_pins[] = { 12 };
52
-
static int gpio13_pins[] = { 13 };
53
-
static int gpio14_pins[] = { 14 };
54
-
static int gpio15_pins[] = { 15 };
55
-
static int gpio16_pins[] = { 16 };
56
-
static int gpio17_pins[] = { 17 };
57
-
static int gpio18_pins[] = { 18 };
58
-
59
39
static const struct pinctrl_pin_desc sm6115_lpi_pins[] = {
60
40
PINCTRL_PIN(0, "gpio0"),
61
41
PINCTRL_PIN(1, "gpio1"),
-15
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
-15
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
···
36
36
LPI_MUX__,
37
37
};
38
38
39
-
static int gpio0_pins[] = { 0 };
40
-
static int gpio1_pins[] = { 1 };
41
-
static int gpio2_pins[] = { 2 };
42
-
static int gpio3_pins[] = { 3 };
43
-
static int gpio4_pins[] = { 4 };
44
-
static int gpio5_pins[] = { 5 };
45
-
static int gpio6_pins[] = { 6 };
46
-
static int gpio7_pins[] = { 7 };
47
-
static int gpio8_pins[] = { 8 };
48
-
static int gpio9_pins[] = { 9 };
49
-
static int gpio10_pins[] = { 10 };
50
-
static int gpio11_pins[] = { 11 };
51
-
static int gpio12_pins[] = { 12 };
52
-
static int gpio13_pins[] = { 13 };
53
-
54
39
static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
55
40
PINCTRL_PIN(0, "gpio0"),
56
41
PINCTRL_PIN(1, "gpio1"),
-16
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
-16
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
···
36
36
LPI_MUX__,
37
37
};
38
38
39
-
static int gpio0_pins[] = { 0 };
40
-
static int gpio1_pins[] = { 1 };
41
-
static int gpio2_pins[] = { 2 };
42
-
static int gpio3_pins[] = { 3 };
43
-
static int gpio4_pins[] = { 4 };
44
-
static int gpio5_pins[] = { 5 };
45
-
static int gpio6_pins[] = { 6 };
46
-
static int gpio7_pins[] = { 7 };
47
-
static int gpio8_pins[] = { 8 };
48
-
static int gpio9_pins[] = { 9 };
49
-
static int gpio10_pins[] = { 10 };
50
-
static int gpio11_pins[] = { 11 };
51
-
static int gpio12_pins[] = { 12 };
52
-
static int gpio13_pins[] = { 13 };
53
-
static int gpio14_pins[] = { 14 };
54
-
55
39
static const struct pinctrl_pin_desc sm8350_lpi_pins[] = {
56
40
PINCTRL_PIN(0, "gpio0"),
57
41
PINCTRL_PIN(1, "gpio1"),
-24
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
-24
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
···
52
52
LPI_MUX__,
53
53
};
54
54
55
-
static int gpio0_pins[] = { 0 };
56
-
static int gpio1_pins[] = { 1 };
57
-
static int gpio2_pins[] = { 2 };
58
-
static int gpio3_pins[] = { 3 };
59
-
static int gpio4_pins[] = { 4 };
60
-
static int gpio5_pins[] = { 5 };
61
-
static int gpio6_pins[] = { 6 };
62
-
static int gpio7_pins[] = { 7 };
63
-
static int gpio8_pins[] = { 8 };
64
-
static int gpio9_pins[] = { 9 };
65
-
static int gpio10_pins[] = { 10 };
66
-
static int gpio11_pins[] = { 11 };
67
-
static int gpio12_pins[] = { 12 };
68
-
static int gpio13_pins[] = { 13 };
69
-
static int gpio14_pins[] = { 14 };
70
-
static int gpio15_pins[] = { 15 };
71
-
static int gpio16_pins[] = { 16 };
72
-
static int gpio17_pins[] = { 17 };
73
-
static int gpio18_pins[] = { 18 };
74
-
static int gpio19_pins[] = { 19 };
75
-
static int gpio20_pins[] = { 20 };
76
-
static int gpio21_pins[] = { 21 };
77
-
static int gpio22_pins[] = { 22 };
78
-
79
55
static const struct pinctrl_pin_desc sm8450_lpi_pins[] = {
80
56
PINCTRL_PIN(0, "gpio0"),
81
57
PINCTRL_PIN(1, "gpio1"),
-24
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
-24
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
···
52
52
LPI_MUX__,
53
53
};
54
54
55
-
static int gpio0_pins[] = { 0 };
56
-
static int gpio1_pins[] = { 1 };
57
-
static int gpio2_pins[] = { 2 };
58
-
static int gpio3_pins[] = { 3 };
59
-
static int gpio4_pins[] = { 4 };
60
-
static int gpio5_pins[] = { 5 };
61
-
static int gpio6_pins[] = { 6 };
62
-
static int gpio7_pins[] = { 7 };
63
-
static int gpio8_pins[] = { 8 };
64
-
static int gpio9_pins[] = { 9 };
65
-
static int gpio10_pins[] = { 10 };
66
-
static int gpio11_pins[] = { 11 };
67
-
static int gpio12_pins[] = { 12 };
68
-
static int gpio13_pins[] = { 13 };
69
-
static int gpio14_pins[] = { 14 };
70
-
static int gpio15_pins[] = { 15 };
71
-
static int gpio16_pins[] = { 16 };
72
-
static int gpio17_pins[] = { 17 };
73
-
static int gpio18_pins[] = { 18 };
74
-
static int gpio19_pins[] = { 19 };
75
-
static int gpio20_pins[] = { 20 };
76
-
static int gpio21_pins[] = { 21 };
77
-
static int gpio22_pins[] = { 22 };
78
-
79
55
static const struct pinctrl_pin_desc sm8550_lpi_pins[] = {
80
56
PINCTRL_PIN(0, "gpio0"),
81
57
PINCTRL_PIN(1, "gpio1"),
+231
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
+231
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022-2023 Linaro Ltd.
4
+
*/
5
+
6
+
#include <linux/gpio/driver.h>
7
+
#include <linux/module.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-lpass-lpi.h"
11
+
12
+
enum lpass_lpi_functions {
13
+
LPI_MUX_dmic1_clk,
14
+
LPI_MUX_dmic1_data,
15
+
LPI_MUX_dmic2_clk,
16
+
LPI_MUX_dmic2_data,
17
+
LPI_MUX_dmic3_clk,
18
+
LPI_MUX_dmic3_data,
19
+
LPI_MUX_dmic4_clk,
20
+
LPI_MUX_dmic4_data,
21
+
LPI_MUX_i2s0_clk,
22
+
LPI_MUX_i2s0_data,
23
+
LPI_MUX_i2s0_ws,
24
+
LPI_MUX_i2s1_clk,
25
+
LPI_MUX_i2s1_data,
26
+
LPI_MUX_i2s1_ws,
27
+
LPI_MUX_i2s2_clk,
28
+
LPI_MUX_i2s2_data,
29
+
LPI_MUX_i2s2_ws,
30
+
LPI_MUX_i2s3_clk,
31
+
LPI_MUX_i2s3_data,
32
+
LPI_MUX_i2s3_ws,
33
+
LPI_MUX_i2s4_clk,
34
+
LPI_MUX_i2s4_data,
35
+
LPI_MUX_i2s4_ws,
36
+
LPI_MUX_qca_swr_clk,
37
+
LPI_MUX_qca_swr_data,
38
+
LPI_MUX_slimbus_clk,
39
+
LPI_MUX_slimbus_data,
40
+
LPI_MUX_swr_rx_clk,
41
+
LPI_MUX_swr_rx_data,
42
+
LPI_MUX_swr_tx_clk,
43
+
LPI_MUX_swr_tx_data,
44
+
LPI_MUX_wsa_swr_clk,
45
+
LPI_MUX_wsa_swr_data,
46
+
LPI_MUX_wsa2_swr_clk,
47
+
LPI_MUX_wsa2_swr_data,
48
+
LPI_MUX_ext_mclk1_a,
49
+
LPI_MUX_ext_mclk1_b,
50
+
LPI_MUX_ext_mclk1_c,
51
+
LPI_MUX_ext_mclk1_d,
52
+
LPI_MUX_ext_mclk1_e,
53
+
LPI_MUX_gpio,
54
+
LPI_MUX__,
55
+
};
56
+
57
+
static const struct pinctrl_pin_desc sm8650_lpi_pins[] = {
58
+
PINCTRL_PIN(0, "gpio0"),
59
+
PINCTRL_PIN(1, "gpio1"),
60
+
PINCTRL_PIN(2, "gpio2"),
61
+
PINCTRL_PIN(3, "gpio3"),
62
+
PINCTRL_PIN(4, "gpio4"),
63
+
PINCTRL_PIN(5, "gpio5"),
64
+
PINCTRL_PIN(6, "gpio6"),
65
+
PINCTRL_PIN(7, "gpio7"),
66
+
PINCTRL_PIN(8, "gpio8"),
67
+
PINCTRL_PIN(9, "gpio9"),
68
+
PINCTRL_PIN(10, "gpio10"),
69
+
PINCTRL_PIN(11, "gpio11"),
70
+
PINCTRL_PIN(12, "gpio12"),
71
+
PINCTRL_PIN(13, "gpio13"),
72
+
PINCTRL_PIN(14, "gpio14"),
73
+
PINCTRL_PIN(15, "gpio15"),
74
+
PINCTRL_PIN(16, "gpio16"),
75
+
PINCTRL_PIN(17, "gpio17"),
76
+
PINCTRL_PIN(18, "gpio18"),
77
+
PINCTRL_PIN(19, "gpio19"),
78
+
PINCTRL_PIN(20, "gpio20"),
79
+
PINCTRL_PIN(21, "gpio21"),
80
+
PINCTRL_PIN(22, "gpio22"),
81
+
};
82
+
83
+
static const char * const gpio_groups[] = {
84
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
85
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
86
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
87
+
"gpio22",
88
+
};
89
+
90
+
static const char * const dmic1_clk_groups[] = { "gpio6" };
91
+
static const char * const dmic1_data_groups[] = { "gpio7" };
92
+
static const char * const dmic2_clk_groups[] = { "gpio8" };
93
+
static const char * const dmic2_data_groups[] = { "gpio9" };
94
+
static const char * const dmic3_clk_groups[] = { "gpio12" };
95
+
static const char * const dmic3_data_groups[] = { "gpio13" };
96
+
static const char * const dmic4_clk_groups[] = { "gpio17" };
97
+
static const char * const dmic4_data_groups[] = { "gpio18" };
98
+
static const char * const i2s0_clk_groups[] = { "gpio0" };
99
+
static const char * const i2s0_ws_groups[] = { "gpio1" };
100
+
static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
101
+
static const char * const i2s1_clk_groups[] = { "gpio6" };
102
+
static const char * const i2s1_ws_groups[] = { "gpio7" };
103
+
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
104
+
static const char * const i2s2_clk_groups[] = { "gpio10" };
105
+
static const char * const i2s2_ws_groups[] = { "gpio11" };
106
+
static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" };
107
+
static const char * const i2s3_clk_groups[] = { "gpio12" };
108
+
static const char * const i2s3_ws_groups[] = { "gpio13" };
109
+
static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" };
110
+
static const char * const i2s4_clk_groups[] = { "gpio19"};
111
+
static const char * const i2s4_ws_groups[] = { "gpio20"};
112
+
static const char * const i2s4_data_groups[] = { "gpio21", "gpio22"};
113
+
static const char * const qca_swr_clk_groups[] = { "gpio19" };
114
+
static const char * const qca_swr_data_groups[] = { "gpio20" };
115
+
static const char * const slimbus_clk_groups[] = { "gpio19"};
116
+
static const char * const slimbus_data_groups[] = { "gpio20"};
117
+
static const char * const swr_tx_clk_groups[] = { "gpio0" };
118
+
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
119
+
static const char * const swr_rx_clk_groups[] = { "gpio3" };
120
+
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" };
121
+
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
122
+
static const char * const wsa_swr_data_groups[] = { "gpio11" };
123
+
static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
124
+
static const char * const wsa2_swr_data_groups[] = { "gpio16" };
125
+
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
126
+
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
127
+
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
128
+
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
129
+
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
130
+
131
+
static const struct lpi_pingroup sm8650_groups[] = {
132
+
LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _),
133
+
LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _),
134
+
LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _),
135
+
LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _),
136
+
LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _),
137
+
LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _),
138
+
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
139
+
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
140
+
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
141
+
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
142
+
LPI_PINGROUP(10, 11, i2s2_clk, wsa_swr_clk, _, _),
143
+
LPI_PINGROUP(11, 11, i2s2_ws, wsa_swr_data, _, _),
144
+
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _),
145
+
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _),
146
+
LPI_PINGROUP(14, 11, swr_tx_data, ext_mclk1_d, _, _),
147
+
LPI_PINGROUP(15, 11, i2s2_data, wsa2_swr_clk, _, _),
148
+
LPI_PINGROUP(16, 11, i2s2_data, wsa2_swr_data, _, _),
149
+
LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _),
150
+
LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _),
151
+
LPI_PINGROUP(19, 11, i2s4_clk, slimbus_clk, qca_swr_clk, _),
152
+
LPI_PINGROUP(20, 11, i2s4_ws, slimbus_data, qca_swr_data, _),
153
+
LPI_PINGROUP(21, LPI_NO_SLEW, i2s4_data, _, _, _),
154
+
LPI_PINGROUP(22, LPI_NO_SLEW, i2s4_data, ext_mclk1_e, _, _),
155
+
};
156
+
157
+
static const struct lpi_function sm8650_functions[] = {
158
+
LPI_FUNCTION(gpio),
159
+
LPI_FUNCTION(dmic1_clk),
160
+
LPI_FUNCTION(dmic1_data),
161
+
LPI_FUNCTION(dmic2_clk),
162
+
LPI_FUNCTION(dmic2_data),
163
+
LPI_FUNCTION(dmic3_clk),
164
+
LPI_FUNCTION(dmic3_data),
165
+
LPI_FUNCTION(dmic4_clk),
166
+
LPI_FUNCTION(dmic4_data),
167
+
LPI_FUNCTION(i2s0_clk),
168
+
LPI_FUNCTION(i2s0_data),
169
+
LPI_FUNCTION(i2s0_ws),
170
+
LPI_FUNCTION(i2s1_clk),
171
+
LPI_FUNCTION(i2s1_data),
172
+
LPI_FUNCTION(i2s1_ws),
173
+
LPI_FUNCTION(i2s2_clk),
174
+
LPI_FUNCTION(i2s2_data),
175
+
LPI_FUNCTION(i2s2_ws),
176
+
LPI_FUNCTION(i2s3_clk),
177
+
LPI_FUNCTION(i2s3_data),
178
+
LPI_FUNCTION(i2s3_ws),
179
+
LPI_FUNCTION(i2s4_clk),
180
+
LPI_FUNCTION(i2s4_data),
181
+
LPI_FUNCTION(i2s4_ws),
182
+
LPI_FUNCTION(qca_swr_clk),
183
+
LPI_FUNCTION(qca_swr_data),
184
+
LPI_FUNCTION(slimbus_clk),
185
+
LPI_FUNCTION(slimbus_data),
186
+
LPI_FUNCTION(swr_rx_clk),
187
+
LPI_FUNCTION(swr_rx_data),
188
+
LPI_FUNCTION(swr_tx_clk),
189
+
LPI_FUNCTION(swr_tx_data),
190
+
LPI_FUNCTION(wsa_swr_clk),
191
+
LPI_FUNCTION(wsa_swr_data),
192
+
LPI_FUNCTION(wsa2_swr_clk),
193
+
LPI_FUNCTION(wsa2_swr_data),
194
+
LPI_FUNCTION(ext_mclk1_a),
195
+
LPI_FUNCTION(ext_mclk1_b),
196
+
LPI_FUNCTION(ext_mclk1_c),
197
+
LPI_FUNCTION(ext_mclk1_d),
198
+
LPI_FUNCTION(ext_mclk1_e),
199
+
};
200
+
201
+
static const struct lpi_pinctrl_variant_data sm8650_lpi_data = {
202
+
.pins = sm8650_lpi_pins,
203
+
.npins = ARRAY_SIZE(sm8650_lpi_pins),
204
+
.groups = sm8650_groups,
205
+
.ngroups = ARRAY_SIZE(sm8650_groups),
206
+
.functions = sm8650_functions,
207
+
.nfunctions = ARRAY_SIZE(sm8650_functions),
208
+
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
209
+
};
210
+
211
+
static const struct of_device_id lpi_pinctrl_of_match[] = {
212
+
{
213
+
.compatible = "qcom,sm8650-lpass-lpi-pinctrl",
214
+
.data = &sm8650_lpi_data,
215
+
},
216
+
{ }
217
+
};
218
+
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
219
+
220
+
static struct platform_driver lpi_pinctrl_driver = {
221
+
.driver = {
222
+
.name = "qcom-sm8650-lpass-lpi-pinctrl",
223
+
.of_match_table = lpi_pinctrl_of_match,
224
+
},
225
+
.probe = lpi_pinctrl_probe,
226
+
.remove_new = lpi_pinctrl_remove,
227
+
};
228
+
229
+
module_platform_driver(lpi_pinctrl_driver);
230
+
MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");
231
+
MODULE_LICENSE("GPL");
+1762
drivers/pinctrl/qcom/pinctrl-sm8650.c
+1762
drivers/pinctrl/qcom/pinctrl-sm8650.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5
+
* Copyright (c) 2023, Linaro Limited
6
+
*/
7
+
8
+
#include <linux/module.h>
9
+
#include <linux/of.h>
10
+
#include <linux/platform_device.h>
11
+
12
+
#include "pinctrl-msm.h"
13
+
14
+
#define REG_SIZE 0x1000
15
+
16
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
17
+
{ \
18
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
19
+
gpio##id##_pins, \
20
+
ARRAY_SIZE(gpio##id##_pins)), \
21
+
.funcs = (int[]){ \
22
+
msm_mux_gpio, /* gpio mode */ \
23
+
msm_mux_##f1, \
24
+
msm_mux_##f2, \
25
+
msm_mux_##f3, \
26
+
msm_mux_##f4, \
27
+
msm_mux_##f5, \
28
+
msm_mux_##f6, \
29
+
msm_mux_##f7, \
30
+
msm_mux_##f8, \
31
+
msm_mux_##f9, \
32
+
msm_mux_##f10 \
33
+
}, \
34
+
.nfuncs = 11, \
35
+
.ctl_reg = REG_SIZE * id, \
36
+
.io_reg = 0x4 + REG_SIZE * id, \
37
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
38
+
.intr_status_reg = 0xc + REG_SIZE * id, \
39
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
40
+
.mux_bit = 2, \
41
+
.pull_bit = 0, \
42
+
.drv_bit = 6, \
43
+
.i2c_pull_bit = 13, \
44
+
.egpio_enable = 12, \
45
+
.egpio_present = 11, \
46
+
.oe_bit = 9, \
47
+
.in_bit = 0, \
48
+
.out_bit = 1, \
49
+
.intr_enable_bit = 0, \
50
+
.intr_status_bit = 0, \
51
+
.intr_wakeup_present_bit = 6, \
52
+
.intr_wakeup_enable_bit = 7, \
53
+
.intr_target_bit = 8, \
54
+
.intr_target_kpss_val = 3, \
55
+
.intr_raw_status_bit = 4, \
56
+
.intr_polarity_bit = 1, \
57
+
.intr_detection_bit = 2, \
58
+
.intr_detection_width = 2, \
59
+
}
60
+
61
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
62
+
{ \
63
+
.grp = PINCTRL_PINGROUP(#pg_name, \
64
+
pg_name##_pins, \
65
+
ARRAY_SIZE(pg_name##_pins)), \
66
+
.ctl_reg = ctl, \
67
+
.io_reg = 0, \
68
+
.intr_cfg_reg = 0, \
69
+
.intr_status_reg = 0, \
70
+
.intr_target_reg = 0, \
71
+
.mux_bit = -1, \
72
+
.pull_bit = pull, \
73
+
.drv_bit = drv, \
74
+
.oe_bit = -1, \
75
+
.in_bit = -1, \
76
+
.out_bit = -1, \
77
+
.intr_enable_bit = -1, \
78
+
.intr_status_bit = -1, \
79
+
.intr_target_bit = -1, \
80
+
.intr_raw_status_bit = -1, \
81
+
.intr_polarity_bit = -1, \
82
+
.intr_detection_bit = -1, \
83
+
.intr_detection_width = -1, \
84
+
}
85
+
86
+
#define UFS_RESET(pg_name, ctl, io) \
87
+
{ \
88
+
.grp = PINCTRL_PINGROUP(#pg_name, \
89
+
pg_name##_pins, \
90
+
ARRAY_SIZE(pg_name##_pins)), \
91
+
.ctl_reg = ctl, \
92
+
.io_reg = io, \
93
+
.intr_cfg_reg = 0, \
94
+
.intr_status_reg = 0, \
95
+
.intr_target_reg = 0, \
96
+
.mux_bit = -1, \
97
+
.pull_bit = 3, \
98
+
.drv_bit = 0, \
99
+
.oe_bit = -1, \
100
+
.in_bit = -1, \
101
+
.out_bit = 0, \
102
+
.intr_enable_bit = -1, \
103
+
.intr_status_bit = -1, \
104
+
.intr_target_bit = -1, \
105
+
.intr_raw_status_bit = -1, \
106
+
.intr_polarity_bit = -1, \
107
+
.intr_detection_bit = -1, \
108
+
.intr_detection_width = -1, \
109
+
}
110
+
111
+
static const struct pinctrl_pin_desc sm8650_pins[] = {
112
+
PINCTRL_PIN(0, "GPIO_0"),
113
+
PINCTRL_PIN(1, "GPIO_1"),
114
+
PINCTRL_PIN(2, "GPIO_2"),
115
+
PINCTRL_PIN(3, "GPIO_3"),
116
+
PINCTRL_PIN(4, "GPIO_4"),
117
+
PINCTRL_PIN(5, "GPIO_5"),
118
+
PINCTRL_PIN(6, "GPIO_6"),
119
+
PINCTRL_PIN(7, "GPIO_7"),
120
+
PINCTRL_PIN(8, "GPIO_8"),
121
+
PINCTRL_PIN(9, "GPIO_9"),
122
+
PINCTRL_PIN(10, "GPIO_10"),
123
+
PINCTRL_PIN(11, "GPIO_11"),
124
+
PINCTRL_PIN(12, "GPIO_12"),
125
+
PINCTRL_PIN(13, "GPIO_13"),
126
+
PINCTRL_PIN(14, "GPIO_14"),
127
+
PINCTRL_PIN(15, "GPIO_15"),
128
+
PINCTRL_PIN(16, "GPIO_16"),
129
+
PINCTRL_PIN(17, "GPIO_17"),
130
+
PINCTRL_PIN(18, "GPIO_18"),
131
+
PINCTRL_PIN(19, "GPIO_19"),
132
+
PINCTRL_PIN(20, "GPIO_20"),
133
+
PINCTRL_PIN(21, "GPIO_21"),
134
+
PINCTRL_PIN(22, "GPIO_22"),
135
+
PINCTRL_PIN(23, "GPIO_23"),
136
+
PINCTRL_PIN(24, "GPIO_24"),
137
+
PINCTRL_PIN(25, "GPIO_25"),
138
+
PINCTRL_PIN(26, "GPIO_26"),
139
+
PINCTRL_PIN(27, "GPIO_27"),
140
+
PINCTRL_PIN(28, "GPIO_28"),
141
+
PINCTRL_PIN(29, "GPIO_29"),
142
+
PINCTRL_PIN(30, "GPIO_30"),
143
+
PINCTRL_PIN(31, "GPIO_31"),
144
+
PINCTRL_PIN(32, "GPIO_32"),
145
+
PINCTRL_PIN(33, "GPIO_33"),
146
+
PINCTRL_PIN(34, "GPIO_34"),
147
+
PINCTRL_PIN(35, "GPIO_35"),
148
+
PINCTRL_PIN(36, "GPIO_36"),
149
+
PINCTRL_PIN(37, "GPIO_37"),
150
+
PINCTRL_PIN(38, "GPIO_38"),
151
+
PINCTRL_PIN(39, "GPIO_39"),
152
+
PINCTRL_PIN(40, "GPIO_40"),
153
+
PINCTRL_PIN(41, "GPIO_41"),
154
+
PINCTRL_PIN(42, "GPIO_42"),
155
+
PINCTRL_PIN(43, "GPIO_43"),
156
+
PINCTRL_PIN(44, "GPIO_44"),
157
+
PINCTRL_PIN(45, "GPIO_45"),
158
+
PINCTRL_PIN(46, "GPIO_46"),
159
+
PINCTRL_PIN(47, "GPIO_47"),
160
+
PINCTRL_PIN(48, "GPIO_48"),
161
+
PINCTRL_PIN(49, "GPIO_49"),
162
+
PINCTRL_PIN(50, "GPIO_50"),
163
+
PINCTRL_PIN(51, "GPIO_51"),
164
+
PINCTRL_PIN(52, "GPIO_52"),
165
+
PINCTRL_PIN(53, "GPIO_53"),
166
+
PINCTRL_PIN(54, "GPIO_54"),
167
+
PINCTRL_PIN(55, "GPIO_55"),
168
+
PINCTRL_PIN(56, "GPIO_56"),
169
+
PINCTRL_PIN(57, "GPIO_57"),
170
+
PINCTRL_PIN(58, "GPIO_58"),
171
+
PINCTRL_PIN(59, "GPIO_59"),
172
+
PINCTRL_PIN(60, "GPIO_60"),
173
+
PINCTRL_PIN(61, "GPIO_61"),
174
+
PINCTRL_PIN(62, "GPIO_62"),
175
+
PINCTRL_PIN(63, "GPIO_63"),
176
+
PINCTRL_PIN(64, "GPIO_64"),
177
+
PINCTRL_PIN(65, "GPIO_65"),
178
+
PINCTRL_PIN(66, "GPIO_66"),
179
+
PINCTRL_PIN(67, "GPIO_67"),
180
+
PINCTRL_PIN(68, "GPIO_68"),
181
+
PINCTRL_PIN(69, "GPIO_69"),
182
+
PINCTRL_PIN(70, "GPIO_70"),
183
+
PINCTRL_PIN(71, "GPIO_71"),
184
+
PINCTRL_PIN(72, "GPIO_72"),
185
+
PINCTRL_PIN(73, "GPIO_73"),
186
+
PINCTRL_PIN(74, "GPIO_74"),
187
+
PINCTRL_PIN(75, "GPIO_75"),
188
+
PINCTRL_PIN(76, "GPIO_76"),
189
+
PINCTRL_PIN(77, "GPIO_77"),
190
+
PINCTRL_PIN(78, "GPIO_78"),
191
+
PINCTRL_PIN(79, "GPIO_79"),
192
+
PINCTRL_PIN(80, "GPIO_80"),
193
+
PINCTRL_PIN(81, "GPIO_81"),
194
+
PINCTRL_PIN(82, "GPIO_82"),
195
+
PINCTRL_PIN(83, "GPIO_83"),
196
+
PINCTRL_PIN(84, "GPIO_84"),
197
+
PINCTRL_PIN(85, "GPIO_85"),
198
+
PINCTRL_PIN(86, "GPIO_86"),
199
+
PINCTRL_PIN(87, "GPIO_87"),
200
+
PINCTRL_PIN(88, "GPIO_88"),
201
+
PINCTRL_PIN(89, "GPIO_89"),
202
+
PINCTRL_PIN(90, "GPIO_90"),
203
+
PINCTRL_PIN(91, "GPIO_91"),
204
+
PINCTRL_PIN(92, "GPIO_92"),
205
+
PINCTRL_PIN(93, "GPIO_93"),
206
+
PINCTRL_PIN(94, "GPIO_94"),
207
+
PINCTRL_PIN(95, "GPIO_95"),
208
+
PINCTRL_PIN(96, "GPIO_96"),
209
+
PINCTRL_PIN(97, "GPIO_97"),
210
+
PINCTRL_PIN(98, "GPIO_98"),
211
+
PINCTRL_PIN(99, "GPIO_99"),
212
+
PINCTRL_PIN(100, "GPIO_100"),
213
+
PINCTRL_PIN(101, "GPIO_101"),
214
+
PINCTRL_PIN(102, "GPIO_102"),
215
+
PINCTRL_PIN(103, "GPIO_103"),
216
+
PINCTRL_PIN(104, "GPIO_104"),
217
+
PINCTRL_PIN(105, "GPIO_105"),
218
+
PINCTRL_PIN(106, "GPIO_106"),
219
+
PINCTRL_PIN(107, "GPIO_107"),
220
+
PINCTRL_PIN(108, "GPIO_108"),
221
+
PINCTRL_PIN(109, "GPIO_109"),
222
+
PINCTRL_PIN(110, "GPIO_110"),
223
+
PINCTRL_PIN(111, "GPIO_111"),
224
+
PINCTRL_PIN(112, "GPIO_112"),
225
+
PINCTRL_PIN(113, "GPIO_113"),
226
+
PINCTRL_PIN(114, "GPIO_114"),
227
+
PINCTRL_PIN(115, "GPIO_115"),
228
+
PINCTRL_PIN(116, "GPIO_116"),
229
+
PINCTRL_PIN(117, "GPIO_117"),
230
+
PINCTRL_PIN(118, "GPIO_118"),
231
+
PINCTRL_PIN(119, "GPIO_119"),
232
+
PINCTRL_PIN(120, "GPIO_120"),
233
+
PINCTRL_PIN(121, "GPIO_121"),
234
+
PINCTRL_PIN(122, "GPIO_122"),
235
+
PINCTRL_PIN(123, "GPIO_123"),
236
+
PINCTRL_PIN(124, "GPIO_124"),
237
+
PINCTRL_PIN(125, "GPIO_125"),
238
+
PINCTRL_PIN(126, "GPIO_126"),
239
+
PINCTRL_PIN(127, "GPIO_127"),
240
+
PINCTRL_PIN(128, "GPIO_128"),
241
+
PINCTRL_PIN(129, "GPIO_129"),
242
+
PINCTRL_PIN(130, "GPIO_130"),
243
+
PINCTRL_PIN(131, "GPIO_131"),
244
+
PINCTRL_PIN(132, "GPIO_132"),
245
+
PINCTRL_PIN(133, "GPIO_133"),
246
+
PINCTRL_PIN(134, "GPIO_134"),
247
+
PINCTRL_PIN(135, "GPIO_135"),
248
+
PINCTRL_PIN(136, "GPIO_136"),
249
+
PINCTRL_PIN(137, "GPIO_137"),
250
+
PINCTRL_PIN(138, "GPIO_138"),
251
+
PINCTRL_PIN(139, "GPIO_139"),
252
+
PINCTRL_PIN(140, "GPIO_140"),
253
+
PINCTRL_PIN(141, "GPIO_141"),
254
+
PINCTRL_PIN(142, "GPIO_142"),
255
+
PINCTRL_PIN(143, "GPIO_143"),
256
+
PINCTRL_PIN(144, "GPIO_144"),
257
+
PINCTRL_PIN(145, "GPIO_145"),
258
+
PINCTRL_PIN(146, "GPIO_146"),
259
+
PINCTRL_PIN(147, "GPIO_147"),
260
+
PINCTRL_PIN(148, "GPIO_148"),
261
+
PINCTRL_PIN(149, "GPIO_149"),
262
+
PINCTRL_PIN(150, "GPIO_150"),
263
+
PINCTRL_PIN(151, "GPIO_151"),
264
+
PINCTRL_PIN(152, "GPIO_152"),
265
+
PINCTRL_PIN(153, "GPIO_153"),
266
+
PINCTRL_PIN(154, "GPIO_154"),
267
+
PINCTRL_PIN(155, "GPIO_155"),
268
+
PINCTRL_PIN(156, "GPIO_156"),
269
+
PINCTRL_PIN(157, "GPIO_157"),
270
+
PINCTRL_PIN(158, "GPIO_158"),
271
+
PINCTRL_PIN(159, "GPIO_159"),
272
+
PINCTRL_PIN(160, "GPIO_160"),
273
+
PINCTRL_PIN(161, "GPIO_161"),
274
+
PINCTRL_PIN(162, "GPIO_162"),
275
+
PINCTRL_PIN(163, "GPIO_163"),
276
+
PINCTRL_PIN(164, "GPIO_164"),
277
+
PINCTRL_PIN(165, "GPIO_165"),
278
+
PINCTRL_PIN(166, "GPIO_166"),
279
+
PINCTRL_PIN(167, "GPIO_167"),
280
+
PINCTRL_PIN(168, "GPIO_168"),
281
+
PINCTRL_PIN(169, "GPIO_169"),
282
+
PINCTRL_PIN(170, "GPIO_170"),
283
+
PINCTRL_PIN(171, "GPIO_171"),
284
+
PINCTRL_PIN(172, "GPIO_172"),
285
+
PINCTRL_PIN(173, "GPIO_173"),
286
+
PINCTRL_PIN(174, "GPIO_174"),
287
+
PINCTRL_PIN(175, "GPIO_175"),
288
+
PINCTRL_PIN(176, "GPIO_176"),
289
+
PINCTRL_PIN(177, "GPIO_177"),
290
+
PINCTRL_PIN(178, "GPIO_178"),
291
+
PINCTRL_PIN(179, "GPIO_179"),
292
+
PINCTRL_PIN(180, "GPIO_180"),
293
+
PINCTRL_PIN(181, "GPIO_181"),
294
+
PINCTRL_PIN(182, "GPIO_182"),
295
+
PINCTRL_PIN(183, "GPIO_183"),
296
+
PINCTRL_PIN(184, "GPIO_184"),
297
+
PINCTRL_PIN(185, "GPIO_185"),
298
+
PINCTRL_PIN(186, "GPIO_186"),
299
+
PINCTRL_PIN(187, "GPIO_187"),
300
+
PINCTRL_PIN(188, "GPIO_188"),
301
+
PINCTRL_PIN(189, "GPIO_189"),
302
+
PINCTRL_PIN(190, "GPIO_190"),
303
+
PINCTRL_PIN(191, "GPIO_191"),
304
+
PINCTRL_PIN(192, "GPIO_192"),
305
+
PINCTRL_PIN(193, "GPIO_193"),
306
+
PINCTRL_PIN(194, "GPIO_194"),
307
+
PINCTRL_PIN(195, "GPIO_195"),
308
+
PINCTRL_PIN(196, "GPIO_196"),
309
+
PINCTRL_PIN(197, "GPIO_197"),
310
+
PINCTRL_PIN(198, "GPIO_198"),
311
+
PINCTRL_PIN(199, "GPIO_199"),
312
+
PINCTRL_PIN(200, "GPIO_200"),
313
+
PINCTRL_PIN(201, "GPIO_201"),
314
+
PINCTRL_PIN(202, "GPIO_202"),
315
+
PINCTRL_PIN(203, "GPIO_203"),
316
+
PINCTRL_PIN(204, "GPIO_204"),
317
+
PINCTRL_PIN(205, "GPIO_205"),
318
+
PINCTRL_PIN(206, "GPIO_206"),
319
+
PINCTRL_PIN(207, "GPIO_207"),
320
+
PINCTRL_PIN(208, "GPIO_208"),
321
+
PINCTRL_PIN(209, "GPIO_209"),
322
+
PINCTRL_PIN(210, "UFS_RESET"),
323
+
PINCTRL_PIN(211, "SDC2_CLK"),
324
+
PINCTRL_PIN(212, "SDC2_CMD"),
325
+
PINCTRL_PIN(213, "SDC2_DATA"),
326
+
};
327
+
328
+
#define DECLARE_MSM_GPIO_PINS(pin) \
329
+
static const unsigned int gpio##pin##_pins[] = { pin }
330
+
DECLARE_MSM_GPIO_PINS(0);
331
+
DECLARE_MSM_GPIO_PINS(1);
332
+
DECLARE_MSM_GPIO_PINS(2);
333
+
DECLARE_MSM_GPIO_PINS(3);
334
+
DECLARE_MSM_GPIO_PINS(4);
335
+
DECLARE_MSM_GPIO_PINS(5);
336
+
DECLARE_MSM_GPIO_PINS(6);
337
+
DECLARE_MSM_GPIO_PINS(7);
338
+
DECLARE_MSM_GPIO_PINS(8);
339
+
DECLARE_MSM_GPIO_PINS(9);
340
+
DECLARE_MSM_GPIO_PINS(10);
341
+
DECLARE_MSM_GPIO_PINS(11);
342
+
DECLARE_MSM_GPIO_PINS(12);
343
+
DECLARE_MSM_GPIO_PINS(13);
344
+
DECLARE_MSM_GPIO_PINS(14);
345
+
DECLARE_MSM_GPIO_PINS(15);
346
+
DECLARE_MSM_GPIO_PINS(16);
347
+
DECLARE_MSM_GPIO_PINS(17);
348
+
DECLARE_MSM_GPIO_PINS(18);
349
+
DECLARE_MSM_GPIO_PINS(19);
350
+
DECLARE_MSM_GPIO_PINS(20);
351
+
DECLARE_MSM_GPIO_PINS(21);
352
+
DECLARE_MSM_GPIO_PINS(22);
353
+
DECLARE_MSM_GPIO_PINS(23);
354
+
DECLARE_MSM_GPIO_PINS(24);
355
+
DECLARE_MSM_GPIO_PINS(25);
356
+
DECLARE_MSM_GPIO_PINS(26);
357
+
DECLARE_MSM_GPIO_PINS(27);
358
+
DECLARE_MSM_GPIO_PINS(28);
359
+
DECLARE_MSM_GPIO_PINS(29);
360
+
DECLARE_MSM_GPIO_PINS(30);
361
+
DECLARE_MSM_GPIO_PINS(31);
362
+
DECLARE_MSM_GPIO_PINS(32);
363
+
DECLARE_MSM_GPIO_PINS(33);
364
+
DECLARE_MSM_GPIO_PINS(34);
365
+
DECLARE_MSM_GPIO_PINS(35);
366
+
DECLARE_MSM_GPIO_PINS(36);
367
+
DECLARE_MSM_GPIO_PINS(37);
368
+
DECLARE_MSM_GPIO_PINS(38);
369
+
DECLARE_MSM_GPIO_PINS(39);
370
+
DECLARE_MSM_GPIO_PINS(40);
371
+
DECLARE_MSM_GPIO_PINS(41);
372
+
DECLARE_MSM_GPIO_PINS(42);
373
+
DECLARE_MSM_GPIO_PINS(43);
374
+
DECLARE_MSM_GPIO_PINS(44);
375
+
DECLARE_MSM_GPIO_PINS(45);
376
+
DECLARE_MSM_GPIO_PINS(46);
377
+
DECLARE_MSM_GPIO_PINS(47);
378
+
DECLARE_MSM_GPIO_PINS(48);
379
+
DECLARE_MSM_GPIO_PINS(49);
380
+
DECLARE_MSM_GPIO_PINS(50);
381
+
DECLARE_MSM_GPIO_PINS(51);
382
+
DECLARE_MSM_GPIO_PINS(52);
383
+
DECLARE_MSM_GPIO_PINS(53);
384
+
DECLARE_MSM_GPIO_PINS(54);
385
+
DECLARE_MSM_GPIO_PINS(55);
386
+
DECLARE_MSM_GPIO_PINS(56);
387
+
DECLARE_MSM_GPIO_PINS(57);
388
+
DECLARE_MSM_GPIO_PINS(58);
389
+
DECLARE_MSM_GPIO_PINS(59);
390
+
DECLARE_MSM_GPIO_PINS(60);
391
+
DECLARE_MSM_GPIO_PINS(61);
392
+
DECLARE_MSM_GPIO_PINS(62);
393
+
DECLARE_MSM_GPIO_PINS(63);
394
+
DECLARE_MSM_GPIO_PINS(64);
395
+
DECLARE_MSM_GPIO_PINS(65);
396
+
DECLARE_MSM_GPIO_PINS(66);
397
+
DECLARE_MSM_GPIO_PINS(67);
398
+
DECLARE_MSM_GPIO_PINS(68);
399
+
DECLARE_MSM_GPIO_PINS(69);
400
+
DECLARE_MSM_GPIO_PINS(70);
401
+
DECLARE_MSM_GPIO_PINS(71);
402
+
DECLARE_MSM_GPIO_PINS(72);
403
+
DECLARE_MSM_GPIO_PINS(73);
404
+
DECLARE_MSM_GPIO_PINS(74);
405
+
DECLARE_MSM_GPIO_PINS(75);
406
+
DECLARE_MSM_GPIO_PINS(76);
407
+
DECLARE_MSM_GPIO_PINS(77);
408
+
DECLARE_MSM_GPIO_PINS(78);
409
+
DECLARE_MSM_GPIO_PINS(79);
410
+
DECLARE_MSM_GPIO_PINS(80);
411
+
DECLARE_MSM_GPIO_PINS(81);
412
+
DECLARE_MSM_GPIO_PINS(82);
413
+
DECLARE_MSM_GPIO_PINS(83);
414
+
DECLARE_MSM_GPIO_PINS(84);
415
+
DECLARE_MSM_GPIO_PINS(85);
416
+
DECLARE_MSM_GPIO_PINS(86);
417
+
DECLARE_MSM_GPIO_PINS(87);
418
+
DECLARE_MSM_GPIO_PINS(88);
419
+
DECLARE_MSM_GPIO_PINS(89);
420
+
DECLARE_MSM_GPIO_PINS(90);
421
+
DECLARE_MSM_GPIO_PINS(91);
422
+
DECLARE_MSM_GPIO_PINS(92);
423
+
DECLARE_MSM_GPIO_PINS(93);
424
+
DECLARE_MSM_GPIO_PINS(94);
425
+
DECLARE_MSM_GPIO_PINS(95);
426
+
DECLARE_MSM_GPIO_PINS(96);
427
+
DECLARE_MSM_GPIO_PINS(97);
428
+
DECLARE_MSM_GPIO_PINS(98);
429
+
DECLARE_MSM_GPIO_PINS(99);
430
+
DECLARE_MSM_GPIO_PINS(100);
431
+
DECLARE_MSM_GPIO_PINS(101);
432
+
DECLARE_MSM_GPIO_PINS(102);
433
+
DECLARE_MSM_GPIO_PINS(103);
434
+
DECLARE_MSM_GPIO_PINS(104);
435
+
DECLARE_MSM_GPIO_PINS(105);
436
+
DECLARE_MSM_GPIO_PINS(106);
437
+
DECLARE_MSM_GPIO_PINS(107);
438
+
DECLARE_MSM_GPIO_PINS(108);
439
+
DECLARE_MSM_GPIO_PINS(109);
440
+
DECLARE_MSM_GPIO_PINS(110);
441
+
DECLARE_MSM_GPIO_PINS(111);
442
+
DECLARE_MSM_GPIO_PINS(112);
443
+
DECLARE_MSM_GPIO_PINS(113);
444
+
DECLARE_MSM_GPIO_PINS(114);
445
+
DECLARE_MSM_GPIO_PINS(115);
446
+
DECLARE_MSM_GPIO_PINS(116);
447
+
DECLARE_MSM_GPIO_PINS(117);
448
+
DECLARE_MSM_GPIO_PINS(118);
449
+
DECLARE_MSM_GPIO_PINS(119);
450
+
DECLARE_MSM_GPIO_PINS(120);
451
+
DECLARE_MSM_GPIO_PINS(121);
452
+
DECLARE_MSM_GPIO_PINS(122);
453
+
DECLARE_MSM_GPIO_PINS(123);
454
+
DECLARE_MSM_GPIO_PINS(124);
455
+
DECLARE_MSM_GPIO_PINS(125);
456
+
DECLARE_MSM_GPIO_PINS(126);
457
+
DECLARE_MSM_GPIO_PINS(127);
458
+
DECLARE_MSM_GPIO_PINS(128);
459
+
DECLARE_MSM_GPIO_PINS(129);
460
+
DECLARE_MSM_GPIO_PINS(130);
461
+
DECLARE_MSM_GPIO_PINS(131);
462
+
DECLARE_MSM_GPIO_PINS(132);
463
+
DECLARE_MSM_GPIO_PINS(133);
464
+
DECLARE_MSM_GPIO_PINS(134);
465
+
DECLARE_MSM_GPIO_PINS(135);
466
+
DECLARE_MSM_GPIO_PINS(136);
467
+
DECLARE_MSM_GPIO_PINS(137);
468
+
DECLARE_MSM_GPIO_PINS(138);
469
+
DECLARE_MSM_GPIO_PINS(139);
470
+
DECLARE_MSM_GPIO_PINS(140);
471
+
DECLARE_MSM_GPIO_PINS(141);
472
+
DECLARE_MSM_GPIO_PINS(142);
473
+
DECLARE_MSM_GPIO_PINS(143);
474
+
DECLARE_MSM_GPIO_PINS(144);
475
+
DECLARE_MSM_GPIO_PINS(145);
476
+
DECLARE_MSM_GPIO_PINS(146);
477
+
DECLARE_MSM_GPIO_PINS(147);
478
+
DECLARE_MSM_GPIO_PINS(148);
479
+
DECLARE_MSM_GPIO_PINS(149);
480
+
DECLARE_MSM_GPIO_PINS(150);
481
+
DECLARE_MSM_GPIO_PINS(151);
482
+
DECLARE_MSM_GPIO_PINS(152);
483
+
DECLARE_MSM_GPIO_PINS(153);
484
+
DECLARE_MSM_GPIO_PINS(154);
485
+
DECLARE_MSM_GPIO_PINS(155);
486
+
DECLARE_MSM_GPIO_PINS(156);
487
+
DECLARE_MSM_GPIO_PINS(157);
488
+
DECLARE_MSM_GPIO_PINS(158);
489
+
DECLARE_MSM_GPIO_PINS(159);
490
+
DECLARE_MSM_GPIO_PINS(160);
491
+
DECLARE_MSM_GPIO_PINS(161);
492
+
DECLARE_MSM_GPIO_PINS(162);
493
+
DECLARE_MSM_GPIO_PINS(163);
494
+
DECLARE_MSM_GPIO_PINS(164);
495
+
DECLARE_MSM_GPIO_PINS(165);
496
+
DECLARE_MSM_GPIO_PINS(166);
497
+
DECLARE_MSM_GPIO_PINS(167);
498
+
DECLARE_MSM_GPIO_PINS(168);
499
+
DECLARE_MSM_GPIO_PINS(169);
500
+
DECLARE_MSM_GPIO_PINS(170);
501
+
DECLARE_MSM_GPIO_PINS(171);
502
+
DECLARE_MSM_GPIO_PINS(172);
503
+
DECLARE_MSM_GPIO_PINS(173);
504
+
DECLARE_MSM_GPIO_PINS(174);
505
+
DECLARE_MSM_GPIO_PINS(175);
506
+
DECLARE_MSM_GPIO_PINS(176);
507
+
DECLARE_MSM_GPIO_PINS(177);
508
+
DECLARE_MSM_GPIO_PINS(178);
509
+
DECLARE_MSM_GPIO_PINS(179);
510
+
DECLARE_MSM_GPIO_PINS(180);
511
+
DECLARE_MSM_GPIO_PINS(181);
512
+
DECLARE_MSM_GPIO_PINS(182);
513
+
DECLARE_MSM_GPIO_PINS(183);
514
+
DECLARE_MSM_GPIO_PINS(184);
515
+
DECLARE_MSM_GPIO_PINS(185);
516
+
DECLARE_MSM_GPIO_PINS(186);
517
+
DECLARE_MSM_GPIO_PINS(187);
518
+
DECLARE_MSM_GPIO_PINS(188);
519
+
DECLARE_MSM_GPIO_PINS(189);
520
+
DECLARE_MSM_GPIO_PINS(190);
521
+
DECLARE_MSM_GPIO_PINS(191);
522
+
DECLARE_MSM_GPIO_PINS(192);
523
+
DECLARE_MSM_GPIO_PINS(193);
524
+
DECLARE_MSM_GPIO_PINS(194);
525
+
DECLARE_MSM_GPIO_PINS(195);
526
+
DECLARE_MSM_GPIO_PINS(196);
527
+
DECLARE_MSM_GPIO_PINS(197);
528
+
DECLARE_MSM_GPIO_PINS(198);
529
+
DECLARE_MSM_GPIO_PINS(199);
530
+
DECLARE_MSM_GPIO_PINS(200);
531
+
DECLARE_MSM_GPIO_PINS(201);
532
+
DECLARE_MSM_GPIO_PINS(202);
533
+
DECLARE_MSM_GPIO_PINS(203);
534
+
DECLARE_MSM_GPIO_PINS(204);
535
+
DECLARE_MSM_GPIO_PINS(205);
536
+
DECLARE_MSM_GPIO_PINS(206);
537
+
DECLARE_MSM_GPIO_PINS(207);
538
+
DECLARE_MSM_GPIO_PINS(208);
539
+
DECLARE_MSM_GPIO_PINS(209);
540
+
541
+
static const unsigned int ufs_reset_pins[] = { 210 };
542
+
static const unsigned int sdc2_clk_pins[] = { 211 };
543
+
static const unsigned int sdc2_cmd_pins[] = { 212 };
544
+
static const unsigned int sdc2_data_pins[] = { 213 };
545
+
546
+
enum sm8650_functions {
547
+
msm_mux_gpio,
548
+
msm_mux_aoss_cti,
549
+
msm_mux_atest_char,
550
+
msm_mux_atest_usb,
551
+
msm_mux_audio_ext_mclk0,
552
+
msm_mux_audio_ext_mclk1,
553
+
msm_mux_audio_ref_clk,
554
+
msm_mux_cam_aon_mclk2,
555
+
msm_mux_cam_aon_mclk4,
556
+
msm_mux_cam_mclk,
557
+
msm_mux_cci_async_in,
558
+
msm_mux_cci_i2c_scl,
559
+
msm_mux_cci_i2c_sda,
560
+
msm_mux_cci_timer,
561
+
msm_mux_cmu_rng,
562
+
msm_mux_coex_uart1_rx,
563
+
msm_mux_coex_uart1_tx,
564
+
msm_mux_coex_uart2_rx,
565
+
msm_mux_coex_uart2_tx,
566
+
msm_mux_cri_trng,
567
+
msm_mux_dbg_out_clk,
568
+
msm_mux_ddr_bist_complete,
569
+
msm_mux_ddr_bist_fail,
570
+
msm_mux_ddr_bist_start,
571
+
msm_mux_ddr_bist_stop,
572
+
msm_mux_ddr_pxi0,
573
+
msm_mux_ddr_pxi1,
574
+
msm_mux_ddr_pxi2,
575
+
msm_mux_ddr_pxi3,
576
+
msm_mux_do_not,
577
+
msm_mux_dp_hot,
578
+
msm_mux_egpio,
579
+
msm_mux_gcc_gp1,
580
+
msm_mux_gcc_gp2,
581
+
msm_mux_gcc_gp3,
582
+
msm_mux_gnss_adc0,
583
+
msm_mux_gnss_adc1,
584
+
msm_mux_i2chub0_se0,
585
+
msm_mux_i2chub0_se1,
586
+
msm_mux_i2chub0_se2,
587
+
msm_mux_i2chub0_se3,
588
+
msm_mux_i2chub0_se4,
589
+
msm_mux_i2chub0_se5,
590
+
msm_mux_i2chub0_se6,
591
+
msm_mux_i2chub0_se7,
592
+
msm_mux_i2chub0_se8,
593
+
msm_mux_i2chub0_se9,
594
+
msm_mux_i2s0_data0,
595
+
msm_mux_i2s0_data1,
596
+
msm_mux_i2s0_sck,
597
+
msm_mux_i2s0_ws,
598
+
msm_mux_i2s1_data0,
599
+
msm_mux_i2s1_data1,
600
+
msm_mux_i2s1_sck,
601
+
msm_mux_i2s1_ws,
602
+
msm_mux_ibi_i3c,
603
+
msm_mux_jitter_bist,
604
+
msm_mux_mdp_vsync,
605
+
msm_mux_mdp_vsync0_out,
606
+
msm_mux_mdp_vsync1_out,
607
+
msm_mux_mdp_vsync2_out,
608
+
msm_mux_mdp_vsync3_out,
609
+
msm_mux_mdp_vsync_e,
610
+
msm_mux_nav_gpio0,
611
+
msm_mux_nav_gpio1,
612
+
msm_mux_nav_gpio2,
613
+
msm_mux_nav_gpio3,
614
+
msm_mux_pcie0_clk_req_n,
615
+
msm_mux_pcie1_clk_req_n,
616
+
msm_mux_phase_flag,
617
+
msm_mux_pll_bist_sync,
618
+
msm_mux_pll_clk_aux,
619
+
msm_mux_prng_rosc0,
620
+
msm_mux_prng_rosc1,
621
+
msm_mux_prng_rosc2,
622
+
msm_mux_prng_rosc3,
623
+
msm_mux_qdss_cti,
624
+
msm_mux_qdss_gpio,
625
+
msm_mux_qlink_big_enable,
626
+
msm_mux_qlink_big_request,
627
+
msm_mux_qlink_little_enable,
628
+
msm_mux_qlink_little_request,
629
+
msm_mux_qlink_wmss,
630
+
msm_mux_qspi0,
631
+
msm_mux_qspi1,
632
+
msm_mux_qspi2,
633
+
msm_mux_qspi3,
634
+
msm_mux_qspi_clk,
635
+
msm_mux_qspi_cs,
636
+
msm_mux_qup1_se0,
637
+
msm_mux_qup1_se1,
638
+
msm_mux_qup1_se2,
639
+
msm_mux_qup1_se3,
640
+
msm_mux_qup1_se4,
641
+
msm_mux_qup1_se5,
642
+
msm_mux_qup1_se6,
643
+
msm_mux_qup1_se7,
644
+
msm_mux_qup2_se0,
645
+
msm_mux_qup2_se1,
646
+
msm_mux_qup2_se2,
647
+
msm_mux_qup2_se3,
648
+
msm_mux_qup2_se4,
649
+
msm_mux_qup2_se5,
650
+
msm_mux_qup2_se6,
651
+
msm_mux_qup2_se7,
652
+
msm_mux_sd_write_protect,
653
+
msm_mux_sdc40,
654
+
msm_mux_sdc41,
655
+
msm_mux_sdc42,
656
+
msm_mux_sdc43,
657
+
msm_mux_sdc4_clk,
658
+
msm_mux_sdc4_cmd,
659
+
msm_mux_tb_trig_sdc2,
660
+
msm_mux_tb_trig_sdc4,
661
+
msm_mux_tgu_ch0_trigout,
662
+
msm_mux_tgu_ch1_trigout,
663
+
msm_mux_tgu_ch2_trigout,
664
+
msm_mux_tgu_ch3_trigout,
665
+
msm_mux_tmess_prng0,
666
+
msm_mux_tmess_prng1,
667
+
msm_mux_tmess_prng2,
668
+
msm_mux_tmess_prng3,
669
+
msm_mux_tsense_pwm1,
670
+
msm_mux_tsense_pwm2,
671
+
msm_mux_tsense_pwm3,
672
+
msm_mux_uim0_clk,
673
+
msm_mux_uim0_data,
674
+
msm_mux_uim0_present,
675
+
msm_mux_uim0_reset,
676
+
msm_mux_uim1_clk,
677
+
msm_mux_uim1_data,
678
+
msm_mux_uim1_present,
679
+
msm_mux_uim1_reset,
680
+
msm_mux_usb1_hs,
681
+
msm_mux_usb_phy,
682
+
msm_mux_vfr_0,
683
+
msm_mux_vfr_1,
684
+
msm_mux_vsense_trigger_mirnat,
685
+
msm_mux__,
686
+
};
687
+
688
+
static const char *const gpio_groups[] = {
689
+
"gpio0", "gpio1", "gpio2", "gpio3",
690
+
"gpio4", "gpio5", "gpio6", "gpio7",
691
+
"gpio8", "gpio9", "gpio10", "gpio11",
692
+
"gpio12", "gpio13", "gpio14", "gpio15",
693
+
"gpio16", "gpio17", "gpio18", "gpio19",
694
+
"gpio20", "gpio21", "gpio22", "gpio23",
695
+
"gpio24", "gpio25", "gpio26", "gpio27",
696
+
"gpio28", "gpio29", "gpio30", "gpio31",
697
+
"gpio32", "gpio33", "gpio34", "gpio35",
698
+
"gpio36", "gpio37", "gpio38", "gpio39",
699
+
"gpio40", "gpio41", "gpio42", "gpio43",
700
+
"gpio44", "gpio45", "gpio46", "gpio47",
701
+
"gpio48", "gpio49", "gpio50", "gpio51",
702
+
"gpio52", "gpio53", "gpio54", "gpio55",
703
+
"gpio56", "gpio57", "gpio58", "gpio59",
704
+
"gpio60", "gpio61", "gpio62", "gpio63",
705
+
"gpio64", "gpio65", "gpio66", "gpio67",
706
+
"gpio68", "gpio69", "gpio70", "gpio71",
707
+
"gpio72", "gpio73", "gpio74", "gpio75",
708
+
"gpio76", "gpio77", "gpio78", "gpio79",
709
+
"gpio80", "gpio81", "gpio82", "gpio83",
710
+
"gpio84", "gpio85", "gpio86", "gpio87",
711
+
"gpio88", "gpio89", "gpio90", "gpio91",
712
+
"gpio92", "gpio93", "gpio94", "gpio95",
713
+
"gpio96", "gpio97", "gpio98", "gpio99",
714
+
"gpio100", "gpio101", "gpio102", "gpio103",
715
+
"gpio104", "gpio105", "gpio106", "gpio107",
716
+
"gpio108", "gpio109", "gpio110", "gpio111",
717
+
"gpio112", "gpio113", "gpio114", "gpio115",
718
+
"gpio116", "gpio117", "gpio118", "gpio119",
719
+
"gpio120", "gpio121", "gpio122", "gpio123",
720
+
"gpio124", "gpio125", "gpio126", "gpio127",
721
+
"gpio128", "gpio129", "gpio130", "gpio131",
722
+
"gpio132", "gpio133", "gpio134", "gpio135",
723
+
"gpio136", "gpio137", "gpio138", "gpio139",
724
+
"gpio140", "gpio141", "gpio142", "gpio143",
725
+
"gpio144", "gpio145", "gpio146", "gpio147",
726
+
"gpio148", "gpio149", "gpio150", "gpio151",
727
+
"gpio152", "gpio153", "gpio154", "gpio155",
728
+
"gpio156", "gpio157", "gpio158", "gpio159",
729
+
"gpio160", "gpio161", "gpio162", "gpio163",
730
+
"gpio164", "gpio165", "gpio166", "gpio167",
731
+
"gpio168", "gpio169", "gpio170", "gpio171",
732
+
"gpio172", "gpio173", "gpio174", "gpio175",
733
+
"gpio176", "gpio177", "gpio178", "gpio179",
734
+
"gpio180", "gpio181", "gpio182", "gpio183",
735
+
"gpio184", "gpio185", "gpio186", "gpio187",
736
+
"gpio188", "gpio189", "gpio190", "gpio191",
737
+
"gpio192", "gpio193", "gpio194", "gpio195",
738
+
"gpio196", "gpio197", "gpio198", "gpio199",
739
+
"gpio200", "gpio201", "gpio202", "gpio203",
740
+
"gpio204", "gpio205", "gpio206", "gpio207",
741
+
"gpio208", "gpio209",
742
+
};
743
+
744
+
static const char * const egpio_groups[] = {
745
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
746
+
"gpio6", "gpio7", "gpio165", "gpio166", "gpio167", "gpio168",
747
+
"gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio174",
748
+
"gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180",
749
+
"gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
750
+
"gpio187", "gpio188", "gpio189", "gpio190", "gpio191", "gpio192",
751
+
"gpio193", "gpio194", "gpio195", "gpio196", "gpio197", "gpio198",
752
+
"gpio199", "gpio200", "gpio201", "gpio202", "gpio203", "gpio204",
753
+
"gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
754
+
};
755
+
756
+
static const char * const aoss_cti_groups[] = {
757
+
"gpio50", "gpio51", "gpio60", "gpio61",
758
+
};
759
+
760
+
static const char *const atest_char_groups[] = {
761
+
"gpio130", "gpio131", "gpio132", "gpio133",
762
+
"gpio137",
763
+
};
764
+
765
+
static const char *const atest_usb_groups[] = {
766
+
"gpio71", "gpio72", "gpio74", "gpio130",
767
+
"gpio131",
768
+
};
769
+
770
+
static const char *const audio_ext_mclk0_groups[] = {
771
+
"gpio125",
772
+
};
773
+
774
+
static const char *const audio_ext_mclk1_groups[] = {
775
+
"gpio124",
776
+
};
777
+
778
+
static const char *const audio_ref_clk_groups[] = {
779
+
"gpio124",
780
+
};
781
+
782
+
static const char *const cam_aon_mclk2_groups[] = {
783
+
"gpio102",
784
+
};
785
+
786
+
static const char *const cam_aon_mclk4_groups[] = {
787
+
"gpio104",
788
+
};
789
+
790
+
static const char *const cam_mclk_groups[] = {
791
+
"gpio100", "gpio101", "gpio103", "gpio105",
792
+
"gpio106", "gpio108",
793
+
};
794
+
795
+
static const char *const cci_async_in_groups[] = {
796
+
"gpio15", "gpio163", "gpio164",
797
+
};
798
+
799
+
static const char *const cci_i2c_scl_groups[] = {
800
+
"gpio13", "gpio114", "gpio116", "gpio118",
801
+
"gpio120", "gpio153",
802
+
};
803
+
804
+
static const char *const cci_i2c_sda_groups[] = {
805
+
"gpio12", "gpio112", "gpio113", "gpio115",
806
+
"gpio117", "gpio119",
807
+
};
808
+
809
+
static const char *const cci_timer_groups[] = {
810
+
"gpio10", "gpio11", "gpio109", "gpio110",
811
+
"gpio111",
812
+
};
813
+
814
+
static const char *const cmu_rng_groups[] = {
815
+
"gpio95", "gpio96", "gpio112", "gpio127",
816
+
"gpio122", "gpio128",
817
+
};
818
+
819
+
static const char *const coex_uart1_rx_groups[] = {
820
+
"gpio148",
821
+
};
822
+
823
+
static const char *const coex_uart1_tx_groups[] = {
824
+
"gpio149",
825
+
};
826
+
827
+
static const char *const coex_uart2_rx_groups[] = {
828
+
"gpio150",
829
+
};
830
+
831
+
static const char *const coex_uart2_tx_groups[] = {
832
+
"gpio151",
833
+
};
834
+
835
+
static const char *const cri_trng_groups[] = {
836
+
"gpio187",
837
+
};
838
+
839
+
static const char *const dbg_out_clk_groups[] = {
840
+
"gpio92",
841
+
};
842
+
843
+
static const char *const ddr_bist_complete_groups[] = {
844
+
"gpio44",
845
+
};
846
+
847
+
static const char *const ddr_bist_fail_groups[] = {
848
+
"gpio40",
849
+
};
850
+
851
+
static const char *const ddr_bist_start_groups[] = {
852
+
"gpio41",
853
+
};
854
+
855
+
static const char *const ddr_bist_stop_groups[] = {
856
+
"gpio45",
857
+
};
858
+
859
+
static const char *const ddr_pxi0_groups[] = {
860
+
"gpio75", "gpio76",
861
+
};
862
+
863
+
static const char *const ddr_pxi1_groups[] = {
864
+
"gpio44", "gpio45",
865
+
};
866
+
867
+
static const char *const ddr_pxi2_groups[] = {
868
+
"gpio51", "gpio62",
869
+
};
870
+
871
+
static const char *const ddr_pxi3_groups[] = {
872
+
"gpio46", "gpio47",
873
+
};
874
+
875
+
static const char *const do_not_groups[] = {
876
+
"gpio36", "gpio37", "gpio38", "gpio39",
877
+
"gpio134", "gpio135", "gpio136",
878
+
};
879
+
880
+
static const char *const dp_hot_groups[] = {
881
+
"gpio47",
882
+
};
883
+
884
+
static const char *const gcc_gp1_groups[] = {
885
+
"gpio86", "gpio134",
886
+
};
887
+
888
+
static const char *const gcc_gp2_groups[] = {
889
+
"gpio87", "gpio135",
890
+
};
891
+
892
+
static const char *const gcc_gp3_groups[] = {
893
+
"gpio88", "gpio136",
894
+
};
895
+
896
+
static const char *const gnss_adc0_groups[] = {
897
+
"gpio89", "gpio91",
898
+
};
899
+
900
+
static const char *const gnss_adc1_groups[] = {
901
+
"gpio90", "gpio92",
902
+
};
903
+
904
+
static const char *const i2chub0_se0_groups[] = {
905
+
"gpio64", "gpio65",
906
+
};
907
+
908
+
static const char *const i2chub0_se1_groups[] = {
909
+
"gpio66", "gpio67",
910
+
};
911
+
912
+
static const char *const i2chub0_se2_groups[] = {
913
+
"gpio68", "gpio69",
914
+
};
915
+
916
+
static const char *const i2chub0_se3_groups[] = {
917
+
"gpio70", "gpio71",
918
+
};
919
+
920
+
static const char *const i2chub0_se4_groups[] = {
921
+
"gpio72", "gpio73",
922
+
};
923
+
924
+
static const char *const i2chub0_se5_groups[] = {
925
+
"gpio74", "gpio75",
926
+
};
927
+
928
+
static const char *const i2chub0_se6_groups[] = {
929
+
"gpio76", "gpio77",
930
+
};
931
+
932
+
static const char *const i2chub0_se7_groups[] = {
933
+
"gpio78", "gpio79",
934
+
};
935
+
936
+
static const char *const i2chub0_se8_groups[] = {
937
+
"gpio206", "gpio207",
938
+
};
939
+
940
+
static const char *const i2chub0_se9_groups[] = {
941
+
"gpio80", "gpio81",
942
+
};
943
+
944
+
static const char *const i2s0_data0_groups[] = {
945
+
"gpio127",
946
+
};
947
+
948
+
static const char *const i2s0_data1_groups[] = {
949
+
"gpio128",
950
+
};
951
+
952
+
static const char *const i2s0_sck_groups[] = {
953
+
"gpio126",
954
+
};
955
+
956
+
static const char *const i2s0_ws_groups[] = {
957
+
"gpio129",
958
+
};
959
+
960
+
static const char *const i2s1_data0_groups[] = {
961
+
"gpio122",
962
+
};
963
+
964
+
static const char *const i2s1_data1_groups[] = {
965
+
"gpio124",
966
+
};
967
+
968
+
static const char *const i2s1_sck_groups[] = {
969
+
"gpio121",
970
+
};
971
+
972
+
static const char *const i2s1_ws_groups[] = {
973
+
"gpio123",
974
+
};
975
+
976
+
static const char *const ibi_i3c_groups[] = {
977
+
"gpio0", "gpio1", "gpio4", "gpio5",
978
+
"gpio8", "gpio9", "gpio12", "gpio13",
979
+
"gpio32", "gpio33", "gpio36", "gpio37",
980
+
"gpio48", "gpio49", "gpio56", "gpio57",
981
+
};
982
+
983
+
static const char *const jitter_bist_groups[] = {
984
+
"gpio73",
985
+
};
986
+
987
+
static const char *const mdp_vsync_groups[] = {
988
+
"gpio86", "gpio87", "gpio133", "gpio137",
989
+
};
990
+
991
+
static const char *const mdp_vsync0_out_groups[] = {
992
+
"gpio86",
993
+
};
994
+
995
+
static const char *const mdp_vsync1_out_groups[] = {
996
+
"gpio86",
997
+
};
998
+
999
+
static const char *const mdp_vsync2_out_groups[] = {
1000
+
"gpio87",
1001
+
};
1002
+
1003
+
static const char *const mdp_vsync3_out_groups[] = {
1004
+
"gpio87",
1005
+
};
1006
+
1007
+
static const char *const mdp_vsync_e_groups[] = {
1008
+
"gpio88",
1009
+
};
1010
+
1011
+
static const char *const nav_gpio0_groups[] = {
1012
+
"gpio154",
1013
+
};
1014
+
1015
+
static const char *const nav_gpio1_groups[] = {
1016
+
"gpio155",
1017
+
};
1018
+
1019
+
static const char *const nav_gpio2_groups[] = {
1020
+
"gpio152",
1021
+
};
1022
+
1023
+
static const char *const nav_gpio3_groups[] = {
1024
+
"gpio154",
1025
+
};
1026
+
1027
+
static const char *const pcie0_clk_req_n_groups[] = {
1028
+
"gpio95",
1029
+
};
1030
+
1031
+
static const char *const pcie1_clk_req_n_groups[] = {
1032
+
"gpio98",
1033
+
};
1034
+
1035
+
static const char *const phase_flag_groups[] = {
1036
+
"gpio0", "gpio1", "gpio3", "gpio4",
1037
+
"gpio5", "gpio7", "gpio8", "gpio9",
1038
+
"gpio11", "gpio12", "gpio13", "gpio15",
1039
+
"gpio16", "gpio17", "gpio19", "gpio94",
1040
+
"gpio95", "gpio96", "gpio109", "gpio111",
1041
+
"gpio112", "gpio113", "gpio114", "gpio115",
1042
+
"gpio116", "gpio117", "gpio118", "gpio119",
1043
+
"gpio120", "gpio153", "gpio163", "gpio164",
1044
+
};
1045
+
1046
+
static const char *const pll_bist_sync_groups[] = {
1047
+
"gpio68",
1048
+
};
1049
+
1050
+
static const char *const pll_clk_aux_groups[] = {
1051
+
"gpio106",
1052
+
};
1053
+
1054
+
static const char *const prng_rosc0_groups[] = {
1055
+
"gpio186",
1056
+
};
1057
+
1058
+
static const char *const prng_rosc1_groups[] = {
1059
+
"gpio183",
1060
+
};
1061
+
1062
+
static const char *const prng_rosc2_groups[] = {
1063
+
"gpio182",
1064
+
};
1065
+
1066
+
static const char *const prng_rosc3_groups[] = {
1067
+
"gpio181",
1068
+
};
1069
+
1070
+
static const char *const qdss_cti_groups[] = {
1071
+
"gpio27", "gpio31", "gpio78", "gpio79",
1072
+
"gpio82", "gpio83", "gpio159", "gpio162",
1073
+
};
1074
+
1075
+
static const char *const qdss_gpio_groups[] = {
1076
+
"gpio3", "gpio7", "gpio8", "gpio13",
1077
+
"gpio15", "gpio100", "gpio101", "gpio102",
1078
+
"gpio103", "gpio104", "gpio105", "gpio113",
1079
+
"gpio114", "gpio115", "gpio116", "gpio117",
1080
+
"gpio118", "gpio140", "gpio141", "gpio142",
1081
+
"gpio143", "gpio144", "gpio145", "gpio146",
1082
+
"gpio147", "gpio148", "gpio149", "gpio150",
1083
+
"gpio151", "gpio152", "gpio153", "gpio154",
1084
+
"gpio155", "gpio156", "gpio157", "gpio158",
1085
+
};
1086
+
1087
+
static const char *const qlink_big_enable_groups[] = {
1088
+
"gpio160",
1089
+
};
1090
+
1091
+
static const char *const qlink_big_request_groups[] = {
1092
+
"gpio159",
1093
+
};
1094
+
1095
+
static const char *const qlink_little_enable_groups[] = {
1096
+
"gpio157",
1097
+
};
1098
+
1099
+
static const char *const qlink_little_request_groups[] = {
1100
+
"gpio156",
1101
+
};
1102
+
1103
+
static const char *const qlink_wmss_groups[] = {
1104
+
"gpio158",
1105
+
};
1106
+
1107
+
static const char *const qspi0_groups[] = {
1108
+
"gpio134",
1109
+
};
1110
+
1111
+
static const char *const qspi1_groups[] = {
1112
+
"gpio136",
1113
+
};
1114
+
1115
+
static const char *const qspi2_groups[] = {
1116
+
"gpio56",
1117
+
};
1118
+
1119
+
static const char *const qspi3_groups[] = {
1120
+
"gpio57",
1121
+
};
1122
+
1123
+
static const char *const qspi_clk_groups[] = {
1124
+
"gpio135",
1125
+
};
1126
+
1127
+
static const char *const qspi_cs_groups[] = {
1128
+
"gpio58", "gpio59",
1129
+
};
1130
+
1131
+
static const char *const qup1_se0_groups[] = {
1132
+
"gpio32", "gpio33", "gpio34", "gpio35",
1133
+
};
1134
+
1135
+
static const char *const qup1_se1_groups[] = {
1136
+
"gpio36", "gpio37", "gpio38", "gpio39",
1137
+
};
1138
+
1139
+
static const char *const qup1_se2_groups[] = {
1140
+
"gpio40", "gpio41", "gpio42", "gpio43",
1141
+
"gpio44", "gpio45", "gpio46",
1142
+
};
1143
+
1144
+
static const char *const qup1_se3_groups[] = {
1145
+
"gpio44", "gpio45", "gpio46", "gpio47",
1146
+
};
1147
+
1148
+
static const char *const qup1_se4_groups[] = {
1149
+
"gpio48", "gpio49", "gpio50", "gpio51",
1150
+
};
1151
+
1152
+
static const char *const qup1_se5_groups[] = {
1153
+
"gpio52", "gpio53", "gpio54", "gpio55",
1154
+
};
1155
+
1156
+
static const char *const qup1_se6_groups[] = {
1157
+
"gpio56", "gpio57", "gpio58", "gpio59",
1158
+
};
1159
+
1160
+
static const char *const qup1_se7_groups[] = {
1161
+
"gpio60", "gpio61", "gpio62", "gpio63",
1162
+
};
1163
+
1164
+
static const char *const qup2_se0_groups[] = {
1165
+
"gpio0", "gpio1", "gpio2", "gpio3",
1166
+
};
1167
+
1168
+
static const char *const qup2_se1_groups[] = {
1169
+
"gpio4", "gpio5", "gpio6", "gpio7",
1170
+
};
1171
+
1172
+
static const char *const qup2_se2_groups[] = {
1173
+
"gpio8", "gpio9", "gpio10", "gpio11",
1174
+
"gpio13", "gpio15", "gpio12",
1175
+
};
1176
+
1177
+
static const char *const qup2_se3_groups[] = {
1178
+
"gpio12", "gpio13", "gpio14", "gpio15",
1179
+
};
1180
+
1181
+
static const char *const qup2_se4_groups[] = {
1182
+
"gpio16", "gpio17", "gpio18", "gpio19",
1183
+
};
1184
+
1185
+
static const char *const qup2_se5_groups[] = {
1186
+
"gpio20", "gpio21", "gpio22", "gpio23",
1187
+
"gpio23",
1188
+
};
1189
+
1190
+
static const char *const qup2_se6_groups[] = {
1191
+
"gpio24", "gpio25", "gpio26", "gpio27",
1192
+
};
1193
+
1194
+
static const char *const qup2_se7_groups[] = {
1195
+
"gpio28", "gpio29", "gpio30", "gpio31",
1196
+
};
1197
+
1198
+
static const char *const sd_write_protect_groups[] = {
1199
+
"gpio93",
1200
+
};
1201
+
1202
+
static const char *const sdc40_groups[] = {
1203
+
"gpio134",
1204
+
};
1205
+
1206
+
static const char *const sdc41_groups[] = {
1207
+
"gpio136",
1208
+
};
1209
+
1210
+
static const char *const sdc42_groups[] = {
1211
+
"gpio56",
1212
+
};
1213
+
1214
+
static const char *const sdc43_groups[] = {
1215
+
"gpio57",
1216
+
};
1217
+
1218
+
static const char *const sdc4_clk_groups[] = {
1219
+
"gpio135",
1220
+
};
1221
+
1222
+
static const char *const sdc4_cmd_groups[] = {
1223
+
"gpio59",
1224
+
};
1225
+
1226
+
static const char *const tb_trig_sdc2_groups[] = {
1227
+
"gpio8",
1228
+
};
1229
+
1230
+
static const char *const tb_trig_sdc4_groups[] = {
1231
+
"gpio58",
1232
+
};
1233
+
1234
+
static const char *const tgu_ch0_trigout_groups[] = {
1235
+
"gpio8",
1236
+
};
1237
+
1238
+
static const char *const tgu_ch1_trigout_groups[] = {
1239
+
"gpio9",
1240
+
};
1241
+
1242
+
static const char *const tgu_ch2_trigout_groups[] = {
1243
+
"gpio10",
1244
+
};
1245
+
1246
+
static const char *const tgu_ch3_trigout_groups[] = {
1247
+
"gpio11",
1248
+
};
1249
+
1250
+
static const char *const tmess_prng0_groups[] = {
1251
+
"gpio94",
1252
+
};
1253
+
1254
+
static const char *const tmess_prng1_groups[] = {
1255
+
"gpio95",
1256
+
};
1257
+
1258
+
static const char *const tmess_prng2_groups[] = {
1259
+
"gpio96",
1260
+
};
1261
+
1262
+
static const char *const tmess_prng3_groups[] = {
1263
+
"gpio109",
1264
+
};
1265
+
1266
+
static const char *const tsense_pwm1_groups[] = {
1267
+
"gpio58",
1268
+
};
1269
+
1270
+
static const char *const tsense_pwm2_groups[] = {
1271
+
"gpio58",
1272
+
};
1273
+
1274
+
static const char *const tsense_pwm3_groups[] = {
1275
+
"gpio58",
1276
+
};
1277
+
1278
+
static const char *const uim0_clk_groups[] = {
1279
+
"gpio131",
1280
+
};
1281
+
1282
+
static const char *const uim0_data_groups[] = {
1283
+
"gpio130",
1284
+
};
1285
+
1286
+
static const char *const uim0_present_groups[] = {
1287
+
"gpio47",
1288
+
};
1289
+
1290
+
static const char *const uim0_reset_groups[] = {
1291
+
"gpio132",
1292
+
};
1293
+
1294
+
static const char *const uim1_clk_groups[] = {
1295
+
"gpio135",
1296
+
};
1297
+
1298
+
static const char *const uim1_data_groups[] = {
1299
+
"gpio134",
1300
+
};
1301
+
1302
+
static const char *const uim1_present_groups[] = {
1303
+
"gpio76",
1304
+
};
1305
+
1306
+
static const char *const uim1_reset_groups[] = {
1307
+
"gpio136",
1308
+
};
1309
+
1310
+
static const char *const usb1_hs_groups[] = {
1311
+
"gpio89",
1312
+
};
1313
+
1314
+
static const char *const usb_phy_groups[] = {
1315
+
"gpio29", "gpio54",
1316
+
};
1317
+
1318
+
static const char *const vfr_0_groups[] = {
1319
+
"gpio150",
1320
+
};
1321
+
1322
+
static const char *const vfr_1_groups[] = {
1323
+
"gpio155",
1324
+
};
1325
+
1326
+
static const char *const vsense_trigger_mirnat_groups[] = {
1327
+
"gpio60",
1328
+
};
1329
+
1330
+
static const struct pinfunction sm8650_functions[] = {
1331
+
MSM_PIN_FUNCTION(gpio),
1332
+
MSM_PIN_FUNCTION(aoss_cti),
1333
+
MSM_PIN_FUNCTION(atest_char),
1334
+
MSM_PIN_FUNCTION(atest_usb),
1335
+
MSM_PIN_FUNCTION(audio_ext_mclk0),
1336
+
MSM_PIN_FUNCTION(audio_ext_mclk1),
1337
+
MSM_PIN_FUNCTION(audio_ref_clk),
1338
+
MSM_PIN_FUNCTION(cam_aon_mclk2),
1339
+
MSM_PIN_FUNCTION(cam_aon_mclk4),
1340
+
MSM_PIN_FUNCTION(cam_mclk),
1341
+
MSM_PIN_FUNCTION(cci_async_in),
1342
+
MSM_PIN_FUNCTION(cci_i2c_scl),
1343
+
MSM_PIN_FUNCTION(cci_i2c_sda),
1344
+
MSM_PIN_FUNCTION(cci_timer),
1345
+
MSM_PIN_FUNCTION(cmu_rng),
1346
+
MSM_PIN_FUNCTION(coex_uart1_rx),
1347
+
MSM_PIN_FUNCTION(coex_uart1_tx),
1348
+
MSM_PIN_FUNCTION(coex_uart2_rx),
1349
+
MSM_PIN_FUNCTION(coex_uart2_tx),
1350
+
MSM_PIN_FUNCTION(cri_trng),
1351
+
MSM_PIN_FUNCTION(dbg_out_clk),
1352
+
MSM_PIN_FUNCTION(ddr_bist_complete),
1353
+
MSM_PIN_FUNCTION(ddr_bist_fail),
1354
+
MSM_PIN_FUNCTION(ddr_bist_start),
1355
+
MSM_PIN_FUNCTION(ddr_bist_stop),
1356
+
MSM_PIN_FUNCTION(ddr_pxi0),
1357
+
MSM_PIN_FUNCTION(ddr_pxi1),
1358
+
MSM_PIN_FUNCTION(ddr_pxi2),
1359
+
MSM_PIN_FUNCTION(ddr_pxi3),
1360
+
MSM_PIN_FUNCTION(do_not),
1361
+
MSM_PIN_FUNCTION(dp_hot),
1362
+
MSM_PIN_FUNCTION(egpio),
1363
+
MSM_PIN_FUNCTION(gcc_gp1),
1364
+
MSM_PIN_FUNCTION(gcc_gp2),
1365
+
MSM_PIN_FUNCTION(gcc_gp3),
1366
+
MSM_PIN_FUNCTION(gnss_adc0),
1367
+
MSM_PIN_FUNCTION(gnss_adc1),
1368
+
MSM_PIN_FUNCTION(i2chub0_se0),
1369
+
MSM_PIN_FUNCTION(i2chub0_se1),
1370
+
MSM_PIN_FUNCTION(i2chub0_se2),
1371
+
MSM_PIN_FUNCTION(i2chub0_se3),
1372
+
MSM_PIN_FUNCTION(i2chub0_se4),
1373
+
MSM_PIN_FUNCTION(i2chub0_se5),
1374
+
MSM_PIN_FUNCTION(i2chub0_se6),
1375
+
MSM_PIN_FUNCTION(i2chub0_se7),
1376
+
MSM_PIN_FUNCTION(i2chub0_se8),
1377
+
MSM_PIN_FUNCTION(i2chub0_se9),
1378
+
MSM_PIN_FUNCTION(i2s0_data0),
1379
+
MSM_PIN_FUNCTION(i2s0_data1),
1380
+
MSM_PIN_FUNCTION(i2s0_sck),
1381
+
MSM_PIN_FUNCTION(i2s0_ws),
1382
+
MSM_PIN_FUNCTION(i2s1_data0),
1383
+
MSM_PIN_FUNCTION(i2s1_data1),
1384
+
MSM_PIN_FUNCTION(i2s1_sck),
1385
+
MSM_PIN_FUNCTION(i2s1_ws),
1386
+
MSM_PIN_FUNCTION(ibi_i3c),
1387
+
MSM_PIN_FUNCTION(jitter_bist),
1388
+
MSM_PIN_FUNCTION(mdp_vsync),
1389
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
1390
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
1391
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
1392
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
1393
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1394
+
MSM_PIN_FUNCTION(nav_gpio0),
1395
+
MSM_PIN_FUNCTION(nav_gpio1),
1396
+
MSM_PIN_FUNCTION(nav_gpio2),
1397
+
MSM_PIN_FUNCTION(nav_gpio3),
1398
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
1399
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
1400
+
MSM_PIN_FUNCTION(phase_flag),
1401
+
MSM_PIN_FUNCTION(pll_bist_sync),
1402
+
MSM_PIN_FUNCTION(pll_clk_aux),
1403
+
MSM_PIN_FUNCTION(prng_rosc0),
1404
+
MSM_PIN_FUNCTION(prng_rosc1),
1405
+
MSM_PIN_FUNCTION(prng_rosc2),
1406
+
MSM_PIN_FUNCTION(prng_rosc3),
1407
+
MSM_PIN_FUNCTION(qdss_cti),
1408
+
MSM_PIN_FUNCTION(qdss_gpio),
1409
+
MSM_PIN_FUNCTION(qlink_big_enable),
1410
+
MSM_PIN_FUNCTION(qlink_big_request),
1411
+
MSM_PIN_FUNCTION(qlink_little_enable),
1412
+
MSM_PIN_FUNCTION(qlink_little_request),
1413
+
MSM_PIN_FUNCTION(qlink_wmss),
1414
+
MSM_PIN_FUNCTION(qspi0),
1415
+
MSM_PIN_FUNCTION(qspi1),
1416
+
MSM_PIN_FUNCTION(qspi2),
1417
+
MSM_PIN_FUNCTION(qspi3),
1418
+
MSM_PIN_FUNCTION(qspi_clk),
1419
+
MSM_PIN_FUNCTION(qspi_cs),
1420
+
MSM_PIN_FUNCTION(qup1_se0),
1421
+
MSM_PIN_FUNCTION(qup1_se1),
1422
+
MSM_PIN_FUNCTION(qup1_se2),
1423
+
MSM_PIN_FUNCTION(qup1_se3),
1424
+
MSM_PIN_FUNCTION(qup1_se4),
1425
+
MSM_PIN_FUNCTION(qup1_se5),
1426
+
MSM_PIN_FUNCTION(qup1_se6),
1427
+
MSM_PIN_FUNCTION(qup1_se7),
1428
+
MSM_PIN_FUNCTION(qup2_se0),
1429
+
MSM_PIN_FUNCTION(qup2_se1),
1430
+
MSM_PIN_FUNCTION(qup2_se2),
1431
+
MSM_PIN_FUNCTION(qup2_se3),
1432
+
MSM_PIN_FUNCTION(qup2_se4),
1433
+
MSM_PIN_FUNCTION(qup2_se5),
1434
+
MSM_PIN_FUNCTION(qup2_se6),
1435
+
MSM_PIN_FUNCTION(qup2_se7),
1436
+
MSM_PIN_FUNCTION(sd_write_protect),
1437
+
MSM_PIN_FUNCTION(sdc40),
1438
+
MSM_PIN_FUNCTION(sdc41),
1439
+
MSM_PIN_FUNCTION(sdc42),
1440
+
MSM_PIN_FUNCTION(sdc43),
1441
+
MSM_PIN_FUNCTION(sdc4_clk),
1442
+
MSM_PIN_FUNCTION(sdc4_cmd),
1443
+
MSM_PIN_FUNCTION(tb_trig_sdc2),
1444
+
MSM_PIN_FUNCTION(tb_trig_sdc4),
1445
+
MSM_PIN_FUNCTION(tgu_ch0_trigout),
1446
+
MSM_PIN_FUNCTION(tgu_ch1_trigout),
1447
+
MSM_PIN_FUNCTION(tgu_ch2_trigout),
1448
+
MSM_PIN_FUNCTION(tgu_ch3_trigout),
1449
+
MSM_PIN_FUNCTION(tmess_prng0),
1450
+
MSM_PIN_FUNCTION(tmess_prng1),
1451
+
MSM_PIN_FUNCTION(tmess_prng2),
1452
+
MSM_PIN_FUNCTION(tmess_prng3),
1453
+
MSM_PIN_FUNCTION(tsense_pwm1),
1454
+
MSM_PIN_FUNCTION(tsense_pwm2),
1455
+
MSM_PIN_FUNCTION(tsense_pwm3),
1456
+
MSM_PIN_FUNCTION(uim0_clk),
1457
+
MSM_PIN_FUNCTION(uim0_data),
1458
+
MSM_PIN_FUNCTION(uim0_present),
1459
+
MSM_PIN_FUNCTION(uim0_reset),
1460
+
MSM_PIN_FUNCTION(uim1_clk),
1461
+
MSM_PIN_FUNCTION(uim1_data),
1462
+
MSM_PIN_FUNCTION(uim1_present),
1463
+
MSM_PIN_FUNCTION(uim1_reset),
1464
+
MSM_PIN_FUNCTION(usb1_hs),
1465
+
MSM_PIN_FUNCTION(usb_phy),
1466
+
MSM_PIN_FUNCTION(vfr_0),
1467
+
MSM_PIN_FUNCTION(vfr_1),
1468
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1469
+
};
1470
+
1471
+
/*
1472
+
* Every pin is maintained as a single group, and missing or non-existing pin
1473
+
* would be maintained as dummy group to synchronize pin group index with
1474
+
* pin descriptor registered with pinctrl core.
1475
+
* Clients would not be able to request these dummy pin groups.
1476
+
*/
1477
+
static const struct msm_pingroup sm8650_groups[] = {
1478
+
[0] = PINGROUP(0, qup2_se0, ibi_i3c, phase_flag, _, _, _, _, _, _, egpio),
1479
+
[1] = PINGROUP(1, qup2_se0, ibi_i3c, phase_flag, _, _, _, _, _, _, egpio),
1480
+
[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, egpio),
1481
+
[3] = PINGROUP(3, qup2_se0, phase_flag, _, qdss_gpio, _, _, _, _, _, egpio),
1482
+
[4] = PINGROUP(4, qup2_se1, ibi_i3c, phase_flag, _, _, _, _, _, _, egpio),
1483
+
[5] = PINGROUP(5, qup2_se1, ibi_i3c, phase_flag, _, _, _, _, _, _, egpio),
1484
+
[6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, egpio),
1485
+
[7] = PINGROUP(7, qup2_se1, phase_flag, _, qdss_gpio, _, _, _, _, _, egpio),
1486
+
[8] = PINGROUP(8, qup2_se2, ibi_i3c, tb_trig_sdc2, phase_flag, tgu_ch0_trigout, _, qdss_gpio, _, _, _),
1487
+
[9] = PINGROUP(9, qup2_se2, ibi_i3c, phase_flag, tgu_ch1_trigout, _, _, _, _, _, _),
1488
+
[10] = PINGROUP(10, qup2_se2, cci_timer, tgu_ch2_trigout, _, _, _, _, _, _, _),
1489
+
[11] = PINGROUP(11, qup2_se2, cci_timer, phase_flag, tgu_ch3_trigout, _, _, _, _, _, _),
1490
+
[12] = PINGROUP(12, qup2_se3, cci_i2c_sda, ibi_i3c, qup2_se2, phase_flag, _, _, _, _, _),
1491
+
[13] = PINGROUP(13, qup2_se3, cci_i2c_scl, ibi_i3c, qup2_se2, phase_flag, _, qdss_gpio, _, _, _),
1492
+
[14] = PINGROUP(14, qup2_se3, _, _, _, _, _, _, _, _, _),
1493
+
[15] = PINGROUP(15, qup2_se3, cci_async_in, qup2_se2, phase_flag, _, qdss_gpio, _, _, _, _),
1494
+
[16] = PINGROUP(16, qup2_se4, phase_flag, _, _, _, _, _, _, _, _),
1495
+
[17] = PINGROUP(17, qup2_se4, phase_flag, _, _, _, _, _, _, _, _),
1496
+
[18] = PINGROUP(18, qup2_se4, _, _, _, _, _, _, _, _, _),
1497
+
[19] = PINGROUP(19, qup2_se4, phase_flag, _, _, _, _, _, _, _, _),
1498
+
[20] = PINGROUP(20, qup2_se5, _, _, _, _, _, _, _, _, _),
1499
+
[21] = PINGROUP(21, qup2_se5, _, _, _, _, _, _, _, _, _),
1500
+
[22] = PINGROUP(22, qup2_se5, _, _, _, _, _, _, _, _, _),
1501
+
[23] = PINGROUP(23, qup2_se5, qup2_se5, _, _, _, _, _, _, _, _),
1502
+
[24] = PINGROUP(24, qup2_se6, _, _, _, _, _, _, _, _, _),
1503
+
[25] = PINGROUP(25, qup2_se6, _, _, _, _, _, _, _, _, _),
1504
+
[26] = PINGROUP(26, qup2_se6, _, _, _, _, _, _, _, _, _),
1505
+
[27] = PINGROUP(27, qup2_se6, qdss_cti, _, _, _, _, _, _, _, _),
1506
+
[28] = PINGROUP(28, qup2_se7, _, _, _, _, _, _, _, _, _),
1507
+
[29] = PINGROUP(29, qup2_se7, usb_phy, _, _, _, _, _, _, _, _),
1508
+
[30] = PINGROUP(30, qup2_se7, _, _, _, _, _, _, _, _, _),
1509
+
[31] = PINGROUP(31, qup2_se7, qdss_cti, _, _, _, _, _, _, _, _),
1510
+
[32] = PINGROUP(32, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _),
1511
+
[33] = PINGROUP(33, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _),
1512
+
[34] = PINGROUP(34, qup1_se0, _, _, _, _, _, _, _, _, _),
1513
+
[35] = PINGROUP(35, qup1_se0, _, _, _, _, _, _, _, _, _),
1514
+
[36] = PINGROUP(36, qup1_se1, do_not, ibi_i3c, _, _, _, _, _, _, _),
1515
+
[37] = PINGROUP(37, qup1_se1, do_not, ibi_i3c, _, _, _, _, _, _, _),
1516
+
[38] = PINGROUP(38, qup1_se1, do_not, _, _, _, _, _, _, _, _),
1517
+
[39] = PINGROUP(39, qup1_se1, do_not, _, _, _, _, _, _, _, _),
1518
+
[40] = PINGROUP(40, qup1_se2, ddr_bist_fail, _, _, _, _, _, _, _, _),
1519
+
[41] = PINGROUP(41, qup1_se2, ddr_bist_start, _, _, _, _, _, _, _, _),
1520
+
[42] = PINGROUP(42, qup1_se2, _, _, _, _, _, _, _, _, _),
1521
+
[43] = PINGROUP(43, qup1_se2, _, _, _, _, _, _, _, _, _),
1522
+
[44] = PINGROUP(44, qup1_se3, qup1_se2, ddr_bist_complete, ddr_pxi1, _, _, _, _, _, _),
1523
+
[45] = PINGROUP(45, qup1_se3, qup1_se2, ddr_bist_stop, ddr_pxi1, _, _, _, _, _, _),
1524
+
[46] = PINGROUP(46, qup1_se3, qup1_se2, ddr_pxi3, _, _, _, _, _, _, _),
1525
+
[47] = PINGROUP(47, qup1_se3, uim0_present, dp_hot, ddr_pxi3, _, _, _, _, _, _),
1526
+
[48] = PINGROUP(48, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
1527
+
[49] = PINGROUP(49, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
1528
+
[50] = PINGROUP(50, qup1_se4, aoss_cti, _, _, _, _, _, _, _, _),
1529
+
[51] = PINGROUP(51, qup1_se4, aoss_cti, ddr_pxi2, _, _, _, _, _, _, _),
1530
+
[52] = PINGROUP(52, qup1_se5, _, _, _, _, _, _, _, _, _),
1531
+
[53] = PINGROUP(53, qup1_se5, _, _, _, _, _, _, _, _, _),
1532
+
[54] = PINGROUP(54, qup1_se5, usb_phy, _, _, _, _, _, _, _, _),
1533
+
[55] = PINGROUP(55, qup1_se5, _, _, _, _, _, _, _, _, _),
1534
+
[56] = PINGROUP(56, qup1_se6, ibi_i3c, qspi2, sdc42, _, _, _, _, _, _),
1535
+
[57] = PINGROUP(57, qup1_se6, ibi_i3c, qspi3, sdc43, _, _, _, _, _, _),
1536
+
[58] = PINGROUP(58, qup1_se6, qspi_cs, tb_trig_sdc4, tsense_pwm1, tsense_pwm2, tsense_pwm3, _, _, _, _),
1537
+
[59] = PINGROUP(59, qup1_se6, _, qspi_cs, sdc4_cmd, _, _, _, _, _, _),
1538
+
[60] = PINGROUP(60, qup1_se7, aoss_cti, vsense_trigger_mirnat, _, _, _, _, _, _, _),
1539
+
[61] = PINGROUP(61, qup1_se7, aoss_cti, _, _, _, _, _, _, _, _),
1540
+
[62] = PINGROUP(62, qup1_se7, ddr_pxi2, _, _, _, _, _, _, _, _),
1541
+
[63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _),
1542
+
[64] = PINGROUP(64, i2chub0_se0, _, _, _, _, _, _, _, _, _),
1543
+
[65] = PINGROUP(65, i2chub0_se0, _, _, _, _, _, _, _, _, _),
1544
+
[66] = PINGROUP(66, i2chub0_se1, _, _, _, _, _, _, _, _, _),
1545
+
[67] = PINGROUP(67, i2chub0_se1, _, _, _, _, _, _, _, _, _),
1546
+
[68] = PINGROUP(68, i2chub0_se2, pll_bist_sync, _, _, _, _, _, _, _, _),
1547
+
[69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _),
1548
+
[70] = PINGROUP(70, i2chub0_se3, _, _, _, _, _, _, _, _, _),
1549
+
[71] = PINGROUP(71, i2chub0_se3, _, atest_usb, _, _, _, _, _, _, _),
1550
+
[72] = PINGROUP(72, i2chub0_se4, _, atest_usb, _, _, _, _, _, _, _),
1551
+
[73] = PINGROUP(73, i2chub0_se4, jitter_bist, _, _, _, _, _, _, _, _),
1552
+
[74] = PINGROUP(74, i2chub0_se5, atest_usb, _, _, _, _, _, _, _, _),
1553
+
[75] = PINGROUP(75, i2chub0_se5, ddr_pxi0, _, _, _, _, _, _, _, _),
1554
+
[76] = PINGROUP(76, i2chub0_se6, ddr_pxi0, uim1_present, _, _, _, _, _, _, _),
1555
+
[77] = PINGROUP(77, i2chub0_se6, _, _, _, _, _, _, _, _, _),
1556
+
[78] = PINGROUP(78, i2chub0_se7, qdss_cti, _, _, _, _, _, _, _, _),
1557
+
[79] = PINGROUP(79, i2chub0_se7, qdss_cti, _, _, _, _, _, _, _, _),
1558
+
[80] = PINGROUP(80, i2chub0_se9, _, _, _, _, _, _, _, _, _),
1559
+
[81] = PINGROUP(81, i2chub0_se9, _, _, _, _, _, _, _, _, _),
1560
+
[82] = PINGROUP(82, qdss_cti, _, _, _, _, _, _, _, _, _),
1561
+
[83] = PINGROUP(83, qdss_cti, _, _, _, _, _, _, _, _, _),
1562
+
[84] = PINGROUP(84, _, _, _, _, _, _, _, _, _, _),
1563
+
[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _, _),
1564
+
[86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _, _),
1565
+
[87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, gcc_gp2, _, _, _, _, _, _),
1566
+
[88] = PINGROUP(88, mdp_vsync_e, gcc_gp3, _, _, _, _, _, _, _, _),
1567
+
[89] = PINGROUP(89, usb1_hs, gnss_adc0, _, _, _, _, _, _, _, _),
1568
+
[90] = PINGROUP(90, gnss_adc1, _, _, _, _, _, _, _, _, _),
1569
+
[91] = PINGROUP(91, _, gnss_adc0, _, _, _, _, _, _, _, _),
1570
+
[92] = PINGROUP(92, dbg_out_clk, gnss_adc1, _, _, _, _, _, _, _, _),
1571
+
[93] = PINGROUP(93, sd_write_protect, _, _, _, _, _, _, _, _, _),
1572
+
[94] = PINGROUP(94, cmu_rng, phase_flag, tmess_prng0, _, _, _, _, _, _, _),
1573
+
[95] = PINGROUP(95, pcie0_clk_req_n, cmu_rng, phase_flag, tmess_prng1, _, _, _, _, _, _),
1574
+
[96] = PINGROUP(96, cmu_rng, phase_flag, tmess_prng2, _, _, _, _, _, _, _),
1575
+
[97] = PINGROUP(97, _, _, _, _, _, _, _, _, _, _),
1576
+
[98] = PINGROUP(98, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _),
1577
+
[99] = PINGROUP(99, _, _, _, _, _, _, _, _, _, _),
1578
+
[100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _),
1579
+
[101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _),
1580
+
[102] = PINGROUP(102, cam_aon_mclk2, qdss_gpio, _, _, _, _, _, _, _, _),
1581
+
[103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _),
1582
+
[104] = PINGROUP(104, cam_aon_mclk4, qdss_gpio, _, _, _, _, _, _, _, _),
1583
+
[105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _),
1584
+
[106] = PINGROUP(106, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _),
1585
+
[107] = PINGROUP(107, _, _, _, _, _, _, _, _, _, _),
1586
+
[108] = PINGROUP(108, cam_mclk, _, _, _, _, _, _, _, _, _),
1587
+
[109] = PINGROUP(109, cci_timer, phase_flag, tmess_prng3, _, _, _, _, _, _, _),
1588
+
[110] = PINGROUP(110, cci_timer, _, _, _, _, _, _, _, _, _),
1589
+
[111] = PINGROUP(111, cci_timer, phase_flag, _, _, _, _, _, _, _, _),
1590
+
[112] = PINGROUP(112, cci_i2c_sda, cmu_rng, phase_flag, _, _, _, _, _, _, _),
1591
+
[113] = PINGROUP(113, cci_i2c_sda, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1592
+
[114] = PINGROUP(114, cci_i2c_scl, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1593
+
[115] = PINGROUP(115, cci_i2c_sda, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1594
+
[116] = PINGROUP(116, cci_i2c_scl, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1595
+
[117] = PINGROUP(117, cci_i2c_sda, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1596
+
[118] = PINGROUP(118, cci_i2c_scl, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1597
+
[119] = PINGROUP(119, cci_i2c_sda, phase_flag, _, _, _, _, _, _, _, _),
1598
+
[120] = PINGROUP(120, cci_i2c_scl, phase_flag, _, _, _, _, _, _, _, _),
1599
+
[121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _, _),
1600
+
[122] = PINGROUP(122, i2s1_data0, cmu_rng, _, _, _, _, _, _, _, _),
1601
+
[123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _, _),
1602
+
[124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _, _),
1603
+
[125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _, _),
1604
+
[126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _, _),
1605
+
[127] = PINGROUP(127, i2s0_data0, cmu_rng, _, _, _, _, _, _, _, _),
1606
+
[128] = PINGROUP(128, i2s0_data1, cmu_rng, _, _, _, _, _, _, _, _),
1607
+
[129] = PINGROUP(129, i2s0_ws, cmu_rng, _, _, _, _, _, _, _, _),
1608
+
[130] = PINGROUP(130, uim0_data, atest_usb, atest_char, _, _, _, _, _, _, _),
1609
+
[131] = PINGROUP(131, uim0_clk, atest_usb, atest_char, _, _, _, _, _, _, _),
1610
+
[132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _, _),
1611
+
[133] = PINGROUP(133, mdp_vsync, atest_char, _, _, _, _, _, _, _, _),
1612
+
[134] = PINGROUP(134, uim1_data, do_not, qspi0, sdc40, gcc_gp1, _, _, _, _, _),
1613
+
[135] = PINGROUP(135, uim1_clk, do_not, qspi_clk, sdc4_clk, gcc_gp2, _, _, _, _, _),
1614
+
[136] = PINGROUP(136, uim1_reset, do_not, qspi1, sdc41, gcc_gp3, _, _, _, _, _),
1615
+
[137] = PINGROUP(137, mdp_vsync, atest_char, _, _, _, _, _, _, _, _),
1616
+
[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _),
1617
+
[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _),
1618
+
[140] = PINGROUP(140, _, _, qdss_gpio, _, _, _, _, _, _, _),
1619
+
[141] = PINGROUP(141, _, _, qdss_gpio, _, _, _, _, _, _, _),
1620
+
[142] = PINGROUP(142, _, _, qdss_gpio, _, _, _, _, _, _, _),
1621
+
[143] = PINGROUP(143, _, _, qdss_gpio, _, _, _, _, _, _, _),
1622
+
[144] = PINGROUP(144, _, qdss_gpio, _, _, _, _, _, _, _, _),
1623
+
[145] = PINGROUP(145, _, qdss_gpio, _, _, _, _, _, _, _, _),
1624
+
[146] = PINGROUP(146, _, qdss_gpio, _, _, _, _, _, _, _, _),
1625
+
[147] = PINGROUP(147, _, qdss_gpio, _, _, _, _, _, _, _, _),
1626
+
[148] = PINGROUP(148, coex_uart1_rx, qdss_gpio, _, _, _, _, _, _, _, _),
1627
+
[149] = PINGROUP(149, coex_uart1_tx, qdss_gpio, _, _, _, _, _, _, _, _),
1628
+
[150] = PINGROUP(150, _, vfr_0, coex_uart2_rx, qdss_gpio, _, _, _, _, _, _),
1629
+
[151] = PINGROUP(151, _, coex_uart2_tx, qdss_gpio, _, _, _, _, _, _, _),
1630
+
[152] = PINGROUP(152, nav_gpio2, _, qdss_gpio, _, _, _, _, _, _, _),
1631
+
[153] = PINGROUP(153, cci_i2c_scl, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1632
+
[154] = PINGROUP(154, nav_gpio0, nav_gpio3, qdss_gpio, _, _, _, _, _, _, _),
1633
+
[155] = PINGROUP(155, nav_gpio1, vfr_1, qdss_gpio, _, _, _, _, _, _, _),
1634
+
[156] = PINGROUP(156, qlink_little_request, qdss_gpio, _, _, _, _, _, _, _, _),
1635
+
[157] = PINGROUP(157, qlink_little_enable, qdss_gpio, _, _, _, _, _, _, _, _),
1636
+
[158] = PINGROUP(158, qlink_wmss, qdss_gpio, _, _, _, _, _, _, _, _),
1637
+
[159] = PINGROUP(159, qlink_big_request, qdss_cti, _, _, _, _, _, _, _, _),
1638
+
[160] = PINGROUP(160, qlink_big_enable, _, _, _, _, _, _, _, _, _),
1639
+
[161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _),
1640
+
[162] = PINGROUP(162, qdss_cti, _, _, _, _, _, _, _, _, _),
1641
+
[163] = PINGROUP(163, cci_async_in, phase_flag, _, _, _, _, _, _, _, _),
1642
+
[164] = PINGROUP(164, cci_async_in, phase_flag, _, _, _, _, _, _, _, _),
1643
+
[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, egpio),
1644
+
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, egpio),
1645
+
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, egpio),
1646
+
[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, egpio),
1647
+
[169] = PINGROUP(169, _, _, _, _, _, _, _, _, _, egpio),
1648
+
[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _, egpio),
1649
+
[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _, egpio),
1650
+
[172] = PINGROUP(172, _, _, _, _, _, _, _, _, _, egpio),
1651
+
[173] = PINGROUP(173, _, _, _, _, _, _, _, _, _, egpio),
1652
+
[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, egpio),
1653
+
[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _, egpio),
1654
+
[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, egpio),
1655
+
[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, egpio),
1656
+
[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, egpio),
1657
+
[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _, egpio),
1658
+
[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _, egpio),
1659
+
[181] = PINGROUP(181, prng_rosc3, _, _, _, _, _, _, _, _, egpio),
1660
+
[182] = PINGROUP(182, prng_rosc2, _, _, _, _, _, _, _, _, egpio),
1661
+
[183] = PINGROUP(183, prng_rosc1, _, _, _, _, _, _, _, _, egpio),
1662
+
[184] = PINGROUP(184, _, _, _, _, _, _, _, _, _, egpio),
1663
+
[185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, egpio),
1664
+
[186] = PINGROUP(186, prng_rosc0, _, _, _, _, _, _, _, _, egpio),
1665
+
[187] = PINGROUP(187, cri_trng, _, _, _, _, _, _, _, _, egpio),
1666
+
[188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, egpio),
1667
+
[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, egpio),
1668
+
[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, egpio),
1669
+
[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, egpio),
1670
+
[192] = PINGROUP(192, _, _, _, _, _, _, _, _, _, egpio),
1671
+
[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, egpio),
1672
+
[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, egpio),
1673
+
[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, egpio),
1674
+
[196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, egpio),
1675
+
[197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, egpio),
1676
+
[198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, egpio),
1677
+
[199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, egpio),
1678
+
[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, egpio),
1679
+
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, egpio),
1680
+
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, egpio),
1681
+
[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, egpio),
1682
+
[204] = PINGROUP(204, _, _, _, _, _, _, _, _, _, egpio),
1683
+
[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, egpio),
1684
+
[206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _, egpio),
1685
+
[207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _, egpio),
1686
+
[208] = PINGROUP(208, _, _, _, _, _, _, _, _, _, egpio),
1687
+
[209] = PINGROUP(209, _, _, _, _, _, _, _, _, _, egpio),
1688
+
[210] = UFS_RESET(ufs_reset, 0xde004, 0xdf000),
1689
+
[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
1690
+
[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
1691
+
[213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0),
1692
+
};
1693
+
1694
+
static const struct msm_gpio_wakeirq_map sm8650_pdc_map[] = {
1695
+
{ 0, 94 }, { 3, 105 }, { 4, 78 }, { 7, 67 }, { 8, 64 },
1696
+
{ 11, 121 }, { 12, 71 }, { 15, 82 }, { 18, 75 }, { 19, 63 },
1697
+
{ 20, 114 }, { 23, 84 }, { 27, 61 }, { 29, 112 }, { 31, 113 },
1698
+
{ 32, 66 }, { 35, 52 }, { 36, 123 }, { 39, 56 }, { 43, 59 },
1699
+
{ 46, 79 }, { 47, 124 }, { 48, 125 }, { 51, 93 }, { 54, 60 },
1700
+
{ 55, 104 }, { 56, 72 }, { 57, 77 }, { 59, 51 }, { 63, 85 },
1701
+
{ 64, 107 }, { 65, 108 }, { 66, 109 }, { 67, 83 }, { 68, 110 },
1702
+
{ 69, 111 }, { 75, 96 }, { 76, 97 }, { 77, 98 }, { 80, 89 },
1703
+
{ 81, 90 }, { 84, 106 }, { 85, 100 }, { 86, 87 }, { 87, 88 },
1704
+
{ 88, 65 }, { 90, 92 }, { 92, 99 }, { 95, 118 }, { 96, 119 },
1705
+
{ 98, 101 }, { 99, 62 }, { 112, 120 }, { 133, 80 }, { 136, 69 },
1706
+
{ 137, 81 }, { 148, 57 }, { 150, 58 }, { 152, 127 }, { 153, 74 },
1707
+
{ 154, 126 }, { 155, 73 }, { 156, 128 }, { 159, 129 }, { 162, 86 },
1708
+
{ 163, 122 }, { 166, 139 }, { 169, 140 }, { 171, 141 }, { 172, 142 },
1709
+
{ 174, 102 }, { 176, 143 }, { 177, 55 }, { 181, 144 }, { 182, 145 },
1710
+
{ 185, 146 }, { 187, 95 }, { 188, 130 }, { 190, 131 }, { 191, 132 },
1711
+
{ 192, 133 }, { 193, 134 }, { 195, 68 }, { 196, 135 }, { 197, 136 },
1712
+
{ 198, 54 }, { 199, 103 }, { 200, 53 }, { 201, 137 }, { 202, 70 },
1713
+
{ 203, 138 }, { 204, 76 }, { 205, 91 },
1714
+
};
1715
+
1716
+
static const struct msm_pinctrl_soc_data sm8650_tlmm = {
1717
+
.pins = sm8650_pins,
1718
+
.npins = ARRAY_SIZE(sm8650_pins),
1719
+
.functions = sm8650_functions,
1720
+
.nfunctions = ARRAY_SIZE(sm8650_functions),
1721
+
.groups = sm8650_groups,
1722
+
.ngroups = ARRAY_SIZE(sm8650_groups),
1723
+
.ngpios = 211,
1724
+
.wakeirq_map = sm8650_pdc_map,
1725
+
.nwakeirq_map = ARRAY_SIZE(sm8650_pdc_map),
1726
+
.egpio_func = 10,
1727
+
};
1728
+
1729
+
static int sm8650_tlmm_probe(struct platform_device *pdev)
1730
+
{
1731
+
return msm_pinctrl_probe(pdev, &sm8650_tlmm);
1732
+
}
1733
+
1734
+
static const struct of_device_id sm8650_tlmm_of_match[] = {
1735
+
{ .compatible = "qcom,sm8650-tlmm", },
1736
+
{},
1737
+
};
1738
+
1739
+
static struct platform_driver sm8650_tlmm_driver = {
1740
+
.driver = {
1741
+
.name = "sm8650-tlmm",
1742
+
.of_match_table = sm8650_tlmm_of_match,
1743
+
},
1744
+
.probe = sm8650_tlmm_probe,
1745
+
.remove_new = msm_pinctrl_remove,
1746
+
};
1747
+
1748
+
static int __init sm8650_tlmm_init(void)
1749
+
{
1750
+
return platform_driver_register(&sm8650_tlmm_driver);
1751
+
}
1752
+
arch_initcall(sm8650_tlmm_init);
1753
+
1754
+
static void __exit sm8650_tlmm_exit(void)
1755
+
{
1756
+
platform_driver_unregister(&sm8650_tlmm_driver);
1757
+
}
1758
+
module_exit(sm8650_tlmm_exit);
1759
+
1760
+
MODULE_DESCRIPTION("QTI SM8650 TLMM driver");
1761
+
MODULE_LICENSE("GPL");
1762
+
MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match);
+1876
drivers/pinctrl/qcom/pinctrl-x1e80100.c
+1876
drivers/pinctrl/qcom/pinctrl-x1e80100.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
14
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15
+
{ \
16
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
17
+
gpio##id##_pins, \
18
+
ARRAY_SIZE(gpio##id##_pins)), \
19
+
.funcs = (int[]){ \
20
+
msm_mux_gpio, /* gpio mode */ \
21
+
msm_mux_##f1, \
22
+
msm_mux_##f2, \
23
+
msm_mux_##f3, \
24
+
msm_mux_##f4, \
25
+
msm_mux_##f5, \
26
+
msm_mux_##f6, \
27
+
msm_mux_##f7, \
28
+
msm_mux_##f8, \
29
+
msm_mux_##f9 \
30
+
}, \
31
+
.nfuncs = 10, \
32
+
.ctl_reg = REG_SIZE * id, \
33
+
.io_reg = 0x4 + REG_SIZE * id, \
34
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
+
.intr_status_reg = 0xc + REG_SIZE * id, \
36
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
+
.mux_bit = 2, \
38
+
.pull_bit = 0, \
39
+
.drv_bit = 6, \
40
+
.i2c_pull_bit = 13, \
41
+
.egpio_enable = 12, \
42
+
.egpio_present = 11, \
43
+
.oe_bit = 9, \
44
+
.in_bit = 0, \
45
+
.out_bit = 1, \
46
+
.intr_enable_bit = 0, \
47
+
.intr_status_bit = 0, \
48
+
.intr_target_bit = 5, \
49
+
.intr_target_kpss_val = 3, \
50
+
.intr_raw_status_bit = 4, \
51
+
.intr_polarity_bit = 1, \
52
+
.intr_detection_bit = 2, \
53
+
.intr_detection_width = 2, \
54
+
}
55
+
56
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
57
+
{ \
58
+
.grp = PINCTRL_PINGROUP(#pg_name, \
59
+
pg_name##_pins, \
60
+
ARRAY_SIZE(pg_name##_pins)), \
61
+
.ctl_reg = ctl, \
62
+
.io_reg = 0, \
63
+
.intr_cfg_reg = 0, \
64
+
.intr_status_reg = 0, \
65
+
.intr_target_reg = 0, \
66
+
.mux_bit = -1, \
67
+
.pull_bit = pull, \
68
+
.drv_bit = drv, \
69
+
.oe_bit = -1, \
70
+
.in_bit = -1, \
71
+
.out_bit = -1, \
72
+
.intr_enable_bit = -1, \
73
+
.intr_status_bit = -1, \
74
+
.intr_target_bit = -1, \
75
+
.intr_raw_status_bit = -1, \
76
+
.intr_polarity_bit = -1, \
77
+
.intr_detection_bit = -1, \
78
+
.intr_detection_width = -1, \
79
+
}
80
+
81
+
#define UFS_RESET(pg_name, offset) \
82
+
{ \
83
+
.grp = PINCTRL_PINGROUP(#pg_name, \
84
+
pg_name##_pins, \
85
+
ARRAY_SIZE(pg_name##_pins)), \
86
+
.ctl_reg = offset, \
87
+
.io_reg = offset + 0x4, \
88
+
.intr_cfg_reg = 0, \
89
+
.intr_status_reg = 0, \
90
+
.intr_target_reg = 0, \
91
+
.mux_bit = -1, \
92
+
.pull_bit = 3, \
93
+
.drv_bit = 0, \
94
+
.oe_bit = -1, \
95
+
.in_bit = -1, \
96
+
.out_bit = 0, \
97
+
.intr_enable_bit = -1, \
98
+
.intr_status_bit = -1, \
99
+
.intr_target_bit = -1, \
100
+
.intr_raw_status_bit = -1, \
101
+
.intr_polarity_bit = -1, \
102
+
.intr_detection_bit = -1, \
103
+
.intr_detection_width = -1, \
104
+
}
105
+
106
+
static const struct pinctrl_pin_desc x1e80100_pins[] = {
107
+
PINCTRL_PIN(0, "GPIO_0"),
108
+
PINCTRL_PIN(1, "GPIO_1"),
109
+
PINCTRL_PIN(2, "GPIO_2"),
110
+
PINCTRL_PIN(3, "GPIO_3"),
111
+
PINCTRL_PIN(4, "GPIO_4"),
112
+
PINCTRL_PIN(5, "GPIO_5"),
113
+
PINCTRL_PIN(6, "GPIO_6"),
114
+
PINCTRL_PIN(7, "GPIO_7"),
115
+
PINCTRL_PIN(8, "GPIO_8"),
116
+
PINCTRL_PIN(9, "GPIO_9"),
117
+
PINCTRL_PIN(10, "GPIO_10"),
118
+
PINCTRL_PIN(11, "GPIO_11"),
119
+
PINCTRL_PIN(12, "GPIO_12"),
120
+
PINCTRL_PIN(13, "GPIO_13"),
121
+
PINCTRL_PIN(14, "GPIO_14"),
122
+
PINCTRL_PIN(15, "GPIO_15"),
123
+
PINCTRL_PIN(16, "GPIO_16"),
124
+
PINCTRL_PIN(17, "GPIO_17"),
125
+
PINCTRL_PIN(18, "GPIO_18"),
126
+
PINCTRL_PIN(19, "GPIO_19"),
127
+
PINCTRL_PIN(20, "GPIO_20"),
128
+
PINCTRL_PIN(21, "GPIO_21"),
129
+
PINCTRL_PIN(22, "GPIO_22"),
130
+
PINCTRL_PIN(23, "GPIO_23"),
131
+
PINCTRL_PIN(24, "GPIO_24"),
132
+
PINCTRL_PIN(25, "GPIO_25"),
133
+
PINCTRL_PIN(26, "GPIO_26"),
134
+
PINCTRL_PIN(27, "GPIO_27"),
135
+
PINCTRL_PIN(28, "GPIO_28"),
136
+
PINCTRL_PIN(29, "GPIO_29"),
137
+
PINCTRL_PIN(30, "GPIO_30"),
138
+
PINCTRL_PIN(31, "GPIO_31"),
139
+
PINCTRL_PIN(32, "GPIO_32"),
140
+
PINCTRL_PIN(33, "GPIO_33"),
141
+
PINCTRL_PIN(34, "GPIO_34"),
142
+
PINCTRL_PIN(35, "GPIO_35"),
143
+
PINCTRL_PIN(36, "GPIO_36"),
144
+
PINCTRL_PIN(37, "GPIO_37"),
145
+
PINCTRL_PIN(38, "GPIO_38"),
146
+
PINCTRL_PIN(39, "GPIO_39"),
147
+
PINCTRL_PIN(40, "GPIO_40"),
148
+
PINCTRL_PIN(41, "GPIO_41"),
149
+
PINCTRL_PIN(42, "GPIO_42"),
150
+
PINCTRL_PIN(43, "GPIO_43"),
151
+
PINCTRL_PIN(44, "GPIO_44"),
152
+
PINCTRL_PIN(45, "GPIO_45"),
153
+
PINCTRL_PIN(46, "GPIO_46"),
154
+
PINCTRL_PIN(47, "GPIO_47"),
155
+
PINCTRL_PIN(48, "GPIO_48"),
156
+
PINCTRL_PIN(49, "GPIO_49"),
157
+
PINCTRL_PIN(50, "GPIO_50"),
158
+
PINCTRL_PIN(51, "GPIO_51"),
159
+
PINCTRL_PIN(52, "GPIO_52"),
160
+
PINCTRL_PIN(53, "GPIO_53"),
161
+
PINCTRL_PIN(54, "GPIO_54"),
162
+
PINCTRL_PIN(55, "GPIO_55"),
163
+
PINCTRL_PIN(56, "GPIO_56"),
164
+
PINCTRL_PIN(57, "GPIO_57"),
165
+
PINCTRL_PIN(58, "GPIO_58"),
166
+
PINCTRL_PIN(59, "GPIO_59"),
167
+
PINCTRL_PIN(60, "GPIO_60"),
168
+
PINCTRL_PIN(61, "GPIO_61"),
169
+
PINCTRL_PIN(62, "GPIO_62"),
170
+
PINCTRL_PIN(63, "GPIO_63"),
171
+
PINCTRL_PIN(64, "GPIO_64"),
172
+
PINCTRL_PIN(65, "GPIO_65"),
173
+
PINCTRL_PIN(66, "GPIO_66"),
174
+
PINCTRL_PIN(67, "GPIO_67"),
175
+
PINCTRL_PIN(68, "GPIO_68"),
176
+
PINCTRL_PIN(69, "GPIO_69"),
177
+
PINCTRL_PIN(70, "GPIO_70"),
178
+
PINCTRL_PIN(71, "GPIO_71"),
179
+
PINCTRL_PIN(72, "GPIO_72"),
180
+
PINCTRL_PIN(73, "GPIO_73"),
181
+
PINCTRL_PIN(74, "GPIO_74"),
182
+
PINCTRL_PIN(75, "GPIO_75"),
183
+
PINCTRL_PIN(76, "GPIO_76"),
184
+
PINCTRL_PIN(77, "GPIO_77"),
185
+
PINCTRL_PIN(78, "GPIO_78"),
186
+
PINCTRL_PIN(79, "GPIO_79"),
187
+
PINCTRL_PIN(80, "GPIO_80"),
188
+
PINCTRL_PIN(81, "GPIO_81"),
189
+
PINCTRL_PIN(82, "GPIO_82"),
190
+
PINCTRL_PIN(83, "GPIO_83"),
191
+
PINCTRL_PIN(84, "GPIO_84"),
192
+
PINCTRL_PIN(85, "GPIO_85"),
193
+
PINCTRL_PIN(86, "GPIO_86"),
194
+
PINCTRL_PIN(87, "GPIO_87"),
195
+
PINCTRL_PIN(88, "GPIO_88"),
196
+
PINCTRL_PIN(89, "GPIO_89"),
197
+
PINCTRL_PIN(90, "GPIO_90"),
198
+
PINCTRL_PIN(91, "GPIO_91"),
199
+
PINCTRL_PIN(92, "GPIO_92"),
200
+
PINCTRL_PIN(93, "GPIO_93"),
201
+
PINCTRL_PIN(94, "GPIO_94"),
202
+
PINCTRL_PIN(95, "GPIO_95"),
203
+
PINCTRL_PIN(96, "GPIO_96"),
204
+
PINCTRL_PIN(97, "GPIO_97"),
205
+
PINCTRL_PIN(98, "GPIO_98"),
206
+
PINCTRL_PIN(99, "GPIO_99"),
207
+
PINCTRL_PIN(100, "GPIO_100"),
208
+
PINCTRL_PIN(101, "GPIO_101"),
209
+
PINCTRL_PIN(102, "GPIO_102"),
210
+
PINCTRL_PIN(103, "GPIO_103"),
211
+
PINCTRL_PIN(104, "GPIO_104"),
212
+
PINCTRL_PIN(105, "GPIO_105"),
213
+
PINCTRL_PIN(106, "GPIO_106"),
214
+
PINCTRL_PIN(107, "GPIO_107"),
215
+
PINCTRL_PIN(108, "GPIO_108"),
216
+
PINCTRL_PIN(109, "GPIO_109"),
217
+
PINCTRL_PIN(110, "GPIO_110"),
218
+
PINCTRL_PIN(111, "GPIO_111"),
219
+
PINCTRL_PIN(112, "GPIO_112"),
220
+
PINCTRL_PIN(113, "GPIO_113"),
221
+
PINCTRL_PIN(114, "GPIO_114"),
222
+
PINCTRL_PIN(115, "GPIO_115"),
223
+
PINCTRL_PIN(116, "GPIO_116"),
224
+
PINCTRL_PIN(117, "GPIO_117"),
225
+
PINCTRL_PIN(118, "GPIO_118"),
226
+
PINCTRL_PIN(119, "GPIO_119"),
227
+
PINCTRL_PIN(120, "GPIO_120"),
228
+
PINCTRL_PIN(121, "GPIO_121"),
229
+
PINCTRL_PIN(122, "GPIO_122"),
230
+
PINCTRL_PIN(123, "GPIO_123"),
231
+
PINCTRL_PIN(124, "GPIO_124"),
232
+
PINCTRL_PIN(125, "GPIO_125"),
233
+
PINCTRL_PIN(126, "GPIO_126"),
234
+
PINCTRL_PIN(127, "GPIO_127"),
235
+
PINCTRL_PIN(128, "GPIO_128"),
236
+
PINCTRL_PIN(129, "GPIO_129"),
237
+
PINCTRL_PIN(130, "GPIO_130"),
238
+
PINCTRL_PIN(131, "GPIO_131"),
239
+
PINCTRL_PIN(132, "GPIO_132"),
240
+
PINCTRL_PIN(133, "GPIO_133"),
241
+
PINCTRL_PIN(134, "GPIO_134"),
242
+
PINCTRL_PIN(135, "GPIO_135"),
243
+
PINCTRL_PIN(136, "GPIO_136"),
244
+
PINCTRL_PIN(137, "GPIO_137"),
245
+
PINCTRL_PIN(138, "GPIO_138"),
246
+
PINCTRL_PIN(139, "GPIO_139"),
247
+
PINCTRL_PIN(140, "GPIO_140"),
248
+
PINCTRL_PIN(141, "GPIO_141"),
249
+
PINCTRL_PIN(142, "GPIO_142"),
250
+
PINCTRL_PIN(143, "GPIO_143"),
251
+
PINCTRL_PIN(144, "GPIO_144"),
252
+
PINCTRL_PIN(145, "GPIO_145"),
253
+
PINCTRL_PIN(146, "GPIO_146"),
254
+
PINCTRL_PIN(147, "GPIO_147"),
255
+
PINCTRL_PIN(148, "GPIO_148"),
256
+
PINCTRL_PIN(149, "GPIO_149"),
257
+
PINCTRL_PIN(150, "GPIO_150"),
258
+
PINCTRL_PIN(151, "GPIO_151"),
259
+
PINCTRL_PIN(152, "GPIO_152"),
260
+
PINCTRL_PIN(153, "GPIO_153"),
261
+
PINCTRL_PIN(154, "GPIO_154"),
262
+
PINCTRL_PIN(155, "GPIO_155"),
263
+
PINCTRL_PIN(156, "GPIO_156"),
264
+
PINCTRL_PIN(157, "GPIO_157"),
265
+
PINCTRL_PIN(158, "GPIO_158"),
266
+
PINCTRL_PIN(159, "GPIO_159"),
267
+
PINCTRL_PIN(160, "GPIO_160"),
268
+
PINCTRL_PIN(161, "GPIO_161"),
269
+
PINCTRL_PIN(162, "GPIO_162"),
270
+
PINCTRL_PIN(163, "GPIO_163"),
271
+
PINCTRL_PIN(164, "GPIO_164"),
272
+
PINCTRL_PIN(165, "GPIO_165"),
273
+
PINCTRL_PIN(166, "GPIO_166"),
274
+
PINCTRL_PIN(167, "GPIO_167"),
275
+
PINCTRL_PIN(168, "GPIO_168"),
276
+
PINCTRL_PIN(169, "GPIO_169"),
277
+
PINCTRL_PIN(170, "GPIO_170"),
278
+
PINCTRL_PIN(171, "GPIO_171"),
279
+
PINCTRL_PIN(172, "GPIO_172"),
280
+
PINCTRL_PIN(173, "GPIO_173"),
281
+
PINCTRL_PIN(174, "GPIO_174"),
282
+
PINCTRL_PIN(175, "GPIO_175"),
283
+
PINCTRL_PIN(176, "GPIO_176"),
284
+
PINCTRL_PIN(177, "GPIO_177"),
285
+
PINCTRL_PIN(178, "GPIO_178"),
286
+
PINCTRL_PIN(179, "GPIO_179"),
287
+
PINCTRL_PIN(180, "GPIO_180"),
288
+
PINCTRL_PIN(181, "GPIO_181"),
289
+
PINCTRL_PIN(182, "GPIO_182"),
290
+
PINCTRL_PIN(183, "GPIO_183"),
291
+
PINCTRL_PIN(184, "GPIO_184"),
292
+
PINCTRL_PIN(185, "GPIO_185"),
293
+
PINCTRL_PIN(186, "GPIO_186"),
294
+
PINCTRL_PIN(187, "GPIO_187"),
295
+
PINCTRL_PIN(188, "GPIO_188"),
296
+
PINCTRL_PIN(189, "GPIO_189"),
297
+
PINCTRL_PIN(190, "GPIO_190"),
298
+
PINCTRL_PIN(191, "GPIO_191"),
299
+
PINCTRL_PIN(192, "GPIO_192"),
300
+
PINCTRL_PIN(193, "GPIO_193"),
301
+
PINCTRL_PIN(194, "GPIO_194"),
302
+
PINCTRL_PIN(195, "GPIO_195"),
303
+
PINCTRL_PIN(196, "GPIO_196"),
304
+
PINCTRL_PIN(197, "GPIO_197"),
305
+
PINCTRL_PIN(198, "GPIO_198"),
306
+
PINCTRL_PIN(199, "GPIO_199"),
307
+
PINCTRL_PIN(200, "GPIO_200"),
308
+
PINCTRL_PIN(201, "GPIO_201"),
309
+
PINCTRL_PIN(202, "GPIO_202"),
310
+
PINCTRL_PIN(203, "GPIO_203"),
311
+
PINCTRL_PIN(204, "GPIO_204"),
312
+
PINCTRL_PIN(205, "GPIO_205"),
313
+
PINCTRL_PIN(206, "GPIO_206"),
314
+
PINCTRL_PIN(207, "GPIO_207"),
315
+
PINCTRL_PIN(208, "GPIO_208"),
316
+
PINCTRL_PIN(209, "GPIO_209"),
317
+
PINCTRL_PIN(210, "GPIO_210"),
318
+
PINCTRL_PIN(211, "GPIO_211"),
319
+
PINCTRL_PIN(212, "GPIO_212"),
320
+
PINCTRL_PIN(213, "GPIO_213"),
321
+
PINCTRL_PIN(214, "GPIO_214"),
322
+
PINCTRL_PIN(215, "GPIO_215"),
323
+
PINCTRL_PIN(216, "GPIO_216"),
324
+
PINCTRL_PIN(217, "GPIO_217"),
325
+
PINCTRL_PIN(218, "GPIO_218"),
326
+
PINCTRL_PIN(219, "GPIO_219"),
327
+
PINCTRL_PIN(220, "GPIO_220"),
328
+
PINCTRL_PIN(221, "GPIO_221"),
329
+
PINCTRL_PIN(222, "GPIO_222"),
330
+
PINCTRL_PIN(223, "GPIO_223"),
331
+
PINCTRL_PIN(224, "GPIO_224"),
332
+
PINCTRL_PIN(225, "GPIO_225"),
333
+
PINCTRL_PIN(226, "GPIO_226"),
334
+
PINCTRL_PIN(227, "GPIO_227"),
335
+
PINCTRL_PIN(228, "GPIO_228"),
336
+
PINCTRL_PIN(229, "GPIO_229"),
337
+
PINCTRL_PIN(230, "GPIO_230"),
338
+
PINCTRL_PIN(231, "GPIO_231"),
339
+
PINCTRL_PIN(232, "GPIO_232"),
340
+
PINCTRL_PIN(233, "GPIO_233"),
341
+
PINCTRL_PIN(234, "GPIO_234"),
342
+
PINCTRL_PIN(235, "GPIO_235"),
343
+
PINCTRL_PIN(236, "GPIO_236"),
344
+
PINCTRL_PIN(237, "GPIO_237"),
345
+
PINCTRL_PIN(238, "UFS_RESET"),
346
+
PINCTRL_PIN(239, "SDC2_CLK"),
347
+
PINCTRL_PIN(240, "SDC2_CMD"),
348
+
PINCTRL_PIN(241, "SDC2_DATA"),
349
+
};
350
+
351
+
#define DECLARE_MSM_GPIO_PINS(pin) \
352
+
static const unsigned int gpio##pin##_pins[] = { pin }
353
+
DECLARE_MSM_GPIO_PINS(0);
354
+
DECLARE_MSM_GPIO_PINS(1);
355
+
DECLARE_MSM_GPIO_PINS(2);
356
+
DECLARE_MSM_GPIO_PINS(3);
357
+
DECLARE_MSM_GPIO_PINS(4);
358
+
DECLARE_MSM_GPIO_PINS(5);
359
+
DECLARE_MSM_GPIO_PINS(6);
360
+
DECLARE_MSM_GPIO_PINS(7);
361
+
DECLARE_MSM_GPIO_PINS(8);
362
+
DECLARE_MSM_GPIO_PINS(9);
363
+
DECLARE_MSM_GPIO_PINS(10);
364
+
DECLARE_MSM_GPIO_PINS(11);
365
+
DECLARE_MSM_GPIO_PINS(12);
366
+
DECLARE_MSM_GPIO_PINS(13);
367
+
DECLARE_MSM_GPIO_PINS(14);
368
+
DECLARE_MSM_GPIO_PINS(15);
369
+
DECLARE_MSM_GPIO_PINS(16);
370
+
DECLARE_MSM_GPIO_PINS(17);
371
+
DECLARE_MSM_GPIO_PINS(18);
372
+
DECLARE_MSM_GPIO_PINS(19);
373
+
DECLARE_MSM_GPIO_PINS(20);
374
+
DECLARE_MSM_GPIO_PINS(21);
375
+
DECLARE_MSM_GPIO_PINS(22);
376
+
DECLARE_MSM_GPIO_PINS(23);
377
+
DECLARE_MSM_GPIO_PINS(24);
378
+
DECLARE_MSM_GPIO_PINS(25);
379
+
DECLARE_MSM_GPIO_PINS(26);
380
+
DECLARE_MSM_GPIO_PINS(27);
381
+
DECLARE_MSM_GPIO_PINS(28);
382
+
DECLARE_MSM_GPIO_PINS(29);
383
+
DECLARE_MSM_GPIO_PINS(30);
384
+
DECLARE_MSM_GPIO_PINS(31);
385
+
DECLARE_MSM_GPIO_PINS(32);
386
+
DECLARE_MSM_GPIO_PINS(33);
387
+
DECLARE_MSM_GPIO_PINS(34);
388
+
DECLARE_MSM_GPIO_PINS(35);
389
+
DECLARE_MSM_GPIO_PINS(36);
390
+
DECLARE_MSM_GPIO_PINS(37);
391
+
DECLARE_MSM_GPIO_PINS(38);
392
+
DECLARE_MSM_GPIO_PINS(39);
393
+
DECLARE_MSM_GPIO_PINS(40);
394
+
DECLARE_MSM_GPIO_PINS(41);
395
+
DECLARE_MSM_GPIO_PINS(42);
396
+
DECLARE_MSM_GPIO_PINS(43);
397
+
DECLARE_MSM_GPIO_PINS(44);
398
+
DECLARE_MSM_GPIO_PINS(45);
399
+
DECLARE_MSM_GPIO_PINS(46);
400
+
DECLARE_MSM_GPIO_PINS(47);
401
+
DECLARE_MSM_GPIO_PINS(48);
402
+
DECLARE_MSM_GPIO_PINS(49);
403
+
DECLARE_MSM_GPIO_PINS(50);
404
+
DECLARE_MSM_GPIO_PINS(51);
405
+
DECLARE_MSM_GPIO_PINS(52);
406
+
DECLARE_MSM_GPIO_PINS(53);
407
+
DECLARE_MSM_GPIO_PINS(54);
408
+
DECLARE_MSM_GPIO_PINS(55);
409
+
DECLARE_MSM_GPIO_PINS(56);
410
+
DECLARE_MSM_GPIO_PINS(57);
411
+
DECLARE_MSM_GPIO_PINS(58);
412
+
DECLARE_MSM_GPIO_PINS(59);
413
+
DECLARE_MSM_GPIO_PINS(60);
414
+
DECLARE_MSM_GPIO_PINS(61);
415
+
DECLARE_MSM_GPIO_PINS(62);
416
+
DECLARE_MSM_GPIO_PINS(63);
417
+
DECLARE_MSM_GPIO_PINS(64);
418
+
DECLARE_MSM_GPIO_PINS(65);
419
+
DECLARE_MSM_GPIO_PINS(66);
420
+
DECLARE_MSM_GPIO_PINS(67);
421
+
DECLARE_MSM_GPIO_PINS(68);
422
+
DECLARE_MSM_GPIO_PINS(69);
423
+
DECLARE_MSM_GPIO_PINS(70);
424
+
DECLARE_MSM_GPIO_PINS(71);
425
+
DECLARE_MSM_GPIO_PINS(72);
426
+
DECLARE_MSM_GPIO_PINS(73);
427
+
DECLARE_MSM_GPIO_PINS(74);
428
+
DECLARE_MSM_GPIO_PINS(75);
429
+
DECLARE_MSM_GPIO_PINS(76);
430
+
DECLARE_MSM_GPIO_PINS(77);
431
+
DECLARE_MSM_GPIO_PINS(78);
432
+
DECLARE_MSM_GPIO_PINS(79);
433
+
DECLARE_MSM_GPIO_PINS(80);
434
+
DECLARE_MSM_GPIO_PINS(81);
435
+
DECLARE_MSM_GPIO_PINS(82);
436
+
DECLARE_MSM_GPIO_PINS(83);
437
+
DECLARE_MSM_GPIO_PINS(84);
438
+
DECLARE_MSM_GPIO_PINS(85);
439
+
DECLARE_MSM_GPIO_PINS(86);
440
+
DECLARE_MSM_GPIO_PINS(87);
441
+
DECLARE_MSM_GPIO_PINS(88);
442
+
DECLARE_MSM_GPIO_PINS(89);
443
+
DECLARE_MSM_GPIO_PINS(90);
444
+
DECLARE_MSM_GPIO_PINS(91);
445
+
DECLARE_MSM_GPIO_PINS(92);
446
+
DECLARE_MSM_GPIO_PINS(93);
447
+
DECLARE_MSM_GPIO_PINS(94);
448
+
DECLARE_MSM_GPIO_PINS(95);
449
+
DECLARE_MSM_GPIO_PINS(96);
450
+
DECLARE_MSM_GPIO_PINS(97);
451
+
DECLARE_MSM_GPIO_PINS(98);
452
+
DECLARE_MSM_GPIO_PINS(99);
453
+
DECLARE_MSM_GPIO_PINS(100);
454
+
DECLARE_MSM_GPIO_PINS(101);
455
+
DECLARE_MSM_GPIO_PINS(102);
456
+
DECLARE_MSM_GPIO_PINS(103);
457
+
DECLARE_MSM_GPIO_PINS(104);
458
+
DECLARE_MSM_GPIO_PINS(105);
459
+
DECLARE_MSM_GPIO_PINS(106);
460
+
DECLARE_MSM_GPIO_PINS(107);
461
+
DECLARE_MSM_GPIO_PINS(108);
462
+
DECLARE_MSM_GPIO_PINS(109);
463
+
DECLARE_MSM_GPIO_PINS(110);
464
+
DECLARE_MSM_GPIO_PINS(111);
465
+
DECLARE_MSM_GPIO_PINS(112);
466
+
DECLARE_MSM_GPIO_PINS(113);
467
+
DECLARE_MSM_GPIO_PINS(114);
468
+
DECLARE_MSM_GPIO_PINS(115);
469
+
DECLARE_MSM_GPIO_PINS(116);
470
+
DECLARE_MSM_GPIO_PINS(117);
471
+
DECLARE_MSM_GPIO_PINS(118);
472
+
DECLARE_MSM_GPIO_PINS(119);
473
+
DECLARE_MSM_GPIO_PINS(120);
474
+
DECLARE_MSM_GPIO_PINS(121);
475
+
DECLARE_MSM_GPIO_PINS(122);
476
+
DECLARE_MSM_GPIO_PINS(123);
477
+
DECLARE_MSM_GPIO_PINS(124);
478
+
DECLARE_MSM_GPIO_PINS(125);
479
+
DECLARE_MSM_GPIO_PINS(126);
480
+
DECLARE_MSM_GPIO_PINS(127);
481
+
DECLARE_MSM_GPIO_PINS(128);
482
+
DECLARE_MSM_GPIO_PINS(129);
483
+
DECLARE_MSM_GPIO_PINS(130);
484
+
DECLARE_MSM_GPIO_PINS(131);
485
+
DECLARE_MSM_GPIO_PINS(132);
486
+
DECLARE_MSM_GPIO_PINS(133);
487
+
DECLARE_MSM_GPIO_PINS(134);
488
+
DECLARE_MSM_GPIO_PINS(135);
489
+
DECLARE_MSM_GPIO_PINS(136);
490
+
DECLARE_MSM_GPIO_PINS(137);
491
+
DECLARE_MSM_GPIO_PINS(138);
492
+
DECLARE_MSM_GPIO_PINS(139);
493
+
DECLARE_MSM_GPIO_PINS(140);
494
+
DECLARE_MSM_GPIO_PINS(141);
495
+
DECLARE_MSM_GPIO_PINS(142);
496
+
DECLARE_MSM_GPIO_PINS(143);
497
+
DECLARE_MSM_GPIO_PINS(144);
498
+
DECLARE_MSM_GPIO_PINS(145);
499
+
DECLARE_MSM_GPIO_PINS(146);
500
+
DECLARE_MSM_GPIO_PINS(147);
501
+
DECLARE_MSM_GPIO_PINS(148);
502
+
DECLARE_MSM_GPIO_PINS(149);
503
+
DECLARE_MSM_GPIO_PINS(150);
504
+
DECLARE_MSM_GPIO_PINS(151);
505
+
DECLARE_MSM_GPIO_PINS(152);
506
+
DECLARE_MSM_GPIO_PINS(153);
507
+
DECLARE_MSM_GPIO_PINS(154);
508
+
DECLARE_MSM_GPIO_PINS(155);
509
+
DECLARE_MSM_GPIO_PINS(156);
510
+
DECLARE_MSM_GPIO_PINS(157);
511
+
DECLARE_MSM_GPIO_PINS(158);
512
+
DECLARE_MSM_GPIO_PINS(159);
513
+
DECLARE_MSM_GPIO_PINS(160);
514
+
DECLARE_MSM_GPIO_PINS(161);
515
+
DECLARE_MSM_GPIO_PINS(162);
516
+
DECLARE_MSM_GPIO_PINS(163);
517
+
DECLARE_MSM_GPIO_PINS(164);
518
+
DECLARE_MSM_GPIO_PINS(165);
519
+
DECLARE_MSM_GPIO_PINS(166);
520
+
DECLARE_MSM_GPIO_PINS(167);
521
+
DECLARE_MSM_GPIO_PINS(168);
522
+
DECLARE_MSM_GPIO_PINS(169);
523
+
DECLARE_MSM_GPIO_PINS(170);
524
+
DECLARE_MSM_GPIO_PINS(171);
525
+
DECLARE_MSM_GPIO_PINS(172);
526
+
DECLARE_MSM_GPIO_PINS(173);
527
+
DECLARE_MSM_GPIO_PINS(174);
528
+
DECLARE_MSM_GPIO_PINS(175);
529
+
DECLARE_MSM_GPIO_PINS(176);
530
+
DECLARE_MSM_GPIO_PINS(177);
531
+
DECLARE_MSM_GPIO_PINS(178);
532
+
DECLARE_MSM_GPIO_PINS(179);
533
+
DECLARE_MSM_GPIO_PINS(180);
534
+
DECLARE_MSM_GPIO_PINS(181);
535
+
DECLARE_MSM_GPIO_PINS(182);
536
+
DECLARE_MSM_GPIO_PINS(183);
537
+
DECLARE_MSM_GPIO_PINS(184);
538
+
DECLARE_MSM_GPIO_PINS(185);
539
+
DECLARE_MSM_GPIO_PINS(186);
540
+
DECLARE_MSM_GPIO_PINS(187);
541
+
DECLARE_MSM_GPIO_PINS(188);
542
+
DECLARE_MSM_GPIO_PINS(189);
543
+
DECLARE_MSM_GPIO_PINS(190);
544
+
DECLARE_MSM_GPIO_PINS(191);
545
+
DECLARE_MSM_GPIO_PINS(192);
546
+
DECLARE_MSM_GPIO_PINS(193);
547
+
DECLARE_MSM_GPIO_PINS(194);
548
+
DECLARE_MSM_GPIO_PINS(195);
549
+
DECLARE_MSM_GPIO_PINS(196);
550
+
DECLARE_MSM_GPIO_PINS(197);
551
+
DECLARE_MSM_GPIO_PINS(198);
552
+
DECLARE_MSM_GPIO_PINS(199);
553
+
DECLARE_MSM_GPIO_PINS(200);
554
+
DECLARE_MSM_GPIO_PINS(201);
555
+
DECLARE_MSM_GPIO_PINS(202);
556
+
DECLARE_MSM_GPIO_PINS(203);
557
+
DECLARE_MSM_GPIO_PINS(204);
558
+
DECLARE_MSM_GPIO_PINS(205);
559
+
DECLARE_MSM_GPIO_PINS(206);
560
+
DECLARE_MSM_GPIO_PINS(207);
561
+
DECLARE_MSM_GPIO_PINS(208);
562
+
DECLARE_MSM_GPIO_PINS(209);
563
+
DECLARE_MSM_GPIO_PINS(210);
564
+
DECLARE_MSM_GPIO_PINS(211);
565
+
DECLARE_MSM_GPIO_PINS(212);
566
+
DECLARE_MSM_GPIO_PINS(213);
567
+
DECLARE_MSM_GPIO_PINS(214);
568
+
DECLARE_MSM_GPIO_PINS(215);
569
+
DECLARE_MSM_GPIO_PINS(216);
570
+
DECLARE_MSM_GPIO_PINS(217);
571
+
DECLARE_MSM_GPIO_PINS(218);
572
+
DECLARE_MSM_GPIO_PINS(219);
573
+
DECLARE_MSM_GPIO_PINS(220);
574
+
DECLARE_MSM_GPIO_PINS(221);
575
+
DECLARE_MSM_GPIO_PINS(222);
576
+
DECLARE_MSM_GPIO_PINS(223);
577
+
DECLARE_MSM_GPIO_PINS(224);
578
+
DECLARE_MSM_GPIO_PINS(225);
579
+
DECLARE_MSM_GPIO_PINS(226);
580
+
DECLARE_MSM_GPIO_PINS(227);
581
+
DECLARE_MSM_GPIO_PINS(228);
582
+
DECLARE_MSM_GPIO_PINS(229);
583
+
DECLARE_MSM_GPIO_PINS(230);
584
+
DECLARE_MSM_GPIO_PINS(231);
585
+
DECLARE_MSM_GPIO_PINS(232);
586
+
DECLARE_MSM_GPIO_PINS(233);
587
+
DECLARE_MSM_GPIO_PINS(234);
588
+
DECLARE_MSM_GPIO_PINS(235);
589
+
DECLARE_MSM_GPIO_PINS(236);
590
+
DECLARE_MSM_GPIO_PINS(237);
591
+
592
+
static const unsigned int ufs_reset_pins[] = { 238 };
593
+
static const unsigned int sdc2_clk_pins[] = { 239 };
594
+
static const unsigned int sdc2_cmd_pins[] = { 240 };
595
+
static const unsigned int sdc2_data_pins[] = { 241 };
596
+
597
+
enum x1e80100_functions {
598
+
msm_mux_gpio,
599
+
msm_mux_RESOUT_GPIO,
600
+
msm_mux_aon_cci,
601
+
msm_mux_aoss_cti,
602
+
msm_mux_atest_char,
603
+
msm_mux_atest_char0,
604
+
msm_mux_atest_char1,
605
+
msm_mux_atest_char2,
606
+
msm_mux_atest_char3,
607
+
msm_mux_atest_usb,
608
+
msm_mux_audio_ext,
609
+
msm_mux_audio_ref,
610
+
msm_mux_cam_aon,
611
+
msm_mux_cam_mclk,
612
+
msm_mux_cci_async,
613
+
msm_mux_cci_i2c,
614
+
msm_mux_cci_timer0,
615
+
msm_mux_cci_timer1,
616
+
msm_mux_cci_timer2,
617
+
msm_mux_cci_timer3,
618
+
msm_mux_cci_timer4,
619
+
msm_mux_cmu_rng0,
620
+
msm_mux_cmu_rng1,
621
+
msm_mux_cmu_rng2,
622
+
msm_mux_cmu_rng3,
623
+
msm_mux_cri_trng,
624
+
msm_mux_dbg_out,
625
+
msm_mux_ddr_bist,
626
+
msm_mux_ddr_pxi0,
627
+
msm_mux_ddr_pxi1,
628
+
msm_mux_ddr_pxi2,
629
+
msm_mux_ddr_pxi3,
630
+
msm_mux_ddr_pxi4,
631
+
msm_mux_ddr_pxi5,
632
+
msm_mux_ddr_pxi6,
633
+
msm_mux_ddr_pxi7,
634
+
msm_mux_edp0_hot,
635
+
msm_mux_edp0_lcd,
636
+
msm_mux_edp1_hot,
637
+
msm_mux_edp1_lcd,
638
+
msm_mux_eusb0_ac,
639
+
msm_mux_eusb1_ac,
640
+
msm_mux_eusb2_ac,
641
+
msm_mux_eusb3_ac,
642
+
msm_mux_eusb5_ac,
643
+
msm_mux_eusb6_ac,
644
+
msm_mux_gcc_gp1,
645
+
msm_mux_gcc_gp2,
646
+
msm_mux_gcc_gp3,
647
+
msm_mux_i2s0_data0,
648
+
msm_mux_i2s0_data1,
649
+
msm_mux_i2s0_sck,
650
+
msm_mux_i2s0_ws,
651
+
msm_mux_i2s1_data0,
652
+
msm_mux_i2s1_data1,
653
+
msm_mux_i2s1_sck,
654
+
msm_mux_i2s1_ws,
655
+
msm_mux_ibi_i3c,
656
+
msm_mux_jitter_bist,
657
+
msm_mux_mdp_vsync0,
658
+
msm_mux_mdp_vsync1,
659
+
msm_mux_mdp_vsync2,
660
+
msm_mux_mdp_vsync3,
661
+
msm_mux_mdp_vsync4,
662
+
msm_mux_mdp_vsync5,
663
+
msm_mux_mdp_vsync6,
664
+
msm_mux_mdp_vsync7,
665
+
msm_mux_mdp_vsync8,
666
+
msm_mux_pcie3_clk,
667
+
msm_mux_pcie4_clk,
668
+
msm_mux_pcie5_clk,
669
+
msm_mux_pcie6a_clk,
670
+
msm_mux_pcie6b_clk,
671
+
msm_mux_phase_flag,
672
+
msm_mux_pll_bist,
673
+
msm_mux_pll_clk,
674
+
msm_mux_prng_rosc0,
675
+
msm_mux_prng_rosc1,
676
+
msm_mux_prng_rosc2,
677
+
msm_mux_prng_rosc3,
678
+
msm_mux_qdss_cti,
679
+
msm_mux_qdss_gpio,
680
+
msm_mux_qspi00,
681
+
msm_mux_qspi01,
682
+
msm_mux_qspi02,
683
+
msm_mux_qspi03,
684
+
msm_mux_qspi0_clk,
685
+
msm_mux_qspi0_cs0,
686
+
msm_mux_qspi0_cs1,
687
+
msm_mux_qup0_se0,
688
+
msm_mux_qup0_se1,
689
+
msm_mux_qup0_se2,
690
+
msm_mux_qup0_se3,
691
+
msm_mux_qup0_se4,
692
+
msm_mux_qup0_se5,
693
+
msm_mux_qup0_se6,
694
+
msm_mux_qup0_se7,
695
+
msm_mux_qup1_se0,
696
+
msm_mux_qup1_se1,
697
+
msm_mux_qup1_se2,
698
+
msm_mux_qup1_se3,
699
+
msm_mux_qup1_se4,
700
+
msm_mux_qup1_se5,
701
+
msm_mux_qup1_se6,
702
+
msm_mux_qup1_se7,
703
+
msm_mux_qup2_se0,
704
+
msm_mux_qup2_se1,
705
+
msm_mux_qup2_se2,
706
+
msm_mux_qup2_se3,
707
+
msm_mux_qup2_se4,
708
+
msm_mux_qup2_se5,
709
+
msm_mux_qup2_se6,
710
+
msm_mux_qup2_se7,
711
+
msm_mux_sd_write,
712
+
msm_mux_sdc4_clk,
713
+
msm_mux_sdc4_cmd,
714
+
msm_mux_sdc4_data0,
715
+
msm_mux_sdc4_data1,
716
+
msm_mux_sdc4_data2,
717
+
msm_mux_sdc4_data3,
718
+
msm_mux_sys_throttle,
719
+
msm_mux_tb_trig,
720
+
msm_mux_tgu_ch0,
721
+
msm_mux_tgu_ch1,
722
+
msm_mux_tgu_ch2,
723
+
msm_mux_tgu_ch3,
724
+
msm_mux_tgu_ch4,
725
+
msm_mux_tgu_ch5,
726
+
msm_mux_tgu_ch6,
727
+
msm_mux_tgu_ch7,
728
+
msm_mux_tmess_prng0,
729
+
msm_mux_tmess_prng1,
730
+
msm_mux_tmess_prng2,
731
+
msm_mux_tmess_prng3,
732
+
msm_mux_tsense_pwm1,
733
+
msm_mux_tsense_pwm2,
734
+
msm_mux_tsense_pwm3,
735
+
msm_mux_tsense_pwm4,
736
+
msm_mux_usb0_dp,
737
+
msm_mux_usb0_phy,
738
+
msm_mux_usb0_sbrx,
739
+
msm_mux_usb0_sbtx,
740
+
msm_mux_usb1_dp,
741
+
msm_mux_usb1_phy,
742
+
msm_mux_usb1_sbrx,
743
+
msm_mux_usb1_sbtx,
744
+
msm_mux_usb2_dp,
745
+
msm_mux_usb2_phy,
746
+
msm_mux_usb2_sbrx,
747
+
msm_mux_usb2_sbtx,
748
+
msm_mux_vsense_trigger,
749
+
msm_mux__,
750
+
};
751
+
752
+
static const char * const gpio_groups[] = {
753
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
754
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
755
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
756
+
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
757
+
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
758
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
759
+
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
760
+
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
761
+
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
762
+
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
763
+
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
764
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
765
+
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
766
+
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
767
+
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
768
+
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
769
+
"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
770
+
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
771
+
"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
772
+
"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
773
+
"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
774
+
"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
775
+
"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
776
+
"gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
777
+
"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
778
+
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
779
+
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
780
+
"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
781
+
"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
782
+
"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
783
+
"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
784
+
"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
785
+
"gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212",
786
+
"gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218",
787
+
"gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224",
788
+
"gpio225", "gpio226", "gpio227", "gpio228", "gpio229", "gpio230",
789
+
"gpio231", "gpio232", "gpio233", "gpio234", "gpio235", "gpio236",
790
+
"gpio237",
791
+
};
792
+
793
+
static const char * const RESOUT_GPIO_groups[] = {
794
+
"gpio160",
795
+
};
796
+
797
+
static const char * const aon_cci_groups[] = {
798
+
"gpio235", "gpio236",
799
+
};
800
+
801
+
static const char * const aoss_cti_groups[] = {
802
+
"gpio60", "gpio61", "gpio62", "gpio63",
803
+
};
804
+
805
+
static const char * const atest_char_groups[] = {
806
+
"gpio181",
807
+
};
808
+
809
+
static const char * const atest_char0_groups[] = {
810
+
"gpio185",
811
+
};
812
+
813
+
static const char * const atest_char1_groups[] = {
814
+
"gpio184",
815
+
};
816
+
817
+
static const char * const atest_char2_groups[] = {
818
+
"gpio188",
819
+
};
820
+
821
+
static const char * const atest_char3_groups[] = {
822
+
"gpio182",
823
+
};
824
+
825
+
static const char * const atest_usb_groups[] = {
826
+
"gpio9", "gpio10", "gpio35", "gpio38", "gpio41", "gpio42",
827
+
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
828
+
"gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54",
829
+
"gpio58", "gpio59", "gpio65", "gpio66", "gpio67", "gpio72",
830
+
"gpio73", "gpio74", "gpio75", "gpio80", "gpio81", "gpio83",
831
+
};
832
+
833
+
static const char * const audio_ext_groups[] = {
834
+
"gpio134", "gpio142",
835
+
};
836
+
837
+
static const char * const audio_ref_groups[] = {
838
+
"gpio142",
839
+
};
840
+
841
+
static const char * const cam_aon_groups[] = {
842
+
"gpio100",
843
+
};
844
+
845
+
static const char * const cam_mclk_groups[] = {
846
+
"gpio96", "gpio97", "gpio98", "gpio99",
847
+
};
848
+
849
+
static const char * const cci_async_groups[] = {
850
+
"gpio111", "gpio112", "gpio113",
851
+
};
852
+
853
+
static const char * const cci_i2c_groups[] = {
854
+
"gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
855
+
};
856
+
857
+
static const char * const cci_timer0_groups[] = {
858
+
"gpio109",
859
+
};
860
+
861
+
static const char * const cci_timer1_groups[] = {
862
+
"gpio110",
863
+
};
864
+
865
+
static const char * const cci_timer2_groups[] = {
866
+
"gpio111",
867
+
};
868
+
869
+
static const char * const cci_timer3_groups[] = {
870
+
"gpio112",
871
+
};
872
+
873
+
static const char * const cci_timer4_groups[] = {
874
+
"gpio113",
875
+
};
876
+
877
+
static const char * const cmu_rng0_groups[] = {
878
+
"gpio48",
879
+
};
880
+
881
+
static const char * const cmu_rng1_groups[] = {
882
+
"gpio47",
883
+
};
884
+
885
+
static const char * const cmu_rng2_groups[] = {
886
+
"gpio46",
887
+
};
888
+
889
+
static const char * const cmu_rng3_groups[] = {
890
+
"gpio45",
891
+
};
892
+
893
+
static const char * const cri_trng_groups[] = {
894
+
"gpio187",
895
+
};
896
+
897
+
static const char * const dbg_out_groups[] = {
898
+
"gpio51",
899
+
};
900
+
901
+
static const char * const ddr_bist_groups[] = {
902
+
"gpio54", "gpio55", "gpio56", "gpio57",
903
+
};
904
+
905
+
static const char * const ddr_pxi0_groups[] = {
906
+
"gpio9", "gpio38",
907
+
};
908
+
909
+
static const char * const ddr_pxi1_groups[] = {
910
+
"gpio10", "gpio41",
911
+
};
912
+
913
+
static const char * const ddr_pxi2_groups[] = {
914
+
"gpio42", "gpio43",
915
+
};
916
+
917
+
static const char * const ddr_pxi3_groups[] = {
918
+
"gpio44", "gpio45",
919
+
};
920
+
921
+
static const char * const ddr_pxi4_groups[] = {
922
+
"gpio46", "gpio47",
923
+
};
924
+
925
+
static const char * const ddr_pxi5_groups[] = {
926
+
"gpio48", "gpio49",
927
+
};
928
+
929
+
static const char * const ddr_pxi6_groups[] = {
930
+
"gpio50", "gpio51",
931
+
};
932
+
933
+
static const char * const ddr_pxi7_groups[] = {
934
+
"gpio52", "gpio53",
935
+
};
936
+
937
+
static const char * const edp0_hot_groups[] = {
938
+
"gpio119",
939
+
};
940
+
941
+
static const char * const edp0_lcd_groups[] = {
942
+
"gpio120",
943
+
};
944
+
945
+
static const char * const edp1_hot_groups[] = {
946
+
"gpio120",
947
+
};
948
+
949
+
static const char * const edp1_lcd_groups[] = {
950
+
"gpio115", "gpio119",
951
+
};
952
+
953
+
static const char * const eusb0_ac_groups[] = {
954
+
"gpio168",
955
+
};
956
+
957
+
static const char * const eusb1_ac_groups[] = {
958
+
"gpio177",
959
+
};
960
+
961
+
static const char * const eusb2_ac_groups[] = {
962
+
"gpio186",
963
+
};
964
+
965
+
static const char * const eusb3_ac_groups[] = {
966
+
"gpio169",
967
+
};
968
+
969
+
static const char * const eusb5_ac_groups[] = {
970
+
"gpio187",
971
+
};
972
+
973
+
static const char * const eusb6_ac_groups[] = {
974
+
"gpio178",
975
+
};
976
+
977
+
static const char * const gcc_gp1_groups[] = {
978
+
"gpio71", "gpio72",
979
+
};
980
+
981
+
static const char * const gcc_gp2_groups[] = {
982
+
"gpio64", "gpio73",
983
+
};
984
+
985
+
static const char * const gcc_gp3_groups[] = {
986
+
"gpio74", "gpio82",
987
+
};
988
+
989
+
static const char * const i2s0_data0_groups[] = {
990
+
"gpio136",
991
+
};
992
+
993
+
static const char * const i2s0_data1_groups[] = {
994
+
"gpio137",
995
+
};
996
+
997
+
static const char * const i2s0_sck_groups[] = {
998
+
"gpio135",
999
+
};
1000
+
1001
+
static const char * const i2s0_ws_groups[] = {
1002
+
"gpio138",
1003
+
};
1004
+
1005
+
static const char * const i2s1_data0_groups[] = {
1006
+
"gpio140",
1007
+
};
1008
+
1009
+
static const char * const i2s1_data1_groups[] = {
1010
+
"gpio142",
1011
+
};
1012
+
1013
+
static const char * const i2s1_sck_groups[] = {
1014
+
"gpio139",
1015
+
};
1016
+
1017
+
static const char * const i2s1_ws_groups[] = {
1018
+
"gpio141",
1019
+
};
1020
+
1021
+
static const char * const ibi_i3c_groups[] = {
1022
+
"gpio0", "gpio1", "gpio32", "gpio33", "gpio36", "gpio37", "gpio68",
1023
+
"gpio69",
1024
+
};
1025
+
1026
+
static const char * const jitter_bist_groups[] = {
1027
+
"gpio42",
1028
+
};
1029
+
1030
+
static const char * const mdp_vsync0_groups[] = {
1031
+
"gpio114",
1032
+
};
1033
+
1034
+
static const char * const mdp_vsync1_groups[] = {
1035
+
"gpio114",
1036
+
};
1037
+
1038
+
static const char * const mdp_vsync2_groups[] = {
1039
+
"gpio115",
1040
+
};
1041
+
1042
+
static const char * const mdp_vsync3_groups[] = {
1043
+
"gpio115",
1044
+
};
1045
+
1046
+
static const char * const mdp_vsync4_groups[] = {
1047
+
"gpio109",
1048
+
};
1049
+
1050
+
static const char * const mdp_vsync5_groups[] = {
1051
+
"gpio110",
1052
+
};
1053
+
1054
+
static const char * const mdp_vsync6_groups[] = {
1055
+
"gpio111",
1056
+
};
1057
+
1058
+
static const char * const mdp_vsync7_groups[] = {
1059
+
"gpio112",
1060
+
};
1061
+
1062
+
static const char * const mdp_vsync8_groups[] = {
1063
+
"gpio113",
1064
+
};
1065
+
1066
+
static const char * const pcie3_clk_groups[] = {
1067
+
"gpio144",
1068
+
};
1069
+
1070
+
static const char * const pcie4_clk_groups[] = {
1071
+
"gpio147",
1072
+
};
1073
+
1074
+
static const char * const pcie5_clk_groups[] = {
1075
+
"gpio150",
1076
+
};
1077
+
1078
+
static const char * const pcie6a_clk_groups[] = {
1079
+
"gpio153",
1080
+
};
1081
+
1082
+
static const char * const pcie6b_clk_groups[] = {
1083
+
"gpio156",
1084
+
};
1085
+
1086
+
static const char * const phase_flag_groups[] = {
1087
+
"gpio6", "gpio7", "gpio8", "gpio11", "gpio12", "gpio13",
1088
+
"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
1089
+
"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25",
1090
+
"gpio26", "gpio27", "gpio39", "gpio40", "gpio76", "gpio77",
1091
+
"gpio78", "gpio181", "gpio182", "gpio184", "gpio185",
1092
+
"gpio186", "gpio187", "gpio188",
1093
+
};
1094
+
1095
+
static const char * const pll_bist_groups[] = {
1096
+
"gpio28",
1097
+
};
1098
+
1099
+
static const char * const pll_clk_groups[] = {
1100
+
"gpio35",
1101
+
};
1102
+
1103
+
static const char * const prng_rosc0_groups[] = {
1104
+
"gpio186",
1105
+
};
1106
+
1107
+
static const char * const prng_rosc1_groups[] = {
1108
+
"gpio188",
1109
+
};
1110
+
1111
+
static const char * const prng_rosc2_groups[] = {
1112
+
"gpio182",
1113
+
};
1114
+
1115
+
static const char * const prng_rosc3_groups[] = {
1116
+
"gpio181",
1117
+
};
1118
+
1119
+
static const char * const qdss_cti_groups[] = {
1120
+
"gpio18", "gpio19", "gpio23", "gpio27", "gpio161", "gpio162",
1121
+
"gpio215", "gpio217",
1122
+
};
1123
+
1124
+
static const char * const qdss_gpio_groups[] = {
1125
+
"gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
1126
+
"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
1127
+
"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
1128
+
"gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224",
1129
+
"gpio225", "gpio226", "gpio227", "gpio228", "gpio229", "gpio230",
1130
+
"gpio231", "gpio232", "gpio233", "gpio234", "gpio235", "gpio236",
1131
+
};
1132
+
1133
+
static const char * const qspi00_groups[] = {
1134
+
"gpio128",
1135
+
};
1136
+
1137
+
static const char * const qspi01_groups[] = {
1138
+
"gpio129",
1139
+
};
1140
+
1141
+
static const char * const qspi02_groups[] = {
1142
+
"gpio130",
1143
+
};
1144
+
1145
+
static const char * const qspi03_groups[] = {
1146
+
"gpio131",
1147
+
};
1148
+
1149
+
static const char * const qspi0_clk_groups[] = {
1150
+
"gpio127",
1151
+
};
1152
+
1153
+
static const char * const qspi0_cs0_groups[] = {
1154
+
"gpio132",
1155
+
};
1156
+
1157
+
static const char * const qspi0_cs1_groups[] = {
1158
+
"gpio133",
1159
+
};
1160
+
1161
+
static const char * const qup0_se0_groups[] = {
1162
+
"gpio0", "gpio1", "gpio2", "gpio3",
1163
+
};
1164
+
1165
+
static const char * const qup0_se1_groups[] = {
1166
+
"gpio4", "gpio5", "gpio6", "gpio7",
1167
+
};
1168
+
1169
+
static const char * const qup0_se2_groups[] = {
1170
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio17", "gpio18", "gpio19",
1171
+
};
1172
+
1173
+
static const char * const qup0_se3_groups[] = {
1174
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio21", "gpio22", "gpio23",
1175
+
};
1176
+
1177
+
static const char * const qup0_se4_groups[] = {
1178
+
"gpio16", "gpio17", "gpio18", "gpio19",
1179
+
};
1180
+
1181
+
static const char * const qup0_se5_groups[] = {
1182
+
"gpio20", "gpio21", "gpio22", "gpio23",
1183
+
};
1184
+
1185
+
static const char * const qup0_se6_groups[] = {
1186
+
"gpio24", "gpio25", "gpio26", "gpio27",
1187
+
};
1188
+
1189
+
static const char * const qup0_se7_groups[] = {
1190
+
"gpio12", "gpio13", "gpio14", "gpio15",
1191
+
};
1192
+
1193
+
static const char * const qup1_se0_groups[] = {
1194
+
"gpio32", "gpio33", "gpio34", "gpio35",
1195
+
};
1196
+
1197
+
static const char * const qup1_se1_groups[] = {
1198
+
"gpio36", "gpio37", "gpio38", "gpio39",
1199
+
};
1200
+
1201
+
static const char * const qup1_se2_groups[] = {
1202
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio49", "gpio50", "gpio51",
1203
+
};
1204
+
1205
+
static const char * const qup1_se3_groups[] = {
1206
+
"gpio33", "gpio34", "gpio35", "gpio44", "gpio45", "gpio46", "gpio47",
1207
+
};
1208
+
1209
+
static const char * const qup1_se4_groups[] = {
1210
+
"gpio48", "gpio49", "gpio50", "gpio51",
1211
+
};
1212
+
1213
+
static const char * const qup1_se5_groups[] = {
1214
+
"gpio52", "gpio53", "gpio54", "gpio55",
1215
+
};
1216
+
1217
+
static const char * const qup1_se6_groups[] = {
1218
+
"gpio56", "gpio57", "gpio58", "gpio59",
1219
+
};
1220
+
1221
+
static const char * const qup1_se7_groups[] = {
1222
+
"gpio52", "gpio53", "gpio54", "gpio55",
1223
+
};
1224
+
1225
+
static const char * const qup2_se0_groups[] = {
1226
+
"gpio64", "gpio65", "gpio66", "gpio67",
1227
+
};
1228
+
1229
+
static const char * const qup2_se1_groups[] = {
1230
+
"gpio68", "gpio69", "gpio70", "gpio71",
1231
+
};
1232
+
1233
+
static const char * const qup2_se2_groups[] = {
1234
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio81", "gpio82", "gpio83",
1235
+
};
1236
+
1237
+
static const char * const qup2_se3_groups[] = {
1238
+
"gpio65", "gpio66", "gpio67", "gpio76", "gpio77", "gpio78", "gpio79",
1239
+
};
1240
+
1241
+
static const char * const qup2_se4_groups[] = {
1242
+
"gpio80", "gpio81", "gpio82", "gpio83",
1243
+
};
1244
+
1245
+
static const char * const qup2_se5_groups[] = {
1246
+
"gpio84", "gpio85", "gpio86", "gpio87",
1247
+
};
1248
+
1249
+
static const char * const qup2_se6_groups[] = {
1250
+
"gpio88", "gpio89", "gpio90", "gpio91",
1251
+
};
1252
+
1253
+
static const char * const qup2_se7_groups[] = {
1254
+
"gpio84", "gpio85", "gpio86", "gpio87",
1255
+
};
1256
+
1257
+
static const char * const sd_write_groups[] = {
1258
+
"gpio162",
1259
+
};
1260
+
1261
+
static const char * const sdc4_clk_groups[] = {
1262
+
"gpio127",
1263
+
};
1264
+
1265
+
static const char * const sdc4_cmd_groups[] = {
1266
+
"gpio132",
1267
+
};
1268
+
1269
+
static const char * const sdc4_data0_groups[] = {
1270
+
"gpio128",
1271
+
};
1272
+
1273
+
static const char * const sdc4_data1_groups[] = {
1274
+
"gpio129",
1275
+
};
1276
+
1277
+
static const char * const sdc4_data2_groups[] = {
1278
+
"gpio130",
1279
+
};
1280
+
1281
+
static const char * const sdc4_data3_groups[] = {
1282
+
"gpio131",
1283
+
};
1284
+
1285
+
static const char * const sys_throttle_groups[] = {
1286
+
"gpio39", "gpio94",
1287
+
};
1288
+
1289
+
static const char * const tb_trig_groups[] = {
1290
+
"gpio133", "gpio137",
1291
+
};
1292
+
1293
+
static const char * const tgu_ch0_groups[] = {
1294
+
"gpio81",
1295
+
};
1296
+
1297
+
static const char * const tgu_ch1_groups[] = {
1298
+
"gpio65",
1299
+
};
1300
+
1301
+
static const char * const tgu_ch2_groups[] = {
1302
+
"gpio66",
1303
+
};
1304
+
1305
+
static const char * const tgu_ch3_groups[] = {
1306
+
"gpio67",
1307
+
};
1308
+
1309
+
static const char * const tgu_ch4_groups[] = {
1310
+
"gpio68",
1311
+
};
1312
+
1313
+
static const char * const tgu_ch5_groups[] = {
1314
+
"gpio69",
1315
+
};
1316
+
1317
+
static const char * const tgu_ch6_groups[] = {
1318
+
"gpio83",
1319
+
};
1320
+
1321
+
static const char * const tgu_ch7_groups[] = {
1322
+
"gpio80",
1323
+
};
1324
+
1325
+
static const char * const tmess_prng0_groups[] = {
1326
+
"gpio92",
1327
+
};
1328
+
1329
+
static const char * const tmess_prng1_groups[] = {
1330
+
"gpio93",
1331
+
};
1332
+
1333
+
static const char * const tmess_prng2_groups[] = {
1334
+
"gpio94",
1335
+
};
1336
+
1337
+
static const char * const tmess_prng3_groups[] = {
1338
+
"gpio95",
1339
+
};
1340
+
1341
+
static const char * const tsense_pwm1_groups[] = {
1342
+
"gpio34",
1343
+
};
1344
+
1345
+
static const char * const tsense_pwm2_groups[] = {
1346
+
"gpio34",
1347
+
};
1348
+
1349
+
static const char * const tsense_pwm3_groups[] = {
1350
+
"gpio34",
1351
+
};
1352
+
1353
+
static const char * const tsense_pwm4_groups[] = {
1354
+
"gpio34",
1355
+
};
1356
+
1357
+
static const char * const usb0_dp_groups[] = {
1358
+
"gpio122",
1359
+
};
1360
+
1361
+
static const char * const usb0_phy_groups[] = {
1362
+
"gpio121",
1363
+
};
1364
+
1365
+
static const char * const usb0_sbrx_groups[] = {
1366
+
"gpio163",
1367
+
};
1368
+
1369
+
static const char * const usb0_sbtx_groups[] = {
1370
+
"gpio164", "gpio165",
1371
+
};
1372
+
1373
+
static const char * const usb1_dp_groups[] = {
1374
+
"gpio124",
1375
+
};
1376
+
1377
+
static const char * const usb1_phy_groups[] = {
1378
+
"gpio123",
1379
+
};
1380
+
1381
+
static const char * const usb1_sbrx_groups[] = {
1382
+
"gpio172",
1383
+
};
1384
+
1385
+
static const char * const usb1_sbtx_groups[] = {
1386
+
"gpio173", "gpio174",
1387
+
};
1388
+
1389
+
static const char * const usb2_dp_groups[] = {
1390
+
"gpio126",
1391
+
};
1392
+
1393
+
static const char * const usb2_phy_groups[] = {
1394
+
"gpio125",
1395
+
};
1396
+
1397
+
static const char * const usb2_sbrx_groups[] = {
1398
+
"gpio181",
1399
+
};
1400
+
1401
+
static const char * const usb2_sbtx_groups[] = {
1402
+
"gpio182", "gpio183",
1403
+
};
1404
+
1405
+
static const char * const vsense_trigger_groups[] = {
1406
+
"gpio38",
1407
+
};
1408
+
1409
+
static const struct pinfunction x1e80100_functions[] = {
1410
+
MSM_PIN_FUNCTION(gpio),
1411
+
MSM_PIN_FUNCTION(RESOUT_GPIO),
1412
+
MSM_PIN_FUNCTION(aon_cci),
1413
+
MSM_PIN_FUNCTION(aoss_cti),
1414
+
MSM_PIN_FUNCTION(atest_char),
1415
+
MSM_PIN_FUNCTION(atest_char0),
1416
+
MSM_PIN_FUNCTION(atest_char1),
1417
+
MSM_PIN_FUNCTION(atest_char2),
1418
+
MSM_PIN_FUNCTION(atest_char3),
1419
+
MSM_PIN_FUNCTION(atest_usb),
1420
+
MSM_PIN_FUNCTION(audio_ext),
1421
+
MSM_PIN_FUNCTION(audio_ref),
1422
+
MSM_PIN_FUNCTION(cam_aon),
1423
+
MSM_PIN_FUNCTION(cam_mclk),
1424
+
MSM_PIN_FUNCTION(cci_async),
1425
+
MSM_PIN_FUNCTION(cci_i2c),
1426
+
MSM_PIN_FUNCTION(cci_timer0),
1427
+
MSM_PIN_FUNCTION(cci_timer1),
1428
+
MSM_PIN_FUNCTION(cci_timer2),
1429
+
MSM_PIN_FUNCTION(cci_timer3),
1430
+
MSM_PIN_FUNCTION(cci_timer4),
1431
+
MSM_PIN_FUNCTION(cmu_rng0),
1432
+
MSM_PIN_FUNCTION(cmu_rng1),
1433
+
MSM_PIN_FUNCTION(cmu_rng2),
1434
+
MSM_PIN_FUNCTION(cmu_rng3),
1435
+
MSM_PIN_FUNCTION(cri_trng),
1436
+
MSM_PIN_FUNCTION(dbg_out),
1437
+
MSM_PIN_FUNCTION(ddr_bist),
1438
+
MSM_PIN_FUNCTION(ddr_pxi0),
1439
+
MSM_PIN_FUNCTION(ddr_pxi1),
1440
+
MSM_PIN_FUNCTION(ddr_pxi2),
1441
+
MSM_PIN_FUNCTION(ddr_pxi3),
1442
+
MSM_PIN_FUNCTION(ddr_pxi4),
1443
+
MSM_PIN_FUNCTION(ddr_pxi5),
1444
+
MSM_PIN_FUNCTION(ddr_pxi6),
1445
+
MSM_PIN_FUNCTION(ddr_pxi7),
1446
+
MSM_PIN_FUNCTION(edp0_hot),
1447
+
MSM_PIN_FUNCTION(edp0_lcd),
1448
+
MSM_PIN_FUNCTION(edp1_hot),
1449
+
MSM_PIN_FUNCTION(edp1_lcd),
1450
+
MSM_PIN_FUNCTION(eusb0_ac),
1451
+
MSM_PIN_FUNCTION(eusb1_ac),
1452
+
MSM_PIN_FUNCTION(eusb2_ac),
1453
+
MSM_PIN_FUNCTION(eusb3_ac),
1454
+
MSM_PIN_FUNCTION(eusb5_ac),
1455
+
MSM_PIN_FUNCTION(eusb6_ac),
1456
+
MSM_PIN_FUNCTION(gcc_gp1),
1457
+
MSM_PIN_FUNCTION(gcc_gp2),
1458
+
MSM_PIN_FUNCTION(gcc_gp3),
1459
+
MSM_PIN_FUNCTION(i2s0_data0),
1460
+
MSM_PIN_FUNCTION(i2s0_data1),
1461
+
MSM_PIN_FUNCTION(i2s0_sck),
1462
+
MSM_PIN_FUNCTION(i2s0_ws),
1463
+
MSM_PIN_FUNCTION(i2s1_data0),
1464
+
MSM_PIN_FUNCTION(i2s1_data1),
1465
+
MSM_PIN_FUNCTION(i2s1_sck),
1466
+
MSM_PIN_FUNCTION(i2s1_ws),
1467
+
MSM_PIN_FUNCTION(ibi_i3c),
1468
+
MSM_PIN_FUNCTION(jitter_bist),
1469
+
MSM_PIN_FUNCTION(mdp_vsync0),
1470
+
MSM_PIN_FUNCTION(mdp_vsync1),
1471
+
MSM_PIN_FUNCTION(mdp_vsync2),
1472
+
MSM_PIN_FUNCTION(mdp_vsync3),
1473
+
MSM_PIN_FUNCTION(mdp_vsync4),
1474
+
MSM_PIN_FUNCTION(mdp_vsync5),
1475
+
MSM_PIN_FUNCTION(mdp_vsync6),
1476
+
MSM_PIN_FUNCTION(mdp_vsync7),
1477
+
MSM_PIN_FUNCTION(mdp_vsync8),
1478
+
MSM_PIN_FUNCTION(pcie3_clk),
1479
+
MSM_PIN_FUNCTION(pcie4_clk),
1480
+
MSM_PIN_FUNCTION(pcie5_clk),
1481
+
MSM_PIN_FUNCTION(pcie6a_clk),
1482
+
MSM_PIN_FUNCTION(pcie6b_clk),
1483
+
MSM_PIN_FUNCTION(phase_flag),
1484
+
MSM_PIN_FUNCTION(pll_bist),
1485
+
MSM_PIN_FUNCTION(pll_clk),
1486
+
MSM_PIN_FUNCTION(prng_rosc0),
1487
+
MSM_PIN_FUNCTION(prng_rosc1),
1488
+
MSM_PIN_FUNCTION(prng_rosc2),
1489
+
MSM_PIN_FUNCTION(prng_rosc3),
1490
+
MSM_PIN_FUNCTION(qdss_cti),
1491
+
MSM_PIN_FUNCTION(qdss_gpio),
1492
+
MSM_PIN_FUNCTION(qspi00),
1493
+
MSM_PIN_FUNCTION(qspi01),
1494
+
MSM_PIN_FUNCTION(qspi02),
1495
+
MSM_PIN_FUNCTION(qspi03),
1496
+
MSM_PIN_FUNCTION(qspi0_clk),
1497
+
MSM_PIN_FUNCTION(qspi0_cs0),
1498
+
MSM_PIN_FUNCTION(qspi0_cs1),
1499
+
MSM_PIN_FUNCTION(qup0_se0),
1500
+
MSM_PIN_FUNCTION(qup0_se1),
1501
+
MSM_PIN_FUNCTION(qup0_se2),
1502
+
MSM_PIN_FUNCTION(qup0_se3),
1503
+
MSM_PIN_FUNCTION(qup0_se4),
1504
+
MSM_PIN_FUNCTION(qup0_se5),
1505
+
MSM_PIN_FUNCTION(qup0_se6),
1506
+
MSM_PIN_FUNCTION(qup0_se7),
1507
+
MSM_PIN_FUNCTION(qup1_se0),
1508
+
MSM_PIN_FUNCTION(qup1_se1),
1509
+
MSM_PIN_FUNCTION(qup1_se2),
1510
+
MSM_PIN_FUNCTION(qup1_se3),
1511
+
MSM_PIN_FUNCTION(qup1_se4),
1512
+
MSM_PIN_FUNCTION(qup1_se5),
1513
+
MSM_PIN_FUNCTION(qup1_se6),
1514
+
MSM_PIN_FUNCTION(qup1_se7),
1515
+
MSM_PIN_FUNCTION(qup2_se0),
1516
+
MSM_PIN_FUNCTION(qup2_se1),
1517
+
MSM_PIN_FUNCTION(qup2_se2),
1518
+
MSM_PIN_FUNCTION(qup2_se3),
1519
+
MSM_PIN_FUNCTION(qup2_se4),
1520
+
MSM_PIN_FUNCTION(qup2_se5),
1521
+
MSM_PIN_FUNCTION(qup2_se6),
1522
+
MSM_PIN_FUNCTION(qup2_se7),
1523
+
MSM_PIN_FUNCTION(sd_write),
1524
+
MSM_PIN_FUNCTION(sdc4_clk),
1525
+
MSM_PIN_FUNCTION(sdc4_cmd),
1526
+
MSM_PIN_FUNCTION(sdc4_data0),
1527
+
MSM_PIN_FUNCTION(sdc4_data1),
1528
+
MSM_PIN_FUNCTION(sdc4_data2),
1529
+
MSM_PIN_FUNCTION(sdc4_data3),
1530
+
MSM_PIN_FUNCTION(sys_throttle),
1531
+
MSM_PIN_FUNCTION(tb_trig),
1532
+
MSM_PIN_FUNCTION(tgu_ch0),
1533
+
MSM_PIN_FUNCTION(tgu_ch1),
1534
+
MSM_PIN_FUNCTION(tgu_ch2),
1535
+
MSM_PIN_FUNCTION(tgu_ch3),
1536
+
MSM_PIN_FUNCTION(tgu_ch4),
1537
+
MSM_PIN_FUNCTION(tgu_ch5),
1538
+
MSM_PIN_FUNCTION(tgu_ch6),
1539
+
MSM_PIN_FUNCTION(tgu_ch7),
1540
+
MSM_PIN_FUNCTION(tmess_prng0),
1541
+
MSM_PIN_FUNCTION(tmess_prng1),
1542
+
MSM_PIN_FUNCTION(tmess_prng2),
1543
+
MSM_PIN_FUNCTION(tmess_prng3),
1544
+
MSM_PIN_FUNCTION(tsense_pwm1),
1545
+
MSM_PIN_FUNCTION(tsense_pwm2),
1546
+
MSM_PIN_FUNCTION(tsense_pwm3),
1547
+
MSM_PIN_FUNCTION(tsense_pwm4),
1548
+
MSM_PIN_FUNCTION(usb0_dp),
1549
+
MSM_PIN_FUNCTION(usb0_phy),
1550
+
MSM_PIN_FUNCTION(usb0_sbrx),
1551
+
MSM_PIN_FUNCTION(usb0_sbtx),
1552
+
MSM_PIN_FUNCTION(usb1_dp),
1553
+
MSM_PIN_FUNCTION(usb1_phy),
1554
+
MSM_PIN_FUNCTION(usb1_sbrx),
1555
+
MSM_PIN_FUNCTION(usb1_sbtx),
1556
+
MSM_PIN_FUNCTION(usb2_dp),
1557
+
MSM_PIN_FUNCTION(usb2_phy),
1558
+
MSM_PIN_FUNCTION(usb2_sbrx),
1559
+
MSM_PIN_FUNCTION(usb2_sbtx),
1560
+
MSM_PIN_FUNCTION(vsense_trigger),
1561
+
};
1562
+
1563
+
/*
1564
+
* Every pin is maintained as a single group, and missing or non-existing pin
1565
+
* would be maintained as dummy group to synchronize pin group index with
1566
+
* pin descriptor registered with pinctrl core.
1567
+
* Clients would not be able to request these dummy pin groups.
1568
+
*/
1569
+
static const struct msm_pingroup x1e80100_groups[] = {
1570
+
[0] = PINGROUP(0, qup0_se0, ibi_i3c, _, _, _, _, _, _, _),
1571
+
[1] = PINGROUP(1, qup0_se0, ibi_i3c, _, _, _, _, _, _, _),
1572
+
[2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _),
1573
+
[3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _),
1574
+
[4] = PINGROUP(4, qup0_se1, _, _, _, _, _, _, _, _),
1575
+
[5] = PINGROUP(5, qup0_se1, _, _, _, _, _, _, _, _),
1576
+
[6] = PINGROUP(6, qup0_se1, phase_flag, _, _, _, _, _, _, _),
1577
+
[7] = PINGROUP(7, qup0_se1, phase_flag, _, _, _, _, _, _, _),
1578
+
[8] = PINGROUP(8, qup0_se2, phase_flag, _, _, _, _, _, _, _),
1579
+
[9] = PINGROUP(9, qup0_se2, _, atest_usb, ddr_pxi0, _, _, _, _, _),
1580
+
[10] = PINGROUP(10, qup0_se2, _, atest_usb, ddr_pxi1, _, _, _, _, _),
1581
+
[11] = PINGROUP(11, qup0_se2, phase_flag, _, _, _, _, _, _, _),
1582
+
[12] = PINGROUP(12, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _),
1583
+
[13] = PINGROUP(13, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _),
1584
+
[14] = PINGROUP(14, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _),
1585
+
[15] = PINGROUP(15, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _),
1586
+
[16] = PINGROUP(16, qup0_se4, phase_flag, _, _, _, _, _, _, _),
1587
+
[17] = PINGROUP(17, qup0_se4, qup0_se2, phase_flag, _, _, _, _, _, _),
1588
+
[18] = PINGROUP(18, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _),
1589
+
[19] = PINGROUP(19, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _),
1590
+
[20] = PINGROUP(20, qup0_se5, _, phase_flag, _, _, _, _, _, _),
1591
+
[21] = PINGROUP(21, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _),
1592
+
[22] = PINGROUP(22, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _),
1593
+
[23] = PINGROUP(23, qup0_se5, qup0_se3, phase_flag, _, qdss_cti, _, _, _, _),
1594
+
[24] = PINGROUP(24, qup0_se6, phase_flag, _, _, _, _, _, _, _),
1595
+
[25] = PINGROUP(25, qup0_se6, phase_flag, _, _, _, _, _, _, _),
1596
+
[26] = PINGROUP(26, qup0_se6, phase_flag, _, _, _, _, _, _, _),
1597
+
[27] = PINGROUP(27, qup0_se6, phase_flag, _, qdss_cti, _, _, _, _, _),
1598
+
[28] = PINGROUP(28, pll_bist, _, _, _, _, _, _, _, _),
1599
+
[29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
1600
+
[30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
1601
+
[31] = PINGROUP(31, _, _, _, _, _, _, _, _, _),
1602
+
[32] = PINGROUP(32, qup1_se0, ibi_i3c, _, _, _, _, _, _, _),
1603
+
[33] = PINGROUP(33, qup1_se0, ibi_i3c, qup1_se3, _, _, _, _, _, _),
1604
+
[34] = PINGROUP(34, qup1_se0, qup1_se3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _),
1605
+
[35] = PINGROUP(35, qup1_se0, qup1_se3, pll_clk, atest_usb, _, _, _, _, _),
1606
+
[36] = PINGROUP(36, qup1_se1, ibi_i3c, _, _, _, _, _, _, _),
1607
+
[37] = PINGROUP(37, qup1_se1, ibi_i3c, _, _, _, _, _, _, _),
1608
+
[38] = PINGROUP(38, qup1_se1, vsense_trigger, atest_usb, ddr_pxi0, _, _, _, _, _),
1609
+
[39] = PINGROUP(39, qup1_se1, sys_throttle, phase_flag, _, _, _, _, _, _),
1610
+
[40] = PINGROUP(40, qup1_se2, phase_flag, _, _, _, _, _, _, _),
1611
+
[41] = PINGROUP(41, qup1_se2, atest_usb, ddr_pxi1, _, _, _, _, _, _),
1612
+
[42] = PINGROUP(42, qup1_se2, jitter_bist, atest_usb, ddr_pxi2, _, _, _, _, _),
1613
+
[43] = PINGROUP(43, qup1_se2, _, atest_usb, ddr_pxi2, _, _, _, _, _),
1614
+
[44] = PINGROUP(44, qup1_se3, _, atest_usb, ddr_pxi3, _, _, _, _, _),
1615
+
[45] = PINGROUP(45, qup1_se3, cmu_rng3, _, atest_usb, ddr_pxi3, _, _, _, _),
1616
+
[46] = PINGROUP(46, qup1_se3, cmu_rng2, _, atest_usb, ddr_pxi4, _, _, _, _),
1617
+
[47] = PINGROUP(47, qup1_se3, cmu_rng1, _, atest_usb, ddr_pxi4, _, _, _, _),
1618
+
[48] = PINGROUP(48, qup1_se4, cmu_rng0, _, atest_usb, ddr_pxi5, _, _, _, _),
1619
+
[49] = PINGROUP(49, qup1_se4, qup1_se2, _, atest_usb, ddr_pxi5, _, _, _, _),
1620
+
[50] = PINGROUP(50, qup1_se4, qup1_se2, _, atest_usb, ddr_pxi6, _, _, _, _),
1621
+
[51] = PINGROUP(51, qup1_se4, qup1_se2, dbg_out, atest_usb, ddr_pxi6, _, _, _, _),
1622
+
[52] = PINGROUP(52, qup1_se5, qup1_se7, atest_usb, ddr_pxi7, _, _, _, _, _),
1623
+
[53] = PINGROUP(53, qup1_se5, qup1_se7, _, atest_usb, ddr_pxi7, _, _, _, _),
1624
+
[54] = PINGROUP(54, qup1_se5, qup1_se7, ddr_bist, atest_usb, _, _, _, _, _),
1625
+
[55] = PINGROUP(55, qup1_se5, qup1_se7, ddr_bist, _, _, _, _, _, _),
1626
+
[56] = PINGROUP(56, qup1_se6, ddr_bist, _, _, _, _, _, _, _),
1627
+
[57] = PINGROUP(57, qup1_se6, ddr_bist, _, _, _, _, _, _, _),
1628
+
[58] = PINGROUP(58, qup1_se6, atest_usb, _, _, _, _, _, _, _),
1629
+
[59] = PINGROUP(59, qup1_se6, atest_usb, _, _, _, _, _, _, _),
1630
+
[60] = PINGROUP(60, aoss_cti, _, _, _, _, _, _, _, _),
1631
+
[61] = PINGROUP(61, aoss_cti, _, _, _, _, _, _, _, _),
1632
+
[62] = PINGROUP(62, aoss_cti, _, _, _, _, _, _, _, _),
1633
+
[63] = PINGROUP(63, aoss_cti, _, _, _, _, _, _, _, _),
1634
+
[64] = PINGROUP(64, qup2_se0, gcc_gp2, _, _, _, _, _, _, _),
1635
+
[65] = PINGROUP(65, qup2_se0, qup2_se3, tgu_ch1, atest_usb, _, _, _, _, _),
1636
+
[66] = PINGROUP(66, qup2_se0, qup2_se3, tgu_ch2, atest_usb, _, _, _, _, _),
1637
+
[67] = PINGROUP(67, qup2_se0, qup2_se3, tgu_ch3, atest_usb, _, _, _, _, _),
1638
+
[68] = PINGROUP(68, qup2_se1, ibi_i3c, tgu_ch4, _, _, _, _, _, _),
1639
+
[69] = PINGROUP(69, qup2_se1, ibi_i3c, tgu_ch5, _, _, _, _, _, _),
1640
+
[70] = PINGROUP(70, qup2_se1, _, _, _, _, _, _, _, _),
1641
+
[71] = PINGROUP(71, qup2_se1, gcc_gp1, _, _, _, _, _, _, _),
1642
+
[72] = PINGROUP(72, qup2_se2, gcc_gp1, atest_usb, _, _, _, _, _, _),
1643
+
[73] = PINGROUP(73, qup2_se2, gcc_gp2, atest_usb, _, _, _, _, _, _),
1644
+
[74] = PINGROUP(74, qup2_se2, gcc_gp3, atest_usb, _, _, _, _, _, _),
1645
+
[75] = PINGROUP(75, qup2_se2, atest_usb, _, _, _, _, _, _, _),
1646
+
[76] = PINGROUP(76, qup2_se3, phase_flag, _, _, _, _, _, _, _),
1647
+
[77] = PINGROUP(77, qup2_se3, phase_flag, _, _, _, _, _, _, _),
1648
+
[78] = PINGROUP(78, qup2_se3, phase_flag, _, _, _, _, _, _, _),
1649
+
[79] = PINGROUP(79, qup2_se3, _, _, _, _, _, _, _, _),
1650
+
[80] = PINGROUP(80, qup2_se4, tgu_ch7, atest_usb, _, _, _, _, _, _),
1651
+
[81] = PINGROUP(81, qup2_se4, qup2_se2, tgu_ch0, atest_usb, _, _, _, _, _),
1652
+
[82] = PINGROUP(82, qup2_se4, qup2_se2, gcc_gp3, _, _, _, _, _, _),
1653
+
[83] = PINGROUP(83, qup2_se4, qup2_se2, tgu_ch6, atest_usb, _, _, _, _, _),
1654
+
[84] = PINGROUP(84, qup2_se5, qup2_se7, _, _, _, _, _, _, _),
1655
+
[85] = PINGROUP(85, qup2_se5, qup2_se7, _, _, _, _, _, _, _),
1656
+
[86] = PINGROUP(86, qup2_se5, qup2_se7, _, _, _, _, _, _, _),
1657
+
[87] = PINGROUP(87, qup2_se5, qup2_se7, _, _, _, _, _, _, _),
1658
+
[88] = PINGROUP(88, qup2_se6, _, _, _, _, _, _, _, _),
1659
+
[89] = PINGROUP(89, qup2_se6, _, _, _, _, _, _, _, _),
1660
+
[90] = PINGROUP(90, qup2_se6, _, _, _, _, _, _, _, _),
1661
+
[91] = PINGROUP(91, qup2_se6, _, _, _, _, _, _, _, _),
1662
+
[92] = PINGROUP(92, tmess_prng0, _, _, _, _, _, _, _, _),
1663
+
[93] = PINGROUP(93, tmess_prng1, _, _, _, _, _, _, _, _),
1664
+
[94] = PINGROUP(94, sys_throttle, tmess_prng2, _, _, _, _, _, _, _),
1665
+
[95] = PINGROUP(95, tmess_prng3, _, _, _, _, _, _, _, _),
1666
+
[96] = PINGROUP(96, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1667
+
[97] = PINGROUP(97, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1668
+
[98] = PINGROUP(98, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1669
+
[99] = PINGROUP(99, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1670
+
[100] = PINGROUP(100, cam_aon, qdss_gpio, _, _, _, _, _, _, _),
1671
+
[101] = PINGROUP(101, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1672
+
[102] = PINGROUP(102, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1673
+
[103] = PINGROUP(103, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1674
+
[104] = PINGROUP(104, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1675
+
[105] = PINGROUP(105, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1676
+
[106] = PINGROUP(106, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1677
+
[107] = PINGROUP(107, qdss_gpio, _, _, _, _, _, _, _, _),
1678
+
[108] = PINGROUP(108, qdss_gpio, _, _, _, _, _, _, _, _),
1679
+
[109] = PINGROUP(109, cci_timer0, mdp_vsync4, qdss_gpio, _, _, _, _, _, _),
1680
+
[110] = PINGROUP(110, cci_timer1, mdp_vsync5, qdss_gpio, _, _, _, _, _, _),
1681
+
[111] = PINGROUP(111, cci_timer2, cci_async, mdp_vsync6, qdss_gpio, _, _, _, _, _),
1682
+
[112] = PINGROUP(112, cci_timer3, cci_async, mdp_vsync7, qdss_gpio, _, _, _, _, _),
1683
+
[113] = PINGROUP(113, cci_timer4, cci_async, mdp_vsync8, qdss_gpio, _, _, _, _, _),
1684
+
[114] = PINGROUP(114, mdp_vsync0, mdp_vsync1, _, _, _, _, _, _, _),
1685
+
[115] = PINGROUP(115, mdp_vsync3, mdp_vsync2, edp1_lcd, _, _, _, _, _, _),
1686
+
[116] = PINGROUP(116, _, _, _, _, _, _, _, _, _),
1687
+
[117] = PINGROUP(117, _, _, _, _, _, _, _, _, _),
1688
+
[118] = PINGROUP(118, _, _, _, _, _, _, _, _, _),
1689
+
[119] = PINGROUP(119, edp0_hot, edp1_lcd, _, _, _, _, _, _, _),
1690
+
[120] = PINGROUP(120, edp1_hot, edp0_lcd, _, _, _, _, _, _, _),
1691
+
[121] = PINGROUP(121, usb0_phy, _, _, _, _, _, _, _, _),
1692
+
[122] = PINGROUP(122, usb0_dp, _, _, _, _, _, _, _, _),
1693
+
[123] = PINGROUP(123, usb1_phy, _, _, _, _, _, _, _, _),
1694
+
[124] = PINGROUP(124, usb1_dp, _, _, _, _, _, _, _, _),
1695
+
[125] = PINGROUP(125, usb2_phy, _, _, _, _, _, _, _, _),
1696
+
[126] = PINGROUP(126, usb2_dp, _, _, _, _, _, _, _, _),
1697
+
[127] = PINGROUP(127, qspi0_clk, sdc4_clk, _, _, _, _, _, _, _),
1698
+
[128] = PINGROUP(128, qspi00, sdc4_data0, _, _, _, _, _, _, _),
1699
+
[129] = PINGROUP(129, qspi01, sdc4_data1, _, _, _, _, _, _, _),
1700
+
[130] = PINGROUP(130, qspi02, sdc4_data2, _, _, _, _, _, _, _),
1701
+
[131] = PINGROUP(131, qspi03, sdc4_data3, _, _, _, _, _, _, _),
1702
+
[132] = PINGROUP(132, qspi0_cs0, sdc4_cmd, _, _, _, _, _, _, _),
1703
+
[133] = PINGROUP(133, qspi0_cs1, tb_trig, _, _, _, _, _, _, _),
1704
+
[134] = PINGROUP(134, audio_ext, _, _, _, _, _, _, _, _),
1705
+
[135] = PINGROUP(135, i2s0_sck, _, _, _, _, _, _, _, _),
1706
+
[136] = PINGROUP(136, i2s0_data0, _, _, _, _, _, _, _, _),
1707
+
[137] = PINGROUP(137, i2s0_data1, tb_trig, _, _, _, _, _, _, _),
1708
+
[138] = PINGROUP(138, i2s0_ws, _, _, _, _, _, _, _, _),
1709
+
[139] = PINGROUP(139, i2s1_sck, _, _, _, _, _, _, _, _),
1710
+
[140] = PINGROUP(140, i2s1_data0, _, _, _, _, _, _, _, _),
1711
+
[141] = PINGROUP(141, i2s1_ws, _, _, _, _, _, _, _, _),
1712
+
[142] = PINGROUP(142, i2s1_data1, audio_ext, audio_ref, _, _, _, _, _, _),
1713
+
[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
1714
+
[144] = PINGROUP(144, pcie3_clk, _, _, _, _, _, _, _, _),
1715
+
[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
1716
+
[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
1717
+
[147] = PINGROUP(147, pcie4_clk, _, _, _, _, _, _, _, _),
1718
+
[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
1719
+
[149] = PINGROUP(149, _, _, _, _, _, _, _, _, _),
1720
+
[150] = PINGROUP(150, pcie5_clk, _, _, _, _, _, _, _, _),
1721
+
[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _),
1722
+
[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _),
1723
+
[153] = PINGROUP(153, pcie6a_clk, _, _, _, _, _, _, _, _),
1724
+
[154] = PINGROUP(154, _, _, _, _, _, _, _, _, _),
1725
+
[155] = PINGROUP(155, _, _, _, _, _, _, _, _, _),
1726
+
[156] = PINGROUP(156, pcie6b_clk, _, _, _, _, _, _, _, _),
1727
+
[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _),
1728
+
[158] = PINGROUP(158, _, _, _, _, _, _, _, _, _),
1729
+
[159] = PINGROUP(159, _, _, _, _, _, _, _, _, _),
1730
+
[160] = PINGROUP(160, RESOUT_GPIO, _, _, _, _, _, _, _, _),
1731
+
[161] = PINGROUP(161, qdss_cti, _, _, _, _, _, _, _, _),
1732
+
[162] = PINGROUP(162, sd_write, qdss_cti, _, _, _, _, _, _, _),
1733
+
[163] = PINGROUP(163, usb0_sbrx, _, _, _, _, _, _, _, _),
1734
+
[164] = PINGROUP(164, usb0_sbtx, _, _, _, _, _, _, _, _),
1735
+
[165] = PINGROUP(165, usb0_sbtx, _, _, _, _, _, _, _, _),
1736
+
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),
1737
+
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
1738
+
[168] = PINGROUP(168, eusb0_ac, _, _, _, _, _, _, _, _),
1739
+
[169] = PINGROUP(169, eusb3_ac, _, _, _, _, _, _, _, _),
1740
+
[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
1741
+
[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
1742
+
[172] = PINGROUP(172, usb1_sbrx, _, _, _, _, _, _, _, _),
1743
+
[173] = PINGROUP(173, usb1_sbtx, _, _, _, _, _, _, _, _),
1744
+
[174] = PINGROUP(174, usb1_sbtx, _, _, _, _, _, _, _, _),
1745
+
[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),
1746
+
[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),
1747
+
[177] = PINGROUP(177, eusb1_ac, _, _, _, _, _, _, _, _),
1748
+
[178] = PINGROUP(178, eusb6_ac, _, _, _, _, _, _, _, _),
1749
+
[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
1750
+
[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
1751
+
[181] = PINGROUP(181, usb2_sbrx, prng_rosc3, phase_flag, _, atest_char, _, _, _, _),
1752
+
[182] = PINGROUP(182, usb2_sbtx, prng_rosc2, phase_flag, _, atest_char3, _, _, _, _),
1753
+
[183] = PINGROUP(183, usb2_sbtx, _, _, _, _, _, _, _, _),
1754
+
[184] = PINGROUP(184, phase_flag, _, atest_char1, _, _, _, _, _, _),
1755
+
[185] = PINGROUP(185, phase_flag, _, atest_char0, _, _, _, _, _, _),
1756
+
[186] = PINGROUP(186, eusb2_ac, prng_rosc0, phase_flag, _, _, _, _, _, _),
1757
+
[187] = PINGROUP(187, eusb5_ac, cri_trng, phase_flag, _, _, _, _, _, _),
1758
+
[188] = PINGROUP(188, prng_rosc1, phase_flag, _, atest_char2, _, _, _, _, _),
1759
+
[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _),
1760
+
[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _),
1761
+
[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _),
1762
+
[192] = PINGROUP(192, _, _, _, _, _, _, _, _, _),
1763
+
[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _),
1764
+
[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _),
1765
+
[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _),
1766
+
[196] = PINGROUP(196, _, _, _, _, _, _, _, _, _),
1767
+
[197] = PINGROUP(197, _, _, _, _, _, _, _, _, _),
1768
+
[198] = PINGROUP(198, _, _, _, _, _, _, _, _, _),
1769
+
[199] = PINGROUP(199, _, _, _, _, _, _, _, _, _),
1770
+
[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _),
1771
+
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _),
1772
+
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _),
1773
+
[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _),
1774
+
[204] = PINGROUP(204, _, _, _, _, _, _, _, _, _),
1775
+
[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _),
1776
+
[206] = PINGROUP(206, _, _, _, _, _, _, _, _, _),
1777
+
[207] = PINGROUP(207, _, _, _, _, _, _, _, _, _),
1778
+
[208] = PINGROUP(208, _, _, _, _, _, _, _, _, _),
1779
+
[209] = PINGROUP(209, _, _, _, _, _, _, _, _, _),
1780
+
[210] = PINGROUP(210, _, _, _, _, _, _, _, _, _),
1781
+
[211] = PINGROUP(211, _, _, _, _, _, _, _, _, _),
1782
+
[212] = PINGROUP(212, _, _, _, _, _, _, _, _, _),
1783
+
[213] = PINGROUP(213, _, _, _, _, _, _, _, _, _),
1784
+
[214] = PINGROUP(214, _, _, _, _, _, _, _, _, _),
1785
+
[215] = PINGROUP(215, _, qdss_cti, _, _, _, _, _, _, _),
1786
+
[216] = PINGROUP(216, _, _, _, _, _, _, _, _, _),
1787
+
[217] = PINGROUP(217, _, qdss_cti, _, _, _, _, _, _, _),
1788
+
[218] = PINGROUP(218, _, _, _, _, _, _, _, _, _),
1789
+
[219] = PINGROUP(219, _, qdss_gpio, _, _, _, _, _, _, _),
1790
+
[220] = PINGROUP(220, _, qdss_gpio, _, _, _, _, _, _, _),
1791
+
[221] = PINGROUP(221, _, qdss_gpio, _, _, _, _, _, _, _),
1792
+
[222] = PINGROUP(222, _, qdss_gpio, _, _, _, _, _, _, _),
1793
+
[223] = PINGROUP(223, _, qdss_gpio, _, _, _, _, _, _, _),
1794
+
[224] = PINGROUP(224, _, qdss_gpio, _, _, _, _, _, _, _),
1795
+
[225] = PINGROUP(225, _, qdss_gpio, _, _, _, _, _, _, _),
1796
+
[226] = PINGROUP(226, _, qdss_gpio, _, _, _, _, _, _, _),
1797
+
[227] = PINGROUP(227, _, qdss_gpio, _, _, _, _, _, _, _),
1798
+
[228] = PINGROUP(228, _, qdss_gpio, _, _, _, _, _, _, _),
1799
+
[229] = PINGROUP(229, qdss_gpio, _, _, _, _, _, _, _, _),
1800
+
[230] = PINGROUP(230, qdss_gpio, _, _, _, _, _, _, _, _),
1801
+
[231] = PINGROUP(231, qdss_gpio, _, _, _, _, _, _, _, _),
1802
+
[232] = PINGROUP(232, qdss_gpio, _, _, _, _, _, _, _, _),
1803
+
[233] = PINGROUP(233, qdss_gpio, _, _, _, _, _, _, _, _),
1804
+
[234] = PINGROUP(234, qdss_gpio, _, _, _, _, _, _, _, _),
1805
+
[235] = PINGROUP(235, aon_cci, qdss_gpio, _, _, _, _, _, _, _),
1806
+
[236] = PINGROUP(236, aon_cci, qdss_gpio, _, _, _, _, _, _, _),
1807
+
[237] = PINGROUP(237, _, _, _, _, _, _, _, _, _),
1808
+
[238] = UFS_RESET(ufs_reset, 0x1f9000),
1809
+
[239] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1f2000, 14, 6),
1810
+
[240] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1f2000, 11, 3),
1811
+
[241] = SDC_QDSD_PINGROUP(sdc2_data, 0x1f2000, 9, 0),
1812
+
};
1813
+
1814
+
static const struct msm_gpio_wakeirq_map x1e80100_pdc_map[] = {
1815
+
{ 0, 72 }, { 2, 70 }, { 3, 71 }, { 6, 123 }, { 7, 67 }, { 11, 85 },
1816
+
{ 15, 68 }, { 18, 122 }, { 19, 69 }, { 21, 158 }, { 23, 143 }, { 26, 129 },
1817
+
{ 27, 144 }, { 28, 77 }, { 29, 78 }, { 30, 92 }, { 32, 145 }, { 33, 115 },
1818
+
{ 34, 130 }, { 35, 146 }, { 36, 147 }, { 39, 80 }, { 43, 148 }, { 47, 149 },
1819
+
{ 51, 79 }, { 53, 89 }, { 59, 87 }, { 64, 90 }, { 65, 106 }, { 66, 142 },
1820
+
{ 67, 88 }, { 71, 91 }, { 75, 152 }, { 79, 153 }, { 80, 125 }, { 81, 128 },
1821
+
{ 84, 137 }, { 85, 155 }, { 87, 156 }, { 91, 157 }, { 92, 138 }, { 94, 140 },
1822
+
{ 95, 141 }, { 113, 84 }, { 121, 73 }, { 123, 74 }, { 129, 76 }, { 131, 82 },
1823
+
{ 134, 83 }, { 141, 93 }, { 144, 94 }, { 147, 96 }, { 148, 97 }, { 150, 102 },
1824
+
{ 151, 103 }, { 153, 104 }, { 156, 105 }, { 157, 107 }, { 163, 98 }, { 166, 112 },
1825
+
{ 172, 99 }, { 181, 101 }, { 184, 116 }, { 193, 40 }, { 193, 117 }, { 196, 108 },
1826
+
{ 203, 133 }, { 212, 120 }, { 213, 150 }, { 214, 121 }, { 215, 118 }, { 217, 109 },
1827
+
{ 220, 110 }, { 221, 111 }, { 222, 124 }, { 224, 131 }, { 225, 132 },
1828
+
};
1829
+
1830
+
static const struct msm_pinctrl_soc_data x1e80100_pinctrl = {
1831
+
.pins = x1e80100_pins,
1832
+
.npins = ARRAY_SIZE(x1e80100_pins),
1833
+
.functions = x1e80100_functions,
1834
+
.nfunctions = ARRAY_SIZE(x1e80100_functions),
1835
+
.groups = x1e80100_groups,
1836
+
.ngroups = ARRAY_SIZE(x1e80100_groups),
1837
+
.ngpios = 239,
1838
+
.wakeirq_map = x1e80100_pdc_map,
1839
+
.nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map),
1840
+
.egpio_func = 9,
1841
+
};
1842
+
1843
+
static int x1e80100_pinctrl_probe(struct platform_device *pdev)
1844
+
{
1845
+
return msm_pinctrl_probe(pdev, &x1e80100_pinctrl);
1846
+
}
1847
+
1848
+
static const struct of_device_id x1e80100_pinctrl_of_match[] = {
1849
+
{ .compatible = "qcom,x1e80100-tlmm", },
1850
+
{ },
1851
+
};
1852
+
1853
+
static struct platform_driver x1e80100_pinctrl_driver = {
1854
+
.driver = {
1855
+
.name = "x1e80100-tlmm",
1856
+
.of_match_table = x1e80100_pinctrl_of_match,
1857
+
},
1858
+
.probe = x1e80100_pinctrl_probe,
1859
+
.remove_new = msm_pinctrl_remove,
1860
+
};
1861
+
1862
+
static int __init x1e80100_pinctrl_init(void)
1863
+
{
1864
+
return platform_driver_register(&x1e80100_pinctrl_driver);
1865
+
}
1866
+
arch_initcall(x1e80100_pinctrl_init);
1867
+
1868
+
static void __exit x1e80100_pinctrl_exit(void)
1869
+
{
1870
+
platform_driver_unregister(&x1e80100_pinctrl_driver);
1871
+
}
1872
+
module_exit(x1e80100_pinctrl_exit);
1873
+
1874
+
MODULE_DESCRIPTION("QTI X1E80100 TLMM pinctrl driver");
1875
+
MODULE_LICENSE("GPL");
1876
+
MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match);
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
+5
-5
drivers/pinctrl/renesas/pinctrl-rza2.c
+5
-5
drivers/pinctrl/renesas/pinctrl-rza2.c
···
447
447
448
448
psel_val = func->data;
449
449
450
-
for (i = 0; i < grp->num_pins; ++i) {
450
+
for (i = 0; i < grp->grp.npins; ++i) {
451
451
dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
452
-
port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
453
-
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
452
+
port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])],
453
+
RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
454
454
psel_val[i]);
455
455
rza2_set_pin_function(
456
456
priv->base,
457
-
RZA2_PIN_ID_TO_PORT(grp->pins[i]),
458
-
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
457
+
RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]),
458
+
RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
459
459
psel_val[i]);
460
460
}
461
461
+149
-22
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+149
-22
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
57
57
#define PIN_CFG_FILCLKSEL BIT(12)
58
58
#define PIN_CFG_IOLH_C BIT(13)
59
59
#define PIN_CFG_SOFT_PS BIT(14)
60
+
#define PIN_CFG_OEN BIT(15)
60
61
61
62
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
62
63
(PIN_CFG_IOLH_##group | \
···
108
107
#define IEN(off) (0x1800 + (off) * 8)
109
108
#define ISEL(off) (0x2C00 + (off) * 8)
110
109
#define SD_CH(off, ch) ((off) + (ch) * 4)
110
+
#define ETH_POC(off, ch) ((off) + (ch) * 4)
111
111
#define QSPI (0x3008)
112
+
#define ETH_MODE (0x3018)
112
113
114
+
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
113
115
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
114
116
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
115
117
···
120
116
#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
121
117
122
118
#define PM_MASK 0x03
123
-
#define PVDD_MASK 0x01
124
119
#define PFC_MASK 0x07
125
120
#define IEN_MASK 0x01
126
121
#define IOLH_MASK 0x03
···
138
135
* struct rzg2l_register_offsets - specific register offsets
139
136
* @pwpr: PWPR register offset
140
137
* @sd_ch: SD_CH register offset
138
+
* @eth_poc: ETH_POC register offset
141
139
*/
142
140
struct rzg2l_register_offsets {
143
141
u16 pwpr;
144
142
u16 sd_ch;
143
+
u16 eth_poc;
145
144
};
146
145
147
146
/**
···
172
167
* @iolh_groupb_oi: IOLH group B output impedance specific values
173
168
* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
174
169
* @func_base: base number for port function (see register PFC)
170
+
* @oen_max_pin: the maximum pin number supporting output enable
171
+
* @oen_max_port: the maximum port number supporting output enable
175
172
*/
176
173
struct rzg2l_hwcfg {
177
174
const struct rzg2l_register_offsets regs;
···
183
176
u16 iolh_groupb_oi[4];
184
177
bool drive_strength_ua;
185
178
u8 func_base;
179
+
u8 oen_max_pin;
180
+
u8 oen_max_port;
186
181
};
187
182
188
183
struct rzg2l_dedicated_configs {
···
282
273
struct function_desc *func;
283
274
unsigned int i, *psel_val;
284
275
struct group_desc *group;
285
-
int *pins;
276
+
const unsigned int *pins;
286
277
287
278
func = pinmux_generic_get_function(pctldev, func_selector);
288
279
if (!func)
···
292
283
return -EINVAL;
293
284
294
285
psel_val = func->data;
295
-
pins = group->pins;
286
+
pins = group->grp.pins;
296
287
297
-
for (i = 0; i < group->num_pins; i++) {
288
+
for (i = 0; i < group->grp.npins; i++) {
298
289
unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;
299
290
u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
300
291
u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
···
385
376
goto done;
386
377
}
387
378
388
-
if (num_pinmux)
379
+
if (num_pinmux) {
389
380
nmaps += 1;
381
+
if (num_configs)
382
+
nmaps += 1;
383
+
}
390
384
391
385
if (num_pins)
392
386
nmaps += num_pins;
···
473
461
maps[idx].data.mux.group = name;
474
462
maps[idx].data.mux.function = name;
475
463
idx++;
464
+
465
+
if (num_configs) {
466
+
ret = rzg2l_map_add_config(&maps[idx], name,
467
+
PIN_MAP_TYPE_CONFIGS_GROUP,
468
+
configs, num_configs);
469
+
if (ret < 0)
470
+
goto remove_group;
471
+
472
+
idx++;
473
+
}
476
474
477
475
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
478
476
ret = 0;
···
613
591
return SD_CH(regs->sd_ch, 0);
614
592
if (caps & PIN_CFG_IO_VMC_SD1)
615
593
return SD_CH(regs->sd_ch, 1);
594
+
if (caps & PIN_CFG_IO_VMC_ETH0)
595
+
return ETH_POC(regs->eth_poc, 0);
596
+
if (caps & PIN_CFG_IO_VMC_ETH1)
597
+
return ETH_POC(regs->eth_poc, 1);
616
598
if (caps & PIN_CFG_IO_VMC_QSPI)
617
599
return QSPI;
618
600
···
628
602
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
629
603
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
630
604
int pwr_reg;
605
+
u8 val;
631
606
632
607
if (caps & PIN_CFG_SOFT_PS)
633
608
return pctrl->settings[pin].power_source;
···
637
610
if (pwr_reg < 0)
638
611
return pwr_reg;
639
612
640
-
return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300;
613
+
val = readb(pctrl->base + pwr_reg);
614
+
switch (val) {
615
+
case PVDD_1800:
616
+
return 1800;
617
+
case PVDD_2500:
618
+
return 2500;
619
+
case PVDD_3300:
620
+
return 3300;
621
+
default:
622
+
/* Should not happen. */
623
+
return -EINVAL;
624
+
}
641
625
}
642
626
643
627
static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
···
656
618
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
657
619
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
658
620
int pwr_reg;
621
+
u8 val;
659
622
660
623
if (caps & PIN_CFG_SOFT_PS) {
661
624
pctrl->settings[pin].power_source = ps;
662
625
return 0;
663
626
}
664
627
628
+
switch (ps) {
629
+
case 1800:
630
+
val = PVDD_1800;
631
+
break;
632
+
case 2500:
633
+
val = PVDD_2500;
634
+
break;
635
+
case 3300:
636
+
val = PVDD_3300;
637
+
break;
638
+
default:
639
+
return -EINVAL;
640
+
}
641
+
665
642
pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
666
643
if (pwr_reg < 0)
667
644
return pwr_reg;
668
645
669
-
writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg);
646
+
writeb(val, pctrl->base + pwr_reg);
670
647
pctrl->settings[pin].power_source = ps;
671
648
672
649
return 0;
···
788
735
return false;
789
736
}
790
737
738
+
static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
739
+
{
740
+
if (!(caps & PIN_CFG_OEN))
741
+
return false;
742
+
743
+
if (pin > max_pin)
744
+
return false;
745
+
746
+
return true;
747
+
}
748
+
749
+
static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
750
+
{
751
+
if (pin)
752
+
pin *= 2;
753
+
754
+
if (offset / RZG2L_PINS_PER_PORT == max_port)
755
+
pin += 1;
756
+
757
+
return pin;
758
+
}
759
+
760
+
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
761
+
{
762
+
u8 max_port = pctrl->data->hwcfg->oen_max_port;
763
+
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
764
+
u8 bit;
765
+
766
+
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
767
+
return 0;
768
+
769
+
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
770
+
771
+
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
772
+
}
773
+
774
+
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
775
+
{
776
+
u8 max_port = pctrl->data->hwcfg->oen_max_port;
777
+
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
778
+
unsigned long flags;
779
+
u8 val, bit;
780
+
781
+
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
782
+
return -EINVAL;
783
+
784
+
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
785
+
786
+
spin_lock_irqsave(&pctrl->lock, flags);
787
+
val = readb(pctrl->base + ETH_MODE);
788
+
if (oen)
789
+
val &= ~BIT(bit);
790
+
else
791
+
val |= BIT(bit);
792
+
writeb(val, pctrl->base + ETH_MODE);
793
+
spin_unlock_irqrestore(&pctrl->lock, flags);
794
+
795
+
return 0;
796
+
}
797
+
791
798
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
792
799
unsigned int _pin,
793
800
unsigned long *config)
···
881
768
if (!(cfg & PIN_CFG_IEN))
882
769
return -EINVAL;
883
770
arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
771
+
if (!arg)
772
+
return -EINVAL;
773
+
break;
774
+
775
+
case PIN_CONFIG_OUTPUT_ENABLE:
776
+
arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
884
777
if (!arg)
885
778
return -EINVAL;
886
779
break;
···
961
842
struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
962
843
unsigned int *pin_data = pin->drv_data;
963
844
enum pin_config_param param;
964
-
unsigned int i;
845
+
unsigned int i, arg, index;
965
846
u32 cfg, off;
966
847
int ret;
967
848
u8 bit;
···
983
864
for (i = 0; i < num_configs; i++) {
984
865
param = pinconf_to_config_param(_configs[i]);
985
866
switch (param) {
986
-
case PIN_CONFIG_INPUT_ENABLE: {
987
-
unsigned int arg =
988
-
pinconf_to_config_argument(_configs[i]);
867
+
case PIN_CONFIG_INPUT_ENABLE:
868
+
arg = pinconf_to_config_argument(_configs[i]);
989
869
990
870
if (!(cfg & PIN_CFG_IEN))
991
871
return -EINVAL;
992
872
993
873
rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);
994
874
break;
995
-
}
875
+
876
+
case PIN_CONFIG_OUTPUT_ENABLE:
877
+
arg = pinconf_to_config_argument(_configs[i]);
878
+
ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
879
+
if (ret)
880
+
return ret;
881
+
break;
996
882
997
883
case PIN_CONFIG_POWER_SOURCE:
998
884
settings.power_source = pinconf_to_config_argument(_configs[i]);
999
885
break;
1000
886
1001
-
case PIN_CONFIG_DRIVE_STRENGTH: {
1002
-
unsigned int arg = pinconf_to_config_argument(_configs[i]);
1003
-
unsigned int index;
887
+
case PIN_CONFIG_DRIVE_STRENGTH:
888
+
arg = pinconf_to_config_argument(_configs[i]);
1004
889
1005
890
if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1006
891
return -EINVAL;
···
1019
896
1020
897
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1021
898
break;
1022
-
}
1023
899
1024
900
case PIN_CONFIG_DRIVE_STRENGTH_UA:
1025
901
if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
···
1028
906
settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
1029
907
break;
1030
908
1031
-
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
1032
-
unsigned int arg = pinconf_to_config_argument(_configs[i]);
1033
-
unsigned int index;
909
+
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
910
+
arg = pinconf_to_config_argument(_configs[i]);
1034
911
1035
912
if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1036
913
return -EINVAL;
···
1043
922
1044
923
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1045
924
break;
1046
-
}
1047
925
1048
926
default:
1049
927
return -EOPNOTSUPP;
···
1443
1323
static const u32 r9a08g045_gpio_configs[] = {
1444
1324
RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1445
1325
RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1446
-
PIN_CFG_IO_VMC_ETH0)), /* P1 */
1326
+
PIN_CFG_IO_VMC_ETH0)) |
1327
+
PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */
1447
1328
RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1448
1329
PIN_CFG_IO_VMC_ETH0)), /* P2 */
1449
1330
RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
···
1454
1333
RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1455
1334
RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1456
1335
RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1457
-
PIN_CFG_IO_VMC_ETH1)), /* P7 */
1336
+
PIN_CFG_IO_VMC_ETH1)) |
1337
+
PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */
1458
1338
RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1459
1339
PIN_CFG_IO_VMC_ETH1)), /* P8 */
1460
1340
RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
···
1698
1576
.irq_set_type = rzg2l_gpio_irq_set_type,
1699
1577
.irq_eoi = rzg2l_gpio_irqc_eoi,
1700
1578
.irq_print_chip = rzg2l_gpio_irq_print_chip,
1579
+
.irq_set_affinity = irq_chip_set_affinity_parent,
1701
1580
.flags = IRQCHIP_IMMUTABLE,
1702
1581
GPIOCHIP_IRQ_RESOURCE_HELPERS,
1703
1582
};
···
2000
1877
.regs = {
2001
1878
.pwpr = 0x3014,
2002
1879
.sd_ch = 0x3000,
1880
+
.eth_poc = 0x300c,
2003
1881
},
2004
1882
.iolh_groupa_ua = {
2005
1883
/* 3v3 power source */
···
2013
1889
.regs = {
2014
1890
.pwpr = 0x3000,
2015
1891
.sd_ch = 0x3004,
1892
+
.eth_poc = 0x3010,
2016
1893
},
2017
1894
.iolh_groupa_ua = {
2018
1895
/* 1v8 power source */
···
2037
1912
},
2038
1913
.drive_strength_ua = true,
2039
1914
.func_base = 1,
1915
+
.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
1916
+
.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
2040
1917
};
2041
1918
2042
1919
static struct rzg2l_pinctrl_data r9a07g043_data = {
+3
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+3
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
···
165
165
struct function_desc *func;
166
166
unsigned int i, *psel_val;
167
167
struct group_desc *group;
168
-
int *pins;
168
+
const unsigned int *pins;
169
169
170
170
func = pinmux_generic_get_function(pctldev, func_selector);
171
171
if (!func)
···
175
175
return -EINVAL;
176
176
177
177
psel_val = func->data;
178
-
pins = group->pins;
178
+
pins = group->grp.pins;
179
179
180
-
for (i = 0; i < group->num_pins; i++) {
180
+
for (i = 0; i < group->grp.npins; i++) {
181
181
dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
182
182
RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
183
183
psel_val[i]);
+280
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+280
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
726
726
.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
727
727
};
728
728
729
+
/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
730
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
731
+
EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
732
+
EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
733
+
EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
734
+
};
735
+
736
+
/* pin banks of exynosautov920 pin-controller 1 (AUD) */
737
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {
738
+
EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),
739
+
EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),
740
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),
741
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),
742
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),
743
+
EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),
744
+
EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),
745
+
};
746
+
747
+
/* pin banks of exynosautov920 pin-controller 2 (HSI0) */
748
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {
749
+
EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),
750
+
EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),
751
+
};
752
+
753
+
/* pin banks of exynosautov920 pin-controller 3 (HSI1) */
754
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {
755
+
EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),
756
+
};
757
+
758
+
/* pin banks of exynosautov920 pin-controller 4 (HSI2) */
759
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {
760
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),
761
+
EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),
762
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),
763
+
EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),
764
+
};
765
+
766
+
/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */
767
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {
768
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),
769
+
};
770
+
771
+
/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */
772
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {
773
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),
774
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),
775
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),
776
+
EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),
777
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),
778
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),
779
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),
780
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),
781
+
EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),
782
+
EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),
783
+
};
784
+
785
+
/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */
786
+
static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {
787
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28),
788
+
EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28),
789
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),
790
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28),
791
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24),
792
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),
793
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24),
794
+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),
795
+
EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
796
+
};
797
+
798
+
static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
799
+
.regs = NULL,
800
+
.nr_regs = 0,
801
+
.value = 0,
802
+
.refcnt = &exynos_shared_retention_refcnt,
803
+
.init = exynos_retention_init,
804
+
};
805
+
806
+
static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
807
+
{
808
+
/* pin-controller instance 0 ALIVE data */
809
+
.pin_banks = exynosautov920_pin_banks0,
810
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
811
+
.eint_wkup_init = exynos_eint_wkup_init,
812
+
.suspend = exynos_pinctrl_suspend,
813
+
.resume = exynos_pinctrl_resume,
814
+
.retention_data = &exynosautov920_retention_data,
815
+
}, {
816
+
/* pin-controller instance 1 AUD data */
817
+
.pin_banks = exynosautov920_pin_banks1,
818
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1),
819
+
}, {
820
+
/* pin-controller instance 2 HSI0 data */
821
+
.pin_banks = exynosautov920_pin_banks2,
822
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
823
+
.eint_gpio_init = exynos_eint_gpio_init,
824
+
.suspend = exynos_pinctrl_suspend,
825
+
.resume = exynos_pinctrl_resume,
826
+
}, {
827
+
/* pin-controller instance 3 HSI1 data */
828
+
.pin_banks = exynosautov920_pin_banks3,
829
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
830
+
.eint_gpio_init = exynos_eint_gpio_init,
831
+
.suspend = exynos_pinctrl_suspend,
832
+
.resume = exynos_pinctrl_resume,
833
+
}, {
834
+
/* pin-controller instance 4 HSI2 data */
835
+
.pin_banks = exynosautov920_pin_banks4,
836
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
837
+
.eint_gpio_init = exynos_eint_gpio_init,
838
+
.suspend = exynos_pinctrl_suspend,
839
+
.resume = exynos_pinctrl_resume,
840
+
}, {
841
+
/* pin-controller instance 5 HSI2UFS data */
842
+
.pin_banks = exynosautov920_pin_banks5,
843
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
844
+
.eint_gpio_init = exynos_eint_gpio_init,
845
+
.suspend = exynos_pinctrl_suspend,
846
+
.resume = exynos_pinctrl_resume,
847
+
}, {
848
+
/* pin-controller instance 6 PERIC0 data */
849
+
.pin_banks = exynosautov920_pin_banks6,
850
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
851
+
.eint_gpio_init = exynos_eint_gpio_init,
852
+
.suspend = exynos_pinctrl_suspend,
853
+
.resume = exynos_pinctrl_resume,
854
+
}, {
855
+
/* pin-controller instance 7 PERIC1 data */
856
+
.pin_banks = exynosautov920_pin_banks7,
857
+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
858
+
.eint_gpio_init = exynos_eint_gpio_init,
859
+
.suspend = exynos_pinctrl_suspend,
860
+
.resume = exynos_pinctrl_resume,
861
+
},
862
+
};
863
+
864
+
const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {
865
+
.ctrl = exynosautov920_pin_ctrl,
866
+
.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
867
+
};
868
+
729
869
/*
730
870
* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
731
871
* gpio/pin-mux/pinconfig controllers.
···
935
795
const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
936
796
.ctrl = fsd_pin_ctrl,
937
797
.num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
798
+
};
799
+
800
+
/* pin banks of gs101 pin-controller (ALIVE) */
801
+
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
802
+
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
803
+
EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
804
+
EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
805
+
EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
806
+
EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
807
+
EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
808
+
EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
809
+
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
810
+
};
811
+
812
+
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
813
+
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
814
+
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
815
+
EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
816
+
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
817
+
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
818
+
};
819
+
820
+
/* pin banks of gs101 pin-controller (GSACORE) */
821
+
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
822
+
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
823
+
EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
824
+
EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
825
+
};
826
+
827
+
/* pin banks of gs101 pin-controller (GSACTRL) */
828
+
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
829
+
EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
830
+
};
831
+
832
+
/* pin banks of gs101 pin-controller (PERIC0) */
833
+
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
834
+
EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
835
+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
836
+
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
837
+
EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
838
+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
839
+
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
840
+
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
841
+
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
842
+
EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
843
+
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
844
+
EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
845
+
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
846
+
EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
847
+
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
848
+
EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
849
+
EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
850
+
EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
851
+
EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
852
+
EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
853
+
EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
854
+
};
855
+
856
+
/* pin banks of gs101 pin-controller (PERIC1) */
857
+
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
858
+
EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
859
+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
860
+
EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
861
+
EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
862
+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
863
+
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
864
+
EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
865
+
EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
866
+
};
867
+
868
+
/* pin banks of gs101 pin-controller (HSI1) */
869
+
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
870
+
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
871
+
EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
872
+
};
873
+
874
+
/* pin banks of gs101 pin-controller (HSI2) */
875
+
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
876
+
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
877
+
EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
878
+
EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
879
+
};
880
+
881
+
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
882
+
{
883
+
/* pin banks of gs101 pin-controller (ALIVE) */
884
+
.pin_banks = gs101_pin_alive,
885
+
.nr_banks = ARRAY_SIZE(gs101_pin_alive),
886
+
.eint_wkup_init = exynos_eint_wkup_init,
887
+
.suspend = exynos_pinctrl_suspend,
888
+
.resume = exynos_pinctrl_resume,
889
+
}, {
890
+
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
891
+
.pin_banks = gs101_pin_far_alive,
892
+
.nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
893
+
.eint_wkup_init = exynos_eint_wkup_init,
894
+
.suspend = exynos_pinctrl_suspend,
895
+
.resume = exynos_pinctrl_resume,
896
+
}, {
897
+
/* pin banks of gs101 pin-controller (GSACORE) */
898
+
.pin_banks = gs101_pin_gsacore,
899
+
.nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
900
+
}, {
901
+
/* pin banks of gs101 pin-controller (GSACTRL) */
902
+
.pin_banks = gs101_pin_gsactrl,
903
+
.nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
904
+
}, {
905
+
/* pin banks of gs101 pin-controller (PERIC0) */
906
+
.pin_banks = gs101_pin_peric0,
907
+
.nr_banks = ARRAY_SIZE(gs101_pin_peric0),
908
+
.eint_gpio_init = exynos_eint_gpio_init,
909
+
.suspend = exynos_pinctrl_suspend,
910
+
.resume = exynos_pinctrl_resume,
911
+
}, {
912
+
/* pin banks of gs101 pin-controller (PERIC1) */
913
+
.pin_banks = gs101_pin_peric1,
914
+
.nr_banks = ARRAY_SIZE(gs101_pin_peric1),
915
+
.eint_gpio_init = exynos_eint_gpio_init,
916
+
.suspend = exynos_pinctrl_suspend,
917
+
.resume = exynos_pinctrl_resume,
918
+
}, {
919
+
/* pin banks of gs101 pin-controller (HSI1) */
920
+
.pin_banks = gs101_pin_hsi1,
921
+
.nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
922
+
.eint_gpio_init = exynos_eint_gpio_init,
923
+
.suspend = exynos_pinctrl_suspend,
924
+
.resume = exynos_pinctrl_resume,
925
+
}, {
926
+
/* pin banks of gs101 pin-controller (HSI2) */
927
+
.pin_banks = gs101_pin_hsi2,
928
+
.nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
929
+
.eint_gpio_init = exynos_eint_gpio_init,
930
+
.suspend = exynos_pinctrl_suspend,
931
+
.resume = exynos_pinctrl_resume,
932
+
},
933
+
};
934
+
935
+
const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
936
+
.ctrl = gs101_pin_ctrl,
937
+
.num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
938
938
};
+101
-10
drivers/pinctrl/samsung/pinctrl-exynos.c
+101
-10
drivers/pinctrl/samsung/pinctrl-exynos.c
···
52
52
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
53
53
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
54
54
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
55
-
unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
55
+
unsigned long reg_mask;
56
56
unsigned int mask;
57
57
unsigned long flags;
58
+
59
+
if (bank->eint_mask_offset)
60
+
reg_mask = bank->pctl_offset + bank->eint_mask_offset;
61
+
else
62
+
reg_mask = our_chip->eint_mask + bank->eint_offset;
58
63
59
64
raw_spin_lock_irqsave(&bank->slock, flags);
60
65
···
75
70
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
76
71
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
77
72
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
78
-
unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
73
+
unsigned long reg_pend;
74
+
75
+
if (bank->eint_pend_offset)
76
+
reg_pend = bank->pctl_offset + bank->eint_pend_offset;
77
+
else
78
+
reg_pend = our_chip->eint_pend + bank->eint_offset;
79
79
80
80
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
81
81
}
···
90
80
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
91
81
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
92
82
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
93
-
unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
83
+
unsigned long reg_mask;
94
84
unsigned int mask;
95
85
unsigned long flags;
96
86
···
104
94
*/
105
95
if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
106
96
exynos_irq_ack(irqd);
97
+
98
+
if (bank->eint_mask_offset)
99
+
reg_mask = bank->pctl_offset + bank->eint_mask_offset;
100
+
else
101
+
reg_mask = our_chip->eint_mask + bank->eint_offset;
107
102
108
103
raw_spin_lock_irqsave(&bank->slock, flags);
109
104
···
126
111
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
127
112
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
128
113
unsigned int con, trig_type;
129
-
unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
114
+
unsigned long reg_con;
130
115
131
116
switch (type) {
132
117
case IRQ_TYPE_EDGE_RISING:
···
154
139
else
155
140
irq_set_handler_locked(irqd, handle_level_irq);
156
141
142
+
if (bank->eint_con_offset)
143
+
reg_con = bank->pctl_offset + bank->eint_con_offset;
144
+
else
145
+
reg_con = our_chip->eint_con + bank->eint_offset;
146
+
157
147
con = readl(bank->eint_base + reg_con);
158
148
con &= ~(EXYNOS_EINT_CON_MASK << shift);
159
149
con |= trig_type << shift;
160
150
writel(con, bank->eint_base + reg_con);
161
151
162
152
return 0;
153
+
}
154
+
155
+
static int exynos_irq_set_affinity(struct irq_data *irqd,
156
+
const struct cpumask *dest, bool force)
157
+
{
158
+
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
159
+
struct samsung_pinctrl_drv_data *d = bank->drvdata;
160
+
struct irq_data *parent = irq_get_irq_data(d->irq);
161
+
162
+
if (parent)
163
+
return parent->chip->irq_set_affinity(parent, dest, force);
164
+
165
+
return -EINVAL;
163
166
}
164
167
165
168
static int exynos_irq_request_resources(struct irq_data *irqd)
···
245
212
.irq_mask = exynos_irq_mask,
246
213
.irq_ack = exynos_irq_ack,
247
214
.irq_set_type = exynos_irq_set_type,
215
+
.irq_set_affinity = exynos_irq_set_affinity,
248
216
.irq_request_resources = exynos_irq_request_resources,
249
217
.irq_release_resources = exynos_irq_release_resources,
250
218
},
···
281
247
unsigned int svc, group, pin;
282
248
int ret;
283
249
284
-
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
250
+
if (bank->eint_con_offset)
251
+
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
252
+
else
253
+
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
285
254
group = EXYNOS_SVC_GROUP(svc);
286
255
pin = svc & EXYNOS_SVC_NUM_MASK;
287
256
···
493
456
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
494
457
};
495
458
459
+
static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {
460
+
.chip = {
461
+
.name = "exynosautov920_wkup_irq_chip",
462
+
.irq_unmask = exynos_irq_unmask,
463
+
.irq_mask = exynos_irq_mask,
464
+
.irq_ack = exynos_irq_ack,
465
+
.irq_set_type = exynos_irq_set_type,
466
+
.irq_set_wake = exynos_wkup_irq_set_wake,
467
+
.irq_request_resources = exynos_irq_request_resources,
468
+
.irq_release_resources = exynos_irq_release_resources,
469
+
},
470
+
.eint_wake_mask_value = &eint_wake_mask_value,
471
+
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
472
+
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
473
+
};
474
+
496
475
/* list of external wakeup controllers supported */
497
476
static const struct of_device_id exynos_wkup_irq_ids[] = {
498
477
{ .compatible = "samsung,s5pv210-wakeup-eint",
···
521
468
.data = &exynos7_wkup_irq_chip },
522
469
{ .compatible = "samsung,exynosautov9-wakeup-eint",
523
470
.data = &exynos7_wkup_irq_chip },
471
+
{ .compatible = "samsung,exynosautov920-wakeup-eint",
472
+
.data = &exynosautov920_wkup_irq_chip },
524
473
{ }
525
474
};
526
475
···
693
638
struct samsung_pin_bank *bank)
694
639
{
695
640
struct exynos_eint_gpio_save *save = bank->soc_priv;
696
-
void __iomem *regs = bank->eint_base;
641
+
const void __iomem *regs = bank->eint_base;
697
642
698
643
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
699
644
+ bank->eint_offset);
···
710
655
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
711
656
}
712
657
658
+
static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata,
659
+
struct samsung_pin_bank *bank)
660
+
{
661
+
struct exynos_eint_gpio_save *save = bank->soc_priv;
662
+
const void __iomem *regs = bank->eint_base;
663
+
664
+
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
665
+
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
666
+
667
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
668
+
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
669
+
}
670
+
713
671
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
714
672
{
715
673
struct samsung_pin_bank *bank = drvdata->pin_banks;
···
730
662
int i;
731
663
732
664
for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
733
-
if (bank->eint_type == EINT_TYPE_GPIO)
734
-
exynos_pinctrl_suspend_bank(drvdata, bank);
665
+
if (bank->eint_type == EINT_TYPE_GPIO) {
666
+
if (bank->eint_con_offset)
667
+
exynosauto_pinctrl_suspend_bank(drvdata, bank);
668
+
else
669
+
exynos_pinctrl_suspend_bank(drvdata, bank);
670
+
}
735
671
else if (bank->eint_type == EINT_TYPE_WKUP) {
736
672
if (!irq_chip) {
737
673
irq_chip = bank->irq_chip;
···
776
704
+ bank->eint_offset);
777
705
}
778
706
707
+
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
708
+
struct samsung_pin_bank *bank)
709
+
{
710
+
struct exynos_eint_gpio_save *save = bank->soc_priv;
711
+
void __iomem *regs = bank->eint_base;
712
+
713
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
714
+
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
715
+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
716
+
readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
717
+
718
+
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
719
+
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
720
+
}
721
+
779
722
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
780
723
{
781
724
struct samsung_pin_bank *bank = drvdata->pin_banks;
782
725
int i;
783
726
784
727
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
785
-
if (bank->eint_type == EINT_TYPE_GPIO)
786
-
exynos_pinctrl_resume_bank(drvdata, bank);
728
+
if (bank->eint_type == EINT_TYPE_GPIO) {
729
+
if (bank->eint_con_offset)
730
+
exynosauto_pinctrl_resume_bank(drvdata, bank);
731
+
else
732
+
exynos_pinctrl_resume_bank(drvdata, bank);
733
+
}
787
734
}
788
735
789
736
static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
+25
drivers/pinctrl/samsung/pinctrl-exynos.h
+25
drivers/pinctrl/samsung/pinctrl-exynos.h
···
31
31
#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
32
32
#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
33
33
#define EXYNOS_SVC_OFFSET 0xB08
34
+
#define EXYNOSAUTO_SVC_OFFSET 0xF008
34
35
35
36
/* helpers to access interrupt service register */
36
37
#define EXYNOS_SVC_GROUP_SHIFT 3
···
139
138
.eint_type = EINT_TYPE_WKUP, \
140
139
.eint_offset = offs, \
141
140
.name = id \
141
+
}
142
+
143
+
#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
144
+
{ \
145
+
.type = &exynos850_bank_type_off, \
146
+
.pctl_offset = reg, \
147
+
.nr_pins = pins, \
148
+
.eint_type = EINT_TYPE_GPIO, \
149
+
.eint_con_offset = con_offs, \
150
+
.eint_mask_offset = mask_offs, \
151
+
.eint_pend_offset = pend_offs, \
152
+
.name = id \
153
+
}
154
+
155
+
#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
156
+
{ \
157
+
.type = &exynos850_bank_type_alive, \
158
+
.pctl_offset = reg, \
159
+
.nr_pins = pins, \
160
+
.eint_type = EINT_TYPE_WKUP, \
161
+
.eint_con_offset = con_offs, \
162
+
.eint_mask_offset = mask_offs, \
163
+
.eint_pend_offset = pend_offs, \
164
+
.name = id \
142
165
}
143
166
144
167
/**
+9
-2
drivers/pinctrl/samsung/pinctrl-samsung.c
+9
-2
drivers/pinctrl/samsung/pinctrl-samsung.c
···
565
565
/* gpiolib gpio_get callback function */
566
566
static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
567
567
{
568
-
void __iomem *reg;
568
+
const void __iomem *reg;
569
569
u32 data;
570
570
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
571
571
const struct samsung_pin_bank_type *type = bank->type;
···
1106
1106
bank->eint_type = bdata->eint_type;
1107
1107
bank->eint_mask = bdata->eint_mask;
1108
1108
bank->eint_offset = bdata->eint_offset;
1109
+
bank->eint_con_offset = bdata->eint_con_offset;
1110
+
bank->eint_mask_offset = bdata->eint_mask_offset;
1111
+
bank->eint_pend_offset = bdata->eint_pend_offset;
1109
1112
bank->name = bdata->name;
1110
1113
1111
1114
raw_spin_lock_init(&bank->slock);
···
1204
1201
1205
1202
for (i = 0; i < drvdata->nr_banks; i++) {
1206
1203
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
1207
-
void __iomem *reg = bank->pctl_base + bank->pctl_offset;
1204
+
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
1208
1205
const u8 *offs = bank->type->reg_offset;
1209
1206
const u8 *widths = bank->type->fld_width;
1210
1207
enum pincfg_type type;
···
1312
1309
.data = &s5pv210_of_data },
1313
1310
#endif
1314
1311
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
1312
+
{ .compatible = "google,gs101-pinctrl",
1313
+
.data = &gs101_of_data },
1315
1314
{ .compatible = "samsung,exynos5433-pinctrl",
1316
1315
.data = &exynos5433_of_data },
1317
1316
{ .compatible = "samsung,exynos7-pinctrl",
···
1324
1319
.data = &exynos850_of_data },
1325
1320
{ .compatible = "samsung,exynosautov9-pinctrl",
1326
1321
.data = &exynosautov9_of_data },
1322
+
{ .compatible = "samsung,exynosautov920-pinctrl",
1323
+
.data = &exynosautov920_of_data },
1327
1324
{ .compatible = "tesla,fsd-pinctrl",
1328
1325
.data = &fsd_of_data },
1329
1326
#endif
+14
drivers/pinctrl/samsung/pinctrl-samsung.h
+14
drivers/pinctrl/samsung/pinctrl-samsung.h
···
122
122
* @eint_type: type of the external interrupt supported by the bank.
123
123
* @eint_mask: bit mask of pins which support EINT function.
124
124
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
125
+
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
126
+
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
127
+
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
125
128
* @name: name to be prefixed for each pin in this pin bank.
126
129
*/
127
130
struct samsung_pin_bank_data {
···
136
133
enum eint_type eint_type;
137
134
u32 eint_mask;
138
135
u32 eint_offset;
136
+
u32 eint_con_offset;
137
+
u32 eint_mask_offset;
138
+
u32 eint_pend_offset;
139
139
const char *name;
140
140
};
141
141
···
153
147
* @eint_type: type of the external interrupt supported by the bank.
154
148
* @eint_mask: bit mask of pins which support EINT function.
155
149
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
150
+
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
151
+
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
152
+
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
156
153
* @name: name to be prefixed for each pin in this pin bank.
157
154
* @id: id of the bank, propagated to the pin range.
158
155
* @pin_base: starting pin number of the bank.
···
179
170
enum eint_type eint_type;
180
171
u32 eint_mask;
181
172
u32 eint_offset;
173
+
u32 eint_con_offset;
174
+
u32 eint_mask_offset;
175
+
u32 eint_pend_offset;
182
176
const char *name;
183
177
u32 id;
184
178
···
362
350
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
363
351
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
364
352
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
353
+
extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
365
354
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
355
+
extern const struct samsung_pinctrl_of_match_data gs101_of_data;
366
356
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
367
357
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
368
358
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
+4
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+4
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
···
654
654
return -EINVAL;
655
655
656
656
pinmux = group->data;
657
-
for (i = 0; i < group->num_pins; i++) {
657
+
for (i = 0; i < group->grp.npins; i++) {
658
658
u32 v = pinmux[i];
659
659
unsigned int gpio = starfive_pinmux_to_gpio(v);
660
660
u32 dout = starfive_pinmux_to_dout(v);
···
797
797
if (!group)
798
798
return -EINVAL;
799
799
800
-
return starfive_pinconf_get(pctldev, group->pins[0], config);
800
+
return starfive_pinconf_get(pctldev, group->grp.pins[0], config);
801
801
}
802
802
803
803
static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
···
876
876
}
877
877
}
878
878
879
-
for (i = 0; i < group->num_pins; i++)
880
-
starfive_padctl_rmw(sfp, group->pins[i], mask, value);
879
+
for (i = 0; i < group->grp.npins; i++)
880
+
starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value);
881
881
882
882
return 0;
883
883
}
+4
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+4
-4
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
···
307
307
return -EINVAL;
308
308
309
309
pinmux = group->data;
310
-
for (i = 0; i < group->num_pins; i++) {
310
+
for (i = 0; i < group->grp.npins; i++) {
311
311
u32 v = pinmux[i];
312
312
313
313
if (info->jh7110_set_one_pin_mux)
···
437
437
if (!group)
438
438
return -EINVAL;
439
439
440
-
return jh7110_pinconf_get(pctldev, group->pins[0], config);
440
+
return jh7110_pinconf_get(pctldev, group->grp.pins[0], config);
441
441
}
442
442
443
443
static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
···
508
508
}
509
509
}
510
510
511
-
for (i = 0; i < group->num_pins; i++)
512
-
jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
511
+
for (i = 0; i < group->grp.npins; i++)
512
+
jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value);
513
513
514
514
return 0;
515
515
}
+1
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
+1
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
+8
drivers/pinctrl/tegra/pinctrl-tegra.c
+8
drivers/pinctrl/tegra/pinctrl-tegra.c
···
636
636
seq_printf(s, "\n\t%s=%u",
637
637
strip_prefix(cfg_params[i].property), val);
638
638
}
639
+
640
+
if (g->mux_reg >= 0) {
641
+
/* read pinmux function and dump to seq_file */
642
+
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
643
+
val = g->funcs[(val >> g->mux_bit) & 0x3];
644
+
645
+
seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name);
646
+
}
639
647
}
640
648
641
649
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
+3
-3
include/linux/pinctrl/machine.h
+3
-3
include/linux/pinctrl/machine.h
···
47
47
struct pinctrl_map_configs {
48
48
const char *group_or_pin;
49
49
unsigned long *configs;
50
-
unsigned num_configs;
50
+
unsigned int num_configs;
51
51
};
52
52
53
53
/**
···
154
154
#ifdef CONFIG_PINCTRL
155
155
156
156
extern int pinctrl_register_mappings(const struct pinctrl_map *map,
157
-
unsigned num_maps);
157
+
unsigned int num_maps);
158
158
extern void pinctrl_unregister_mappings(const struct pinctrl_map *map);
159
159
extern void pinctrl_provide_dummies(void);
160
160
#else
161
161
162
162
static inline int pinctrl_register_mappings(const struct pinctrl_map *map,
163
-
unsigned num_maps)
163
+
unsigned int num_maps)
164
164
{
165
165
return 0;
166
166
}
+5
-5
include/linux/pinctrl/pinconf-generic.h
+5
-5
include/linux/pinctrl/pinconf-generic.h
···
193
193
194
194
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
195
195
struct device_node *np, struct pinctrl_map **map,
196
-
unsigned *reserved_maps, unsigned *num_maps,
196
+
unsigned int *reserved_maps, unsigned int *num_maps,
197
197
enum pinctrl_map_type type);
198
198
int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
199
199
struct device_node *np_config, struct pinctrl_map **map,
200
-
unsigned *num_maps, enum pinctrl_map_type type);
200
+
unsigned int *num_maps, enum pinctrl_map_type type);
201
201
void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev,
202
-
struct pinctrl_map *map, unsigned num_maps);
202
+
struct pinctrl_map *map, unsigned int num_maps);
203
203
204
204
static inline int pinconf_generic_dt_node_to_map_group(struct pinctrl_dev *pctldev,
205
205
struct device_node *np_config, struct pinctrl_map **map,
206
-
unsigned *num_maps)
206
+
unsigned int *num_maps)
207
207
{
208
208
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
209
209
PIN_MAP_TYPE_CONFIGS_GROUP);
···
211
211
212
212
static inline int pinconf_generic_dt_node_to_map_pin(struct pinctrl_dev *pctldev,
213
213
struct device_node *np_config, struct pinctrl_map **map,
214
-
unsigned *num_maps)
214
+
unsigned int *num_maps)
215
215
{
216
216
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
217
217
PIN_MAP_TYPE_CONFIGS_PIN);
+8
-8
include/linux/pinctrl/pinconf.h
+8
-8
include/linux/pinctrl/pinconf.h
···
40
40
bool is_generic;
41
41
#endif
42
42
int (*pin_config_get) (struct pinctrl_dev *pctldev,
43
-
unsigned pin,
43
+
unsigned int pin,
44
44
unsigned long *config);
45
45
int (*pin_config_set) (struct pinctrl_dev *pctldev,
46
-
unsigned pin,
46
+
unsigned int pin,
47
47
unsigned long *configs,
48
-
unsigned num_configs);
48
+
unsigned int num_configs);
49
49
int (*pin_config_group_get) (struct pinctrl_dev *pctldev,
50
-
unsigned selector,
50
+
unsigned int selector,
51
51
unsigned long *config);
52
52
int (*pin_config_group_set) (struct pinctrl_dev *pctldev,
53
-
unsigned selector,
53
+
unsigned int selector,
54
54
unsigned long *configs,
55
-
unsigned num_configs);
55
+
unsigned int num_configs);
56
56
void (*pin_config_dbg_show) (struct pinctrl_dev *pctldev,
57
57
struct seq_file *s,
58
-
unsigned offset);
58
+
unsigned int offset);
59
59
void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
60
60
struct seq_file *s,
61
-
unsigned selector);
61
+
unsigned int selector);
62
62
void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
63
63
struct seq_file *s,
64
64
unsigned long config);
+12
-12
include/linux/pinctrl/pinctrl.h
+12
-12
include/linux/pinctrl/pinctrl.h
···
54
54
* @drv_data: driver-defined per-pin data. pinctrl core does not touch this
55
55
*/
56
56
struct pinctrl_pin_desc {
57
-
unsigned number;
57
+
unsigned int number;
58
58
const char *name;
59
59
void *drv_data;
60
60
};
···
82
82
unsigned int base;
83
83
unsigned int pin_base;
84
84
unsigned int npins;
85
-
unsigned const *pins;
85
+
unsigned int const *pins;
86
86
struct gpio_chip *gc;
87
87
};
88
88
···
108
108
struct pinctrl_ops {
109
109
int (*get_groups_count) (struct pinctrl_dev *pctldev);
110
110
const char *(*get_group_name) (struct pinctrl_dev *pctldev,
111
-
unsigned selector);
111
+
unsigned int selector);
112
112
int (*get_group_pins) (struct pinctrl_dev *pctldev,
113
-
unsigned selector,
114
-
const unsigned **pins,
115
-
unsigned *num_pins);
113
+
unsigned int selector,
114
+
const unsigned int **pins,
115
+
unsigned int *num_pins);
116
116
void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
117
-
unsigned offset);
117
+
unsigned int offset);
118
118
int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
119
119
struct device_node *np_config,
120
-
struct pinctrl_map **map, unsigned *num_maps);
120
+
struct pinctrl_map **map, unsigned int *num_maps);
121
121
void (*dt_free_map) (struct pinctrl_dev *pctldev,
122
-
struct pinctrl_map *map, unsigned num_maps);
122
+
struct pinctrl_map *map, unsigned int num_maps);
123
123
};
124
124
125
125
/**
···
193
193
struct pinctrl_gpio_range *range);
194
194
extern void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
195
195
struct pinctrl_gpio_range *ranges,
196
-
unsigned nranges);
196
+
unsigned int nranges);
197
197
extern void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev,
198
198
struct pinctrl_gpio_range *range);
199
199
···
203
203
pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
204
204
unsigned int pin);
205
205
extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
206
-
const char *pin_group, const unsigned **pins,
207
-
unsigned *num_pins);
206
+
const char *pin_group, const unsigned int **pins,
207
+
unsigned int *num_pins);
208
208
209
209
/**
210
210
* struct pinfunction - Description about a function
+11
-11
include/linux/pinctrl/pinmux.h
+11
-11
include/linux/pinctrl/pinmux.h
···
57
57
* the pin request.
58
58
*/
59
59
struct pinmux_ops {
60
-
int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
61
-
int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
60
+
int (*request) (struct pinctrl_dev *pctldev, unsigned int offset);
61
+
int (*free) (struct pinctrl_dev *pctldev, unsigned int offset);
62
62
int (*get_functions_count) (struct pinctrl_dev *pctldev);
63
63
const char *(*get_function_name) (struct pinctrl_dev *pctldev,
64
-
unsigned selector);
64
+
unsigned int selector);
65
65
int (*get_function_groups) (struct pinctrl_dev *pctldev,
66
-
unsigned selector,
67
-
const char * const **groups,
68
-
unsigned *num_groups);
69
-
int (*set_mux) (struct pinctrl_dev *pctldev, unsigned func_selector,
70
-
unsigned group_selector);
66
+
unsigned int selector,
67
+
const char * const **groups,
68
+
unsigned int *num_groups);
69
+
int (*set_mux) (struct pinctrl_dev *pctldev, unsigned int func_selector,
70
+
unsigned int group_selector);
71
71
int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
72
72
struct pinctrl_gpio_range *range,
73
-
unsigned offset);
73
+
unsigned int offset);
74
74
void (*gpio_disable_free) (struct pinctrl_dev *pctldev,
75
75
struct pinctrl_gpio_range *range,
76
-
unsigned offset);
76
+
unsigned int offset);
77
77
int (*gpio_set_direction) (struct pinctrl_dev *pctldev,
78
78
struct pinctrl_gpio_range *range,
79
-
unsigned offset,
79
+
unsigned int offset,
80
80
bool input);
81
81
bool strict;
82
82
};